SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.61 | 100.00 | 90.48 | 97.60 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.61 | 100.00 | 90.48 | 97.60 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.61 | 100.00 | 90.48 | 97.60 | 100.00 | 100.00 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.61 | 100.00 | 90.48 | 97.60 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
78.91 | 86.27 | 76.47 | 100.00 | 81.82 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
90.00 | 100.00 | 100.00 | 100.00 | 100.00 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1566 | 1566 | 0 | 0 |
OutputsKnown_A | 295631125 | 295271917 | 0 | 0 |
gen_flops.OutputDelay_A | 147888855 | 147702483 | 0 | 2349 |
gen_no_flops.OutputDelay_A | 147742270 | 147562666 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1566 | 1566 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T5 | 6 | 6 | 0 | 0 |
T6 | 6 | 6 | 0 | 0 |
T7 | 6 | 6 | 0 | 0 |
T8 | 6 | 6 | 0 | 0 |
T15 | 6 | 6 | 0 | 0 |
T34 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 295631125 | 295271917 | 0 | 0 |
T1 | 21396 | 20850 | 0 | 0 |
T2 | 11694 | 11304 | 0 | 0 |
T3 | 578310 | 564066 | 0 | 0 |
T4 | 209844 | 209496 | 0 | 0 |
T5 | 1431168 | 1429500 | 0 | 0 |
T6 | 222330 | 219864 | 0 | 0 |
T7 | 867504 | 866106 | 0 | 0 |
T8 | 278526 | 278190 | 0 | 0 |
T15 | 692118 | 690840 | 0 | 0 |
T34 | 21822 | 21516 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 147888855 | 147702483 | 0 | 2349 |
T1 | 10698 | 10416 | 0 | 9 |
T2 | 5847 | 5643 | 0 | 9 |
T3 | 289155 | 281979 | 0 | 9 |
T4 | 104922 | 104739 | 0 | 9 |
T5 | 715584 | 714714 | 0 | 9 |
T6 | 111165 | 109878 | 0 | 9 |
T7 | 433752 | 433017 | 0 | 9 |
T8 | 139263 | 139086 | 0 | 9 |
T15 | 346059 | 345393 | 0 | 9 |
T34 | 10911 | 10749 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 147742270 | 147562666 | 0 | 0 |
T1 | 10698 | 10425 | 0 | 0 |
T2 | 5847 | 5652 | 0 | 0 |
T3 | 289155 | 282033 | 0 | 0 |
T4 | 104922 | 104748 | 0 | 0 |
T5 | 715584 | 714750 | 0 | 0 |
T6 | 111165 | 109932 | 0 | 0 |
T7 | 433752 | 433053 | 0 | 0 |
T8 | 139263 | 139095 | 0 | 0 |
T15 | 346059 | 345420 | 0 | 0 |
T34 | 10911 | 10758 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 261 | 261 | 0 | 0 |
OutputsKnown_A | 49296285 | 49236417 | 0 | 0 |
gen_flops.OutputDelay_A | 49296285 | 49234161 | 0 | 783 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 261 | 261 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 49296285 | 49236417 | 0 | 0 |
T1 | 3566 | 3475 | 0 | 0 |
T2 | 1949 | 1884 | 0 | 0 |
T3 | 96385 | 94011 | 0 | 0 |
T4 | 34974 | 34916 | 0 | 0 |
T5 | 238528 | 238250 | 0 | 0 |
T6 | 37055 | 36644 | 0 | 0 |
T7 | 144584 | 144351 | 0 | 0 |
T8 | 46421 | 46365 | 0 | 0 |
T15 | 115353 | 115140 | 0 | 0 |
T34 | 3637 | 3586 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 49296285 | 49234161 | 0 | 783 |
T1 | 3566 | 3472 | 0 | 3 |
T2 | 1949 | 1881 | 0 | 3 |
T3 | 96385 | 93993 | 0 | 3 |
T4 | 34974 | 34913 | 0 | 3 |
T5 | 238528 | 238238 | 0 | 3 |
T6 | 37055 | 36626 | 0 | 3 |
T7 | 144584 | 144339 | 0 | 3 |
T8 | 46421 | 46362 | 0 | 3 |
T15 | 115353 | 115131 | 0 | 3 |
T34 | 3637 | 3583 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 261 | 261 | 0 | 0 |
OutputsKnown_A | 49296285 | 49236417 | 0 | 0 |
gen_flops.OutputDelay_A | 49296285 | 49234161 | 0 | 783 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 261 | 261 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 49296285 | 49236417 | 0 | 0 |
T1 | 3566 | 3475 | 0 | 0 |
T2 | 1949 | 1884 | 0 | 0 |
T3 | 96385 | 94011 | 0 | 0 |
T4 | 34974 | 34916 | 0 | 0 |
T5 | 238528 | 238250 | 0 | 0 |
T6 | 37055 | 36644 | 0 | 0 |
T7 | 144584 | 144351 | 0 | 0 |
T8 | 46421 | 46365 | 0 | 0 |
T15 | 115353 | 115140 | 0 | 0 |
T34 | 3637 | 3586 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 49296285 | 49234161 | 0 | 783 |
T1 | 3566 | 3472 | 0 | 3 |
T2 | 1949 | 1881 | 0 | 3 |
T3 | 96385 | 93993 | 0 | 3 |
T4 | 34974 | 34913 | 0 | 3 |
T5 | 238528 | 238238 | 0 | 3 |
T6 | 37055 | 36626 | 0 | 3 |
T7 | 144584 | 144339 | 0 | 3 |
T8 | 46421 | 46362 | 0 | 3 |
T15 | 115353 | 115131 | 0 | 3 |
T34 | 3637 | 3583 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 261 | 261 | 0 | 0 |
OutputsKnown_A | 49149700 | 49089832 | 0 | 0 |
gen_no_flops.OutputDelay_A | 49149700 | 49089832 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 261 | 261 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 49149700 | 49089832 | 0 | 0 |
T1 | 3566 | 3475 | 0 | 0 |
T2 | 1949 | 1884 | 0 | 0 |
T3 | 96385 | 94011 | 0 | 0 |
T4 | 34974 | 34916 | 0 | 0 |
T5 | 238528 | 238250 | 0 | 0 |
T6 | 37055 | 36644 | 0 | 0 |
T7 | 144584 | 144351 | 0 | 0 |
T8 | 46421 | 46365 | 0 | 0 |
T15 | 115353 | 115140 | 0 | 0 |
T34 | 3637 | 3586 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 49149700 | 49089832 | 0 | 0 |
T1 | 3566 | 3475 | 0 | 0 |
T2 | 1949 | 1884 | 0 | 0 |
T3 | 96385 | 94011 | 0 | 0 |
T4 | 34974 | 34916 | 0 | 0 |
T5 | 238528 | 238250 | 0 | 0 |
T6 | 37055 | 36644 | 0 | 0 |
T7 | 144584 | 144351 | 0 | 0 |
T8 | 46421 | 46365 | 0 | 0 |
T15 | 115353 | 115140 | 0 | 0 |
T34 | 3637 | 3586 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 261 | 261 | 0 | 0 |
OutputsKnown_A | 49296285 | 49236417 | 0 | 0 |
gen_flops.OutputDelay_A | 49296285 | 49234161 | 0 | 783 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 261 | 261 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 49296285 | 49236417 | 0 | 0 |
T1 | 3566 | 3475 | 0 | 0 |
T2 | 1949 | 1884 | 0 | 0 |
T3 | 96385 | 94011 | 0 | 0 |
T4 | 34974 | 34916 | 0 | 0 |
T5 | 238528 | 238250 | 0 | 0 |
T6 | 37055 | 36644 | 0 | 0 |
T7 | 144584 | 144351 | 0 | 0 |
T8 | 46421 | 46365 | 0 | 0 |
T15 | 115353 | 115140 | 0 | 0 |
T34 | 3637 | 3586 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 49296285 | 49234161 | 0 | 783 |
T1 | 3566 | 3472 | 0 | 3 |
T2 | 1949 | 1881 | 0 | 3 |
T3 | 96385 | 93993 | 0 | 3 |
T4 | 34974 | 34913 | 0 | 3 |
T5 | 238528 | 238238 | 0 | 3 |
T6 | 37055 | 36626 | 0 | 3 |
T7 | 144584 | 144339 | 0 | 3 |
T8 | 46421 | 46362 | 0 | 3 |
T15 | 115353 | 115131 | 0 | 3 |
T34 | 3637 | 3583 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 261 | 261 | 0 | 0 |
OutputsKnown_A | 49296285 | 49236417 | 0 | 0 |
gen_no_flops.OutputDelay_A | 49296285 | 49236417 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 261 | 261 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 49296285 | 49236417 | 0 | 0 |
T1 | 3566 | 3475 | 0 | 0 |
T2 | 1949 | 1884 | 0 | 0 |
T3 | 96385 | 94011 | 0 | 0 |
T4 | 34974 | 34916 | 0 | 0 |
T5 | 238528 | 238250 | 0 | 0 |
T6 | 37055 | 36644 | 0 | 0 |
T7 | 144584 | 144351 | 0 | 0 |
T8 | 46421 | 46365 | 0 | 0 |
T15 | 115353 | 115140 | 0 | 0 |
T34 | 3637 | 3586 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 49296285 | 49236417 | 0 | 0 |
T1 | 3566 | 3475 | 0 | 0 |
T2 | 1949 | 1884 | 0 | 0 |
T3 | 96385 | 94011 | 0 | 0 |
T4 | 34974 | 34916 | 0 | 0 |
T5 | 238528 | 238250 | 0 | 0 |
T6 | 37055 | 36644 | 0 | 0 |
T7 | 144584 | 144351 | 0 | 0 |
T8 | 46421 | 46365 | 0 | 0 |
T15 | 115353 | 115140 | 0 | 0 |
T34 | 3637 | 3586 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 261 | 261 | 0 | 0 |
OutputsKnown_A | 49296285 | 49236417 | 0 | 0 |
gen_no_flops.OutputDelay_A | 49296285 | 49236417 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 261 | 261 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 49296285 | 49236417 | 0 | 0 |
T1 | 3566 | 3475 | 0 | 0 |
T2 | 1949 | 1884 | 0 | 0 |
T3 | 96385 | 94011 | 0 | 0 |
T4 | 34974 | 34916 | 0 | 0 |
T5 | 238528 | 238250 | 0 | 0 |
T6 | 37055 | 36644 | 0 | 0 |
T7 | 144584 | 144351 | 0 | 0 |
T8 | 46421 | 46365 | 0 | 0 |
T15 | 115353 | 115140 | 0 | 0 |
T34 | 3637 | 3586 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 49296285 | 49236417 | 0 | 0 |
T1 | 3566 | 3475 | 0 | 0 |
T2 | 1949 | 1884 | 0 | 0 |
T3 | 96385 | 94011 | 0 | 0 |
T4 | 34974 | 34916 | 0 | 0 |
T5 | 238528 | 238250 | 0 | 0 |
T6 | 37055 | 36644 | 0 | 0 |
T7 | 144584 | 144351 | 0 | 0 |
T8 | 46421 | 46365 | 0 | 0 |
T15 | 115353 | 115140 | 0 | 0 |
T34 | 3637 | 3586 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |