Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.77 60.77


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.77 60.77


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_rsp_chk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_regs.u_chk.u_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.23 89.23


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.23 89.23


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_chk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.23 89.23


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.23 89.23


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_cmd_intg_check.u_cmd_intg_chk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_secded_inv_64_57_dec
TotalCoveredPercent
Totals 4 3 75.00
Total Bits 260 232 89.23
Total Bits 0->1 130 116 89.23
Total Bits 1->0 130 116 89.23

Ports 4 3 75.00
Port Bits 260 232 89.23
Port Bits 0->1 130 116 89.23
Port Bits 1->0 130 116 89.23

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[42:0] Yes Yes T3,*T8,*T7 Yes T3,T7,T4 INPUT
data_i[56:43] No No No INPUT
data_i[63:57] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[56:0] Yes Yes T3,T8,T7 Yes T3,T7,T4 OUTPUT
syndrome_o[6:0] Yes Yes T7,T6,T15 Yes T2,T7,T34 OUTPUT
err_o[1:0] Yes Yes T3,T7,T4 Yes T3,T7,T5 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk
TotalCoveredPercent
Totals 4 3 75.00
Total Bits 260 158 60.77
Total Bits 0->1 130 79 60.77
Total Bits 1->0 130 79 60.77

Ports 4 3 75.00
Port Bits 260 158 60.77
Port Bits 0->1 130 79 60.77
Port Bits 1->0 130 79 60.77

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[5:0] Yes Yes *T8,*T34,*T6 Yes T6,T15,T32 INPUT
data_i[56:6] No No No INPUT
data_i[63:57] Yes Yes T8,T6,T15 Yes T8,T6,T15 INPUT
data_o[56:0] Yes Yes T8,T34,T6 Yes T6,T15,T32 OUTPUT
syndrome_o[6:0] Yes Yes T6,T15,T32 Yes T2,T34,T6 OUTPUT
err_o[1:0] Yes Yes T6,T15,T32 Yes T34,T6,T15 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_reg_regs.u_chk.u_chk
TotalCoveredPercent
Totals 4 3 75.00
Total Bits 260 232 89.23
Total Bits 0->1 130 116 89.23
Total Bits 1->0 130 116 89.23

Ports 4 3 75.00
Port Bits 260 232 89.23
Port Bits 0->1 130 116 89.23
Port Bits 1->0 130 116 89.23

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[42:0] Yes Yes T3,*T7,*T15 Yes T3,T7,T15 INPUT
data_i[56:43] No No No INPUT
data_i[63:57] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[56:0] Yes Yes T3,T7,T15 Yes T3,T7,T15 OUTPUT
syndrome_o[6:0] Yes Yes T7,T15,T70 Yes T7,T15,T70 OUTPUT
err_o[1:0] Yes Yes T7,T15,T70 Yes T7,T15,T70 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk
TotalCoveredPercent
Totals 4 3 75.00
Total Bits 260 232 89.23
Total Bits 0->1 130 116 89.23
Total Bits 1->0 130 116 89.23

Ports 4 3 75.00
Port Bits 260 232 89.23
Port Bits 0->1 130 116 89.23
Port Bits 1->0 130 116 89.23

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[42:0] Yes Yes T3,*T7,*T4 Yes T3,T7,T4 INPUT
data_i[56:43] No No No INPUT
data_i[63:57] Yes Yes T3,T7,T4 Yes T3,T7,T4 INPUT
data_o[56:0] Yes Yes T3,T7,T4 Yes T3,T7,T4 OUTPUT
syndrome_o[6:0] Yes Yes T7,T6,T43 Yes T7,T6,T71 OUTPUT
err_o[1:0] Yes Yes T3,T7,T4 Yes T3,T7,T5 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%