Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.24	96.32	89.82	92.10	94.67	90.44	98.00	56.31

Total test records in report: 482

T319	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/37.rv_dm_stress_all.2251980328	Aug 21 07:34:16 PM UTC 24	Aug 21 07:34:36 PM UTC 24	7470761617 ps
T320	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/48.rv_dm_stress_all.1578692836	Aug 21 07:34:20 PM UTC 24	Aug 21 07:34:37 PM UTC 24	9929430537 ps
T195	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/40.rv_dm_stress_all.3958781321	Aug 21 07:34:17 PM UTC 24	Aug 21 07:34:38 PM UTC 24	5935693637 ps
T55	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.2832517449	Aug 21 07:33:33 PM UTC 24	Aug 21 07:34:44 PM UTC 24	16784492513 ps
T321	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.1007913160	Aug 21 07:33:35 PM UTC 24	Aug 21 07:34:48 PM UTC 24	24059409540 ps
T322	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/13.rv_dm_autoincr_sba_tl_access.782102723	Aug 21 07:33:52 PM UTC 24	Aug 21 07:34:50 PM UTC 24	36070306898 ps
T323	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/10.rv_dm_autoincr_sba_tl_access.688662433	Aug 21 07:33:47 PM UTC 24	Aug 21 07:34:59 PM UTC 24	40654374575 ps
T324	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.3770716871	Aug 21 07:34:05 PM UTC 24	Aug 21 07:35:05 PM UTC 24	68698875119 ps
T325	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/17.rv_dm_autoincr_sba_tl_access.1902514969	Aug 21 07:34:02 PM UTC 24	Aug 21 07:35:28 PM UTC 24	46423310537 ps
T326	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/16.rv_dm_autoincr_sba_tl_access.3498241658	Aug 21 07:33:59 PM UTC 24	Aug 21 07:36:16 PM UTC 24	151672607429 ps
T327	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/11.rv_dm_autoincr_sba_tl_access.3299210284	Aug 21 07:33:49 PM UTC 24	Aug 21 07:38:28 PM UTC 24	89206984540 ps
T328	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.3791156611	Aug 21 07:33:29 PM UTC 24	Aug 21 07:38:50 PM UTC 24	113653979008 ps
T96	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2416556540	Aug 21 07:31:55 PM UTC 24	Aug 21 07:31:57 PM UTC 24	120117340 ps
T97	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.727408673	Aug 21 07:31:56 PM UTC 24	Aug 21 07:31:57 PM UTC 24	398116260 ps
T98	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.587916829	Aug 21 07:31:55 PM UTC 24	Aug 21 07:31:58 PM UTC 24	479805140 ps
T329	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.176345067	Aug 21 07:31:56 PM UTC 24	Aug 21 07:31:58 PM UTC 24	1938250393 ps
T114	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.2269268657	Aug 21 07:31:56 PM UTC 24	Aug 21 07:32:00 PM UTC 24	290853856 ps
T330	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.3772368184	Aug 21 07:31:56 PM UTC 24	Aug 21 07:32:01 PM UTC 24	51591182 ps
T331	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2046466080	Aug 21 07:31:59 PM UTC 24	Aug 21 07:32:01 PM UTC 24	225862755 ps
T332	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3415038871	Aug 21 07:31:56 PM UTC 24	Aug 21 07:32:01 PM UTC 24	44711933 ps
T333	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.906623385	Aug 21 07:31:49 PM UTC 24	Aug 21 07:32:01 PM UTC 24	511170546 ps
T334	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2473932646	Aug 21 07:31:49 PM UTC 24	Aug 21 07:32:01 PM UTC 24	317281973 ps
T123	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2921448771	Aug 21 07:31:56 PM UTC 24	Aug 21 07:32:02 PM UTC 24	252652245 ps
T335	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2366659562	Aug 21 07:31:59 PM UTC 24	Aug 21 07:32:02 PM UTC 24	1127634408 ps
T166	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3655766833	Aug 21 07:31:57 PM UTC 24	Aug 21 07:32:02 PM UTC 24	174923087 ps
T336	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.684650381	Aug 21 07:31:49 PM UTC 24	Aug 21 07:32:02 PM UTC 24	559982529 ps
T124	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.3436559372	Aug 21 07:31:56 PM UTC 24	Aug 21 07:32:02 PM UTC 24	430361498 ps
T337	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2435561957	Aug 21 07:31:59 PM UTC 24	Aug 21 07:32:03 PM UTC 24	1582367335 ps
T338	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.723026386	Aug 21 07:31:49 PM UTC 24	Aug 21 07:32:05 PM UTC 24	91061817 ps
T339	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2789523212	Aug 21 07:31:49 PM UTC 24	Aug 21 07:32:05 PM UTC 24	51053749 ps
T340	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2647254498	Aug 21 07:32:02 PM UTC 24	Aug 21 07:32:05 PM UTC 24	65827957 ps
T341	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_walk.3023002313	Aug 21 07:32:02 PM UTC 24	Aug 21 07:32:06 PM UTC 24	71725544 ps
T342	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3130757460	Aug 21 07:31:56 PM UTC 24	Aug 21 07:32:06 PM UTC 24	13988928212 ps
T343	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.4211635472	Aug 21 07:32:04 PM UTC 24	Aug 21 07:32:07 PM UTC 24	155044669 ps
T125	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_rw.190068369	Aug 21 07:32:02 PM UTC 24	Aug 21 07:32:07 PM UTC 24	176431013 ps
T126	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.65586526	Aug 21 07:32:02 PM UTC 24	Aug 21 07:32:07 PM UTC 24	356371204 ps
T167	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2844313560	Aug 21 07:31:56 PM UTC 24	Aug 21 07:32:07 PM UTC 24	3522847427 ps
T344	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.840271928	Aug 21 07:32:18 PM UTC 24	Aug 21 07:32:24 PM UTC 24	189210189 ps
T345	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1284635558	Aug 21 07:32:06 PM UTC 24	Aug 21 07:32:08 PM UTC 24	140345529 ps
T346	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_errors.552831364	Aug 21 07:32:02 PM UTC 24	Aug 21 07:32:08 PM UTC 24	892242269 ps
T347	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1406348218	Aug 21 07:32:06 PM UTC 24	Aug 21 07:32:08 PM UTC 24	287413532 ps
T348	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.236638021	Aug 21 07:32:06 PM UTC 24	Aug 21 07:32:08 PM UTC 24	212334862 ps
T349	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3142419315	Aug 21 07:32:02 PM UTC 24	Aug 21 07:32:08 PM UTC 24	2102827226 ps
T350	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2855250009	Aug 21 07:31:56 PM UTC 24	Aug 21 07:32:09 PM UTC 24	8298078919 ps
T127	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.837518948	Aug 21 07:31:56 PM UTC 24	Aug 21 07:32:09 PM UTC 24	1216580498 ps
T128	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3762717486	Aug 21 07:31:49 PM UTC 24	Aug 21 07:32:10 PM UTC 24	249933148 ps
T351	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2821122089	Aug 21 07:31:49 PM UTC 24	Aug 21 07:32:10 PM UTC 24	130772656 ps
T129	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.318911972	Aug 21 07:31:49 PM UTC 24	Aug 21 07:32:10 PM UTC 24	131560234 ps
T352	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_walk.242631607	Aug 21 07:32:09 PM UTC 24	Aug 21 07:32:10 PM UTC 24	28121051 ps
T353	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_partial_access.594860943	Aug 21 07:32:09 PM UTC 24	Aug 21 07:32:10 PM UTC 24	43744043 ps
T354	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.2470898445	Aug 21 07:31:49 PM UTC 24	Aug 21 07:32:11 PM UTC 24	308941643 ps
T130	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1184817460	Aug 21 07:31:49 PM UTC 24	Aug 21 07:32:12 PM UTC 24	642825471 ps
T131	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2978076251	Aug 21 07:32:04 PM UTC 24	Aug 21 07:32:12 PM UTC 24	170146986 ps
T355	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.64139769	Aug 21 07:32:11 PM UTC 24	Aug 21 07:32:13 PM UTC 24	152156100 ps
T132	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_rw.3859555510	Aug 21 07:32:10 PM UTC 24	Aug 21 07:32:13 PM UTC 24	72519543 ps
T356	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3920488590	Aug 21 07:32:07 PM UTC 24	Aug 21 07:32:14 PM UTC 24	5751401509 ps
T357	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1238891781	Aug 21 07:31:49 PM UTC 24	Aug 21 07:32:14 PM UTC 24	4429607034 ps
T138	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2798910308	Aug 21 07:32:10 PM UTC 24	Aug 21 07:32:14 PM UTC 24	1192604218 ps
T358	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_errors.2676209934	Aug 21 07:32:08 PM UTC 24	Aug 21 07:32:14 PM UTC 24	351180069 ps
T359	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3608257055	Aug 21 07:32:11 PM UTC 24	Aug 21 07:32:14 PM UTC 24	346973683 ps
T360	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2661947782	Aug 21 07:32:12 PM UTC 24	Aug 21 07:32:14 PM UTC 24	167053398 ps
T361	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3255222316	Aug 21 07:32:11 PM UTC 24	Aug 21 07:32:15 PM UTC 24	275037477 ps
T134	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2286760840	Aug 21 07:31:56 PM UTC 24	Aug 21 07:32:16 PM UTC 24	10401830126 ps
T135	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1644717322	Aug 21 07:32:12 PM UTC 24	Aug 21 07:32:17 PM UTC 24	2007929086 ps
T362	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_walk.3962766768	Aug 21 07:32:15 PM UTC 24	Aug 21 07:32:17 PM UTC 24	38066739 ps
T363	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1840820786	Aug 21 07:31:49 PM UTC 24	Aug 21 07:32:17 PM UTC 24	5643341862 ps
T364	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_partial_access.296737862	Aug 21 07:32:16 PM UTC 24	Aug 21 07:32:18 PM UTC 24	118110684 ps
T156	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3466451565	Aug 21 07:32:10 PM UTC 24	Aug 21 07:32:19 PM UTC 24	1081133310 ps
T139	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_rw.1138170702	Aug 21 07:32:16 PM UTC 24	Aug 21 07:32:19 PM UTC 24	265309686 ps
T365	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_errors.2709155668	Aug 21 07:32:14 PM UTC 24	Aug 21 07:32:19 PM UTC 24	149454723 ps
T140	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_rw.1446113704	Aug 21 07:32:22 PM UTC 24	Aug 21 07:32:25 PM UTC 24	1105062269 ps
T141	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3111230060	Aug 21 07:32:16 PM UTC 24	Aug 21 07:32:20 PM UTC 24	239951398 ps
T366	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1606510604	Aug 21 07:32:06 PM UTC 24	Aug 21 07:32:20 PM UTC 24	13165371487 ps
T168	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2359060646	Aug 21 07:32:02 PM UTC 24	Aug 21 07:32:20 PM UTC 24	4033252898 ps
T367	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1198916956	Aug 21 07:32:18 PM UTC 24	Aug 21 07:32:20 PM UTC 24	247908190 ps
T368	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.654056031	Aug 21 07:32:07 PM UTC 24	Aug 21 07:32:22 PM UTC 24	4255840834 ps
T369	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1348800325	Aug 21 07:32:13 PM UTC 24	Aug 21 07:32:22 PM UTC 24	6488269511 ps
T136	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2890159343	Aug 21 07:31:49 PM UTC 24	Aug 21 07:32:24 PM UTC 24	8448972569 ps
T169	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.212824645	Aug 21 07:31:49 PM UTC 24	Aug 21 07:32:24 PM UTC 24	2748818570 ps
T370	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2060426249	Aug 21 07:32:22 PM UTC 24	Aug 21 07:32:26 PM UTC 24	97666035 ps
T142	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1306416004	Aug 21 07:32:18 PM UTC 24	Aug 21 07:32:26 PM UTC 24	1512741216 ps
T371	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3410862509	Aug 21 07:32:24 PM UTC 24	Aug 21 07:32:27 PM UTC 24	594235267 ps
T147	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_rw.1930197247	Aug 21 07:32:27 PM UTC 24	Aug 21 07:32:30 PM UTC 24	65054351 ps
T372	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.1121257279	Aug 21 07:32:13 PM UTC 24	Aug 21 07:32:30 PM UTC 24	11908959757 ps
T373	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.675849551	Aug 21 07:32:21 PM UTC 24	Aug 21 07:32:30 PM UTC 24	7427609327 ps
T374	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_errors.1870024348	Aug 21 07:32:22 PM UTC 24	Aug 21 07:32:32 PM UTC 24	366256510 ps
T143	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.365046453	Aug 21 07:32:22 PM UTC 24	Aug 21 07:32:33 PM UTC 24	232978349 ps
T375	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_errors.4162577063	Aug 21 07:32:26 PM UTC 24	Aug 21 07:32:34 PM UTC 24	224351574 ps
T148	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3194395575	Aug 21 07:31:49 PM UTC 24	Aug 21 07:32:34 PM UTC 24	22315025973 ps
T376	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2671150023	Aug 21 07:32:24 PM UTC 24	Aug 21 07:32:34 PM UTC 24	4964932968 ps
T107	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2048168745	Aug 21 07:32:29 PM UTC 24	Aug 21 07:32:34 PM UTC 24	80147361 ps
T377	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2248296980	Aug 21 07:32:31 PM UTC 24	Aug 21 07:32:36 PM UTC 24	4896354606 ps
T378	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1796907656	Aug 21 07:32:31 PM UTC 24	Aug 21 07:32:36 PM UTC 24	547541375 ps
T157	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1624410667	Aug 21 07:32:29 PM UTC 24	Aug 21 07:32:37 PM UTC 24	617230231 ps
T379	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1041643019	Aug 21 07:32:04 PM UTC 24	Aug 21 07:32:38 PM UTC 24	22253447172 ps
T149	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.500714080	Aug 21 07:31:56 PM UTC 24	Aug 21 07:32:39 PM UTC 24	3795809703 ps
T150	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_rw.2006645496	Aug 21 07:32:35 PM UTC 24	Aug 21 07:32:39 PM UTC 24	109991900 ps
T380	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_errors.891035384	Aug 21 07:32:35 PM UTC 24	Aug 21 07:32:40 PM UTC 24	350771410 ps
T381	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1617621454	Aug 21 07:32:37 PM UTC 24	Aug 21 07:32:40 PM UTC 24	292530390 ps
T382	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_aliasing.763567132	Aug 21 07:32:11 PM UTC 24	Aug 21 07:32:40 PM UTC 24	625313636 ps
T383	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.464554990	Aug 21 07:32:21 PM UTC 24	Aug 21 07:32:40 PM UTC 24	6454114221 ps
T384	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1332873488	Aug 21 07:32:35 PM UTC 24	Aug 21 07:32:40 PM UTC 24	146490745 ps
T144	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.652311769	Aug 21 07:32:35 PM UTC 24	Aug 21 07:32:42 PM UTC 24	243719509 ps
T385	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2384396149	Aug 21 07:31:49 PM UTC 24	Aug 21 07:32:43 PM UTC 24	10038540410 ps
T200	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3148294814	Aug 21 07:32:22 PM UTC 24	Aug 21 07:32:43 PM UTC 24	10255096772 ps
T386	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.4170219763	Aug 21 07:33:01 PM UTC 24	Aug 21 07:33:07 PM UTC 24	1752165484 ps
T197	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1471585350	Aug 21 07:32:09 PM UTC 24	Aug 21 07:32:43 PM UTC 24	4114787970 ps
T201	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3583966772	Aug 21 07:32:14 PM UTC 24	Aug 21 07:32:44 PM UTC 24	4744246809 ps
T109	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.121195059	Aug 21 07:31:49 PM UTC 24	Aug 21 07:32:44 PM UTC 24	2327464093 ps
T387	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_errors.2302603506	Aug 21 07:32:40 PM UTC 24	Aug 21 07:32:44 PM UTC 24	171025901 ps
T388	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.145376293	Aug 21 07:32:31 PM UTC 24	Aug 21 07:32:44 PM UTC 24	6816873431 ps
T389	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.4173085406	Aug 21 07:32:42 PM UTC 24	Aug 21 07:32:44 PM UTC 24	490263862 ps
T390	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.710819215	Aug 21 07:32:37 PM UTC 24	Aug 21 07:32:44 PM UTC 24	6053276274 ps
T391	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2214024748	Aug 21 07:32:11 PM UTC 24	Aug 21 07:32:45 PM UTC 24	21110410667 ps
T392	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_rw.1241949169	Aug 21 07:32:42 PM UTC 24	Aug 21 07:32:45 PM UTC 24	350413538 ps
T393	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.952530126	Aug 21 07:32:42 PM UTC 24	Aug 21 07:32:47 PM UTC 24	173672208 ps
T151	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_rw.3911008265	Aug 21 07:32:44 PM UTC 24	Aug 21 07:32:47 PM UTC 24	153648142 ps
T394	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3654021843	Aug 21 07:32:24 PM UTC 24	Aug 21 07:32:49 PM UTC 24	7364456395 ps
T395	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_errors.4124934557	Aug 21 07:32:44 PM UTC 24	Aug 21 07:32:49 PM UTC 24	210761922 ps
T396	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_intg_err.72861165	Aug 21 07:32:40 PM UTC 24	Aug 21 07:32:49 PM UTC 24	530714889 ps
T158	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.659882139	Aug 21 07:32:42 PM UTC 24	Aug 21 07:32:50 PM UTC 24	1595996600 ps
T397	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1585932458	Aug 21 07:32:46 PM UTC 24	Aug 21 07:32:50 PM UTC 24	379483771 ps
T101	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3528873365	Aug 21 07:31:56 PM UTC 24	Aug 21 07:32:50 PM UTC 24	3479677208 ps
T398	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1371719183	Aug 21 07:32:42 PM UTC 24	Aug 21 07:32:51 PM UTC 24	1862794468 ps
T198	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_intg_err.38952124	Aug 21 07:32:26 PM UTC 24	Aug 21 07:32:51 PM UTC 24	2707136319 ps
T152	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2139419745	Aug 21 07:31:49 PM UTC 24	Aug 21 07:32:51 PM UTC 24	14361009944 ps
T399	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1765927652	Aug 21 07:32:02 PM UTC 24	Aug 21 07:32:51 PM UTC 24	14659644638 ps
T110	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2253253133	Aug 21 07:32:46 PM UTC 24	Aug 21 07:32:51 PM UTC 24	82350464 ps
T400	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.81874463	Aug 21 07:32:49 PM UTC 24	Aug 21 07:32:52 PM UTC 24	78203909 ps
T401	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.4018864267	Aug 21 07:32:50 PM UTC 24	Aug 21 07:32:52 PM UTC 24	698400808 ps
T402	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2294694668	Aug 21 07:32:46 PM UTC 24	Aug 21 07:32:52 PM UTC 24	2996048171 ps
T102	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.249423897	Aug 21 07:32:14 PM UTC 24	Aug 21 07:32:53 PM UTC 24	4315835089 ps
T403	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3752140410	Aug 21 07:32:50 PM UTC 24	Aug 21 07:32:53 PM UTC 24	167420251 ps
T159	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1005169472	Aug 21 07:32:46 PM UTC 24	Aug 21 07:32:54 PM UTC 24	582665738 ps
T137	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3947031687	Aug 21 07:32:06 PM UTC 24	Aug 21 07:32:54 PM UTC 24	13786727369 ps
T404	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.4172342844	Aug 21 07:32:49 PM UTC 24	Aug 21 07:32:55 PM UTC 24	352511209 ps
T405	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.1683960138	Aug 21 07:32:47 PM UTC 24	Aug 21 07:32:55 PM UTC 24	1751796149 ps
T153	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_rw.2230969146	Aug 21 07:32:52 PM UTC 24	Aug 21 07:32:55 PM UTC 24	91684458 ps
T406	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.901745998	Aug 21 07:32:52 PM UTC 24	Aug 21 07:32:55 PM UTC 24	525269448 ps
T407	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_errors.463140717	Aug 21 07:32:52 PM UTC 24	Aug 21 07:32:56 PM UTC 24	152911417 ps
T408	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.305054303	Aug 21 07:32:52 PM UTC 24	Aug 21 07:32:56 PM UTC 24	117367550 ps
T409	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3806870965	Aug 21 07:32:55 PM UTC 24	Aug 21 07:32:57 PM UTC 24	84993177 ps
T410	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_rw.1000566864	Aug 21 07:32:54 PM UTC 24	Aug 21 07:32:57 PM UTC 24	378907137 ps
T411	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2987534106	Aug 21 07:32:35 PM UTC 24	Aug 21 07:32:58 PM UTC 24	2085051621 ps
T412	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.4058327035	Aug 21 07:32:10 PM UTC 24	Aug 21 07:32:58 PM UTC 24	5686435106 ps
T413	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3603513309	Aug 21 07:32:54 PM UTC 24	Aug 21 07:32:58 PM UTC 24	146425561 ps
T414	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.4027487964	Aug 21 07:32:54 PM UTC 24	Aug 21 07:32:59 PM UTC 24	661560332 ps
T415	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.309541276	Aug 21 07:32:55 PM UTC 24	Aug 21 07:32:59 PM UTC 24	3021597383 ps
T416	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2656483319	Aug 21 07:32:52 PM UTC 24	Aug 21 07:32:59 PM UTC 24	637987480 ps
T417	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2220747034	Aug 21 07:32:50 PM UTC 24	Aug 21 07:32:59 PM UTC 24	2717107871 ps
T418	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_errors.972328233	Aug 21 07:32:56 PM UTC 24	Aug 21 07:32:59 PM UTC 24	269098801 ps
T154	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_rw.1466201876	Aug 21 07:32:56 PM UTC 24	Aug 21 07:33:00 PM UTC 24	258917204 ps
T419	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1823694620	Aug 21 07:32:57 PM UTC 24	Aug 21 07:33:00 PM UTC 24	520635504 ps
T199	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1468541338	Aug 21 07:32:44 PM UTC 24	Aug 21 07:33:00 PM UTC 24	3275189091 ps
T420	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_errors.1387867902	Aug 21 07:32:54 PM UTC 24	Aug 21 07:33:00 PM UTC 24	310461415 ps
T421	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.238058644	Aug 21 07:32:46 PM UTC 24	Aug 21 07:33:01 PM UTC 24	6564140974 ps
T422	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_rw.3410818779	Aug 21 07:33:00 PM UTC 24	Aug 21 07:33:02 PM UTC 24	157883385 ps
T423	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2333166130	Aug 21 07:32:57 PM UTC 24	Aug 21 07:33:02 PM UTC 24	140085978 ps
T424	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1707191090	Aug 21 07:32:52 PM UTC 24	Aug 21 07:33:02 PM UTC 24	6796867671 ps
T425	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3159870413	Aug 21 07:32:57 PM UTC 24	Aug 21 07:33:03 PM UTC 24	860045498 ps
T426	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.284789125	Aug 21 07:33:01 PM UTC 24	Aug 21 07:33:03 PM UTC 24	111109110 ps
T427	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.822987631	Aug 21 07:33:01 PM UTC 24	Aug 21 07:33:03 PM UTC 24	240404110 ps
T103	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.1404287857	Aug 21 07:32:08 PM UTC 24	Aug 21 07:33:04 PM UTC 24	3800545012 ps
T104	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3492023930	Aug 21 07:33:00 PM UTC 24	Aug 21 07:33:04 PM UTC 24	140790989 ps
T155	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_rw.2553187417	Aug 21 07:33:01 PM UTC 24	Aug 21 07:33:04 PM UTC 24	128615542 ps
T428	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1926366102	Aug 21 07:32:58 PM UTC 24	Aug 21 07:33:04 PM UTC 24	3308182280 ps
T429	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2946935790	Aug 21 07:31:59 PM UTC 24	Aug 21 07:33:05 PM UTC 24	1181758339 ps
T430	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1891653925	Aug 21 07:32:37 PM UTC 24	Aug 21 07:33:05 PM UTC 24	7176708305 ps
T205	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1503339987	Aug 21 07:32:47 PM UTC 24	Aug 21 07:33:05 PM UTC 24	1025961180 ps
T431	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1423359858	Aug 21 07:33:03 PM UTC 24	Aug 21 07:33:05 PM UTC 24	396710200 ps
T432	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_errors.2079671420	Aug 21 07:32:59 PM UTC 24	Aug 21 07:33:06 PM UTC 24	695884806 ps
T433	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_rw.3365169746	Aug 21 07:33:05 PM UTC 24	Aug 21 07:33:08 PM UTC 24	852364019 ps
T206	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_intg_err.945713191	Aug 21 07:32:56 PM UTC 24	Aug 21 07:33:07 PM UTC 24	1807749447 ps
T145	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.522544275	Aug 21 07:33:00 PM UTC 24	Aug 21 07:33:08 PM UTC 24	3057100269 ps
T434	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.794732801	Aug 21 07:33:06 PM UTC 24	Aug 21 07:33:08 PM UTC 24	167368383 ps
T435	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1981277431	Aug 21 07:32:54 PM UTC 24	Aug 21 07:33:09 PM UTC 24	2079788803 ps
T436	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_rw.843710275	Aug 21 07:33:06 PM UTC 24	Aug 21 07:33:09 PM UTC 24	316674914 ps
T437	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_errors.4040572349	Aug 21 07:33:01 PM UTC 24	Aug 21 07:33:09 PM UTC 24	286338984 ps
T438	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.321958934	Aug 21 07:32:17 PM UTC 24	Aug 21 07:33:09 PM UTC 24	17513623824 ps
T439	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1573978921	Aug 21 07:33:03 PM UTC 24	Aug 21 07:33:09 PM UTC 24	83998241 ps
T440	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_errors.2443605526	Aug 21 07:33:05 PM UTC 24	Aug 21 07:33:09 PM UTC 24	252344333 ps
T441	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3056575333	Aug 21 07:33:07 PM UTC 24	Aug 21 07:33:09 PM UTC 24	147982834 ps
T442	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.662045128	Aug 21 07:33:06 PM UTC 24	Aug 21 07:33:10 PM UTC 24	318259735 ps
T443	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.611510858	Aug 21 07:33:03 PM UTC 24	Aug 21 07:33:10 PM UTC 24	5729034860 ps
T444	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1964904352	Aug 21 07:32:52 PM UTC 24	Aug 21 07:33:10 PM UTC 24	10612932357 ps
T445	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_errors.3169508792	Aug 21 07:33:06 PM UTC 24	Aug 21 07:33:10 PM UTC 24	109646182 ps
T446	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2315284879	Aug 21 07:33:02 PM UTC 24	Aug 21 07:33:10 PM UTC 24	284946998 ps
T447	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3498621552	Aug 21 07:33:07 PM UTC 24	Aug 21 07:33:11 PM UTC 24	53688477 ps
T448	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1256241653	Aug 21 07:32:02 PM UTC 24	Aug 21 07:33:12 PM UTC 24	28005477984 ps
T449	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3841146067	Aug 21 07:33:10 PM UTC 24	Aug 21 07:33:12 PM UTC 24	184253536 ps
T450	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.793234005	Aug 21 07:31:55 PM UTC 24	Aug 21 07:33:13 PM UTC 24	3650791559 ps
T451	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1692046054	Aug 21 07:33:06 PM UTC 24	Aug 21 07:33:13 PM UTC 24	253250841 ps
T452	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.87125518	Aug 21 07:33:10 PM UTC 24	Aug 21 07:33:14 PM UTC 24	971684737 ps
T453	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_rw.4168849757	Aug 21 07:33:10 PM UTC 24	Aug 21 07:33:14 PM UTC 24	164694599 ps
T454	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_rw.3263300858	Aug 21 07:33:11 PM UTC 24	Aug 21 07:33:14 PM UTC 24	154794920 ps
T146	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2709817913	Aug 21 07:33:05 PM UTC 24	Aug 21 07:33:14 PM UTC 24	583180888 ps
T106	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2000344520	Aug 21 07:32:21 PM UTC 24	Aug 21 07:33:14 PM UTC 24	3704613926 ps
T455	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_errors.1027283863	Aug 21 07:33:10 PM UTC 24	Aug 21 07:33:14 PM UTC 24	182842412 ps
T105	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.4059693009	Aug 21 07:33:10 PM UTC 24	Aug 21 07:33:15 PM UTC 24	212413845 ps
T456	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.3196933111	Aug 21 07:32:53 PM UTC 24	Aug 21 07:33:17 PM UTC 24	7621217617 ps
T457	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2590480326	Aug 21 07:33:06 PM UTC 24	Aug 21 07:33:17 PM UTC 24	672652272 ps
T458	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.569347234	Aug 21 07:31:59 PM UTC 24	Aug 21 07:33:17 PM UTC 24	28249916477 ps
T459	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_errors.2990194063	Aug 21 07:33:11 PM UTC 24	Aug 21 07:33:17 PM UTC 24	846715292 ps
T460	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3971540114	Aug 21 07:33:11 PM UTC 24	Aug 21 07:33:18 PM UTC 24	107964167 ps
T461	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.228492315	Aug 21 07:32:52 PM UTC 24	Aug 21 07:33:18 PM UTC 24	1494659756 ps
T462	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1314047970	Aug 21 07:33:10 PM UTC 24	Aug 21 07:33:18 PM UTC 24	839841362 ps
T463	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_intg_err.834608564	Aug 21 07:33:01 PM UTC 24	Aug 21 07:33:20 PM UTC 24	1083922808 ps
T464	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1871106244	Aug 21 07:32:05 PM UTC 24	Aug 21 07:33:20 PM UTC 24	4141363563 ps
T465	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3620478146	Aug 21 07:33:06 PM UTC 24	Aug 21 07:33:20 PM UTC 24	13837938151 ps
T466	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.112802781	Aug 21 07:33:11 PM UTC 24	Aug 21 07:33:21 PM UTC 24	892985450 ps
T467	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2165459766	Aug 21 07:33:08 PM UTC 24	Aug 21 07:33:22 PM UTC 24	4643840920 ps
T468	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2072280937	Aug 21 07:32:07 PM UTC 24	Aug 21 07:33:23 PM UTC 24	25504991659 ps
T202	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3382402469	Aug 21 07:33:05 PM UTC 24	Aug 21 07:33:26 PM UTC 24	5367547897 ps
T469	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.4013837345	Aug 21 07:33:03 PM UTC 24	Aug 21 07:33:27 PM UTC 24	5996854367 ps
T203	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_intg_err.554413980	Aug 21 07:33:11 PM UTC 24	Aug 21 07:33:29 PM UTC 24	11214487134 ps
T470	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_intg_err.241688937	Aug 21 07:33:10 PM UTC 24	Aug 21 07:33:33 PM UTC 24	8499179648 ps
T204	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3527209041	Aug 21 07:32:59 PM UTC 24	Aug 21 07:33:34 PM UTC 24	5114054832 ps
T471	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.831676384	Aug 21 07:32:44 PM UTC 24	Aug 21 07:33:38 PM UTC 24	6851555560 ps
T472	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.2801921275	Aug 21 07:32:33 PM UTC 24	Aug 21 07:33:41 PM UTC 24	16165771630 ps
T473	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3318794972	Aug 21 07:32:58 PM UTC 24	Aug 21 07:33:42 PM UTC 24	14167443761 ps
T474	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2319963871	Aug 21 07:33:06 PM UTC 24	Aug 21 07:33:43 PM UTC 24	13474899393 ps
T99	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3257858776	Aug 21 07:32:39 PM UTC 24	Aug 21 07:33:46 PM UTC 24	15447403037 ps
T475	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.1186231813	Aug 21 07:32:44 PM UTC 24	Aug 21 07:33:47 PM UTC 24	23888119868 ps
T476	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.3228776867	Aug 21 07:33:10 PM UTC 24	Aug 21 07:33:51 PM UTC 24	12417026567 ps
T100	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2453952009	Aug 21 07:32:02 PM UTC 24	Aug 21 07:34:02 PM UTC 24	8664846253 ps
T111	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.1316932712	Aug 21 07:32:24 PM UTC 24	Aug 21 07:34:08 PM UTC 24	9694086726 ps
T477	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1845922151	Aug 21 07:31:56 PM UTC 24	Aug 21 07:34:14 PM UTC 24	41149700163 ps
T478	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2031101299	Aug 21 07:32:56 PM UTC 24	Aug 21 07:34:15 PM UTC 24	24633960752 ps
T479	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1843470297	Aug 21 07:33:10 PM UTC 24	Aug 21 07:34:53 PM UTC 24	35954175500 ps
T480	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3470396320	Aug 21 07:32:13 PM UTC 24	Aug 21 07:35:29 PM UTC 24	79169278329 ps
T481	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.4271516182	Aug 21 07:32:02 PM UTC 24	Aug 21 07:36:06 PM UTC 24	150888255555 ps
T482	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.616968476	Aug 21 07:31:49 PM UTC 24	Aug 21 07:36:25 PM UTC 24	101331120939 ps

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_tl_access.2829596156
Short name	T18
Test name
Test status
Simulation time	2647589874 ps
CPU time	5.32 seconds
Started	Aug 21 07:33:12 PM UTC 24
Finished	Aug 21 07:33:19 PM UTC 24
Peak memory	216276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2829596156 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc h/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2829596156
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all.665835155
Short name	T15
Test name
Test status
Simulation time	14593409209 ps
CPU time	5.95 seconds
Started	Aug 21 07:33:28 PM UTC 24
Finished	Aug 21 07:33:35 PM UTC 24
Peak memory	216284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=665835155 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.665835155
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/2.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.3277508689
Short name	T70
Test name
Test status
Simulation time	11574656570 ps
CPU time	26.45 seconds
Started	Aug 21 07:33:25 PM UTC 24
Finished	Aug 21 07:33:53 PM UTC 24
Peak memory	233416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100000 00000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/low risc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3277508689 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all_with_rand_reset.3277508689
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/0.rv_dm_dataaddr_rw_access.3351125464
Short name	T6
Test name
Test status
Simulation time	207678177 ps
CPU time	0.97 seconds
Started	Aug 21 07:33:16 PM UTC 24
Finished	Aug 21 07:33:18 PM UTC 24
Peak memory	215952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3351125464 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.3351125464
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_dataaddr_rw_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.4152236888
Short name	T61
Test name
Test status
Simulation time	2808781742 ps
CPU time	15.3 seconds
Started	Aug 21 07:33:30 PM UTC 24
Finished	Aug 21 07:33:46 PM UTC 24
Peak memory	232656 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100000 00000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/low risc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4152236888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all_with_rand_reset.4152236888
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.591724141
Short name	T79
Test name
Test status
Simulation time	4303414983 ps
CPU time	12.27 seconds
Started	Aug 21 07:33:13 PM UTC 24
Finished	Aug 21 07:33:27 PM UTC 24
Peak memory	226652 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=591724141 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.591724141
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3257858776
Short name	T99
Test name
Test status
Simulation time	15447403037 ps
CPU time	64.53 seconds
Started	Aug 21 07:32:39 PM UTC 24
Finished	Aug 21 07:33:46 PM UTC 24
Peak memory	232776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm _tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/h w/dv/tools/sim.tcl +ntb_random_seed=3257858776 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.3257858776
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/8.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2844313560
Short name	T167
Test name
Test status
Simulation time	3522847427 ps
CPU time	10.44 seconds
Started	Aug 21 07:31:56 PM UTC 24
Finished	Aug 21 07:32:07 PM UTC 24
Peak memory	226104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2844313560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.2844313560
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_tl_intg_err/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.4220010436
Short name	T89
Test name
Test status
Simulation time	11307669 ps
CPU time	0.86 seconds
Started	Aug 21 07:33:21 PM UTC 24
Finished	Aug 21 07:33:23 PM UTC 24
Peak memory	215948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4220010436 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_scanmode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_scanmode.4220010436
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_scanmode/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.2689801070
Short name	T20
Test name
Test status
Simulation time	104716975 ps
CPU time	1.22 seconds
Started	Aug 21 07:33:20 PM UTC 24
Finished	Aug 21 07:33:22 PM UTC 24
Peak memory	251956 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2689801070 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra tch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_buffered_enable.2689801070
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_buffered_enable/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/6.rv_dm_autoincr_sba_tl_access.1648462410
Short name	T255
Test name
Test status
Simulation time	21209647872 ps
CPU time	24.46 seconds
Started	Aug 21 07:33:37 PM UTC 24
Finished	Aug 21 07:34:03 PM UTC 24
Peak memory	226584 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1648462410 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit an/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.1648462410
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/6.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3528873365
Short name	T101
Test name
Test status
Simulation time	3479677208 ps
CPU time	52.84 seconds
Started	Aug 21 07:31:56 PM UTC 24
Finished	Aug 21 07:32:50 PM UTC 24
Peak memory	230076 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm _tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/h w/dv/tools/sim.tcl +ntb_random_seed=3528873365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.3528873365
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.3511079943
Short name	T26
Test name
Test status
Simulation time	3125735815 ps
CPU time	50.06 seconds
Started	Aug 21 07:33:28 PM UTC 24
Finished	Aug 21 07:34:20 PM UTC 24
Peak memory	233168 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100000 00000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/low risc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3511079943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all_with_rand_reset.3511079943
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.796346134
Short name	T46
Test name
Test status
Simulation time	243850502 ps
CPU time	0.86 seconds
Started	Aug 21 07:33:20 PM UTC 24
Finished	Aug 21 07:33:22 PM UTC 24
Peak memory	225868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=796346134 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc ratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sparse_lc_gate_fsm.796346134
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_sparse_lc_gate_fsm/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.1357584722
Short name	T24
Test name
Test status
Simulation time	172943865 ps
CPU time	1.23 seconds
Started	Aug 21 07:33:20 PM UTC 24
Finished	Aug 21 07:33:22 PM UTC 24
Peak memory	213472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1357584722 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc h/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.1357584722
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_dmi_failed_op/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/14.rv_dm_stress_all.4007442994
Short name	T31
Test name
Test status
Simulation time	5926198693 ps
CPU time	11.98 seconds
Started	Aug 21 07:33:56 PM UTC 24
Finished	Aug 21 07:34:09 PM UTC 24
Peak memory	226336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4007442994 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.4007442994
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/14.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.1316932712
Short name	T111
Test name
Test status
Simulation time	9694086726 ps
CPU time	101.73 seconds
Started	Aug 21 07:32:24 PM UTC 24
Finished	Aug 21 07:34:08 PM UTC 24
Peak memory	230272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm _tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/h w/dv/tools/sim.tcl +ntb_random_seed=1316932712 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.1316932712
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/6.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3492023930
Short name	T104
Test name
Test status
Simulation time	140790989 ps
CPU time	3.5 seconds
Started	Aug 21 07:33:00 PM UTC 24
Finished	Aug 21 07:33:04 PM UTC 24
Peak memory	230048 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns= 10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/ dv/tools/sim.tcl +ntb_random_seed=3492023930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.3492023930
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2000344520
Short name	T106
Test name
Test status
Simulation time	3704613926 ps
CPU time	51.38 seconds
Started	Aug 21 07:32:21 PM UTC 24
Finished	Aug 21 07:33:14 PM UTC 24
Peak memory	230336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm _tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/h w/dv/tools/sim.tcl +ntb_random_seed=2000344520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.2000344520
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/5.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all_with_rand_reset.1931578652
Short name	T71
Test name
Test status
Simulation time	1344933491 ps
CPU time	21.73 seconds
Started	Aug 21 07:33:38 PM UTC 24
Finished	Aug 21 07:34:01 PM UTC 24
Peak memory	233132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100000 00000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/low risc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1931578652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all_with_rand_reset.1931578652
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.2832517449
Short name	T55
Test name
Test status
Simulation time	16784492513 ps
CPU time	69.02 seconds
Started	Aug 21 07:33:33 PM UTC 24
Finished	Aug 21 07:34:44 PM UTC 24
Peak memory	243520 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100000 00000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/low risc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2832517449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all_with_rand_reset.2832517449
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/1.rv_dm_sec_cm.1333668843
Short name	T84
Test name
Test status
Simulation time	1429970592 ps
CPU time	2.97 seconds
Started	Aug 21 07:33:27 PM UTC 24
Finished	Aug 21 07:33:31 PM UTC 24
Peak memory	254636 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1333668843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.1333668843
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_sec_cm/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1503339987
Short name	T205
Test name
Test status
Simulation time	1025961180 ps
CPU time	17.31 seconds
Started	Aug 21 07:32:47 PM UTC 24
Finished	Aug 21 07:33:05 PM UTC 24
Peak memory	225976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1503339987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.1503339987
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/10.rv_dm_tl_intg_err/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_rw.3859555510
Short name	T132
Test name
Test status
Simulation time	72519543 ps
CPU time	2.21 seconds
Started	Aug 21 07:32:10 PM UTC 24
Finished	Aug 21 07:32:13 PM UTC 24
Peak memory	230076 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3859555510 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.3859555510
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/3.rv_dm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.739023412
Short name	T3
Test name
Test status
Simulation time	390069222 ps
CPU time	1.48 seconds
Started	Aug 21 07:33:15 PM UTC 24
Finished	Aug 21 07:33:17 PM UTC 24
Peak memory	215952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=739023412 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra tch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.739023412
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_cmderr_exception/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/29.rv_dm_stress_all.1723972992
Short name	T316
Test name
Test status
Simulation time	4584464978 ps
CPU time	16.28 seconds
Started	Aug 21 07:34:13 PM UTC 24
Finished	Aug 21 07:34:30 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1723972992 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.1723972992
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/29.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.367857677
Short name	T32
Test name
Test status
Simulation time	9272021137 ps
CPU time	41.59 seconds
Started	Aug 21 07:33:21 PM UTC 24
Finished	Aug 21 07:34:04 PM UTC 24
Peak memory	233260 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100000 00000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/low risc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=367857677 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all_with_rand_reset.367857677
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.1289838842
Short name	T48
Test name
Test status
Simulation time	282387036 ps
CPU time	0.93 seconds
Started	Aug 21 07:33:21 PM UTC 24
Finished	Aug 21 07:33:23 PM UTC 24
Peak memory	215892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1289838842 -asser t nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.1289838842
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.2438091747
Short name	T64
Test name
Test status
Simulation time	81706719 ps
CPU time	0.92 seconds
Started	Aug 21 07:33:19 PM UTC 24
Finished	Aug 21 07:33:21 PM UTC 24
Peak memory	225812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2438091747 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra tch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.2438091747
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_rom_read_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.2736159746
Short name	T35
Test name
Test status
Simulation time	3146147752 ps
CPU time	4.56 seconds
Started	Aug 21 07:33:32 PM UTC 24
Finished	Aug 21 07:33:38 PM UTC 24
Peak memory	216012 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2736159746 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.2736159746
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/4.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/13.rv_dm_bad_sba_tl_access.3712101099
Short name	T175
Test name
Test status
Simulation time	5924462344 ps
CPU time	20.35 seconds
Started	Aug 21 07:33:52 PM UTC 24
Finished	Aug 21 07:34:14 PM UTC 24
Peak memory	226572 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3712101099 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc ratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.3712101099
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/13.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.3156455980
Short name	T19
Test name
Test status
Simulation time	4834478397 ps
CPU time	2.84 seconds
Started	Aug 21 07:33:17 PM UTC 24
Finished	Aug 21 07:33:21 PM UTC 24
Peak memory	216092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3156455980 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.3156455980
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_sba_debug_disabled/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.365046453
Short name	T143
Test name
Test status
Simulation time	232978349 ps
CPU time	9.25 seconds
Started	Aug 21 07:32:22 PM UTC 24
Finished	Aug 21 07:32:33 PM UTC 24
Peak memory	215556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3 65046453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same _csr_outstanding.365046453
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/5.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.1007913160
Short name	T321
Test name
Test status
Simulation time	24059409540 ps
CPU time	71.96 seconds
Started	Aug 21 07:33:35 PM UTC 24
Finished	Aug 21 07:34:48 PM UTC 24
Peak memory	226512 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1007913160 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit an/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.1007913160
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/5.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.3527363810
Short name	T42
Test name
Test status
Simulation time	2131038107 ps
CPU time	7.26 seconds
Started	Aug 21 07:33:21 PM UTC 24
Finished	Aug 21 07:33:29 PM UTC 24
Peak memory	226264 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3527363810 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.3527363810
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.212824645
Short name	T169
Test name
Test status
Simulation time	2748818570 ps
CPU time	18.78 seconds
Started	Aug 21 07:31:49 PM UTC 24
Finished	Aug 21 07:32:24 PM UTC 24
Peak memory	226016 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=212824645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.212824645
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_tl_intg_err/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/10.rv_dm_autoincr_sba_tl_access.688662433
Short name	T323
Test name
Test status
Simulation time	40654374575 ps
CPU time	69.62 seconds
Started	Aug 21 07:33:47 PM UTC 24
Finished	Aug 21 07:34:59 PM UTC 24
Peak memory	226572 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=688662433 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.688662433
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/10.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2473932646
Short name	T334
Test name
Test status
Simulation time	317281973 ps
CPU time	1.44 seconds
Started	Aug 21 07:31:49 PM UTC 24
Finished	Aug 21 07:32:01 PM UTC 24
Peak memory	215332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2473932646 -a ssert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_ csr_aliasing.2473932646
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2890159343
Short name	T136
Test name
Test status
Simulation time	8448972569 ps
CPU time	23.28 seconds
Started	Aug 21 07:31:49 PM UTC 24
Finished	Aug 21 07:32:24 PM UTC 24
Peak memory	215772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2890159343 -a ssert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_ csr_hw_reset.2890159343
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/1.rv_dm_bad_sba_tl_access.3344169421
Short name	T43
Test name
Test status
Simulation time	1009026944 ps
CPU time	1.62 seconds
Started	Aug 21 07:33:22 PM UTC 24
Finished	Aug 21 07:33:25 PM UTC 24
Peak memory	215444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3344169421 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc ratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.3344169421
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.3125080699
Short name	T5
Test name
Test status
Simulation time	453364419 ps
CPU time	2.35 seconds
Started	Aug 21 07:33:16 PM UTC 24
Finished	Aug 21 07:33:19 PM UTC 24
Peak memory	215820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3125080699 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.3125080699
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_cmderr_halt_resume/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3527209041
Short name	T204
Test name
Test status
Simulation time	5114054832 ps
CPU time	33.51 seconds
Started	Aug 21 07:32:59 PM UTC 24
Finished	Aug 21 07:33:34 PM UTC 24
Peak memory	232768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3527209041 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.3527209041
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/14.rv_dm_tl_intg_err/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_intg_err.554413980
Short name	T203
Test name
Test status
Simulation time	11214487134 ps
CPU time	16.5 seconds
Started	Aug 21 07:33:11 PM UTC 24
Finished	Aug 21 07:33:29 PM UTC 24
Peak memory	225940 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=554413980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.554413980
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/19.rv_dm_tl_intg_err/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/0.rv_dm_smoke.1014815929
Short name	T1
Test name
Test status
Simulation time	585999801 ps
CPU time	1.49 seconds
Started	Aug 21 07:33:11 PM UTC 24
Finished	Aug 21 07:33:14 PM UTC 24
Peak memory	215372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1014815929 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.1014815929
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_smoke/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/1.rv_dm_dataaddr_rw_access.2924685224
Short name	T40
Test name
Test status
Simulation time	133893613 ps
CPU time	1.09 seconds
Started	Aug 21 07:33:24 PM UTC 24
Finished	Aug 21 07:33:26 PM UTC 24
Peak memory	215632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2924685224 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.2924685224
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_dataaddr_rw_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/18.rv_dm_autoincr_sba_tl_access.3555044480
Short name	T173
Test name
Test status
Simulation time	5702890684 ps
CPU time	10.64 seconds
Started	Aug 21 07:34:04 PM UTC 24
Finished	Aug 21 07:34:16 PM UTC 24
Peak memory	226516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3555044480 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit an/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.3555044480
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/18.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/18.rv_dm_stress_all.3827202871
Short name	T184
Test name
Test status
Simulation time	4580534336 ps
CPU time	7.4 seconds
Started	Aug 21 07:34:04 PM UTC 24
Finished	Aug 21 07:34:13 PM UTC 24
Peak memory	226412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3827202871 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.3827202871
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/18.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/19.rv_dm_bad_sba_tl_access.3261833415
Short name	T189
Test name
Test status
Simulation time	7314267398 ps
CPU time	5.98 seconds
Started	Aug 21 07:34:05 PM UTC 24
Finished	Aug 21 07:34:13 PM UTC 24
Peak memory	226516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3261833415 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc ratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.3261833415
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/19.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.2868148401
Short name	T10
Test name
Test status
Simulation time	3992205923 ps
CPU time	6.91 seconds
Started	Aug 21 07:34:05 PM UTC 24
Finished	Aug 21 07:34:14 PM UTC 24
Peak memory	216224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2868148401 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.2868148401
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/20.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/38.rv_dm_stress_all.2541604720
Short name	T194
Test name
Test status
Simulation time	2586747352 ps
CPU time	4.72 seconds
Started	Aug 21 07:34:17 PM UTC 24
Finished	Aug 21 07:34:22 PM UTC 24
Peak memory	216028 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2541604720 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.2541604720
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/38.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3194395575
Short name	T148
Test name
Test status
Simulation time	22315025973 ps
CPU time	33.75 seconds
Started	Aug 21 07:31:49 PM UTC 24
Finished	Aug 21 07:32:34 PM UTC 24
Peak memory	213732 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl + ntb_random_seed=3194395575 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 0.rv_dm_csr_aliasing.3194395575
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_csr_aliasing/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2139419745
Short name	T152
Test name
Test status
Simulation time	14361009944 ps
CPU time	42.72 seconds
Started	Aug 21 07:31:49 PM UTC 24
Finished	Aug 21 07:32:51 PM UTC 24
Peak memory	215640 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2139419745 -a ssert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.2139419745
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_csr_bit_bash/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3762717486
Short name	T128
Test name
Test status
Simulation time	249933148 ps
CPU time	2.41 seconds
Started	Aug 21 07:31:49 PM UTC 24
Finished	Aug 21 07:32:10 PM UTC 24
Peak memory	225788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3762717486 -a ssert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.3762717486
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_csr_hw_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2821122089
Short name	T351
Test name
Test status
Simulation time	130772656 ps
CPU time	2.29 seconds
Started	Aug 21 07:31:49 PM UTC 24
Finished	Aug 21 07:32:10 PM UTC 24
Peak memory	225980 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns= 10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/ dv/tools/sim.tcl +ntb_random_seed=2821122089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.2821122089
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.318911972
Short name	T129
Test name
Test status
Simulation time	131560234 ps
CPU time	2.52 seconds
Started	Aug 21 07:31:49 PM UTC 24
Finished	Aug 21 07:32:10 PM UTC 24
Peak memory	229864 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=318911972 -assert n opostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.318911972
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.616968476
Short name	T482
Test name
Test status
Simulation time	101331120939 ps
CPU time	254.94 seconds
Started	Aug 21 07:31:49 PM UTC 24
Finished	Aug 21 07:36:25 PM UTC 24
Peak memory	215548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=616968476 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_c sr_aliasing.616968476
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2384396149
Short name	T385
Test name
Test status
Simulation time	10038540410 ps
CPU time	35.38 seconds
Started	Aug 21 07:31:49 PM UTC 24
Finished	Aug 21 07:32:43 PM UTC 24
Peak memory	215704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=2384396149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_bit_bash.2384396149
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1238891781
Short name	T357
Test name
Test status
Simulation time	4429607034 ps
CPU time	13.7 seconds
Started	Aug 21 07:31:49 PM UTC 24
Finished	Aug 21 07:32:14 PM UTC 24
Peak memory	215744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1238891781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.1238891781
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1840820786
Short name	T363
Test name
Test status
Simulation time	5643341862 ps
CPU time	16.97 seconds
Started	Aug 21 07:31:49 PM UTC 24
Finished	Aug 21 07:32:17 PM UTC 24
Peak memory	215576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1840820786 -a ssert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_ csr_bit_bash.1840820786
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.906623385
Short name	T333
Test name
Test status
Simulation time	511170546 ps
CPU time	1.24 seconds
Started	Aug 21 07:31:49 PM UTC 24
Finished	Aug 21 07:32:01 PM UTC 24
Peak memory	213344 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=906623385 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_c sr_hw_reset.906623385
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.684650381
Short name	T336
Test name
Test status
Simulation time	559982529 ps
CPU time	2.17 seconds
Started	Aug 21 07:31:49 PM UTC 24
Finished	Aug 21 07:32:02 PM UTC 24
Peak memory	215532 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=684650381 -assert n opostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.684650381
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2789523212
Short name	T339
Test name
Test status
Simulation time	51053749 ps
CPU time	0.72 seconds
Started	Aug 21 07:31:49 PM UTC 24
Finished	Aug 21 07:32:05 PM UTC 24
Peak memory	215392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=278 9523212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_p artial_access.2789523212
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_mem_partial_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.723026386
Short name	T338
Test name
Test status
Simulation time	91061817 ps
CPU time	0.75 seconds
Started	Aug 21 07:31:49 PM UTC 24
Finished	Aug 21 07:32:05 PM UTC 24
Peak memory	215332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=723026386 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.723026386
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_mem_walk/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1184817460
Short name	T130
Test name
Test status
Simulation time	642825471 ps
CPU time	4.27 seconds
Started	Aug 21 07:31:49 PM UTC 24
Finished	Aug 21 07:32:12 PM UTC 24
Peak memory	215684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1 184817460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_sam e_csr_outstanding.1184817460
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.121195059
Short name	T109
Test name
Test status
Simulation time	2327464093 ps
CPU time	43.11 seconds
Started	Aug 21 07:31:49 PM UTC 24
Finished	Aug 21 07:32:44 PM UTC 24
Peak memory	232652 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm _tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/h w/dv/tools/sim.tcl +ntb_random_seed=121195059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.121195059
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.2470898445
Short name	T354
Test name
Test status
Simulation time	308941643 ps
CPU time	3.58 seconds
Started	Aug 21 07:31:49 PM UTC 24
Finished	Aug 21 07:32:11 PM UTC 24
Peak memory	226076 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2470898445 -assert nop ostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.2470898445
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_tl_errors/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.793234005
Short name	T450
Test name
Test status
Simulation time	3650791559 ps
CPU time	75.2 seconds
Started	Aug 21 07:31:55 PM UTC 24
Finished	Aug 21 07:33:13 PM UTC 24
Peak memory	230020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl + ntb_random_seed=793234005 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 1.rv_dm_csr_aliasing.793234005
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_csr_aliasing/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.500714080
Short name	T149
Test name
Test status
Simulation time	3795809703 ps
CPU time	38.34 seconds
Started	Aug 21 07:31:56 PM UTC 24
Finished	Aug 21 07:32:39 PM UTC 24
Peak memory	225944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=500714080 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.500714080
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_csr_bit_bash/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2921448771
Short name	T123
Test name
Test status
Simulation time	252652245 ps
CPU time	1.53 seconds
Started	Aug 21 07:31:56 PM UTC 24
Finished	Aug 21 07:32:02 PM UTC 24
Peak memory	225412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2921448771 -a ssert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2921448771
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_csr_hw_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3655766833
Short name	T166
Test name
Test status
Simulation time	174923087 ps
CPU time	2.53 seconds
Started	Aug 21 07:31:57 PM UTC 24
Finished	Aug 21 07:32:02 PM UTC 24
Peak memory	225952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns= 10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/ dv/tools/sim.tcl +ntb_random_seed=3655766833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.3655766833
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.3436559372
Short name	T124
Test name
Test status
Simulation time	430361498 ps
CPU time	2.44 seconds
Started	Aug 21 07:31:56 PM UTC 24
Finished	Aug 21 07:32:02 PM UTC 24
Peak memory	225788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3436559372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.3436559372
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1845922151
Short name	T477
Test name
Test status
Simulation time	41149700163 ps
CPU time	135.82 seconds
Started	Aug 21 07:31:56 PM UTC 24
Finished	Aug 21 07:34:14 PM UTC 24
Peak memory	215604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1845922151 -a ssert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_ csr_aliasing.1845922151
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3130757460
Short name	T342
Test name
Test status
Simulation time	13988928212 ps
CPU time	9.16 seconds
Started	Aug 21 07:31:56 PM UTC 24
Finished	Aug 21 07:32:06 PM UTC 24
Peak memory	215768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=3130757460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_bit_bash.3130757460
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2286760840
Short name	T134
Test name
Test status
Simulation time	10401830126 ps
CPU time	19.66 seconds
Started	Aug 21 07:31:56 PM UTC 24
Finished	Aug 21 07:32:16 PM UTC 24
Peak memory	215684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2286760840 -a ssert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_ csr_hw_reset.2286760840
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.176345067
Short name	T329
Test name
Test status
Simulation time	1938250393 ps
CPU time	1.72 seconds
Started	Aug 21 07:31:56 PM UTC 24
Finished	Aug 21 07:31:58 PM UTC 24
Peak memory	215348 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=176345067 -assert n opostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.176345067
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.727408673
Short name	T97
Test name
Test status
Simulation time	398116260 ps
CPU time	0.85 seconds
Started	Aug 21 07:31:56 PM UTC 24
Finished	Aug 21 07:31:57 PM UTC 24
Peak memory	215328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=727408673 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_c sr_aliasing.727408673
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2855250009
Short name	T350
Test name
Test status
Simulation time	8298078919 ps
CPU time	11.88 seconds
Started	Aug 21 07:31:56 PM UTC 24
Finished	Aug 21 07:32:09 PM UTC 24
Peak memory	215704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2855250009 -a ssert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_ csr_bit_bash.2855250009
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2416556540
Short name	T96
Test name
Test status
Simulation time	120117340 ps
CPU time	0.79 seconds
Started	Aug 21 07:31:55 PM UTC 24
Finished	Aug 21 07:31:57 PM UTC 24
Peak memory	214808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2416556540 -a ssert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_ csr_hw_reset.2416556540
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.587916829
Short name	T98
Test name
Test status
Simulation time	479805140 ps
CPU time	1.32 seconds
Started	Aug 21 07:31:55 PM UTC 24
Finished	Aug 21 07:31:58 PM UTC 24
Peak memory	215328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=587916829 -assert n opostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.587916829
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3415038871
Short name	T332
Test name
Test status
Simulation time	44711933 ps
CPU time	0.74 seconds
Started	Aug 21 07:31:56 PM UTC 24
Finished	Aug 21 07:32:01 PM UTC 24
Peak memory	215392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=341 5038871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_p artial_access.3415038871
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_mem_partial_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.3772368184
Short name	T330
Test name
Test status
Simulation time	51591182 ps
CPU time	0.63 seconds
Started	Aug 21 07:31:56 PM UTC 24
Finished	Aug 21 07:32:01 PM UTC 24
Peak memory	215328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3772368184 -a ssert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.3772368184
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_mem_walk/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.837518948
Short name	T127
Test name
Test status
Simulation time	1216580498 ps
CPU time	8.53 seconds
Started	Aug 21 07:31:56 PM UTC 24
Finished	Aug 21 07:32:09 PM UTC 24
Peak memory	215488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=8 37518948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same _csr_outstanding.837518948
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.2269268657
Short name	T114
Test name
Test status
Simulation time	290853856 ps
CPU time	2.98 seconds
Started	Aug 21 07:31:56 PM UTC 24
Finished	Aug 21 07:32:00 PM UTC 24
Peak memory	226076 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2269268657 -assert nop ostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.2269268657
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_tl_errors/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3752140410
Short name	T403
Test name
Test status
Simulation time	167420251 ps
CPU time	2.33 seconds
Started	Aug 21 07:32:50 PM UTC 24
Finished	Aug 21 07:32:53 PM UTC 24
Peak memory	225924 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns= 10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/ dv/tools/sim.tcl +ntb_random_seed=3752140410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.3752140410
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.81874463
Short name	T400
Test name
Test status
Simulation time	78203909 ps
CPU time	2.19 seconds
Started	Aug 21 07:32:49 PM UTC 24
Finished	Aug 21 07:32:52 PM UTC 24
Peak memory	225860 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=81874463 -assert no postproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.81874463
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/10.rv_dm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.238058644
Short name	T421
Test name
Test status
Simulation time	6564140974 ps
CPU time	13.76 seconds
Started	Aug 21 07:32:46 PM UTC 24
Finished	Aug 21 07:33:01 PM UTC 24
Peak memory	215700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=238058644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 0.rv_dm_jtag_dmi_csr_bit_bash.238058644
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2294694668
Short name	T402
Test name
Test status
Simulation time	2996048171 ps
CPU time	4.78 seconds
Started	Aug 21 07:32:46 PM UTC 24
Finished	Aug 21 07:32:52 PM UTC 24
Peak memory	215624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2294694668 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.2294694668
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/10.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1585932458
Short name	T397
Test name
Test status
Simulation time	379483771 ps
CPU time	2.21 seconds
Started	Aug 21 07:32:46 PM UTC 24
Finished	Aug 21 07:32:50 PM UTC 24
Peak memory	215408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1585932458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.1585932458
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/10.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.4172342844
Short name	T404
Test name
Test status
Simulation time	352511209 ps
CPU time	4.89 seconds
Started	Aug 21 07:32:49 PM UTC 24
Finished	Aug 21 07:32:55 PM UTC 24
Peak memory	215552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4 172342844 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_sa me_csr_outstanding.4172342844
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/10.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.1683960138
Short name	T405
Test name
Test status
Simulation time	1751796149 ps
CPU time	7.17 seconds
Started	Aug 21 07:32:47 PM UTC 24
Finished	Aug 21 07:32:55 PM UTC 24
Peak memory	225988 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1683960138 -assert nop ostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.1683960138
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/10.rv_dm_tl_errors/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.305054303
Short name	T408
Test name
Test status
Simulation time	117367550 ps
CPU time	2.78 seconds
Started	Aug 21 07:32:52 PM UTC 24
Finished	Aug 21 07:32:56 PM UTC 24
Peak memory	230044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns= 10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/ dv/tools/sim.tcl +ntb_random_seed=305054303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.305054303
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_rw.2230969146
Short name	T153
Test name
Test status
Simulation time	91684458 ps
CPU time	1.81 seconds
Started	Aug 21 07:32:52 PM UTC 24
Finished	Aug 21 07:32:55 PM UTC 24
Peak memory	225448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2230969146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.2230969146
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/11.rv_dm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1707191090
Short name	T424
Test name
Test status
Simulation time	6796867671 ps
CPU time	8.95 seconds
Started	Aug 21 07:32:52 PM UTC 24
Finished	Aug 21 07:33:02 PM UTC 24
Peak memory	215680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=1707191090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_bit_bash.1707191090
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2220747034
Short name	T417
Test name
Test status
Simulation time	2717107871 ps
CPU time	8.25 seconds
Started	Aug 21 07:32:50 PM UTC 24
Finished	Aug 21 07:32:59 PM UTC 24
Peak memory	215688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2220747034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.2220747034
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/11.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.4018864267
Short name	T401
Test name
Test status
Simulation time	698400808 ps
CPU time	1.27 seconds
Started	Aug 21 07:32:50 PM UTC 24
Finished	Aug 21 07:32:52 PM UTC 24
Peak memory	215336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4018864267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.4018864267
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/11.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2656483319
Short name	T416
Test name
Test status
Simulation time	637987480 ps
CPU time	5.66 seconds
Started	Aug 21 07:32:52 PM UTC 24
Finished	Aug 21 07:32:59 PM UTC 24
Peak memory	215484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2 656483319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_sa me_csr_outstanding.2656483319
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/11.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_errors.463140717
Short name	T407
Test name
Test status
Simulation time	152911417 ps
CPU time	2.72 seconds
Started	Aug 21 07:32:52 PM UTC 24
Finished	Aug 21 07:32:56 PM UTC 24
Peak memory	226084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=463140717 -assert nopo stproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.463140717
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/11.rv_dm_tl_errors/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.228492315
Short name	T461
Test name
Test status
Simulation time	1494659756 ps
CPU time	24.32 seconds
Started	Aug 21 07:32:52 PM UTC 24
Finished	Aug 21 07:33:18 PM UTC 24
Peak memory	232640 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=228492315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.228492315
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/11.rv_dm_tl_intg_err/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3603513309
Short name	T413
Test name
Test status
Simulation time	146425561 ps
CPU time	3.73 seconds
Started	Aug 21 07:32:54 PM UTC 24
Finished	Aug 21 07:32:58 PM UTC 24
Peak memory	232560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns= 10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/ dv/tools/sim.tcl +ntb_random_seed=3603513309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.3603513309
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_rw.1000566864
Short name	T410
Test name
Test status
Simulation time	378907137 ps
CPU time	2.35 seconds
Started	Aug 21 07:32:54 PM UTC 24
Finished	Aug 21 07:32:57 PM UTC 24
Peak memory	225792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1000566864 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.1000566864
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/12.rv_dm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.3196933111
Short name	T456
Test name
Test status
Simulation time	7621217617 ps
CPU time	21.82 seconds
Started	Aug 21 07:32:53 PM UTC 24
Finished	Aug 21 07:33:17 PM UTC 24
Peak memory	215360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=3196933111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_bit_bash.3196933111
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1964904352
Short name	T444
Test name
Test status
Simulation time	10612932357 ps
CPU time	16.26 seconds
Started	Aug 21 07:32:52 PM UTC 24
Finished	Aug 21 07:33:10 PM UTC 24
Peak memory	215688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1964904352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.1964904352
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/12.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.901745998
Short name	T406
Test name
Test status
Simulation time	525269448 ps
CPU time	1.77 seconds
Started	Aug 21 07:32:52 PM UTC 24
Finished	Aug 21 07:32:55 PM UTC 24
Peak memory	215328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=901745998 -assert n opostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.901745998
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/12.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.4027487964
Short name	T414
Test name
Test status
Simulation time	661560332 ps
CPU time	3.83 seconds
Started	Aug 21 07:32:54 PM UTC 24
Finished	Aug 21 07:32:59 PM UTC 24
Peak memory	215680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4 027487964 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_sa me_csr_outstanding.4027487964
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/12.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_errors.1387867902
Short name	T420
Test name
Test status
Simulation time	310461415 ps
CPU time	5.78 seconds
Started	Aug 21 07:32:54 PM UTC 24
Finished	Aug 21 07:33:00 PM UTC 24
Peak memory	225740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1387867902 -assert nop ostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.1387867902
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/12.rv_dm_tl_errors/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1981277431
Short name	T435
Test name
Test status
Simulation time	2079788803 ps
CPU time	13.84 seconds
Started	Aug 21 07:32:54 PM UTC 24
Finished	Aug 21 07:33:09 PM UTC 24
Peak memory	225908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1981277431 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.1981277431
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/12.rv_dm_tl_intg_err/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2333166130
Short name	T423
Test name
Test status
Simulation time	140085978 ps
CPU time	3.87 seconds
Started	Aug 21 07:32:57 PM UTC 24
Finished	Aug 21 07:33:02 PM UTC 24
Peak memory	232196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns= 10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/ dv/tools/sim.tcl +ntb_random_seed=2333166130 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.2333166130
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_rw.1466201876
Short name	T154
Test name
Test status
Simulation time	258917204 ps
CPU time	2.92 seconds
Started	Aug 21 07:32:56 PM UTC 24
Finished	Aug 21 07:33:00 PM UTC 24
Peak memory	229888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1466201876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.1466201876
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/13.rv_dm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2031101299
Short name	T478
Test name
Test status
Simulation time	24633960752 ps
CPU time	77.61 seconds
Started	Aug 21 07:32:56 PM UTC 24
Finished	Aug 21 07:34:15 PM UTC 24
Peak memory	215680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=2031101299 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_bit_bash.2031101299
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.309541276
Short name	T415
Test name
Test status
Simulation time	3021597383 ps
CPU time	2.87 seconds
Started	Aug 21 07:32:55 PM UTC 24
Finished	Aug 21 07:32:59 PM UTC 24
Peak memory	215540 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=309541276 -assert n opostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.309541276
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/13.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3806870965
Short name	T409
Test name
Test status
Simulation time	84993177 ps
CPU time	0.86 seconds
Started	Aug 21 07:32:55 PM UTC 24
Finished	Aug 21 07:32:57 PM UTC 24
Peak memory	215336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3806870965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.3806870965
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/13.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3159870413
Short name	T425
Test name
Test status
Simulation time	860045498 ps
CPU time	4.42 seconds
Started	Aug 21 07:32:57 PM UTC 24
Finished	Aug 21 07:33:03 PM UTC 24
Peak memory	215552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3 159870413 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_sa me_csr_outstanding.3159870413
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/13.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_errors.972328233
Short name	T418
Test name
Test status
Simulation time	269098801 ps
CPU time	2.43 seconds
Started	Aug 21 07:32:56 PM UTC 24
Finished	Aug 21 07:32:59 PM UTC 24
Peak memory	226056 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=972328233 -assert nopo stproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.972328233
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/13.rv_dm_tl_errors/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_intg_err.945713191
Short name	T206
Test name
Test status
Simulation time	1807749447 ps
CPU time	9.91 seconds
Started	Aug 21 07:32:56 PM UTC 24
Finished	Aug 21 07:33:07 PM UTC 24
Peak memory	226048 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=945713191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.945713191
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/13.rv_dm_tl_intg_err/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_rw.3410818779
Short name	T422
Test name
Test status
Simulation time	157883385 ps
CPU time	1.39 seconds
Started	Aug 21 07:33:00 PM UTC 24
Finished	Aug 21 07:33:02 PM UTC 24
Peak memory	225472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3410818779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.3410818779
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/14.rv_dm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3318794972
Short name	T473
Test name
Test status
Simulation time	14167443761 ps
CPU time	42.62 seconds
Started	Aug 21 07:32:58 PM UTC 24
Finished	Aug 21 07:33:42 PM UTC 24
Peak memory	215540 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=3318794972 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_bit_bash.3318794972
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1926366102
Short name	T428
Test name
Test status
Simulation time	3308182280 ps
CPU time	5.14 seconds
Started	Aug 21 07:32:58 PM UTC 24
Finished	Aug 21 07:33:04 PM UTC 24
Peak memory	215624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1926366102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.1926366102
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/14.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1823694620
Short name	T419
Test name
Test status
Simulation time	520635504 ps
CPU time	1.94 seconds
Started	Aug 21 07:32:57 PM UTC 24
Finished	Aug 21 07:33:00 PM UTC 24
Peak memory	215336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1823694620 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.1823694620
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/14.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.522544275
Short name	T145
Test name
Test status
Simulation time	3057100269 ps
CPU time	7.62 seconds
Started	Aug 21 07:33:00 PM UTC 24
Finished	Aug 21 07:33:08 PM UTC 24
Peak memory	215752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=5 22544275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_sam e_csr_outstanding.522544275
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/14.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_errors.2079671420
Short name	T432
Test name
Test status
Simulation time	695884806 ps
CPU time	5.68 seconds
Started	Aug 21 07:32:59 PM UTC 24
Finished	Aug 21 07:33:06 PM UTC 24
Peak memory	225928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2079671420 -assert nop ostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.2079671420
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/14.rv_dm_tl_errors/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1573978921
Short name	T439
Test name
Test status
Simulation time	83998241 ps
CPU time	4.83 seconds
Started	Aug 21 07:33:03 PM UTC 24
Finished	Aug 21 07:33:09 PM UTC 24
Peak memory	232072 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns= 10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/ dv/tools/sim.tcl +ntb_random_seed=1573978921 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.1573978921
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_rw.2553187417
Short name	T155
Test name
Test status
Simulation time	128615542 ps
CPU time	2.33 seconds
Started	Aug 21 07:33:01 PM UTC 24
Finished	Aug 21 07:33:04 PM UTC 24
Peak memory	225852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2553187417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.2553187417
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/15.rv_dm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.284789125
Short name	T426
Test name
Test status
Simulation time	111109110 ps
CPU time	1.22 seconds
Started	Aug 21 07:33:01 PM UTC 24
Finished	Aug 21 07:33:03 PM UTC 24
Peak memory	215332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=284789125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 5.rv_dm_jtag_dmi_csr_bit_bash.284789125
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.4170219763
Short name	T386
Test name
Test status
Simulation time	1752165484 ps
CPU time	5.05 seconds
Started	Aug 21 07:33:01 PM UTC 24
Finished	Aug 21 07:33:07 PM UTC 24
Peak memory	215640 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4170219763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.4170219763
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/15.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.822987631
Short name	T427
Test name
Test status
Simulation time	240404110 ps
CPU time	1.38 seconds
Started	Aug 21 07:33:01 PM UTC 24
Finished	Aug 21 07:33:03 PM UTC 24
Peak memory	215328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=822987631 -assert n opostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.822987631
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/15.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2315284879
Short name	T446
Test name
Test status
Simulation time	284946998 ps
CPU time	7.18 seconds
Started	Aug 21 07:33:02 PM UTC 24
Finished	Aug 21 07:33:10 PM UTC 24
Peak memory	215676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2 315284879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_sa me_csr_outstanding.2315284879
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/15.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_errors.4040572349
Short name	T437
Test name
Test status
Simulation time	286338984 ps
CPU time	6.83 seconds
Started	Aug 21 07:33:01 PM UTC 24
Finished	Aug 21 07:33:09 PM UTC 24
Peak memory	225912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4040572349 -assert nop ostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.4040572349
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/15.rv_dm_tl_errors/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_intg_err.834608564
Short name	T463
Test name
Test status
Simulation time	1083922808 ps
CPU time	17.56 seconds
Started	Aug 21 07:33:01 PM UTC 24
Finished	Aug 21 07:33:20 PM UTC 24
Peak memory	225952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=834608564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.834608564
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/15.rv_dm_tl_intg_err/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.662045128
Short name	T442
Test name
Test status
Simulation time	318259735 ps
CPU time	2.74 seconds
Started	Aug 21 07:33:06 PM UTC 24
Finished	Aug 21 07:33:10 PM UTC 24
Peak memory	227968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns= 10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/ dv/tools/sim.tcl +ntb_random_seed=662045128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.662045128
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_rw.3365169746
Short name	T433
Test name
Test status
Simulation time	852364019 ps
CPU time	2.63 seconds
Started	Aug 21 07:33:05 PM UTC 24
Finished	Aug 21 07:33:08 PM UTC 24
Peak memory	225724 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3365169746 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.3365169746
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/16.rv_dm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.4013837345
Short name	T469
Test name
Test status
Simulation time	5996854367 ps
CPU time	22.7 seconds
Started	Aug 21 07:33:03 PM UTC 24
Finished	Aug 21 07:33:27 PM UTC 24
Peak memory	215616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=4013837345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_bit_bash.4013837345
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.611510858
Short name	T443
Test name
Test status
Simulation time	5729034860 ps
CPU time	5.39 seconds
Started	Aug 21 07:33:03 PM UTC 24
Finished	Aug 21 07:33:10 PM UTC 24
Peak memory	215416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=611510858 -assert n opostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.611510858
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/16.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1423359858
Short name	T431
Test name
Test status
Simulation time	396710200 ps
CPU time	1.18 seconds
Started	Aug 21 07:33:03 PM UTC 24
Finished	Aug 21 07:33:05 PM UTC 24
Peak memory	215336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1423359858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.1423359858
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/16.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2709817913
Short name	T146
Test name
Test status
Simulation time	583180888 ps
CPU time	8.3 seconds
Started	Aug 21 07:33:05 PM UTC 24
Finished	Aug 21 07:33:14 PM UTC 24
Peak memory	215556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2 709817913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_sa me_csr_outstanding.2709817913
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/16.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_errors.2443605526
Short name	T440
Test name
Test status
Simulation time	252344333 ps
CPU time	3.42 seconds
Started	Aug 21 07:33:05 PM UTC 24
Finished	Aug 21 07:33:09 PM UTC 24
Peak memory	225928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2443605526 -assert nop ostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.2443605526
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/16.rv_dm_tl_errors/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3382402469
Short name	T202
Test name
Test status
Simulation time	5367547897 ps
CPU time	20.38 seconds
Started	Aug 21 07:33:05 PM UTC 24
Finished	Aug 21 07:33:26 PM UTC 24
Peak memory	225976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3382402469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.3382402469
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/16.rv_dm_tl_intg_err/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3498621552
Short name	T447
Test name
Test status
Simulation time	53688477 ps
CPU time	2.95 seconds
Started	Aug 21 07:33:07 PM UTC 24
Finished	Aug 21 07:33:11 PM UTC 24
Peak memory	230148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns= 10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/ dv/tools/sim.tcl +ntb_random_seed=3498621552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.3498621552
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_rw.843710275
Short name	T436
Test name
Test status
Simulation time	316674914 ps
CPU time	1.54 seconds
Started	Aug 21 07:33:06 PM UTC 24
Finished	Aug 21 07:33:09 PM UTC 24
Peak memory	225368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=843710275 -assert n opostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.843710275
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/17.rv_dm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3620478146
Short name	T465
Test name
Test status
Simulation time	13837938151 ps
CPU time	13.27 seconds
Started	Aug 21 07:33:06 PM UTC 24
Finished	Aug 21 07:33:20 PM UTC 24
Peak memory	215704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=3620478146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_bit_bash.3620478146
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2319963871
Short name	T474
Test name
Test status
Simulation time	13474899393 ps
CPU time	36.09 seconds
Started	Aug 21 07:33:06 PM UTC 24
Finished	Aug 21 07:33:43 PM UTC 24
Peak memory	215776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2319963871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.2319963871
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/17.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.794732801
Short name	T434
Test name
Test status
Simulation time	167368383 ps
CPU time	1.57 seconds
Started	Aug 21 07:33:06 PM UTC 24
Finished	Aug 21 07:33:08 PM UTC 24
Peak memory	215328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=794732801 -assert n opostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.794732801
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/17.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1692046054
Short name	T451
Test name
Test status
Simulation time	253250841 ps
CPU time	5.39 seconds
Started	Aug 21 07:33:06 PM UTC 24
Finished	Aug 21 07:33:13 PM UTC 24
Peak memory	215540 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1 692046054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_sa me_csr_outstanding.1692046054
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/17.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_errors.3169508792
Short name	T445
Test name
Test status
Simulation time	109646182 ps
CPU time	2.84 seconds
Started	Aug 21 07:33:06 PM UTC 24
Finished	Aug 21 07:33:10 PM UTC 24
Peak memory	225988 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3169508792 -assert nop ostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.3169508792
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/17.rv_dm_tl_errors/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2590480326
Short name	T457
Test name
Test status
Simulation time	672652272 ps
CPU time	9.39 seconds
Started	Aug 21 07:33:06 PM UTC 24
Finished	Aug 21 07:33:17 PM UTC 24
Peak memory	232716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2590480326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.2590480326
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/17.rv_dm_tl_intg_err/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.4059693009
Short name	T105
Test name
Test status
Simulation time	212413845 ps
CPU time	4.34 seconds
Started	Aug 21 07:33:10 PM UTC 24
Finished	Aug 21 07:33:15 PM UTC 24
Peak memory	232344 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns= 10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/ dv/tools/sim.tcl +ntb_random_seed=4059693009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.4059693009
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_rw.4168849757
Short name	T453
Test name
Test status
Simulation time	164694599 ps
CPU time	3.05 seconds
Started	Aug 21 07:33:10 PM UTC 24
Finished	Aug 21 07:33:14 PM UTC 24
Peak memory	226044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4168849757 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.4168849757
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/18.rv_dm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1843470297
Short name	T479
Test name
Test status
Simulation time	35954175500 ps
CPU time	101.86 seconds
Started	Aug 21 07:33:10 PM UTC 24
Finished	Aug 21 07:34:53 PM UTC 24
Peak memory	215544 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=1843470297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_bit_bash.1843470297
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2165459766
Short name	T467
Test name
Test status
Simulation time	4643840920 ps
CPU time	12.91 seconds
Started	Aug 21 07:33:08 PM UTC 24
Finished	Aug 21 07:33:22 PM UTC 24
Peak memory	215624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2165459766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.2165459766
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/18.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3056575333
Short name	T441
Test name
Test status
Simulation time	147982834 ps
CPU time	0.92 seconds
Started	Aug 21 07:33:07 PM UTC 24
Finished	Aug 21 07:33:09 PM UTC 24
Peak memory	215336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3056575333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.3056575333
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/18.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1314047970
Short name	T462
Test name
Test status
Simulation time	839841362 ps
CPU time	7.37 seconds
Started	Aug 21 07:33:10 PM UTC 24
Finished	Aug 21 07:33:18 PM UTC 24
Peak memory	215552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1 314047970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_sa me_csr_outstanding.1314047970
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/18.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_errors.1027283863
Short name	T455
Test name
Test status
Simulation time	182842412 ps
CPU time	3.92 seconds
Started	Aug 21 07:33:10 PM UTC 24
Finished	Aug 21 07:33:14 PM UTC 24
Peak memory	226140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1027283863 -assert nop ostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.1027283863
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/18.rv_dm_tl_errors/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_intg_err.241688937
Short name	T470
Test name
Test status
Simulation time	8499179648 ps
CPU time	22.32 seconds
Started	Aug 21 07:33:10 PM UTC 24
Finished	Aug 21 07:33:33 PM UTC 24
Peak memory	226076 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=241688937 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.241688937
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/18.rv_dm_tl_intg_err/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3971540114
Short name	T460
Test name
Test status
Simulation time	107964167 ps
CPU time	5.29 seconds
Started	Aug 21 07:33:11 PM UTC 24
Finished	Aug 21 07:33:18 PM UTC 24
Peak memory	232060 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns= 10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/ dv/tools/sim.tcl +ntb_random_seed=3971540114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.3971540114
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_rw.3263300858
Short name	T454
Test name
Test status
Simulation time	154794920 ps
CPU time	1.96 seconds
Started	Aug 21 07:33:11 PM UTC 24
Finished	Aug 21 07:33:14 PM UTC 24
Peak memory	225416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3263300858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.3263300858
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/19.rv_dm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.3228776867
Short name	T476
Test name
Test status
Simulation time	12417026567 ps
CPU time	39.39 seconds
Started	Aug 21 07:33:10 PM UTC 24
Finished	Aug 21 07:33:51 PM UTC 24
Peak memory	215768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=3228776867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_bit_bash.3228776867
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.87125518
Short name	T452
Test name
Test status
Simulation time	971684737 ps
CPU time	2.7 seconds
Started	Aug 21 07:33:10 PM UTC 24
Finished	Aug 21 07:33:14 PM UTC 24
Peak memory	215548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=87125518 -assert no postproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/low risc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.87125518
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/19.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3841146067
Short name	T449
Test name
Test status
Simulation time	184253536 ps
CPU time	1.19 seconds
Started	Aug 21 07:33:10 PM UTC 24
Finished	Aug 21 07:33:12 PM UTC 24
Peak memory	215336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3841146067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.3841146067
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/19.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.112802781
Short name	T466
Test name
Test status
Simulation time	892985450 ps
CPU time	8.99 seconds
Started	Aug 21 07:33:11 PM UTC 24
Finished	Aug 21 07:33:21 PM UTC 24
Peak memory	215680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1 12802781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_sam e_csr_outstanding.112802781
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/19.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_errors.2990194063
Short name	T459
Test name
Test status
Simulation time	846715292 ps
CPU time	5.07 seconds
Started	Aug 21 07:33:11 PM UTC 24
Finished	Aug 21 07:33:17 PM UTC 24
Peak memory	225908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2990194063 -assert nop ostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.2990194063
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/19.rv_dm_tl_errors/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2946935790
Short name	T429
Test name
Test status
Simulation time	1181758339 ps
CPU time	64.1 seconds
Started	Aug 21 07:31:59 PM UTC 24
Finished	Aug 21 07:33:05 PM UTC 24
Peak memory	229896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl + ntb_random_seed=2946935790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 2.rv_dm_csr_aliasing.2946935790
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/2.rv_dm_csr_aliasing/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1041643019
Short name	T379
Test name
Test status
Simulation time	22253447172 ps
CPU time	32.57 seconds
Started	Aug 21 07:32:04 PM UTC 24
Finished	Aug 21 07:32:38 PM UTC 24
Peak memory	215236 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1041643019 -a ssert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.1041643019
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/2.rv_dm_csr_bit_bash/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.65586526
Short name	T126
Test name
Test status
Simulation time	356371204 ps
CPU time	2.27 seconds
Started	Aug 21 07:32:02 PM UTC 24
Finished	Aug 21 07:32:07 PM UTC 24
Peak memory	225852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=65586526 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/low risc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.65586526
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/2.rv_dm_csr_hw_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.4211635472
Short name	T343
Test name
Test status
Simulation time	155044669 ps
CPU time	1.83 seconds
Started	Aug 21 07:32:04 PM UTC 24
Finished	Aug 21 07:32:07 PM UTC 24
Peak memory	227336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns= 10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/ dv/tools/sim.tcl +ntb_random_seed=4211635472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.4211635472
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_rw.190068369
Short name	T125
Test name
Test status
Simulation time	176431013 ps
CPU time	1.83 seconds
Started	Aug 21 07:32:02 PM UTC 24
Finished	Aug 21 07:32:07 PM UTC 24
Peak memory	225352 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=190068369 -assert n opostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.190068369
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/2.rv_dm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.4271516182
Short name	T481
Test name
Test status
Simulation time	150888255555 ps
CPU time	238.97 seconds
Started	Aug 21 07:32:02 PM UTC 24
Finished	Aug 21 07:36:06 PM UTC 24
Peak memory	215676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4271516182 -a ssert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_ csr_aliasing.4271516182
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1256241653
Short name	T448
Test name
Test status
Simulation time	28005477984 ps
CPU time	66.55 seconds
Started	Aug 21 07:32:02 PM UTC 24
Finished	Aug 21 07:33:12 PM UTC 24
Peak memory	215772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=1256241653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_bit_bash.1256241653
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3142419315
Short name	T349
Test name
Test status
Simulation time	2102827226 ps
CPU time	3.98 seconds
Started	Aug 21 07:32:02 PM UTC 24
Finished	Aug 21 07:32:08 PM UTC 24
Peak memory	215616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3142419315 -a ssert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_ csr_hw_reset.3142419315
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1765927652
Short name	T399
Test name
Test status
Simulation time	14659644638 ps
CPU time	46.32 seconds
Started	Aug 21 07:32:02 PM UTC 24
Finished	Aug 21 07:32:51 PM UTC 24
Peak memory	215640 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1765927652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1765927652
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2435561957
Short name	T337
Test name
Test status
Simulation time	1582367335 ps
CPU time	3.2 seconds
Started	Aug 21 07:31:59 PM UTC 24
Finished	Aug 21 07:32:03 PM UTC 24
Peak memory	215252 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2435561957 -a ssert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_ csr_aliasing.2435561957
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.569347234
Short name	T458
Test name
Test status
Simulation time	28249916477 ps
CPU time	76.4 seconds
Started	Aug 21 07:31:59 PM UTC 24
Finished	Aug 21 07:33:17 PM UTC 24
Peak memory	215620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=569347234 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_c sr_bit_bash.569347234
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2366659562
Short name	T335
Test name
Test status
Simulation time	1127634408 ps
CPU time	1.73 seconds
Started	Aug 21 07:31:59 PM UTC 24
Finished	Aug 21 07:32:02 PM UTC 24
Peak memory	215332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2366659562 -a ssert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_ csr_hw_reset.2366659562
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2046466080
Short name	T331
Test name
Test status
Simulation time	225862755 ps
CPU time	0.94 seconds
Started	Aug 21 07:31:59 PM UTC 24
Finished	Aug 21 07:32:01 PM UTC 24
Peak memory	215328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2046466080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.2046466080
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2647254498
Short name	T340
Test name
Test status
Simulation time	65827957 ps
CPU time	0.69 seconds
Started	Aug 21 07:32:02 PM UTC 24
Finished	Aug 21 07:32:05 PM UTC 24
Peak memory	215392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=264 7254498 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_p artial_access.2647254498
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/2.rv_dm_mem_partial_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_walk.3023002313
Short name	T341
Test name
Test status
Simulation time	71725544 ps
CPU time	0.99 seconds
Started	Aug 21 07:32:02 PM UTC 24
Finished	Aug 21 07:32:06 PM UTC 24
Peak memory	215328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3023002313 -a ssert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.3023002313
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/2.rv_dm_mem_walk/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2978076251
Short name	T131
Test name
Test status
Simulation time	170146986 ps
CPU time	7.26 seconds
Started	Aug 21 07:32:04 PM UTC 24
Finished	Aug 21 07:32:12 PM UTC 24
Peak memory	215124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2 978076251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_sam e_csr_outstanding.2978076251
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/2.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2453952009
Short name	T100
Test name
Test status
Simulation time	8664846253 ps
CPU time	116.04 seconds
Started	Aug 21 07:32:02 PM UTC 24
Finished	Aug 21 07:34:02 PM UTC 24
Peak memory	232756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm _tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/h w/dv/tools/sim.tcl +ntb_random_seed=2453952009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.2453952009
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/2.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_errors.552831364
Short name	T346
Test name
Test status
Simulation time	892242269 ps
CPU time	3.28 seconds
Started	Aug 21 07:32:02 PM UTC 24
Finished	Aug 21 07:32:08 PM UTC 24
Peak memory	225984 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=552831364 -assert nopo stproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.552831364
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/2.rv_dm_tl_errors/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2359060646
Short name	T168
Test name
Test status
Simulation time	4033252898 ps
CPU time	15.01 seconds
Started	Aug 21 07:32:02 PM UTC 24
Finished	Aug 21 07:32:20 PM UTC 24
Peak memory	232696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2359060646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.2359060646
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/2.rv_dm_tl_intg_err/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1871106244
Short name	T464
Test name
Test status
Simulation time	4141363563 ps
CPU time	73.45 seconds
Started	Aug 21 07:32:05 PM UTC 24
Finished	Aug 21 07:33:20 PM UTC 24
Peak memory	225852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl + ntb_random_seed=1871106244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 3.rv_dm_csr_aliasing.1871106244
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/3.rv_dm_csr_aliasing/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.4058327035
Short name	T412
Test name
Test status
Simulation time	5686435106 ps
CPU time	47.02 seconds
Started	Aug 21 07:32:10 PM UTC 24
Finished	Aug 21 07:32:58 PM UTC 24
Peak memory	225896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4058327035 -a ssert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.4058327035
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/3.rv_dm_csr_bit_bash/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2798910308
Short name	T138
Test name
Test status
Simulation time	1192604218 ps
CPU time	3.34 seconds
Started	Aug 21 07:32:10 PM UTC 24
Finished	Aug 21 07:32:14 PM UTC 24
Peak memory	225780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2798910308 -a ssert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.2798910308
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/3.rv_dm_csr_hw_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3255222316
Short name	T361
Test name
Test status
Simulation time	275037477 ps
CPU time	2.9 seconds
Started	Aug 21 07:32:11 PM UTC 24
Finished	Aug 21 07:32:15 PM UTC 24
Peak memory	228036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns= 10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/ dv/tools/sim.tcl +ntb_random_seed=3255222316 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.3255222316
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2072280937
Short name	T468
Test name
Test status
Simulation time	25504991659 ps
CPU time	73.63 seconds
Started	Aug 21 07:32:07 PM UTC 24
Finished	Aug 21 07:33:23 PM UTC 24
Peak memory	215352 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2072280937 -a ssert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_ csr_aliasing.2072280937
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.654056031
Short name	T368
Test name
Test status
Simulation time	4255840834 ps
CPU time	13.3 seconds
Started	Aug 21 07:32:07 PM UTC 24
Finished	Aug 21 07:32:22 PM UTC 24
Peak memory	215444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=654056031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3 .rv_dm_jtag_dmi_csr_bit_bash.654056031
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3947031687
Short name	T137
Test name
Test status
Simulation time	13786727369 ps
CPU time	46.49 seconds
Started	Aug 21 07:32:06 PM UTC 24
Finished	Aug 21 07:32:54 PM UTC 24
Peak memory	215684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3947031687 -a ssert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_ csr_hw_reset.3947031687
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3920488590
Short name	T356
Test name
Test status
Simulation time	5751401509 ps
CPU time	5.57 seconds
Started	Aug 21 07:32:07 PM UTC 24
Finished	Aug 21 07:32:14 PM UTC 24
Peak memory	215616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3920488590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.3920488590
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1406348218
Short name	T347
Test name
Test status
Simulation time	287413532 ps
CPU time	0.89 seconds
Started	Aug 21 07:32:06 PM UTC 24
Finished	Aug 21 07:32:08 PM UTC 24
Peak memory	215332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1406348218 -a ssert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_ csr_aliasing.1406348218
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1606510604
Short name	T366
Test name
Test status
Simulation time	13165371487 ps
CPU time	12.49 seconds
Started	Aug 21 07:32:06 PM UTC 24
Finished	Aug 21 07:32:20 PM UTC 24
Peak memory	215604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1606510604 -a ssert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_ csr_bit_bash.1606510604
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1284635558
Short name	T345
Test name
Test status
Simulation time	140345529 ps
CPU time	0.82 seconds
Started	Aug 21 07:32:06 PM UTC 24
Finished	Aug 21 07:32:08 PM UTC 24
Peak memory	215332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1284635558 -a ssert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_ csr_hw_reset.1284635558
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.236638021
Short name	T348
Test name
Test status
Simulation time	212334862 ps
CPU time	1.18 seconds
Started	Aug 21 07:32:06 PM UTC 24
Finished	Aug 21 07:32:08 PM UTC 24
Peak memory	215328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=236638021 -assert n opostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.236638021
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_partial_access.594860943
Short name	T353
Test name
Test status
Simulation time	43744043 ps
CPU time	0.84 seconds
Started	Aug 21 07:32:09 PM UTC 24
Finished	Aug 21 07:32:10 PM UTC 24
Peak memory	215392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=594 860943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_pa rtial_access.594860943
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/3.rv_dm_mem_partial_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_walk.242631607
Short name	T352
Test name
Test status
Simulation time	28121051 ps
CPU time	0.73 seconds
Started	Aug 21 07:32:09 PM UTC 24
Finished	Aug 21 07:32:10 PM UTC 24
Peak memory	215332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=242631607 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.242631607
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/3.rv_dm_mem_walk/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3466451565
Short name	T156
Test name
Test status
Simulation time	1081133310 ps
CPU time	8.2 seconds
Started	Aug 21 07:32:10 PM UTC 24
Finished	Aug 21 07:32:19 PM UTC 24
Peak memory	215548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3 466451565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_sam e_csr_outstanding.3466451565
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/3.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.1404287857
Short name	T103
Test name
Test status
Simulation time	3800545012 ps
CPU time	53.98 seconds
Started	Aug 21 07:32:08 PM UTC 24
Finished	Aug 21 07:33:04 PM UTC 24
Peak memory	230300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm _tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/h w/dv/tools/sim.tcl +ntb_random_seed=1404287857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.1404287857
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/3.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_errors.2676209934
Short name	T358
Test name
Test status
Simulation time	351180069 ps
CPU time	4.57 seconds
Started	Aug 21 07:32:08 PM UTC 24
Finished	Aug 21 07:32:14 PM UTC 24
Peak memory	225984 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2676209934 -assert nop ostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.2676209934
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/3.rv_dm_tl_errors/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1471585350
Short name	T197
Test name
Test status
Simulation time	4114787970 ps
CPU time	33.48 seconds
Started	Aug 21 07:32:09 PM UTC 24
Finished	Aug 21 07:32:43 PM UTC 24
Peak memory	225980 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1471585350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.1471585350
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/3.rv_dm_tl_intg_err/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_aliasing.763567132
Short name	T382
Test name
Test status
Simulation time	625313636 ps
CPU time	28.06 seconds
Started	Aug 21 07:32:11 PM UTC 24
Finished	Aug 21 07:32:40 PM UTC 24
Peak memory	225752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl + ntb_random_seed=763567132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 4.rv_dm_csr_aliasing.763567132
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/4.rv_dm_csr_aliasing/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.321958934
Short name	T438
Test name
Test status
Simulation time	17513623824 ps
CPU time	50.46 seconds
Started	Aug 21 07:32:17 PM UTC 24
Finished	Aug 21 07:33:09 PM UTC 24
Peak memory	215660 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=321958934 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.321958934
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/4.rv_dm_csr_bit_bash/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3111230060
Short name	T141
Test name
Test status
Simulation time	239951398 ps
CPU time	3.05 seconds
Started	Aug 21 07:32:16 PM UTC 24
Finished	Aug 21 07:32:20 PM UTC 24
Peak memory	225808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3111230060 -a ssert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.3111230060
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/4.rv_dm_csr_hw_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.840271928
Short name	T344
Test name
Test status
Simulation time	189210189 ps
CPU time	4.77 seconds
Started	Aug 21 07:32:18 PM UTC 24
Finished	Aug 21 07:32:24 PM UTC 24
Peak memory	230168 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns= 10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/ dv/tools/sim.tcl +ntb_random_seed=840271928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.840271928
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_rw.1138170702
Short name	T139
Test name
Test status
Simulation time	265309686 ps
CPU time	2.43 seconds
Started	Aug 21 07:32:16 PM UTC 24
Finished	Aug 21 07:32:19 PM UTC 24
Peak memory	229976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1138170702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.1138170702
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/4.rv_dm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3470396320
Short name	T480
Test name
Test status
Simulation time	79169278329 ps
CPU time	192.51 seconds
Started	Aug 21 07:32:13 PM UTC 24
Finished	Aug 21 07:35:29 PM UTC 24
Peak memory	215604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3470396320 -a ssert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_ csr_aliasing.3470396320
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.1121257279
Short name	T372
Test name
Test status
Simulation time	11908959757 ps
CPU time	15.62 seconds
Started	Aug 21 07:32:13 PM UTC 24
Finished	Aug 21 07:32:30 PM UTC 24
Peak memory	215544 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=1121257279 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_bit_bash.1121257279
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1644717322
Short name	T135
Test name
Test status
Simulation time	2007929086 ps
CPU time	3.54 seconds
Started	Aug 21 07:32:12 PM UTC 24
Finished	Aug 21 07:32:17 PM UTC 24
Peak memory	215548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1644717322 -a ssert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_ csr_hw_reset.1644717322
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1348800325
Short name	T369
Test name
Test status
Simulation time	6488269511 ps
CPU time	7.5 seconds
Started	Aug 21 07:32:13 PM UTC 24
Finished	Aug 21 07:32:22 PM UTC 24
Peak memory	215572 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1348800325 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.1348800325
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2661947782
Short name	T360
Test name
Test status
Simulation time	167053398 ps
CPU time	1.34 seconds
Started	Aug 21 07:32:12 PM UTC 24
Finished	Aug 21 07:32:14 PM UTC 24
Peak memory	215332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2661947782 -a ssert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_ csr_aliasing.2661947782
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2214024748
Short name	T391
Test name
Test status
Simulation time	21110410667 ps
CPU time	32.42 seconds
Started	Aug 21 07:32:11 PM UTC 24
Finished	Aug 21 07:32:45 PM UTC 24
Peak memory	215704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2214024748 -a ssert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_ csr_bit_bash.2214024748
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.64139769
Short name	T355
Test name
Test status
Simulation time	152156100 ps
CPU time	1.03 seconds
Started	Aug 21 07:32:11 PM UTC 24
Finished	Aug 21 07:32:13 PM UTC 24
Peak memory	215324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=64139769 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_hw_reset.64139769
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3608257055
Short name	T359
Test name
Test status
Simulation time	346973683 ps
CPU time	2.2 seconds
Started	Aug 21 07:32:11 PM UTC 24
Finished	Aug 21 07:32:14 PM UTC 24
Peak memory	215400 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3608257055 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.3608257055
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_partial_access.296737862
Short name	T364
Test name
Test status
Simulation time	118110684 ps
CPU time	1.68 seconds
Started	Aug 21 07:32:16 PM UTC 24
Finished	Aug 21 07:32:18 PM UTC 24
Peak memory	215392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=296 737862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_pa rtial_access.296737862
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/4.rv_dm_mem_partial_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_walk.3962766768
Short name	T362
Test name
Test status
Simulation time	38066739 ps
CPU time	0.96 seconds
Started	Aug 21 07:32:15 PM UTC 24
Finished	Aug 21 07:32:17 PM UTC 24
Peak memory	215328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3962766768 -a ssert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.3962766768
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/4.rv_dm_mem_walk/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1306416004
Short name	T142
Test name
Test status
Simulation time	1512741216 ps
CPU time	6.99 seconds
Started	Aug 21 07:32:18 PM UTC 24
Finished	Aug 21 07:32:26 PM UTC 24
Peak memory	215520 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1 306416004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_sam e_csr_outstanding.1306416004
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/4.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.249423897
Short name	T102
Test name
Test status
Simulation time	4315835089 ps
CPU time	36.26 seconds
Started	Aug 21 07:32:14 PM UTC 24
Finished	Aug 21 07:32:53 PM UTC 24
Peak memory	230100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm _tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/h w/dv/tools/sim.tcl +ntb_random_seed=249423897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.249423897
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/4.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_errors.2709155668
Short name	T365
Test name
Test status
Simulation time	149454723 ps
CPU time	3.49 seconds
Started	Aug 21 07:32:14 PM UTC 24
Finished	Aug 21 07:32:19 PM UTC 24
Peak memory	225988 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2709155668 -assert nop ostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2709155668
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/4.rv_dm_tl_errors/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3583966772
Short name	T201
Test name
Test status
Simulation time	4744246809 ps
CPU time	27.31 seconds
Started	Aug 21 07:32:14 PM UTC 24
Finished	Aug 21 07:32:44 PM UTC 24
Peak memory	232612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3583966772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.3583966772
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/4.rv_dm_tl_intg_err/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2060426249
Short name	T370
Test name
Test status
Simulation time	97666035 ps
CPU time	2.64 seconds
Started	Aug 21 07:32:22 PM UTC 24
Finished	Aug 21 07:32:26 PM UTC 24
Peak memory	227928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns= 10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/ dv/tools/sim.tcl +ntb_random_seed=2060426249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.2060426249
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_rw.1446113704
Short name	T140
Test name
Test status
Simulation time	1105062269 ps
CPU time	2.17 seconds
Started	Aug 21 07:32:22 PM UTC 24
Finished	Aug 21 07:32:25 PM UTC 24
Peak memory	225916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1446113704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.1446113704
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/5.rv_dm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.675849551
Short name	T373
Test name
Test status
Simulation time	7427609327 ps
CPU time	8.27 seconds
Started	Aug 21 07:32:21 PM UTC 24
Finished	Aug 21 07:32:30 PM UTC 24
Peak memory	215620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=675849551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5 .rv_dm_jtag_dmi_csr_bit_bash.675849551
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.464554990
Short name	T383
Test name
Test status
Simulation time	6454114221 ps
CPU time	18.27 seconds
Started	Aug 21 07:32:21 PM UTC 24
Finished	Aug 21 07:32:40 PM UTC 24
Peak memory	215712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=464554990 -assert n opostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.464554990
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/5.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1198916956
Short name	T367
Test name
Test status
Simulation time	247908190 ps
CPU time	1.27 seconds
Started	Aug 21 07:32:18 PM UTC 24
Finished	Aug 21 07:32:20 PM UTC 24
Peak memory	215328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1198916956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.1198916956
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/5.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_errors.1870024348
Short name	T374
Test name
Test status
Simulation time	366256510 ps
CPU time	8.24 seconds
Started	Aug 21 07:32:22 PM UTC 24
Finished	Aug 21 07:32:32 PM UTC 24
Peak memory	225988 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1870024348 -assert nop ostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.1870024348
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/5.rv_dm_tl_errors/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3148294814
Short name	T200
Test name
Test status
Simulation time	10255096772 ps
CPU time	19.51 seconds
Started	Aug 21 07:32:22 PM UTC 24
Finished	Aug 21 07:32:43 PM UTC 24
Peak memory	232672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3148294814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.3148294814
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/5.rv_dm_tl_intg_err/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2048168745
Short name	T107
Test name
Test status
Simulation time	80147361 ps
CPU time	4.72 seconds
Started	Aug 21 07:32:29 PM UTC 24
Finished	Aug 21 07:32:34 PM UTC 24
Peak memory	232060 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns= 10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/ dv/tools/sim.tcl +ntb_random_seed=2048168745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.2048168745
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_rw.1930197247
Short name	T147
Test name
Test status
Simulation time	65054351 ps
CPU time	2.15 seconds
Started	Aug 21 07:32:27 PM UTC 24
Finished	Aug 21 07:32:30 PM UTC 24
Peak memory	225944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1930197247 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.1930197247
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/6.rv_dm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3654021843
Short name	T394
Test name
Test status
Simulation time	7364456395 ps
CPU time	23 seconds
Started	Aug 21 07:32:24 PM UTC 24
Finished	Aug 21 07:32:49 PM UTC 24
Peak memory	215640 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=3654021843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_bit_bash.3654021843
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2671150023
Short name	T376
Test name
Test status
Simulation time	4964932968 ps
CPU time	8.88 seconds
Started	Aug 21 07:32:24 PM UTC 24
Finished	Aug 21 07:32:34 PM UTC 24
Peak memory	215616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2671150023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.2671150023
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/6.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3410862509
Short name	T371
Test name
Test status
Simulation time	594235267 ps
CPU time	1.31 seconds
Started	Aug 21 07:32:24 PM UTC 24
Finished	Aug 21 07:32:27 PM UTC 24
Peak memory	215328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3410862509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.3410862509
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/6.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1624410667
Short name	T157
Test name
Test status
Simulation time	617230231 ps
CPU time	6.95 seconds
Started	Aug 21 07:32:29 PM UTC 24
Finished	Aug 21 07:32:37 PM UTC 24
Peak memory	215572 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1 624410667 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_sam e_csr_outstanding.1624410667
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/6.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_errors.4162577063
Short name	T375
Test name
Test status
Simulation time	224351574 ps
CPU time	6.26 seconds
Started	Aug 21 07:32:26 PM UTC 24
Finished	Aug 21 07:32:34 PM UTC 24
Peak memory	226016 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4162577063 -assert nop ostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.4162577063
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/6.rv_dm_tl_errors/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_intg_err.38952124
Short name	T198
Test name
Test status
Simulation time	2707136319 ps
CPU time	23.05 seconds
Started	Aug 21 07:32:26 PM UTC 24
Finished	Aug 21 07:32:51 PM UTC 24
Peak memory	225980 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=38952124 - assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.38952124
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/6.rv_dm_tl_intg_err/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1332873488
Short name	T384
Test name
Test status
Simulation time	146490745 ps
CPU time	3.9 seconds
Started	Aug 21 07:32:35 PM UTC 24
Finished	Aug 21 07:32:40 PM UTC 24
Peak memory	232244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns= 10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/ dv/tools/sim.tcl +ntb_random_seed=1332873488 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.1332873488
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_rw.2006645496
Short name	T150
Test name
Test status
Simulation time	109991900 ps
CPU time	2.57 seconds
Started	Aug 21 07:32:35 PM UTC 24
Finished	Aug 21 07:32:39 PM UTC 24
Peak memory	225792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2006645496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.2006645496
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/7.rv_dm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.145376293
Short name	T388
Test name
Test status
Simulation time	6816873431 ps
CPU time	12.26 seconds
Started	Aug 21 07:32:31 PM UTC 24
Finished	Aug 21 07:32:44 PM UTC 24
Peak memory	215772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=145376293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7 .rv_dm_jtag_dmi_csr_bit_bash.145376293
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2248296980
Short name	T377
Test name
Test status
Simulation time	4896354606 ps
CPU time	3.81 seconds
Started	Aug 21 07:32:31 PM UTC 24
Finished	Aug 21 07:32:36 PM UTC 24
Peak memory	215768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2248296980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.2248296980
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/7.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1796907656
Short name	T378
Test name
Test status
Simulation time	547541375 ps
CPU time	4.14 seconds
Started	Aug 21 07:32:31 PM UTC 24
Finished	Aug 21 07:32:36 PM UTC 24
Peak memory	215400 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1796907656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1796907656
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/7.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.652311769
Short name	T144
Test name
Test status
Simulation time	243719509 ps
CPU time	5.49 seconds
Started	Aug 21 07:32:35 PM UTC 24
Finished	Aug 21 07:32:42 PM UTC 24
Peak memory	215676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=6 52311769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same _csr_outstanding.652311769
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/7.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.2801921275
Short name	T472
Test name
Test status
Simulation time	16165771630 ps
CPU time	65.99 seconds
Started	Aug 21 07:32:33 PM UTC 24
Finished	Aug 21 07:33:41 PM UTC 24
Peak memory	232844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm _tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/h w/dv/tools/sim.tcl +ntb_random_seed=2801921275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.2801921275
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/7.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_errors.891035384
Short name	T380
Test name
Test status
Simulation time	350771410 ps
CPU time	3.35 seconds
Started	Aug 21 07:32:35 PM UTC 24
Finished	Aug 21 07:32:40 PM UTC 24
Peak memory	226112 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=891035384 -assert nopo stproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.891035384
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/7.rv_dm_tl_errors/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2987534106
Short name	T411
Test name
Test status
Simulation time	2085051621 ps
CPU time	21.5 seconds
Started	Aug 21 07:32:35 PM UTC 24
Finished	Aug 21 07:32:58 PM UTC 24
Peak memory	225524 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2987534106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2987534106
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/7.rv_dm_tl_intg_err/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.952530126
Short name	T393
Test name
Test status
Simulation time	173672208 ps
CPU time	3.87 seconds
Started	Aug 21 07:32:42 PM UTC 24
Finished	Aug 21 07:32:47 PM UTC 24
Peak memory	225980 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns= 10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/ dv/tools/sim.tcl +ntb_random_seed=952530126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.952530126
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_rw.1241949169
Short name	T392
Test name
Test status
Simulation time	350413538 ps
CPU time	2.52 seconds
Started	Aug 21 07:32:42 PM UTC 24
Finished	Aug 21 07:32:45 PM UTC 24
Peak memory	225880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1241949169 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.1241949169
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/8.rv_dm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1891653925
Short name	T430
Test name
Test status
Simulation time	7176708305 ps
CPU time	26.22 seconds
Started	Aug 21 07:32:37 PM UTC 24
Finished	Aug 21 07:33:05 PM UTC 24
Peak memory	215544 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=1891653925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_bit_bash.1891653925
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.710819215
Short name	T390
Test name
Test status
Simulation time	6053276274 ps
CPU time	6 seconds
Started	Aug 21 07:32:37 PM UTC 24
Finished	Aug 21 07:32:44 PM UTC 24
Peak memory	215548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=710819215 -assert n opostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.710819215
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/8.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1617621454
Short name	T381
Test name
Test status
Simulation time	292530390 ps
CPU time	1.24 seconds
Started	Aug 21 07:32:37 PM UTC 24
Finished	Aug 21 07:32:40 PM UTC 24
Peak memory	215328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1617621454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.1617621454
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/8.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.659882139
Short name	T158
Test name
Test status
Simulation time	1595996600 ps
CPU time	6.82 seconds
Started	Aug 21 07:32:42 PM UTC 24
Finished	Aug 21 07:32:50 PM UTC 24
Peak memory	215704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=6 59882139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same _csr_outstanding.659882139
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/8.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_errors.2302603506
Short name	T387
Test name
Test status
Simulation time	171025901 ps
CPU time	3.44 seconds
Started	Aug 21 07:32:40 PM UTC 24
Finished	Aug 21 07:32:44 PM UTC 24
Peak memory	225928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2302603506 -assert nop ostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.2302603506
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/8.rv_dm_tl_errors/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_intg_err.72861165
Short name	T396
Test name
Test status
Simulation time	530714889 ps
CPU time	8.6 seconds
Started	Aug 21 07:32:40 PM UTC 24
Finished	Aug 21 07:32:49 PM UTC 24
Peak memory	225924 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=72861165 - assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.72861165
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/8.rv_dm_tl_intg_err/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2253253133
Short name	T110
Test name
Test status
Simulation time	82350464 ps
CPU time	3.83 seconds
Started	Aug 21 07:32:46 PM UTC 24
Finished	Aug 21 07:32:51 PM UTC 24
Peak memory	232424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns= 10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/ dv/tools/sim.tcl +ntb_random_seed=2253253133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.2253253133
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_rw.3911008265
Short name	T151
Test name
Test status
Simulation time	153648142 ps
CPU time	1.86 seconds
Started	Aug 21 07:32:44 PM UTC 24
Finished	Aug 21 07:32:47 PM UTC 24
Peak memory	225408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3911008265 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.3911008265
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/9.rv_dm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.1186231813
Short name	T475
Test name
Test status
Simulation time	23888119868 ps
CPU time	61.81 seconds
Started	Aug 21 07:32:44 PM UTC 24
Finished	Aug 21 07:33:47 PM UTC 24
Peak memory	215616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_s eed=1186231813 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_bit_bash.1186231813
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1371719183
Short name	T398
Test name
Test status
Simulation time	1862794468 ps
CPU time	7.64 seconds
Started	Aug 21 07:32:42 PM UTC 24
Finished	Aug 21 07:32:51 PM UTC 24
Peak memory	215680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1371719183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.1371719183
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/9.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.4173085406
Short name	T389
Test name
Test status
Simulation time	490263862 ps
CPU time	1.64 seconds
Started	Aug 21 07:32:42 PM UTC 24
Finished	Aug 21 07:32:44 PM UTC 24
Peak memory	215328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4173085406 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.4173085406
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/9.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1005169472
Short name	T159
Test name
Test status
Simulation time	582665738 ps
CPU time	6.72 seconds
Started	Aug 21 07:32:46 PM UTC 24
Finished	Aug 21 07:32:54 PM UTC 24
Peak memory	215484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1 005169472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_sam e_csr_outstanding.1005169472
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/9.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.831676384
Short name	T471
Test name
Test status
Simulation time	6851555560 ps
CPU time	52.43 seconds
Started	Aug 21 07:32:44 PM UTC 24
Finished	Aug 21 07:33:38 PM UTC 24
Peak memory	230148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm _tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/h w/dv/tools/sim.tcl +ntb_random_seed=831676384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.831676384
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/9.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_errors.4124934557
Short name	T395
Test name
Test status
Simulation time	210761922 ps
CPU time	4.03 seconds
Started	Aug 21 07:32:44 PM UTC 24
Finished	Aug 21 07:32:49 PM UTC 24
Peak memory	225988 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4124934557 -assert nop ostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.4124934557
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/9.rv_dm_tl_errors/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1468541338
Short name	T199
Test name
Test status
Simulation time	3275189091 ps
CPU time	14.93 seconds
Started	Aug 21 07:32:44 PM UTC 24
Finished	Aug 21 07:33:00 PM UTC 24
Peak memory	225980 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1468541338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.1468541338
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/9.rv_dm_tl_intg_err/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.26219662
Short name	T62
Test name
Test status
Simulation time	299532063 ps
CPU time	1.15 seconds
Started	Aug 21 07:33:18 PM UTC 24
Finished	Aug 21 07:33:21 PM UTC 24
Peak memory	213472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=26219662 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.26219662
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_abstractcmd_status/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.790752065
Short name	T21
Test name
Test status
Simulation time	17308241663 ps
CPU time	15.1 seconds
Started	Aug 21 07:33:14 PM UTC 24
Finished	Aug 21 07:33:30 PM UTC 24
Peak memory	226516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=790752065 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.790752065
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_busy.3328770400
Short name	T13
Test name
Test status
Simulation time	463457993 ps
CPU time	3.09 seconds
Started	Aug 21 07:33:15 PM UTC 24
Finished	Aug 21 07:33:19 PM UTC 24
Peak memory	215816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3328770400 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.3328770400
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_cmderr_busy/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.2284792907
Short name	T2
Test name
Test status
Simulation time	392539614 ps
CPU time	1.65 seconds
Started	Aug 21 07:33:15 PM UTC 24
Finished	Aug 21 07:33:17 PM UTC 24
Peak memory	213468 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2284792907 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.2284792907
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_cmderr_not_supported/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/0.rv_dm_debug_disabled.3151626452
Short name	T83
Test name
Test status
Simulation time	51805081 ps
CPU time	1.06 seconds
Started	Aug 21 07:33:20 PM UTC 24
Finished	Aug 21 07:33:22 PM UTC 24
Peak memory	236056 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3151626452 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.3151626452
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_debug_disabled/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.173264497
Short name	T78
Test name
Test status
Simulation time	5686564855 ps
CPU time	9.61 seconds
Started	Aug 21 07:33:13 PM UTC 24
Finished	Aug 21 07:33:24 PM UTC 24
Peak memory	216276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=173264497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_ tl_access.173264497
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.1334686894
Short name	T44
Test name
Test status
Simulation time	909511605 ps
CPU time	2.05 seconds
Started	Aug 21 07:33:17 PM UTC 24
Finished	Aug 21 07:33:20 PM UTC 24
Peak memory	215944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1334686894 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.1334686894
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_halt_resume_whereto/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/0.rv_dm_hart_unavail.574048951
Short name	T4
Test name
Test status
Simulation time	326349186 ps
CPU time	2.25 seconds
Started	Aug 21 07:33:15 PM UTC 24
Finished	Aug 21 07:33:18 PM UTC 24
Peak memory	215884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=574048951 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.574048951
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_hart_unavail/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/0.rv_dm_hartsel_warl.2635082218
Short name	T27
Test name
Test status
Simulation time	268114093 ps
CPU time	1.47 seconds
Started	Aug 21 07:33:20 PM UTC 24
Finished	Aug 21 07:33:22 PM UTC 24
Peak memory	213468 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2635082218 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch /earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.2635082218
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_hartsel_warl/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.869668714
Short name	T7
Test name
Test status
Simulation time	232324496 ps
CPU time	1.2 seconds
Started	Aug 21 07:33:18 PM UTC 24
Finished	Aug 21 07:33:21 PM UTC 24
Peak memory	213468 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=869668714 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit an/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.869668714
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.147290335
Short name	T93
Test name
Test status
Simulation time	1495848203 ps
CPU time	4.31 seconds
Started	Aug 21 07:33:18 PM UTC 24
Finished	Aug 21 07:33:24 PM UTC 24
Peak memory	215752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=147290335 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.147290335
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_hard_reset.1102643586
Short name	T8
Test name
Test status
Simulation time	317740402 ps
CPU time	1.71 seconds
Started	Aug 21 07:33:18 PM UTC 24
Finished	Aug 21 07:33:21 PM UTC 24
Peak memory	213464 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1102643586 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.1102643586
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_hard_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_idle_hint.525130553
Short name	T36
Test name
Test status
Simulation time	419297865 ps
CPU time	1.38 seconds
Started	Aug 21 07:33:18 PM UTC 24
Finished	Aug 21 07:33:21 PM UTC 24
Peak memory	215952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=525130553 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc ratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.525130553
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_idle_hint/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_halted.3847562584
Short name	T45
Test name
Test status
Simulation time	516522920 ps
CPU time	2.68 seconds
Started	Aug 21 07:33:15 PM UTC 24
Finished	Aug 21 07:33:18 PM UTC 24
Peak memory	215812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3847562584 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.3847562584
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_halted/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_resuming.3524115364
Short name	T12
Test name
Test status
Simulation time	306008496 ps
CPU time	2.21 seconds
Started	Aug 21 07:33:15 PM UTC 24
Finished	Aug 21 07:33:18 PM UTC 24
Peak memory	215892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3524115364 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit an/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.3524115364
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_resuming/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.438750314
Short name	T14
Test name
Test status
Simulation time	222573393 ps
CPU time	1.18 seconds
Started	Aug 21 07:33:18 PM UTC 24
Finished	Aug 21 07:33:20 PM UTC 24
Peak memory	225868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=438750314 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.438750314
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_ndmreset_req/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.2323994675
Short name	T59
Test name
Test status
Simulation time	193069178 ps
CPU time	0.86 seconds
Started	Aug 21 07:33:20 PM UTC 24
Finished	Aug 21 07:33:21 PM UTC 24
Peak memory	215948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2323994675 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.2323994675
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_progbuf_read_write_execute/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.936132625
Short name	T47
Test name
Test status
Simulation time	449568396 ps
CPU time	1.36 seconds
Started	Aug 21 07:33:21 PM UTC 24
Finished	Aug 21 07:33:23 PM UTC 24
Peak memory	251292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=936132625 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.936132625
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_sec_cm/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.3306317448
Short name	T82
Test name
Test status
Simulation time	8983814179 ps
CPU time	10.27 seconds
Started	Aug 21 07:33:12 PM UTC 24
Finished	Aug 21 07:33:24 PM UTC 24
Peak memory	216152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3306317448 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.3306317448
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/1.rv_dm_abstractcmd_status.3726378934
Short name	T63
Test name
Test status
Simulation time	422528017 ps
CPU time	1.26 seconds
Started	Aug 21 07:33:25 PM UTC 24
Finished	Aug 21 07:33:27 PM UTC 24
Peak memory	215952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3726378934 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.3726378934
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_abstractcmd_status/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/1.rv_dm_alert_test.815703620
Short name	T49
Test name
Test status
Simulation time	99209301 ps
CPU time	1.05 seconds
Started	Aug 21 07:33:27 PM UTC 24
Finished	Aug 21 07:33:29 PM UTC 24
Peak memory	215892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=815703620 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.815703620
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/1.rv_dm_autoincr_sba_tl_access.2355429329
Short name	T22
Test name
Test status
Simulation time	5066323325 ps
CPU time	7.82 seconds
Started	Aug 21 07:33:22 PM UTC 24
Finished	Aug 21 07:33:31 PM UTC 24
Peak memory	226580 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2355429329 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit an/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.2355429329
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/1.rv_dm_buffered_enable.1062613883
Short name	T80
Test name
Test status
Simulation time	642684928 ps
CPU time	2.97 seconds
Started	Aug 21 07:33:25 PM UTC 24
Finished	Aug 21 07:33:29 PM UTC 24
Peak memory	258744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1062613883 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra tch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_buffered_enable.1062613883
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_buffered_enable/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_busy.989116489
Short name	T9
Test name
Test status
Simulation time	1319500645 ps
CPU time	2.04 seconds
Started	Aug 21 07:33:22 PM UTC 24
Finished	Aug 21 07:33:25 PM UTC 24
Peak memory	216012 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=989116489 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.989116489
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_cmderr_busy/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.3728453125
Short name	T28
Test name
Test status
Simulation time	182282007 ps
CPU time	1.48 seconds
Started	Aug 21 07:33:22 PM UTC 24
Finished	Aug 21 07:33:25 PM UTC 24
Peak memory	215952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3728453125 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.3728453125
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_cmderr_exception/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.2402634372
Short name	T67
Test name
Test status
Simulation time	1190138051 ps
CPU time	3.93 seconds
Started	Aug 21 07:33:22 PM UTC 24
Finished	Aug 21 07:33:27 PM UTC 24
Peak memory	215820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2402634372 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.2402634372
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_cmderr_halt_resume/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_not_supported.4189677478
Short name	T52
Test name
Test status
Simulation time	407339609 ps
CPU time	1.01 seconds
Started	Aug 21 07:33:22 PM UTC 24
Finished	Aug 21 07:33:24 PM UTC 24
Peak memory	213944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4189677478 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.4189677478
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_cmderr_not_supported/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/1.rv_dm_debug_disabled.3792655568
Short name	T86
Test name
Test status
Simulation time	176848749 ps
CPU time	1.29 seconds
Started	Aug 21 07:33:25 PM UTC 24
Finished	Aug 21 07:33:28 PM UTC 24
Peak memory	234012 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3792655568 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.3792655568
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_debug_disabled/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.1914699084
Short name	T172
Test name
Test status
Simulation time	11530292442 ps
CPU time	17.25 seconds
Started	Aug 21 07:33:22 PM UTC 24
Finished	Aug 21 07:33:40 PM UTC 24
Peak memory	226436 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1914699084 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba _tl_access.1914699084
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.386281016
Short name	T74
Test name
Test status
Simulation time	234669061 ps
CPU time	1.11 seconds
Started	Aug 21 07:33:25 PM UTC 24
Finished	Aug 21 07:33:27 PM UTC 24
Peak memory	213464 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=386281016 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch /earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.386281016
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_dmi_failed_op/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/1.rv_dm_halt_resume_whereto.3816916988
Short name	T53
Test name
Test status
Simulation time	258584345 ps
CPU time	1.09 seconds
Started	Aug 21 07:33:24 PM UTC 24
Finished	Aug 21 07:33:26 PM UTC 24
Peak memory	213092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3816916988 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.3816916988
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_halt_resume_whereto/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/1.rv_dm_hart_unavail.2503893437
Short name	T94
Test name
Test status
Simulation time	255818890 ps
CPU time	1.44 seconds
Started	Aug 21 07:33:22 PM UTC 24
Finished	Aug 21 07:33:25 PM UTC 24
Peak memory	213468 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2503893437 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch /earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.2503893437
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_hart_unavail/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.2997579573
Short name	T87
Test name
Test status
Simulation time	674263772 ps
CPU time	2.89 seconds
Started	Aug 21 07:33:24 PM UTC 24
Finished	Aug 21 07:33:28 PM UTC 24
Peak memory	215820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2997579573 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.2997579573
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.2738712228
Short name	T233
Test name
Test status
Simulation time	349289058 ps
CPU time	1.27 seconds
Started	Aug 21 07:33:24 PM UTC 24
Finished	Aug 21 07:33:26 PM UTC 24
Peak memory	213408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2738712228 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.2738712228
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3772826827
Short name	T75
Test name
Test status
Simulation time	743478961 ps
CPU time	2.22 seconds
Started	Aug 21 07:33:25 PM UTC 24
Finished	Aug 21 07:33:28 PM UTC 24
Peak memory	215816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3772826827 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.3772826827
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_hard_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_idle_hint.3952574340
Short name	T76
Test name
Test status
Simulation time	159867857 ps
CPU time	1 seconds
Started	Aug 21 07:33:24 PM UTC 24
Finished	Aug 21 07:33:26 PM UTC 24
Peak memory	215952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3952574340 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.3952574340
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_idle_hint/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_halted.2581790052
Short name	T90
Test name
Test status
Simulation time	574226390 ps
CPU time	1.4 seconds
Started	Aug 21 07:33:22 PM UTC 24
Finished	Aug 21 07:33:25 PM UTC 24
Peak memory	213752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2581790052 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan /scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.2581790052
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_mem_tl_access_halted/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_resuming.2147941394
Short name	T122
Test name
Test status
Simulation time	159493783 ps
CPU time	1.52 seconds
Started	Aug 21 07:33:22 PM UTC 24
Finished	Aug 21 07:33:25 PM UTC 24
Peak memory	213472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2147941394 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit an/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.2147941394
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_mem_tl_access_resuming/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/1.rv_dm_ndmreset_req.1703607535
Short name	T41
Test name
Test status
Simulation time	219888459 ps
CPU time	1.29 seconds
Started	Aug 21 07:33:24 PM UTC 24
Finished	Aug 21 07:33:26 PM UTC 24
Peak memory	225888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1703607535 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch /earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.1703607535
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_ndmreset_req/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/1.rv_dm_progbuf_read_write_execute.3383793242
Short name	T60
Test name
Test status
Simulation time	207509495 ps
CPU time	1.16 seconds
Started	Aug 21 07:33:25 PM UTC 24
Finished	Aug 21 07:33:27 PM UTC 24
Peak memory	215948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3383793242 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.3383793242
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_progbuf_read_write_execute/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/1.rv_dm_rom_read_access.893516943
Short name	T65
Test name
Test status
Simulation time	37259847 ps
CPU time	1.3 seconds
Started	Aug 21 07:33:25 PM UTC 24
Finished	Aug 21 07:33:27 PM UTC 24
Peak memory	225868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=893516943 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.893516943
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_rom_read_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_debug_disabled.2980232137
Short name	T171
Test name
Test status
Simulation time	1516535605 ps
CPU time	6.42 seconds
Started	Aug 21 07:33:24 PM UTC 24
Finished	Aug 21 07:33:31 PM UTC 24
Peak memory	216016 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2980232137 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.2980232137
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_sba_debug_disabled/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_tl_access.324239927
Short name	T39
Test name
Test status
Simulation time	996498672 ps
CPU time	1.35 seconds
Started	Aug 21 07:33:21 PM UTC 24
Finished	Aug 21 07:33:23 PM UTC 24
Peak memory	215444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=324239927 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch /earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.324239927
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/1.rv_dm_smoke.4053533666
Short name	T211
Test name
Test status
Simulation time	1092427605 ps
CPU time	4.07 seconds
Started	Aug 21 07:33:21 PM UTC 24
Finished	Aug 21 07:33:26 PM UTC 24
Peak memory	215884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4053533666 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.4053533666
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_smoke/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.2784325043
Short name	T51
Test name
Test status
Simulation time	159527519 ps
CPU time	1.64 seconds
Started	Aug 21 07:33:25 PM UTC 24
Finished	Aug 21 07:33:28 PM UTC 24
Peak memory	225808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2784325043 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sparse_lc_gate_fsm.2784325043
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_sparse_lc_gate_fsm/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.186610877
Short name	T16
Test name
Test status
Simulation time	4353436267 ps
CPU time	4.63 seconds
Started	Aug 21 07:33:25 PM UTC 24
Finished	Aug 21 07:33:31 PM UTC 24
Peak memory	226396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=186610877 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.186610877
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/1.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/10.rv_dm_alert_test.3904793469
Short name	T210
Test name
Test status
Simulation time	112339046 ps
CPU time	1.14 seconds
Started	Aug 21 07:33:47 PM UTC 24
Finished	Aug 21 07:33:49 PM UTC 24
Peak memory	215884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3904793469 -asser t nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.3904793469
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/10.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/10.rv_dm_bad_sba_tl_access.1211321827
Short name	T251
Test name
Test status
Simulation time	2809519358 ps
CPU time	10.17 seconds
Started	Aug 21 07:33:47 PM UTC 24
Finished	Aug 21 07:33:58 PM UTC 24
Peak memory	226516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1211321827 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc ratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.1211321827
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/10.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.2697469594
Short name	T243
Test name
Test status
Simulation time	1762207951 ps
CPU time	6 seconds
Started	Aug 21 07:33:46 PM UTC 24
Finished	Aug 21 07:33:53 PM UTC 24
Peak memory	216268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2697469594 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sb a_tl_access.2697469594
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/10.rv_dm_sba_tl_access.309880214
Short name	T252
Test name
Test status
Simulation time	3073821865 ps
CPU time	13.41 seconds
Started	Aug 21 07:33:46 PM UTC 24
Finished	Aug 21 07:34:00 PM UTC 24
Peak memory	216284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=309880214 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch /earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.309880214
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/10.rv_dm_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/10.rv_dm_stress_all.1735342390
Short name	T180
Test name
Test status
Simulation time	2261532424 ps
CPU time	6.53 seconds
Started	Aug 21 07:33:47 PM UTC 24
Finished	Aug 21 07:33:55 PM UTC 24
Peak memory	216076 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1735342390 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.1735342390
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/10.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/11.rv_dm_alert_test.120963312
Short name	T212
Test name
Test status
Simulation time	78818965 ps
CPU time	1.1 seconds
Started	Aug 21 07:33:50 PM UTC 24
Finished	Aug 21 07:33:52 PM UTC 24
Peak memory	215760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=120963312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.120963312
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/11.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/11.rv_dm_autoincr_sba_tl_access.3299210284
Short name	T327
Test name
Test status
Simulation time	89206984540 ps
CPU time	274.88 seconds
Started	Aug 21 07:33:49 PM UTC 24
Finished	Aug 21 07:38:28 PM UTC 24
Peak memory	226516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3299210284 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit an/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.3299210284
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/11.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/11.rv_dm_bad_sba_tl_access.2617148603
Short name	T177
Test name
Test status
Simulation time	2877635629 ps
CPU time	6.08 seconds
Started	Aug 21 07:33:48 PM UTC 24
Finished	Aug 21 07:33:56 PM UTC 24
Peak memory	216204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2617148603 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc ratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.2617148603
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/11.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.1010100097
Short name	T228
Test name
Test status
Simulation time	5289350966 ps
CPU time	8.76 seconds
Started	Aug 21 07:33:48 PM UTC 24
Finished	Aug 21 07:33:59 PM UTC 24
Peak memory	216256 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1010100097 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sb a_tl_access.1010100097
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/11.rv_dm_sba_tl_access.188893807
Short name	T183
Test name
Test status
Simulation time	3424983701 ps
CPU time	2.86 seconds
Started	Aug 21 07:33:48 PM UTC 24
Finished	Aug 21 07:33:53 PM UTC 24
Peak memory	226448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=188893807 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch /earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.188893807
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/11.rv_dm_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/11.rv_dm_stress_all.1813675026
Short name	T182
Test name
Test status
Simulation time	3440515647 ps
CPU time	14.57 seconds
Started	Aug 21 07:33:49 PM UTC 24
Finished	Aug 21 07:34:05 PM UTC 24
Peak memory	226336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1813675026 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.1813675026
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/11.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/12.rv_dm_alert_test.1101412691
Short name	T244
Test name
Test status
Simulation time	39901438 ps
CPU time	0.95 seconds
Started	Aug 21 07:33:51 PM UTC 24
Finished	Aug 21 07:33:53 PM UTC 24
Peak memory	215892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1101412691 -asser t nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.1101412691
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/12.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/12.rv_dm_autoincr_sba_tl_access.486054601
Short name	T263
Test name
Test status
Simulation time	17370921116 ps
CPU time	16.49 seconds
Started	Aug 21 07:33:51 PM UTC 24
Finished	Aug 21 07:34:09 PM UTC 24
Peak memory	226508 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=486054601 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.486054601
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/12.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/12.rv_dm_bad_sba_tl_access.3041843768
Short name	T223
Test name
Test status
Simulation time	2751303288 ps
CPU time	5.46 seconds
Started	Aug 21 07:33:50 PM UTC 24
Finished	Aug 21 07:33:57 PM UTC 24
Peak memory	216408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3041843768 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc ratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.3041843768
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/12.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.1902161733
Short name	T246
Test name
Test status
Simulation time	3491226101 ps
CPU time	4.05 seconds
Started	Aug 21 07:33:50 PM UTC 24
Finished	Aug 21 07:33:55 PM UTC 24
Peak memory	216268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1902161733 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sb a_tl_access.1902161733
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/12.rv_dm_sba_tl_access.3848982673
Short name	T248
Test name
Test status
Simulation time	2024830691 ps
CPU time	4.87 seconds
Started	Aug 21 07:33:50 PM UTC 24
Finished	Aug 21 07:33:56 PM UTC 24
Peak memory	226344 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3848982673 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc h/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.3848982673
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/12.rv_dm_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/12.rv_dm_stress_all.2520604244
Short name	T38
Test name
Test status
Simulation time	3846876589 ps
CPU time	3.58 seconds
Started	Aug 21 07:33:51 PM UTC 24
Finished	Aug 21 07:33:56 PM UTC 24
Peak memory	226324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2520604244 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.2520604244
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/12.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/13.rv_dm_alert_test.822458750
Short name	T247
Test name
Test status
Simulation time	97552042 ps
CPU time	0.86 seconds
Started	Aug 21 07:33:53 PM UTC 24
Finished	Aug 21 07:33:55 PM UTC 24
Peak memory	215956 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=822458750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.822458750
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/13.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/13.rv_dm_autoincr_sba_tl_access.782102723
Short name	T322
Test name
Test status
Simulation time	36070306898 ps
CPU time	55.44 seconds
Started	Aug 21 07:33:52 PM UTC 24
Finished	Aug 21 07:34:50 PM UTC 24
Peak memory	226560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=782102723 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.782102723
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/13.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.2549427370
Short name	T292
Test name
Test status
Simulation time	7918900015 ps
CPU time	24.58 seconds
Started	Aug 21 07:33:52 PM UTC 24
Finished	Aug 21 07:34:18 PM UTC 24
Peak memory	226520 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2549427370 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sb a_tl_access.2549427370
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/13.rv_dm_sba_tl_access.916207269
Short name	T250
Test name
Test status
Simulation time	907875025 ps
CPU time	4.01 seconds
Started	Aug 21 07:33:52 PM UTC 24
Finished	Aug 21 07:33:58 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=916207269 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch /earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.916207269
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/13.rv_dm_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/13.rv_dm_stress_all.70752059
Short name	T30
Test name
Test status
Simulation time	2326701640 ps
CPU time	6.91 seconds
Started	Aug 21 07:33:52 PM UTC 24
Finished	Aug 21 07:34:01 PM UTC 24
Peak memory	226324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=70752059 -asse rt nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.70752059
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/13.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/14.rv_dm_alert_test.951399894
Short name	T217
Test name
Test status
Simulation time	61751856 ps
CPU time	1.2 seconds
Started	Aug 21 07:33:56 PM UTC 24
Finished	Aug 21 07:33:58 PM UTC 24
Peak memory	215956 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=951399894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.951399894
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/14.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/14.rv_dm_autoincr_sba_tl_access.3432305338
Short name	T309
Test name
Test status
Simulation time	8535824313 ps
CPU time	26.43 seconds
Started	Aug 21 07:33:55 PM UTC 24
Finished	Aug 21 07:34:23 PM UTC 24
Peak memory	226584 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3432305338 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit an/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.3432305338
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/14.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/14.rv_dm_bad_sba_tl_access.79050167
Short name	T230
Test name
Test status
Simulation time	2171281091 ps
CPU time	4.24 seconds
Started	Aug 21 07:33:55 PM UTC 24
Finished	Aug 21 07:34:00 PM UTC 24
Peak memory	216284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=79050167 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra tch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.79050167
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/14.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.1014470394
Short name	T267
Test name
Test status
Simulation time	2543395875 ps
CPU time	13.61 seconds
Started	Aug 21 07:33:54 PM UTC 24
Finished	Aug 21 07:34:10 PM UTC 24
Peak memory	226444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1014470394 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sb a_tl_access.1014470394
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/14.rv_dm_sba_tl_access.3986956857
Short name	T240
Test name
Test status
Simulation time	11980343830 ps
CPU time	8.97 seconds
Started	Aug 21 07:33:53 PM UTC 24
Finished	Aug 21 07:34:03 PM UTC 24
Peak memory	216332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3986956857 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc h/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.3986956857
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/14.rv_dm_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/15.rv_dm_alert_test.1757455084
Short name	T222
Test name
Test status
Simulation time	84137533 ps
CPU time	1.32 seconds
Started	Aug 21 07:33:58 PM UTC 24
Finished	Aug 21 07:34:01 PM UTC 24
Peak memory	215756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1757455084 -asser t nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.1757455084
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/15.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/15.rv_dm_autoincr_sba_tl_access.3688456719
Short name	T218
Test name
Test status
Simulation time	2202181375 ps
CPU time	2.89 seconds
Started	Aug 21 07:33:57 PM UTC 24
Finished	Aug 21 07:34:01 PM UTC 24
Peak memory	216344 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3688456719 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit an/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.3688456719
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/15.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/15.rv_dm_bad_sba_tl_access.1411984869
Short name	T254
Test name
Test status
Simulation time	2517030873 ps
CPU time	4.85 seconds
Started	Aug 21 07:33:57 PM UTC 24
Finished	Aug 21 07:34:03 PM UTC 24
Peak memory	216204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1411984869 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc ratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.1411984869
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/15.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.3631847394
Short name	T291
Test name
Test status
Simulation time	5440844634 ps
CPU time	21.18 seconds
Started	Aug 21 07:33:56 PM UTC 24
Finished	Aug 21 07:34:18 PM UTC 24
Peak memory	226564 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3631847394 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sb a_tl_access.3631847394
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/15.rv_dm_sba_tl_access.1948970029
Short name	T216
Test name
Test status
Simulation time	7109386666 ps
CPU time	5.68 seconds
Started	Aug 21 07:33:56 PM UTC 24
Finished	Aug 21 07:34:02 PM UTC 24
Peak memory	216352 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1948970029 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc h/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.1948970029
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/15.rv_dm_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/15.rv_dm_stress_all.3700671657
Short name	T176
Test name
Test status
Simulation time	1926539470 ps
CPU time	5.9 seconds
Started	Aug 21 07:33:57 PM UTC 24
Finished	Aug 21 07:34:04 PM UTC 24
Peak memory	216164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3700671657 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.3700671657
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/15.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/16.rv_dm_alert_test.1111424395
Short name	T231
Test name
Test status
Simulation time	94470042 ps
CPU time	0.86 seconds
Started	Aug 21 07:34:00 PM UTC 24
Finished	Aug 21 07:34:02 PM UTC 24
Peak memory	215892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1111424395 -asser t nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.1111424395
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/16.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/16.rv_dm_autoincr_sba_tl_access.3498241658
Short name	T326
Test name
Test status
Simulation time	151672607429 ps
CPU time	134.14 seconds
Started	Aug 21 07:33:59 PM UTC 24
Finished	Aug 21 07:36:16 PM UTC 24
Peak memory	226484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3498241658 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit an/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.3498241658
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/16.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/16.rv_dm_bad_sba_tl_access.106486787
Short name	T213
Test name
Test status
Simulation time	1988335841 ps
CPU time	3.49 seconds
Started	Aug 21 07:33:59 PM UTC 24
Finished	Aug 21 07:34:04 PM UTC 24
Peak memory	226360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=106486787 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.106486787
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/16.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.1255186530
Short name	T256
Test name
Test status
Simulation time	2593295686 ps
CPU time	4.59 seconds
Started	Aug 21 07:33:58 PM UTC 24
Finished	Aug 21 07:34:04 PM UTC 24
Peak memory	216332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1255186530 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sb a_tl_access.1255186530
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/16.rv_dm_sba_tl_access.453594408
Short name	T262
Test name
Test status
Simulation time	4663157911 ps
CPU time	9.44 seconds
Started	Aug 21 07:33:58 PM UTC 24
Finished	Aug 21 07:34:09 PM UTC 24
Peak memory	226500 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=453594408 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch /earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.453594408
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/16.rv_dm_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/16.rv_dm_stress_all.2853922444
Short name	T25
Test name
Test status
Simulation time	3771726007 ps
CPU time	3.52 seconds
Started	Aug 21 07:33:59 PM UTC 24
Finished	Aug 21 07:34:04 PM UTC 24
Peak memory	226388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2853922444 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.2853922444
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/16.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/17.rv_dm_alert_test.1056147115
Short name	T258
Test name
Test status
Simulation time	147077847 ps
CPU time	1.13 seconds
Started	Aug 21 07:34:03 PM UTC 24
Finished	Aug 21 07:34:05 PM UTC 24
Peak memory	215892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1056147115 -asser t nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.1056147115
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/17.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/17.rv_dm_autoincr_sba_tl_access.1902514969
Short name	T325
Test name
Test status
Simulation time	46423310537 ps
CPU time	84.4 seconds
Started	Aug 21 07:34:02 PM UTC 24
Finished	Aug 21 07:35:28 PM UTC 24
Peak memory	226640 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1902514969 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit an/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.1902514969
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/17.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/17.rv_dm_bad_sba_tl_access.3860573077
Short name	T313
Test name
Test status
Simulation time	6267514635 ps
CPU time	22.87 seconds
Started	Aug 21 07:34:02 PM UTC 24
Finished	Aug 21 07:34:26 PM UTC 24
Peak memory	216416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3860573077 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc ratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.3860573077
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/17.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.1097428297
Short name	T269
Test name
Test status
Simulation time	2198910845 ps
CPU time	7.4 seconds
Started	Aug 21 07:34:02 PM UTC 24
Finished	Aug 21 07:34:10 PM UTC 24
Peak memory	216200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1097428297 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sb a_tl_access.1097428297
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/17.rv_dm_sba_tl_access.4017819382
Short name	T259
Test name
Test status
Simulation time	2484720191 ps
CPU time	2.97 seconds
Started	Aug 21 07:34:01 PM UTC 24
Finished	Aug 21 07:34:06 PM UTC 24
Peak memory	216332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4017819382 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc h/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.4017819382
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/17.rv_dm_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/17.rv_dm_stress_all.3362789302
Short name	T268
Test name
Test status
Simulation time	3346336769 ps
CPU time	5.84 seconds
Started	Aug 21 07:34:03 PM UTC 24
Finished	Aug 21 07:34:10 PM UTC 24
Peak memory	226520 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3362789302 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.3362789302
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/17.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/18.rv_dm_alert_test.1894839130
Short name	T260
Test name
Test status
Simulation time	53349121 ps
CPU time	1.06 seconds
Started	Aug 21 07:34:05 PM UTC 24
Finished	Aug 21 07:34:07 PM UTC 24
Peak memory	215892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1894839130 -asser t nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.1894839130
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/18.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/18.rv_dm_bad_sba_tl_access.3069495200
Short name	T190
Test name
Test status
Simulation time	3031360343 ps
CPU time	2.88 seconds
Started	Aug 21 07:34:04 PM UTC 24
Finished	Aug 21 07:34:08 PM UTC 24
Peak memory	216256 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3069495200 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc ratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.3069495200
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/18.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.1519642448
Short name	T279
Test name
Test status
Simulation time	3420383693 ps
CPU time	8.15 seconds
Started	Aug 21 07:34:04 PM UTC 24
Finished	Aug 21 07:34:13 PM UTC 24
Peak memory	216332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1519642448 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sb a_tl_access.1519642448
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/18.rv_dm_sba_tl_access.2873903636
Short name	T270
Test name
Test status
Simulation time	2294999957 ps
CPU time	6.42 seconds
Started	Aug 21 07:34:03 PM UTC 24
Finished	Aug 21 07:34:11 PM UTC 24
Peak memory	216288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2873903636 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc h/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.2873903636
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/18.rv_dm_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/19.rv_dm_alert_test.1261383714
Short name	T261
Test name
Test status
Simulation time	45621395 ps
CPU time	1.22 seconds
Started	Aug 21 07:34:05 PM UTC 24
Finished	Aug 21 07:34:08 PM UTC 24
Peak memory	215952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1261383714 -asser t nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.1261383714
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/19.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.3770716871
Short name	T324
Test name
Test status
Simulation time	68698875119 ps
CPU time	57.37 seconds
Started	Aug 21 07:34:05 PM UTC 24
Finished	Aug 21 07:35:05 PM UTC 24
Peak memory	226452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3770716871 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit an/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.3770716871
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/19.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.3662307507
Short name	T266
Test name
Test status
Simulation time	1588050960 ps
CPU time	2.85 seconds
Started	Aug 21 07:34:05 PM UTC 24
Finished	Aug 21 07:34:09 PM UTC 24
Peak memory	216128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3662307507 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sb a_tl_access.3662307507
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/19.rv_dm_sba_tl_access.1666080037
Short name	T273
Test name
Test status
Simulation time	2075582081 ps
CPU time	5.38 seconds
Started	Aug 21 07:34:05 PM UTC 24
Finished	Aug 21 07:34:12 PM UTC 24
Peak memory	216280 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1666080037 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc h/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.1666080037
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/19.rv_dm_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.1798471683
Short name	T186
Test name
Test status
Simulation time	4583507530 ps
CPU time	15.82 seconds
Started	Aug 21 07:34:05 PM UTC 24
Finished	Aug 21 07:34:23 PM UTC 24
Peak memory	216084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1798471683 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.1798471683
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/19.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.4173472304
Short name	T50
Test name
Test status
Simulation time	38937122 ps
CPU time	0.83 seconds
Started	Aug 21 07:33:28 PM UTC 24
Finished	Aug 21 07:33:30 PM UTC 24
Peak memory	215892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4173472304 -asser t nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.4173472304
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/2.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.2799061269
Short name	T23
Test name
Test status
Simulation time	2492263463 ps
CPU time	8.16 seconds
Started	Aug 21 07:33:27 PM UTC 24
Finished	Aug 21 07:33:36 PM UTC 24
Peak memory	216412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2799061269 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit an/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.2799061269
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/2.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.2624364496
Short name	T112
Test name
Test status
Simulation time	1967979434 ps
CPU time	5.71 seconds
Started	Aug 21 07:33:27 PM UTC 24
Finished	Aug 21 07:33:34 PM UTC 24
Peak memory	226580 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2624364496 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc ratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.2624364496
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/2.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.3206865213
Short name	T81
Test name
Test status
Simulation time	289757407 ps
CPU time	1.79 seconds
Started	Aug 21 07:33:27 PM UTC 24
Finished	Aug 21 07:33:30 PM UTC 24
Peak memory	252312 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3206865213 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra tch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_buffered_enable.3206865213
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/2.rv_dm_buffered_enable/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.4089198988
Short name	T249
Test name
Test status
Simulation time	15476857051 ps
CPU time	29.36 seconds
Started	Aug 21 07:33:27 PM UTC 24
Finished	Aug 21 07:33:57 PM UTC 24
Peak memory	226452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4089198988 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba _tl_access.4089198988
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.3096081629
Short name	T56
Test name
Test status
Simulation time	1361274430 ps
CPU time	4.26 seconds
Started	Aug 21 07:33:27 PM UTC 24
Finished	Aug 21 07:33:32 PM UTC 24
Peak memory	215880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3096081629 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_halt_resume_whereto.3096081629
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/2.rv_dm_halt_resume_whereto/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.1398220366
Short name	T178
Test name
Test status
Simulation time	62505844 ps
CPU time	1.07 seconds
Started	Aug 21 07:33:27 PM UTC 24
Finished	Aug 21 07:33:29 PM UTC 24
Peak memory	213468 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1398220366 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch /earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.1398220366
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/2.rv_dm_hart_unavail/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.206897389
Short name	T179
Test name
Test status
Simulation time	5164918658 ps
CPU time	17.1 seconds
Started	Aug 21 07:33:27 PM UTC 24
Finished	Aug 21 07:33:45 PM UTC 24
Peak memory	216268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=206897389 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch /earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.206897389
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/2.rv_dm_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.2480885031
Short name	T85
Test name
Test status
Simulation time	1770698465 ps
CPU time	2.68 seconds
Started	Aug 21 07:33:28 PM UTC 24
Finished	Aug 21 07:33:32 PM UTC 24
Peak memory	254768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2480885031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.2480885031
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/2.rv_dm_sec_cm/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/2.rv_dm_sparse_lc_gate_fsm.588043897
Short name	T77
Test name
Test status
Simulation time	244050333 ps
CPU time	2.16 seconds
Started	Aug 21 07:33:28 PM UTC 24
Finished	Aug 21 07:33:31 PM UTC 24
Peak memory	226260 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=588043897 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc ratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sparse_lc_gate_fsm.588043897
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/2.rv_dm_sparse_lc_gate_fsm/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/20.rv_dm_alert_test.3107038277
Short name	T265
Test name
Test status
Simulation time	128203288 ps
CPU time	1.54 seconds
Started	Aug 21 07:34:07 PM UTC 24
Finished	Aug 21 07:34:09 PM UTC 24
Peak memory	215892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3107038277 -asser t nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.3107038277
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/20.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/21.rv_dm_alert_test.3610575625
Short name	T264
Test name
Test status
Simulation time	154128025 ps
CPU time	1.2 seconds
Started	Aug 21 07:34:07 PM UTC 24
Finished	Aug 21 07:34:09 PM UTC 24
Peak memory	215952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3610575625 -asser t nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.3610575625
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/21.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/21.rv_dm_stress_all.711979368
Short name	T17
Test name
Test status
Simulation time	3521080388 ps
CPU time	8.54 seconds
Started	Aug 21 07:34:07 PM UTC 24
Finished	Aug 21 07:34:16 PM UTC 24
Peak memory	226416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=711979368 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.711979368
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/21.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/22.rv_dm_alert_test.89734654
Short name	T272
Test name
Test status
Simulation time	65351845 ps
CPU time	1.21 seconds
Started	Aug 21 07:34:09 PM UTC 24
Finished	Aug 21 07:34:11 PM UTC 24
Peak memory	215608 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=89734654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.89734654
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/22.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.2949772802
Short name	T298
Test name
Test status
Simulation time	2152420322 ps
CPU time	9.98 seconds
Started	Aug 21 07:34:08 PM UTC 24
Finished	Aug 21 07:34:19 PM UTC 24
Peak memory	226404 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2949772802 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.2949772802
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/22.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/23.rv_dm_alert_test.1456559336
Short name	T271
Test name
Test status
Simulation time	83979017 ps
CPU time	0.92 seconds
Started	Aug 21 07:34:09 PM UTC 24
Finished	Aug 21 07:34:11 PM UTC 24
Peak memory	215892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1456559336 -asser t nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.1456559336
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/23.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/23.rv_dm_stress_all.146943579
Short name	T278
Test name
Test status
Simulation time	4234678359 ps
CPU time	2.98 seconds
Started	Aug 21 07:34:09 PM UTC 24
Finished	Aug 21 07:34:13 PM UTC 24
Peak memory	226152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=146943579 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.146943579
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/23.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/24.rv_dm_alert_test.2534635613
Short name	T274
Test name
Test status
Simulation time	34873722 ps
CPU time	1.02 seconds
Started	Aug 21 07:34:10 PM UTC 24
Finished	Aug 21 07:34:13 PM UTC 24
Peak memory	215892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2534635613 -asser t nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.2534635613
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/24.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/24.rv_dm_stress_all.1443587764
Short name	T11
Test name
Test status
Simulation time	3723922984 ps
CPU time	9.89 seconds
Started	Aug 21 07:34:09 PM UTC 24
Finished	Aug 21 07:34:20 PM UTC 24
Peak memory	216152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1443587764 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.1443587764
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/24.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/25.rv_dm_alert_test.3002311536
Short name	T276
Test name
Test status
Simulation time	80474515 ps
CPU time	1.4 seconds
Started	Aug 21 07:34:10 PM UTC 24
Finished	Aug 21 07:34:13 PM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3002311536 -asser t nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.3002311536
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/25.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.2832421640
Short name	T283
Test name
Test status
Simulation time	6167885774 ps
CPU time	4.02 seconds
Started	Aug 21 07:34:10 PM UTC 24
Finished	Aug 21 07:34:16 PM UTC 24
Peak memory	226272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2832421640 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.2832421640
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/25.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/26.rv_dm_alert_test.373375717
Short name	T275
Test name
Test status
Simulation time	36229860 ps
CPU time	1.13 seconds
Started	Aug 21 07:34:10 PM UTC 24
Finished	Aug 21 07:34:13 PM UTC 24
Peak memory	215952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=373375717 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.373375717
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/26.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/26.rv_dm_stress_all.3429225140
Short name	T187
Test name
Test status
Simulation time	3586341359 ps
CPU time	7.36 seconds
Started	Aug 21 07:34:10 PM UTC 24
Finished	Aug 21 07:34:19 PM UTC 24
Peak memory	216172 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3429225140 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.3429225140
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/26.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/27.rv_dm_alert_test.908280658
Short name	T227
Test name
Test status
Simulation time	46303675 ps
CPU time	0.95 seconds
Started	Aug 21 07:34:10 PM UTC 24
Finished	Aug 21 07:34:12 PM UTC 24
Peak memory	215928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=908280658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.908280658
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/27.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.3590630832
Short name	T282
Test name
Test status
Simulation time	3012600628 ps
CPU time	3.54 seconds
Started	Aug 21 07:34:10 PM UTC 24
Finished	Aug 21 07:34:15 PM UTC 24
Peak memory	226324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3590630832 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.3590630832
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/27.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/28.rv_dm_alert_test.850256781
Short name	T280
Test name
Test status
Simulation time	118648995 ps
CPU time	1.01 seconds
Started	Aug 21 07:34:12 PM UTC 24
Finished	Aug 21 07:34:14 PM UTC 24
Peak memory	215892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=850256781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.850256781
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/28.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/28.rv_dm_stress_all.2096728473
Short name	T174
Test name
Test status
Simulation time	2093600310 ps
CPU time	3.95 seconds
Started	Aug 21 07:34:12 PM UTC 24
Finished	Aug 21 07:34:17 PM UTC 24
Peak memory	215884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2096728473 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.2096728473
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/28.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/29.rv_dm_alert_test.1854001659
Short name	T281
Test name
Test status
Simulation time	131945125 ps
CPU time	0.93 seconds
Started	Aug 21 07:34:13 PM UTC 24
Finished	Aug 21 07:34:15 PM UTC 24
Peak memory	215892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1854001659 -asser t nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.1854001659
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/29.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.3265022627
Short name	T160
Test name
Test status
Simulation time	101691044 ps
CPU time	1.04 seconds
Started	Aug 21 07:33:31 PM UTC 24
Finished	Aug 21 07:33:33 PM UTC 24
Peak memory	213476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3265022627 -asser t nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.3265022627
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/3.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.3791156611
Short name	T328
Test name
Test status
Simulation time	113653979008 ps
CPU time	316.15 seconds
Started	Aug 21 07:33:29 PM UTC 24
Finished	Aug 21 07:38:50 PM UTC 24
Peak memory	233300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3791156611 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit an/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.3791156611
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/3.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.174435213
Short name	T121
Test name
Test status
Simulation time	6922033101 ps
CPU time	19.66 seconds
Started	Aug 21 07:33:28 PM UTC 24
Finished	Aug 21 07:33:49 PM UTC 24
Peak memory	226444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=174435213 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.174435213
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/3.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.3888848144
Short name	T192
Test name
Test status
Simulation time	142338238 ps
CPU time	1.43 seconds
Started	Aug 21 07:33:30 PM UTC 24
Finished	Aug 21 07:33:32 PM UTC 24
Peak memory	245556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3888848144 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra tch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_buffered_enable.3888848144
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/3.rv_dm_buffered_enable/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.804434768
Short name	T113
Test name
Test status
Simulation time	1529333329 ps
CPU time	2.89 seconds
Started	Aug 21 07:33:28 PM UTC 24
Finished	Aug 21 07:33:32 PM UTC 24
Peak memory	216144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=804434768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_ tl_access.804434768
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.861212941
Short name	T58
Test name
Test status
Simulation time	265706292 ps
CPU time	1.95 seconds
Started	Aug 21 07:33:30 PM UTC 24
Finished	Aug 21 07:33:33 PM UTC 24
Peak memory	213468 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=861212941 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_halt_resume_whereto.861212941
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/3.rv_dm_halt_resume_whereto/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/3.rv_dm_hart_unavail.3514791028
Short name	T224
Test name
Test status
Simulation time	201754561 ps
CPU time	1.18 seconds
Started	Aug 21 07:33:30 PM UTC 24
Finished	Aug 21 07:33:32 PM UTC 24
Peak memory	213468 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3514791028 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch /earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.3514791028
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/3.rv_dm_hart_unavail/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.3529195557
Short name	T117
Test name
Test status
Simulation time	5676185068 ps
CPU time	17.99 seconds
Started	Aug 21 07:33:28 PM UTC 24
Finished	Aug 21 07:33:48 PM UTC 24
Peak memory	216336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3529195557 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc h/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.3529195557
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/3.rv_dm_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/3.rv_dm_sec_cm.3219913881
Short name	T92
Test name
Test status
Simulation time	2735431200 ps
CPU time	10.53 seconds
Started	Aug 21 07:33:31 PM UTC 24
Finished	Aug 21 07:33:43 PM UTC 24
Peak memory	254768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3219913881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.3219913881
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/3.rv_dm_sec_cm/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.4259176697
Short name	T95
Test name
Test status
Simulation time	65097508 ps
CPU time	0.93 seconds
Started	Aug 21 07:33:30 PM UTC 24
Finished	Aug 21 07:33:32 PM UTC 24
Peak memory	225872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4259176697 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s cratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sparse_lc_gate_fsm.4259176697
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/3.rv_dm_sparse_lc_gate_fsm/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.4239377238
Short name	T37
Test name
Test status
Simulation time	3893725112 ps
CPU time	4.43 seconds
Started	Aug 21 07:33:30 PM UTC 24
Finished	Aug 21 07:33:35 PM UTC 24
Peak memory	216156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4239377238 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.4239377238
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/3.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/30.rv_dm_alert_test.4182359494
Short name	T285
Test name
Test status
Simulation time	97397040 ps
CPU time	1.15 seconds
Started	Aug 21 07:34:14 PM UTC 24
Finished	Aug 21 07:34:16 PM UTC 24
Peak memory	215892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4182359494 -asser t nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.4182359494
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/30.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.111169720
Short name	T288
Test name
Test status
Simulation time	1365853410 ps
CPU time	2.41 seconds
Started	Aug 21 07:34:13 PM UTC 24
Finished	Aug 21 07:34:16 PM UTC 24
Peak memory	216104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=111169720 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.111169720
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/30.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/31.rv_dm_alert_test.2189394667
Short name	T284
Test name
Test status
Simulation time	61004126 ps
CPU time	0.89 seconds
Started	Aug 21 07:34:14 PM UTC 24
Finished	Aug 21 07:34:16 PM UTC 24
Peak memory	215892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2189394667 -asser t nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.2189394667
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/31.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/31.rv_dm_stress_all.3950320125
Short name	T315
Test name
Test status
Simulation time	3711959057 ps
CPU time	13.87 seconds
Started	Aug 21 07:34:14 PM UTC 24
Finished	Aug 21 07:34:29 PM UTC 24
Peak memory	216072 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3950320125 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.3950320125
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/31.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/32.rv_dm_alert_test.806205582
Short name	T287
Test name
Test status
Simulation time	79616866 ps
CPU time	1.02 seconds
Started	Aug 21 07:34:14 PM UTC 24
Finished	Aug 21 07:34:16 PM UTC 24
Peak memory	215900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=806205582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.806205582
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/32.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/32.rv_dm_stress_all.3175246984
Short name	T301
Test name
Test status
Simulation time	3651453913 ps
CPU time	5.82 seconds
Started	Aug 21 07:34:14 PM UTC 24
Finished	Aug 21 07:34:21 PM UTC 24
Peak memory	216036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3175246984 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.3175246984
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/32.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/33.rv_dm_alert_test.4115782913
Short name	T219
Test name
Test status
Simulation time	155239447 ps
CPU time	1.25 seconds
Started	Aug 21 07:34:14 PM UTC 24
Finished	Aug 21 07:34:16 PM UTC 24
Peak memory	215892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4115782913 -asser t nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.4115782913
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/33.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.3495866132
Short name	T33
Test name
Test status
Simulation time	2343444364 ps
CPU time	4.42 seconds
Started	Aug 21 07:34:14 PM UTC 24
Finished	Aug 21 07:34:20 PM UTC 24
Peak memory	226268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3495866132 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.3495866132
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/33.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/34.rv_dm_alert_test.125608759
Short name	T286
Test name
Test status
Simulation time	39297516 ps
CPU time	0.9 seconds
Started	Aug 21 07:34:14 PM UTC 24
Finished	Aug 21 07:34:16 PM UTC 24
Peak memory	215956 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=125608759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.125608759
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/34.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/34.rv_dm_stress_all.1931865618
Short name	T304
Test name
Test status
Simulation time	5905635655 ps
CPU time	6.19 seconds
Started	Aug 21 07:34:14 PM UTC 24
Finished	Aug 21 07:34:21 PM UTC 24
Peak memory	226412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1931865618 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.1931865618
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/34.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/35.rv_dm_alert_test.2323517363
Short name	T289
Test name
Test status
Simulation time	62487748 ps
CPU time	0.9 seconds
Started	Aug 21 07:34:15 PM UTC 24
Finished	Aug 21 07:34:17 PM UTC 24
Peak memory	215892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2323517363 -asser t nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.2323517363
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/35.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/35.rv_dm_stress_all.1213507560
Short name	T54
Test name
Test status
Simulation time	2091474935 ps
CPU time	4.2 seconds
Started	Aug 21 07:34:15 PM UTC 24
Finished	Aug 21 07:34:21 PM UTC 24
Peak memory	216088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1213507560 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.1213507560
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/35.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/36.rv_dm_alert_test.2883432303
Short name	T290
Test name
Test status
Simulation time	82136711 ps
CPU time	1.17 seconds
Started	Aug 21 07:34:16 PM UTC 24
Finished	Aug 21 07:34:18 PM UTC 24
Peak memory	215816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2883432303 -asser t nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.2883432303
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/36.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/36.rv_dm_stress_all.3043006588
Short name	T305
Test name
Test status
Simulation time	3005538997 ps
CPU time	5.19 seconds
Started	Aug 21 07:34:15 PM UTC 24
Finished	Aug 21 07:34:22 PM UTC 24
Peak memory	216160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3043006588 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.3043006588
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/36.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/37.rv_dm_alert_test.134749145
Short name	T294
Test name
Test status
Simulation time	68693498 ps
CPU time	1.21 seconds
Started	Aug 21 07:34:17 PM UTC 24
Finished	Aug 21 07:34:19 PM UTC 24
Peak memory	215960 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=134749145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.134749145
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/37.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/37.rv_dm_stress_all.2251980328
Short name	T319
Test name
Test status
Simulation time	7470761617 ps
CPU time	18.78 seconds
Started	Aug 21 07:34:16 PM UTC 24
Finished	Aug 21 07:34:36 PM UTC 24
Peak memory	226268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2251980328 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.2251980328
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/37.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/38.rv_dm_alert_test.869927574
Short name	T297
Test name
Test status
Simulation time	72561702 ps
CPU time	1.36 seconds
Started	Aug 21 07:34:17 PM UTC 24
Finished	Aug 21 07:34:19 PM UTC 24
Peak memory	215896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=869927574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.869927574
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/38.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/39.rv_dm_alert_test.3324465918
Short name	T295
Test name
Test status
Simulation time	48744141 ps
CPU time	1.04 seconds
Started	Aug 21 07:34:17 PM UTC 24
Finished	Aug 21 07:34:19 PM UTC 24
Peak memory	215952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3324465918 -asser t nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.3324465918
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/39.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/39.rv_dm_stress_all.3694695067
Short name	T185
Test name
Test status
Simulation time	2153439480 ps
CPU time	3.75 seconds
Started	Aug 21 07:34:17 PM UTC 24
Finished	Aug 21 07:34:21 PM UTC 24
Peak memory	226400 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3694695067 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.3694695067
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/39.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/4.rv_dm_alert_test.3830931610
Short name	T161
Test name
Test status
Simulation time	65682889 ps
CPU time	1.1 seconds
Started	Aug 21 07:33:33 PM UTC 24
Finished	Aug 21 07:33:36 PM UTC 24
Peak memory	215892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3830931610 -asser t nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.3830931610
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/4.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/4.rv_dm_autoincr_sba_tl_access.3871089375
Short name	T215
Test name
Test status
Simulation time	4206790325 ps
CPU time	7.77 seconds
Started	Aug 21 07:33:32 PM UTC 24
Finished	Aug 21 07:33:41 PM UTC 24
Peak memory	226224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3871089375 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit an/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.3871089375
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/4.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/4.rv_dm_bad_sba_tl_access.941220896
Short name	T214
Test name
Test status
Simulation time	5643256797 ps
CPU time	7.91 seconds
Started	Aug 21 07:33:32 PM UTC 24
Finished	Aug 21 07:33:41 PM UTC 24
Peak memory	226036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=941220896 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.941220896
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/4.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/4.rv_dm_buffered_enable.1216361901
Short name	T72
Test name
Test status
Simulation time	712562759 ps
CPU time	2.66 seconds
Started	Aug 21 07:33:32 PM UTC 24
Finished	Aug 21 07:33:36 PM UTC 24
Peak memory	252628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1216361901 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra tch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_buffered_enable.1216361901
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/4.rv_dm_buffered_enable/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.1102402191
Short name	T235
Test name
Test status
Simulation time	2991221623 ps
CPU time	4.4 seconds
Started	Aug 21 07:33:31 PM UTC 24
Finished	Aug 21 07:33:36 PM UTC 24
Peak memory	216200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1102402191 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba _tl_access.1102402191
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.3102938085
Short name	T57
Test name
Test status
Simulation time	439605191 ps
CPU time	1.99 seconds
Started	Aug 21 07:33:32 PM UTC 24
Finished	Aug 21 07:33:35 PM UTC 24
Peak memory	213464 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3102938085 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_halt_resume_whereto.3102938085
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/4.rv_dm_halt_resume_whereto/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.2252946841
Short name	T234
Test name
Test status
Simulation time	331915294 ps
CPU time	1.24 seconds
Started	Aug 21 07:33:32 PM UTC 24
Finished	Aug 21 07:33:34 PM UTC 24
Peak memory	213468 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2252946841 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch /earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.2252946841
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/4.rv_dm_hart_unavail/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/4.rv_dm_sba_tl_access.4082925079
Short name	T133
Test name
Test status
Simulation time	7456126293 ps
CPU time	3.59 seconds
Started	Aug 21 07:33:31 PM UTC 24
Finished	Aug 21 07:33:36 PM UTC 24
Peak memory	216212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4082925079 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc h/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.4082925079
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/4.rv_dm_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/4.rv_dm_sec_cm.1771541418
Short name	T91
Test name
Test status
Simulation time	1541968029 ps
CPU time	2.87 seconds
Started	Aug 21 07:33:33 PM UTC 24
Finished	Aug 21 07:33:37 PM UTC 24
Peak memory	254832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1771541418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.1771541418
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/4.rv_dm_sec_cm/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/40.rv_dm_alert_test.3697103009
Short name	T293
Test name
Test status
Simulation time	49653926 ps
CPU time	0.86 seconds
Started	Aug 21 07:34:17 PM UTC 24
Finished	Aug 21 07:34:19 PM UTC 24
Peak memory	215892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3697103009 -asser t nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.3697103009
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/40.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/40.rv_dm_stress_all.3958781321
Short name	T195
Test name
Test status
Simulation time	5935693637 ps
CPU time	19.44 seconds
Started	Aug 21 07:34:17 PM UTC 24
Finished	Aug 21 07:34:38 PM UTC 24
Peak memory	216148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3958781321 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.3958781321
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/40.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/41.rv_dm_alert_test.1954125337
Short name	T296
Test name
Test status
Simulation time	172577866 ps
CPU time	1.05 seconds
Started	Aug 21 07:34:17 PM UTC 24
Finished	Aug 21 07:34:19 PM UTC 24
Peak memory	215892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1954125337 -asser t nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.1954125337
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/41.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/41.rv_dm_stress_all.817591788
Short name	T193
Test name
Test status
Simulation time	3986745971 ps
CPU time	4.7 seconds
Started	Aug 21 07:34:17 PM UTC 24
Finished	Aug 21 07:34:23 PM UTC 24
Peak memory	216036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=817591788 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.817591788
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/41.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/42.rv_dm_alert_test.2282925071
Short name	T300
Test name
Test status
Simulation time	110088558 ps
CPU time	1.1 seconds
Started	Aug 21 07:34:18 PM UTC 24
Finished	Aug 21 07:34:20 PM UTC 24
Peak memory	214508 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2282925071 -asser t nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.2282925071
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/42.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/42.rv_dm_stress_all.322696098
Short name	T317
Test name
Test status
Simulation time	4004737042 ps
CPU time	14.04 seconds
Started	Aug 21 07:34:18 PM UTC 24
Finished	Aug 21 07:34:33 PM UTC 24
Peak memory	215536 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=322696098 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.322696098
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/42.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/43.rv_dm_alert_test.935375496
Short name	T299
Test name
Test status
Simulation time	70941878 ps
CPU time	0.92 seconds
Started	Aug 21 07:34:18 PM UTC 24
Finished	Aug 21 07:34:20 PM UTC 24
Peak memory	215956 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=935375496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.935375496
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/43.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/43.rv_dm_stress_all.222891765
Short name	T191
Test name
Test status
Simulation time	2444490645 ps
CPU time	2.78 seconds
Started	Aug 21 07:34:18 PM UTC 24
Finished	Aug 21 07:34:22 PM UTC 24
Peak memory	216088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=222891765 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.222891765
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/43.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/44.rv_dm_alert_test.2403614044
Short name	T302
Test name
Test status
Simulation time	102448093 ps
CPU time	0.81 seconds
Started	Aug 21 07:34:19 PM UTC 24
Finished	Aug 21 07:34:21 PM UTC 24
Peak memory	215952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2403614044 -asser t nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.2403614044
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/44.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.2434520636
Short name	T311
Test name
Test status
Simulation time	1950730217 ps
CPU time	4.21 seconds
Started	Aug 21 07:34:18 PM UTC 24
Finished	Aug 21 07:34:23 PM UTC 24
Peak memory	226196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2434520636 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.2434520636
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/44.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/45.rv_dm_alert_test.807029713
Short name	T303
Test name
Test status
Simulation time	41462014 ps
CPU time	0.85 seconds
Started	Aug 21 07:34:19 PM UTC 24
Finished	Aug 21 07:34:21 PM UTC 24
Peak memory	215956 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=807029713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.807029713
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/45.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/45.rv_dm_stress_all.797417602
Short name	T196
Test name
Test status
Simulation time	2648708589 ps
CPU time	3.33 seconds
Started	Aug 21 07:34:19 PM UTC 24
Finished	Aug 21 07:34:24 PM UTC 24
Peak memory	216088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=797417602 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.797417602
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/45.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/46.rv_dm_alert_test.522605856
Short name	T306
Test name
Test status
Simulation time	37538524 ps
CPU time	1.17 seconds
Started	Aug 21 07:34:20 PM UTC 24
Finished	Aug 21 07:34:22 PM UTC 24
Peak memory	215864 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=522605856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.522605856
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/46.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.597002522
Short name	T312
Test name
Test status
Simulation time	5338162957 ps
CPU time	3.53 seconds
Started	Aug 21 07:34:20 PM UTC 24
Finished	Aug 21 07:34:24 PM UTC 24
Peak memory	216144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=597002522 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.597002522
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/46.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/47.rv_dm_alert_test.2254046466
Short name	T307
Test name
Test status
Simulation time	70621478 ps
CPU time	1.21 seconds
Started	Aug 21 07:34:20 PM UTC 24
Finished	Aug 21 07:34:22 PM UTC 24
Peak memory	215952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2254046466 -asser t nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.2254046466
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/47.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/47.rv_dm_stress_all.1884256333
Short name	T314
Test name
Test status
Simulation time	2229454035 ps
CPU time	5.2 seconds
Started	Aug 21 07:34:20 PM UTC 24
Finished	Aug 21 07:34:26 PM UTC 24
Peak memory	216032 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1884256333 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.1884256333
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/47.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/48.rv_dm_alert_test.1543658445
Short name	T308
Test name
Test status
Simulation time	127796068 ps
CPU time	1.6 seconds
Started	Aug 21 07:34:20 PM UTC 24
Finished	Aug 21 07:34:22 PM UTC 24
Peak memory	215952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1543658445 -asser t nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.1543658445
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/48.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/48.rv_dm_stress_all.1578692836
Short name	T320
Test name
Test status
Simulation time	9929430537 ps
CPU time	16.35 seconds
Started	Aug 21 07:34:20 PM UTC 24
Finished	Aug 21 07:34:37 PM UTC 24
Peak memory	216024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1578692836 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.1578692836
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/48.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/49.rv_dm_alert_test.2651483769
Short name	T310
Test name
Test status
Simulation time	57669557 ps
CPU time	1.04 seconds
Started	Aug 21 07:34:21 PM UTC 24
Finished	Aug 21 07:34:23 PM UTC 24
Peak memory	215892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2651483769 -asser t nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.2651483769
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/49.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/49.rv_dm_stress_all.3387527712
Short name	T188
Test name
Test status
Simulation time	1392695453 ps
CPU time	2.31 seconds
Started	Aug 21 07:34:21 PM UTC 24
Finished	Aug 21 07:34:24 PM UTC 24
Peak memory	226324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3387527712 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.3387527712
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/49.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/5.rv_dm_alert_test.566817427
Short name	T162
Test name
Test status
Simulation time	67757115 ps
CPU time	1.05 seconds
Started	Aug 21 07:33:36 PM UTC 24
Finished	Aug 21 07:33:38 PM UTC 24
Peak memory	215892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=566817427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.566817427
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/5.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.2911859451
Short name	T238
Test name
Test status
Simulation time	12394036896 ps
CPU time	8.14 seconds
Started	Aug 21 07:33:34 PM UTC 24
Finished	Aug 21 07:33:43 PM UTC 24
Peak memory	226576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2911859451 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc ratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.2911859451
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/5.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/5.rv_dm_buffered_enable.2983021304
Short name	T181
Test name
Test status
Simulation time	313531622 ps
CPU time	2.4 seconds
Started	Aug 21 07:33:35 PM UTC 24
Finished	Aug 21 07:33:38 PM UTC 24
Peak memory	252636 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2983021304 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra tch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_buffered_enable.2983021304
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/5.rv_dm_buffered_enable/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.2945015789
Short name	T221
Test name
Test status
Simulation time	1575157463 ps
CPU time	3.05 seconds
Started	Aug 21 07:33:34 PM UTC 24
Finished	Aug 21 07:33:38 PM UTC 24
Peak memory	216148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2945015789 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba _tl_access.2945015789
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/5.rv_dm_halt_resume_whereto.2760955197
Short name	T207
Test name
Test status
Simulation time	816220483 ps
CPU time	2.48 seconds
Started	Aug 21 07:33:35 PM UTC 24
Finished	Aug 21 07:33:38 PM UTC 24
Peak memory	215948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2760955197 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_halt_resume_whereto.2760955197
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/5.rv_dm_halt_resume_whereto/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/5.rv_dm_sba_tl_access.1369283530
Short name	T257
Test name
Test status
Simulation time	17684861450 ps
CPU time	29.9 seconds
Started	Aug 21 07:33:33 PM UTC 24
Finished	Aug 21 07:34:05 PM UTC 24
Peak memory	226712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1369283530 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc h/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.1369283530
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/5.rv_dm_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.1613067531
Short name	T163
Test name
Test status
Simulation time	3250311190 ps
CPU time	3.73 seconds
Started	Aug 21 07:33:35 PM UTC 24
Finished	Aug 21 07:33:40 PM UTC 24
Peak memory	216152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1613067531 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.1613067531
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/5.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/6.rv_dm_alert_test.3921799759
Short name	T236
Test name
Test status
Simulation time	61213515 ps
CPU time	1.11 seconds
Started	Aug 21 07:33:39 PM UTC 24
Finished	Aug 21 07:33:41 PM UTC 24
Peak memory	215892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3921799759 -asser t nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.3921799759
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/6.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/6.rv_dm_bad_sba_tl_access.1276169474
Short name	T220
Test name
Test status
Simulation time	3475462619 ps
CPU time	2.76 seconds
Started	Aug 21 07:33:36 PM UTC 24
Finished	Aug 21 07:33:40 PM UTC 24
Peak memory	226572 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1276169474 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc ratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.1276169474
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/6.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/6.rv_dm_buffered_enable.2344678258
Short name	T170
Test name
Test status
Simulation time	123142983 ps
CPU time	1.25 seconds
Started	Aug 21 07:33:37 PM UTC 24
Finished	Aug 21 07:33:39 PM UTC 24
Peak memory	251712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2344678258 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra tch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_buffered_enable.2344678258
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/6.rv_dm_buffered_enable/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.637824855
Short name	T115
Test name
Test status
Simulation time	2359270431 ps
CPU time	9.86 seconds
Started	Aug 21 07:33:36 PM UTC 24
Finished	Aug 21 07:33:47 PM UTC 24
Peak memory	216272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=637824855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_ tl_access.637824855
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/6.rv_dm_halt_resume_whereto.3557443769
Short name	T68
Test name
Test status
Simulation time	582586824 ps
CPU time	2.18 seconds
Started	Aug 21 07:33:37 PM UTC 24
Finished	Aug 21 07:33:40 PM UTC 24
Peak memory	215816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3557443769 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_halt_resume_whereto.3557443769
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/6.rv_dm_halt_resume_whereto/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/6.rv_dm_sba_tl_access.3741899371
Short name	T237
Test name
Test status
Simulation time	2327691453 ps
CPU time	4.55 seconds
Started	Aug 21 07:33:36 PM UTC 24
Finished	Aug 21 07:33:42 PM UTC 24
Peak memory	216276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3741899371 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc h/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.3741899371
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/6.rv_dm_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all.3721069379
Short name	T165
Test name
Test status
Simulation time	3245839552 ps
CPU time	5.75 seconds
Started	Aug 21 07:33:37 PM UTC 24
Finished	Aug 21 07:33:44 PM UTC 24
Peak memory	226332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3721069379 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.3721069379
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/6.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/7.rv_dm_alert_test.3267777182
Short name	T164
Test name
Test status
Simulation time	171018517 ps
CPU time	1.05 seconds
Started	Aug 21 07:33:41 PM UTC 24
Finished	Aug 21 07:33:43 PM UTC 24
Peak memory	215892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3267777182 -asser t nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.3267777182
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/7.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.2036747573
Short name	T225
Test name
Test status
Simulation time	11981202048 ps
CPU time	4.35 seconds
Started	Aug 21 07:33:39 PM UTC 24
Finished	Aug 21 07:33:44 PM UTC 24
Peak memory	226508 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2036747573 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit an/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.2036747573
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/7.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.2165978949
Short name	T232
Test name
Test status
Simulation time	5123017547 ps
CPU time	11.53 seconds
Started	Aug 21 07:33:39 PM UTC 24
Finished	Aug 21 07:33:51 PM UTC 24
Peak memory	216404 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2165978949 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc ratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.2165978949
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/7.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/7.rv_dm_buffered_enable.536640327
Short name	T208
Test name
Test status
Simulation time	727793556 ps
CPU time	3.19 seconds
Started	Aug 21 07:33:40 PM UTC 24
Finished	Aug 21 07:33:44 PM UTC 24
Peak memory	252700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=536640327 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_buffered_enable.536640327
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/7.rv_dm_buffered_enable/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3729524942
Short name	T241
Test name
Test status
Simulation time	3973885051 ps
CPU time	10.89 seconds
Started	Aug 21 07:33:39 PM UTC 24
Finished	Aug 21 07:33:50 PM UTC 24
Peak memory	216252 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3729524942 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba _tl_access.3729524942
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.2974620527
Short name	T66
Test name
Test status
Simulation time	1236736731 ps
CPU time	1.68 seconds
Started	Aug 21 07:33:40 PM UTC 24
Finished	Aug 21 07:33:42 PM UTC 24
Peak memory	213464 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2974620527 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/ scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_halt_resume_whereto.2974620527
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/7.rv_dm_halt_resume_whereto/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/7.rv_dm_sba_tl_access.267398101
Short name	T242
Test name
Test status
Simulation time	12500860536 ps
CPU time	11.32 seconds
Started	Aug 21 07:33:39 PM UTC 24
Finished	Aug 21 07:33:51 PM UTC 24
Peak memory	226644 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=267398101 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch /earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.267398101
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/7.rv_dm_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all.3641226359
Short name	T29
Test name
Test status
Simulation time	1788499851 ps
CPU time	4.34 seconds
Started	Aug 21 07:33:41 PM UTC 24
Finished	Aug 21 07:33:46 PM UTC 24
Peak memory	216136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3641226359 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.3641226359
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/7.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.1803097680
Short name	T69
Test name
Test status
Simulation time	279044725 ps
CPU time	7.37 seconds
Started	Aug 21 07:33:41 PM UTC 24
Finished	Aug 21 07:33:50 PM UTC 24
Peak memory	226536 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100000 00000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/low risc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1803097680 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all_with_rand_reset.1803097680
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/8.rv_dm_alert_test.1737626780
Short name	T229
Test name
Test status
Simulation time	39978424 ps
CPU time	1.15 seconds
Started	Aug 21 07:33:44 PM UTC 24
Finished	Aug 21 07:33:46 PM UTC 24
Peak memory	215952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1737626780 -asser t nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.1737626780
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/8.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.3856417233
Short name	T318
Test name
Test status
Simulation time	18002017354 ps
CPU time	51.25 seconds
Started	Aug 21 07:33:42 PM UTC 24
Finished	Aug 21 07:34:35 PM UTC 24
Peak memory	226452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3856417233 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit an/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.3856417233
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/8.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/8.rv_dm_bad_sba_tl_access.931209834
Short name	T226
Test name
Test status
Simulation time	2295382004 ps
CPU time	2.72 seconds
Started	Aug 21 07:33:42 PM UTC 24
Finished	Aug 21 07:33:46 PM UTC 24
Peak memory	216208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=931209834 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.931209834
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/8.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/8.rv_dm_buffered_enable.646170157
Short name	T209
Test name
Test status
Simulation time	264056338 ps
CPU time	1.67 seconds
Started	Aug 21 07:33:42 PM UTC 24
Finished	Aug 21 07:33:45 PM UTC 24
Peak memory	244496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=646170157 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_buffered_enable.646170157
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/8.rv_dm_buffered_enable/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.624577899
Short name	T120
Test name
Test status
Simulation time	4402713202 ps
CPU time	6.23 seconds
Started	Aug 21 07:33:41 PM UTC 24
Finished	Aug 21 07:33:48 PM UTC 24
Peak memory	226512 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=624577899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_ tl_access.624577899
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/8.rv_dm_sba_tl_access.1585870924
Short name	T116
Test name
Test status
Simulation time	6051341128 ps
CPU time	4.87 seconds
Started	Aug 21 07:33:41 PM UTC 24
Finished	Aug 21 07:33:47 PM UTC 24
Peak memory	216416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1585870924 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc h/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.1585870924
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/8.rv_dm_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.2235416271
Short name	T119
Test name
Test status
Simulation time	2827933089 ps
CPU time	5.07 seconds
Started	Aug 21 07:33:42 PM UTC 24
Finished	Aug 21 07:33:48 PM UTC 24
Peak memory	226200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2235416271 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.2235416271
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/8.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.2452372
Short name	T34
Test name
Test status
Simulation time	4973962181 ps
CPU time	45.32 seconds
Started	Aug 21 07:33:43 PM UTC 24
Finished	Aug 21 07:34:30 PM UTC 24
Peak memory	233344 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100000 00000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/low risc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2452372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all_with_rand_reset.2452372
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.2579015615
Short name	T118
Test name
Test status
Simulation time	96992327 ps
CPU time	0.9 seconds
Started	Aug 21 07:33:46 PM UTC 24
Finished	Aug 21 07:33:48 PM UTC 24
Peak memory	216020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2579015615 -asser t nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.2579015615
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/9.rv_dm_alert_test/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/9.rv_dm_autoincr_sba_tl_access.664177588
Short name	T277
Test name
Test status
Simulation time	13121054765 ps
CPU time	26.73 seconds
Started	Aug 21 07:33:45 PM UTC 24
Finished	Aug 21 07:34:13 PM UTC 24
Peak memory	226464 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=664177588 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.664177588
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/9.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.1115306730
Short name	T239
Test name
Test status
Simulation time	2906350325 ps
CPU time	4.76 seconds
Started	Aug 21 07:33:44 PM UTC 24
Finished	Aug 21 07:33:50 PM UTC 24
Peak memory	216204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1115306730 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc ratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.1115306730
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/9.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/9.rv_dm_buffered_enable.4084342221
Short name	T73
Test name
Test status
Simulation time	316794557 ps
CPU time	2.05 seconds
Started	Aug 21 07:33:45 PM UTC 24
Finished	Aug 21 07:33:48 PM UTC 24
Peak memory	258780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4084342221 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra tch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_buffered_enable.4084342221
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/9.rv_dm_buffered_enable/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.3466474603
Short name	T253
Test name
Test status
Simulation time	4646822145 ps
CPU time	16.9 seconds
Started	Aug 21 07:33:44 PM UTC 24
Finished	Aug 21 07:34:02 PM UTC 24
Peak memory	226624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3466474603 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba _tl_access.3466474603
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.3593933065
Short name	T245
Test name
Test status
Simulation time	2919416428 ps
CPU time	9.83 seconds
Started	Aug 21 07:33:44 PM UTC 24
Finished	Aug 21 07:33:54 PM UTC 24
Peak memory	216340 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3593933065 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc h/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.3593933065
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/9.rv_dm_sba_tl_access/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.1225368386
Short name	T88
Test name
Test status
Simulation time	3686699252 ps
CPU time	4.05 seconds
Started	Aug 21 07:33:45 PM UTC 24
Finished	Aug 21 07:33:50 PM UTC 24
Peak memory	226264 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1225368386 -as sert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.1225368386
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/9.rv_dm_stress_all/latest

Test location	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.2034645341
Short name	T108
Test name
Test status
Simulation time	10213807765 ps
CPU time	45.68 seconds
Started	Aug 21 07:33:45 PM UTC 24
Finished	Aug 21 07:34:32 PM UTC 24
Peak memory	233276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100000 00000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/low risc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2034645341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all_with_rand_reset.2034645341
Directory	/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest