Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.96	96.32	89.67	92.10	94.67	90.27	98.53	61.18

Total test records in report: 483

T22	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.3137181366	Aug 25 05:53:09 AM UTC 24	Aug 25 05:54:33 AM UTC 24	12322412001 ps
T324	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/42.rv_dm_stress_all.1804185941	Aug 25 05:54:13 AM UTC 24	Aug 25 05:54:38 AM UTC 24	3703791965 ps
T32	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/35.rv_dm_stress_all.3786252823	Aug 25 05:54:10 AM UTC 24	Aug 25 05:54:39 AM UTC 24	8057235851 ps
T325	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/15.rv_dm_autoincr_sba_tl_access.996097941	Aug 25 05:53:36 AM UTC 24	Aug 25 05:54:39 AM UTC 24	11057681539 ps
T116	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.3989409814	Aug 25 05:52:31 AM UTC 24	Aug 25 05:54:41 AM UTC 24	3970376010 ps
T119	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.3909288218	Aug 25 05:52:37 AM UTC 24	Aug 25 05:54:43 AM UTC 24	10505710696 ps
T326	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/48.rv_dm_stress_all.1217333347	Aug 25 05:54:18 AM UTC 24	Aug 25 05:54:44 AM UTC 24	5006554766 ps
T327	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.625657124	Aug 25 05:53:56 AM UTC 24	Aug 25 05:54:46 AM UTC 24	11331663414 ps
T328	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/37.rv_dm_stress_all.4229348764	Aug 25 05:54:10 AM UTC 24	Aug 25 05:54:50 AM UTC 24	6881205969 ps
T329	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.3358295993	Aug 25 05:53:56 AM UTC 24	Aug 25 05:54:50 AM UTC 24	50135492153 ps
T330	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/16.rv_dm_autoincr_sba_tl_access.1732223248	Aug 25 05:53:41 AM UTC 24	Aug 25 05:54:51 AM UTC 24	14648918223 ps
T331	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.2919295492	Aug 25 05:52:51 AM UTC 24	Aug 25 05:54:56 AM UTC 24	21821579813 ps
T332	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/18.rv_dm_autoincr_sba_tl_access.2649126593	Aug 25 05:53:50 AM UTC 24	Aug 25 05:56:11 AM UTC 24	28514582613 ps
T103	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1508120499	Aug 25 05:48:23 AM UTC 24	Aug 25 05:48:25 AM UTC 24	367703666 ps
T104	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1833230647	Aug 25 05:48:23 AM UTC 24	Aug 25 05:48:25 AM UTC 24	163575695 ps
T105	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2795218621	Aug 25 05:48:23 AM UTC 24	Aug 25 05:48:27 AM UTC 24	310152688 ps
T333	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2247995802	Aug 25 05:48:27 AM UTC 24	Aug 25 05:48:30 AM UTC 24	51099497 ps
T334	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.414888350	Aug 25 05:48:26 AM UTC 24	Aug 25 05:48:34 AM UTC 24	1173226661 ps
T169	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.272606505	Aug 25 05:48:31 AM UTC 24	Aug 25 05:48:41 AM UTC 24	386132956 ps
T335	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.3137153737	Aug 25 05:48:42 AM UTC 24	Aug 25 05:48:44 AM UTC 24	32545250 ps
T336	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3286933911	Aug 25 05:48:23 AM UTC 24	Aug 25 05:48:44 AM UTC 24	10218245277 ps
T337	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.424480425	Aug 25 05:48:44 AM UTC 24	Aug 25 05:48:46 AM UTC 24	90056789 ps
T125	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.655012639	Aug 25 05:48:45 AM UTC 24	Aug 25 05:48:48 AM UTC 24	142342884 ps
T126	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.1591281334	Aug 25 05:48:45 AM UTC 24	Aug 25 05:48:49 AM UTC 24	681500696 ps
T174	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1122269995	Aug 25 05:48:35 AM UTC 24	Aug 25 05:48:49 AM UTC 24	719886756 ps
T338	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3339391174	Aug 25 05:48:50 AM UTC 24	Aug 25 05:48:55 AM UTC 24	190804830 ps
T339	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1872702779	Aug 25 05:48:55 AM UTC 24	Aug 25 05:48:57 AM UTC 24	274921918 ps
T340	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1462895337	Aug 25 05:48:52 AM UTC 24	Aug 25 05:48:59 AM UTC 24	1421280493 ps
T127	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1791721876	Aug 25 05:48:49 AM UTC 24	Aug 25 05:49:00 AM UTC 24	989369450 ps
T341	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.4088255426	Aug 25 05:48:58 AM UTC 24	Aug 25 05:49:01 AM UTC 24	1180709481 ps
T128	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2881131622	Aug 25 05:48:22 AM UTC 24	Aug 25 05:49:05 AM UTC 24	9302367312 ps
T342	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3615201577	Aug 25 05:49:01 AM UTC 24	Aug 25 05:49:10 AM UTC 24	4750956672 ps
T343	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.1782573961	Aug 25 05:49:05 AM UTC 24	Aug 25 05:49:11 AM UTC 24	526725565 ps
T138	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1882435331	Aug 25 05:48:26 AM UTC 24	Aug 25 05:49:13 AM UTC 24	9015146305 ps
T344	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.330760962	Aug 25 05:49:11 AM UTC 24	Aug 25 05:49:14 AM UTC 24	71866080 ps
T345	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1179909639	Aug 25 05:49:13 AM UTC 24	Aug 25 05:49:15 AM UTC 24	78848891 ps
T129	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.4156193765	Aug 25 05:49:15 AM UTC 24	Aug 25 05:49:18 AM UTC 24	208980170 ps
T130	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2664399032	Aug 25 05:49:15 AM UTC 24	Aug 25 05:49:19 AM UTC 24	372097618 ps
T346	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1942062938	Aug 25 05:49:20 AM UTC 24	Aug 25 05:49:22 AM UTC 24	198024670 ps
T170	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3485999912	Aug 25 05:49:20 AM UTC 24	Aug 25 05:49:24 AM UTC 24	108303739 ps
T139	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1041977036	Aug 25 05:48:58 AM UTC 24	Aug 25 05:49:25 AM UTC 24	4482105440 ps
T347	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.4255392322	Aug 25 05:49:23 AM UTC 24	Aug 25 05:49:26 AM UTC 24	360033338 ps
T131	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2668399898	Aug 25 05:49:19 AM UTC 24	Aug 25 05:49:30 AM UTC 24	640085509 ps
T348	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2703316603	Aug 25 05:49:26 AM UTC 24	Aug 25 05:49:30 AM UTC 24	265035252 ps
T349	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1733974310	Aug 25 05:48:29 AM UTC 24	Aug 25 05:49:36 AM UTC 24	28741194350 ps
T350	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1853776848	Aug 25 05:49:25 AM UTC 24	Aug 25 05:49:40 AM UTC 24	19360188368 ps
T171	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.570373970	Aug 25 05:49:11 AM UTC 24	Aug 25 05:49:42 AM UTC 24	3910722241 ps
T351	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2643084921	Aug 25 05:49:00 AM UTC 24	Aug 25 05:49:43 AM UTC 24	7269013870 ps
T352	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_walk.333748836	Aug 25 05:49:43 AM UTC 24	Aug 25 05:49:45 AM UTC 24	76482848 ps
T132	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1392791291	Aug 25 05:48:47 AM UTC 24	Aug 25 05:49:46 AM UTC 24	3751202803 ps
T353	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_partial_access.851674132	Aug 25 05:49:44 AM UTC 24	Aug 25 05:49:46 AM UTC 24	71028313 ps
T133	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.392737094	Aug 25 05:49:44 AM UTC 24	Aug 25 05:49:48 AM UTC 24	288413459 ps
T172	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_errors.1896859560	Aug 25 05:49:41 AM UTC 24	Aug 25 05:49:48 AM UTC 24	431903164 ps
T134	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_rw.3691634189	Aug 25 05:49:47 AM UTC 24	Aug 25 05:49:50 AM UTC 24	56717697 ps
T354	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.2724008536	Aug 25 05:49:49 AM UTC 24	Aug 25 05:49:53 AM UTC 24	264504633 ps
T355	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3815656393	Aug 25 05:49:51 AM UTC 24	Aug 25 05:49:56 AM UTC 24	535661410 ps
T356	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3768814651	Aug 25 05:49:54 AM UTC 24	Aug 25 05:49:58 AM UTC 24	223354656 ps
T140	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2131240853	Aug 25 05:49:27 AM UTC 24	Aug 25 05:49:58 AM UTC 24	10493963649 ps
T108	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.3283597565	Aug 25 05:49:37 AM UTC 24	Aug 25 05:50:01 AM UTC 24	867546342 ps
T143	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3678943696	Aug 25 05:49:48 AM UTC 24	Aug 25 05:50:01 AM UTC 24	529861955 ps
T357	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1488967488	Aug 25 05:49:59 AM UTC 24	Aug 25 05:50:03 AM UTC 24	2198178884 ps
T144	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3174630771	Aug 25 05:49:20 AM UTC 24	Aug 25 05:50:06 AM UTC 24	15176098823 ps
T173	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3238655014	Aug 25 05:49:16 AM UTC 24	Aug 25 05:50:06 AM UTC 24	3334695123 ps
T358	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1146453803	Aug 25 05:49:31 AM UTC 24	Aug 25 05:50:08 AM UTC 24	6032874454 ps
T85	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1742434170	Aug 25 05:48:31 AM UTC 24	Aug 25 05:50:10 AM UTC 24	15169185696 ps
T359	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_walk.2217083831	Aug 25 05:50:08 AM UTC 24	Aug 25 05:50:10 AM UTC 24	131683184 ps
T141	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3452612638	Aug 25 05:49:59 AM UTC 24	Aug 25 05:50:11 AM UTC 24	12622601492 ps
T360	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1515615658	Aug 25 05:48:56 AM UTC 24	Aug 25 05:50:12 AM UTC 24	14512018817 ps
T361	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_partial_access.8721548	Aug 25 05:50:11 AM UTC 24	Aug 25 05:50:14 AM UTC 24	45228351 ps
T362	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_errors.376622667	Aug 25 05:50:07 AM UTC 24	Aug 25 05:50:15 AM UTC 24	83630460 ps
T145	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_rw.2282027581	Aug 25 05:50:12 AM UTC 24	Aug 25 05:50:16 AM UTC 24	145116218 ps
T146	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.874843599	Aug 25 05:50:11 AM UTC 24	Aug 25 05:50:16 AM UTC 24	686582929 ps
T363	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1939744377	Aug 25 05:50:01 AM UTC 24	Aug 25 05:50:16 AM UTC 24	1837321269 ps
T175	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.243114783	Aug 25 05:49:42 AM UTC 24	Aug 25 05:50:16 AM UTC 24	4674123652 ps
T364	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1380641306	Aug 25 05:49:56 AM UTC 24	Aug 25 05:50:16 AM UTC 24	8132283216 ps
T109	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.125651181	Aug 25 05:50:15 AM UTC 24	Aug 25 05:50:19 AM UTC 24	89640308 ps
T365	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1212554405	Aug 25 05:50:16 AM UTC 24	Aug 25 05:50:20 AM UTC 24	464113549 ps
T366	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.893124409	Aug 25 05:50:18 AM UTC 24	Aug 25 05:50:20 AM UTC 24	246788966 ps
T162	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3922831294	Aug 25 05:50:14 AM UTC 24	Aug 25 05:50:21 AM UTC 24	798420320 ps
T367	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3072851456	Aug 25 05:50:18 AM UTC 24	Aug 25 05:50:22 AM UTC 24	529184984 ps
T147	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_aliasing.4171618479	Aug 25 05:49:49 AM UTC 24	Aug 25 05:50:24 AM UTC 24	2148096055 ps
T368	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1149690047	Aug 25 05:49:02 AM UTC 24	Aug 25 05:50:29 AM UTC 24	26655071367 ps
T369	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_walk.2949457607	Aug 25 05:50:27 AM UTC 24	Aug 25 05:50:30 AM UTC 24	144655001 ps
T370	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.370088606	Aug 25 05:50:20 AM UTC 24	Aug 25 05:50:31 AM UTC 24	3619156768 ps
T371	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_errors.1727838489	Aug 25 05:50:23 AM UTC 24	Aug 25 05:50:32 AM UTC 24	518501877 ps
T372	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_partial_access.935241690	Aug 25 05:50:30 AM UTC 24	Aug 25 05:50:32 AM UTC 24	124525122 ps
T193	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2263821178	Aug 25 05:50:07 AM UTC 24	Aug 25 05:50:35 AM UTC 24	1246749295 ps
T154	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2377461035	Aug 25 05:50:30 AM UTC 24	Aug 25 05:50:36 AM UTC 24	389708501 ps
T373	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3580042097	Aug 25 05:50:34 AM UTC 24	Aug 25 05:50:36 AM UTC 24	319788437 ps
T374	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_rw.1894824442	Aug 25 05:50:32 AM UTC 24	Aug 25 05:50:36 AM UTC 24	444867599 ps
T155	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1887309615	Aug 25 05:49:47 AM UTC 24	Aug 25 05:50:37 AM UTC 24	6366510014 ps
T375	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.4144862304	Aug 25 05:50:35 AM UTC 24	Aug 25 05:50:37 AM UTC 24	71133010 ps
T113	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3205598261	Aug 25 05:50:34 AM UTC 24	Aug 25 05:50:39 AM UTC 24	213212355 ps
T197	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1750716366	Aug 25 05:50:24 AM UTC 24	Aug 25 05:50:39 AM UTC 24	487113429 ps
T114	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.733609407	Aug 25 05:49:05 AM UTC 24	Aug 25 05:50:41 AM UTC 24	4874068243 ps
T376	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_rw.1336546686	Aug 25 05:50:38 AM UTC 24	Aug 25 05:50:42 AM UTC 24	583982639 ps
T377	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.866656072	Aug 25 05:50:40 AM UTC 24	Aug 25 05:50:43 AM UTC 24	358728592 ps
T148	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1771759454	Aug 25 05:50:38 AM UTC 24	Aug 25 05:50:44 AM UTC 24	353711342 ps
T378	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_errors.600545986	Aug 25 05:50:37 AM UTC 24	Aug 25 05:50:45 AM UTC 24	745528255 ps
T379	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3957396517	Aug 25 05:50:40 AM UTC 24	Aug 25 05:50:45 AM UTC 24	986514787 ps
T149	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.990264025	Aug 25 05:48:50 AM UTC 24	Aug 25 05:50:45 AM UTC 24	10315699777 ps
T163	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1175838163	Aug 25 05:50:34 AM UTC 24	Aug 25 05:50:46 AM UTC 24	539322649 ps
T380	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2928171052	Aug 25 05:50:13 AM UTC 24	Aug 25 05:50:50 AM UTC 24	783733760 ps
T381	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_rw.3943306757	Aug 25 05:50:46 AM UTC 24	Aug 25 05:50:51 AM UTC 24	294902996 ps
T382	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2131659232	Aug 25 05:50:47 AM UTC 24	Aug 25 05:50:51 AM UTC 24	695655401 ps
T383	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_errors.4080071511	Aug 25 05:50:45 AM UTC 24	Aug 25 05:50:52 AM UTC 24	70707819 ps
T194	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1388779676	Aug 25 05:50:37 AM UTC 24	Aug 25 05:50:52 AM UTC 24	866308490 ps
T384	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.766584743	Aug 25 05:50:18 AM UTC 24	Aug 25 05:50:52 AM UTC 24	7106426762 ps
T385	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.25807843	Aug 25 05:50:50 AM UTC 24	Aug 25 05:50:53 AM UTC 24	486578269 ps
T386	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_errors.3589283763	Aug 25 05:50:53 AM UTC 24	Aug 25 05:50:57 AM UTC 24	393554336 ps
T387	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_rw.1183477317	Aug 25 05:50:54 AM UTC 24	Aug 25 05:50:57 AM UTC 24	46936810 ps
T164	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3356046658	Aug 25 05:50:46 AM UTC 24	Aug 25 05:50:57 AM UTC 24	5443413842 ps
T388	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.4085805032	Aug 25 05:50:21 AM UTC 24	Aug 25 05:51:00 AM UTC 24	20706302009 ps
T389	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3778768392	Aug 25 05:50:51 AM UTC 24	Aug 25 05:51:01 AM UTC 24	4517073390 ps
T390	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1029659505	Aug 25 05:50:58 AM UTC 24	Aug 25 05:51:02 AM UTC 24	350626765 ps
T115	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2630441124	Aug 25 05:50:58 AM UTC 24	Aug 25 05:51:03 AM UTC 24	48474941 ps
T150	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2990066836	Aug 25 05:50:54 AM UTC 24	Aug 25 05:51:03 AM UTC 24	424450976 ps
T391	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.807428385	Aug 25 05:49:35 AM UTC 24	Aug 25 05:51:05 AM UTC 24	25263765825 ps
T392	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.4024891990	Aug 25 05:49:31 AM UTC 24	Aug 25 05:51:05 AM UTC 24	32128735589 ps
T393	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3860374392	Aug 25 05:50:35 AM UTC 24	Aug 25 05:51:08 AM UTC 24	4574492434 ps
T394	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1247883478	Aug 25 05:51:01 AM UTC 24	Aug 25 05:51:08 AM UTC 24	8520637909 ps
T395	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_rw.682463120	Aug 25 05:51:04 AM UTC 24	Aug 25 05:51:08 AM UTC 24	71157689 ps
T396	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2841899263	Aug 25 05:50:42 AM UTC 24	Aug 25 05:51:08 AM UTC 24	8093757029 ps
T397	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_errors.3654412716	Aug 25 05:51:02 AM UTC 24	Aug 25 05:51:09 AM UTC 24	369084905 ps
T398	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2531484961	Aug 25 05:51:07 AM UTC 24	Aug 25 05:51:09 AM UTC 24	178345853 ps
T399	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1684670898	Aug 25 05:50:58 AM UTC 24	Aug 25 05:51:09 AM UTC 24	7214749252 ps
T400	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2629792737	Aug 25 05:51:05 AM UTC 24	Aug 25 05:51:10 AM UTC 24	324220001 ps
T165	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2274193969	Aug 25 05:51:04 AM UTC 24	Aug 25 05:51:12 AM UTC 24	1547602453 ps
T199	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_intg_err.818574191	Aug 25 05:50:46 AM UTC 24	Aug 25 05:51:13 AM UTC 24	3098107271 ps
T156	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_rw.711137671	Aug 25 05:51:10 AM UTC 24	Aug 25 05:51:13 AM UTC 24	109314025 ps
T401	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1917569766	Aug 25 05:51:11 AM UTC 24	Aug 25 05:51:14 AM UTC 24	192014897 ps
T402	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_errors.2456679785	Aug 25 05:51:09 AM UTC 24	Aug 25 05:51:15 AM UTC 24	279839111 ps
T403	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2659196489	Aug 25 05:51:10 AM UTC 24	Aug 25 05:51:16 AM UTC 24	320017373 ps
T404	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.123424127	Aug 25 05:50:21 AM UTC 24	Aug 25 05:51:18 AM UTC 24	19183627073 ps
T405	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.2393223453	Aug 25 05:51:13 AM UTC 24	Aug 25 05:51:18 AM UTC 24	49587104 ps
T157	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.3227656526	Aug 25 05:51:14 AM UTC 24	Aug 25 05:51:18 AM UTC 24	157476935 ps
T200	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2123660583	Aug 25 05:50:53 AM UTC 24	Aug 25 05:51:18 AM UTC 24	2653587972 ps
T196	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3867368845	Aug 25 05:51:02 AM UTC 24	Aug 25 05:51:20 AM UTC 24	953069254 ps
T166	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2754108806	Aug 25 05:51:10 AM UTC 24	Aug 25 05:51:21 AM UTC 24	2856579032 ps
T406	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2160020648	Aug 25 05:51:19 AM UTC 24	Aug 25 05:51:22 AM UTC 24	703397421 ps
T407	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3746850745	Aug 25 05:51:11 AM UTC 24	Aug 25 05:51:22 AM UTC 24	7705913941 ps
T408	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3122879918	Aug 25 05:51:07 AM UTC 24	Aug 25 05:51:23 AM UTC 24	5990316507 ps
T409	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3814732626	Aug 25 05:51:17 AM UTC 24	Aug 25 05:51:23 AM UTC 24	200305818 ps
T151	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2877873439	Aug 25 05:51:15 AM UTC 24	Aug 25 05:51:25 AM UTC 24	306028828 ps
T410	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.4139753263	Aug 25 05:51:23 AM UTC 24	Aug 25 05:51:26 AM UTC 24	259123782 ps
T411	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_errors.3905211267	Aug 25 05:51:19 AM UTC 24	Aug 25 05:51:27 AM UTC 24	225400602 ps
T412	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_rw.2538646444	Aug 25 05:51:22 AM UTC 24	Aug 25 05:51:27 AM UTC 24	127790693 ps
T413	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3101280497	Aug 25 05:51:23 AM UTC 24	Aug 25 05:51:27 AM UTC 24	133530013 ps
T142	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2196180247	Aug 25 05:50:20 AM UTC 24	Aug 25 05:51:28 AM UTC 24	20277930903 ps
T202	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1232156037	Aug 25 05:51:14 AM UTC 24	Aug 25 05:51:30 AM UTC 24	1304827370 ps
T159	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_rw.4206887603	Aug 25 05:51:27 AM UTC 24	Aug 25 05:51:31 AM UTC 24	161209113 ps
T414	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.4057577334	Aug 25 05:51:24 AM UTC 24	Aug 25 05:51:32 AM UTC 24	2545684348 ps
T415	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.181187965	Aug 25 05:51:31 AM UTC 24	Aug 25 05:51:33 AM UTC 24	412015386 ps
T416	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_errors.123063740	Aug 25 05:51:26 AM UTC 24	Aug 25 05:51:34 AM UTC 24	258129320 ps
T417	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.95742743	Aug 25 05:51:29 AM UTC 24	Aug 25 05:51:34 AM UTC 24	52414399 ps
T418	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3592313016	Aug 25 05:51:23 AM UTC 24	Aug 25 05:51:35 AM UTC 24	1626968471 ps
T195	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_intg_err.648342981	Aug 25 05:51:10 AM UTC 24	Aug 25 05:51:36 AM UTC 24	1826903204 ps
T419	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3866166984	Aug 25 05:51:19 AM UTC 24	Aug 25 05:51:36 AM UTC 24	2963878499 ps
T420	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.1579322104	Aug 25 05:51:13 AM UTC 24	Aug 25 05:51:38 AM UTC 24	8606776304 ps
T421	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1146073213	Aug 25 05:51:32 AM UTC 24	Aug 25 05:51:38 AM UTC 24	1986469455 ps
T160	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.776568118	Aug 25 05:50:33 AM UTC 24	Aug 25 05:51:38 AM UTC 24	1506379709 ps
T422	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_rw.1805670702	Aug 25 05:51:35 AM UTC 24	Aug 25 05:51:39 AM UTC 24	270084484 ps
T423	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1688285860	Aug 25 05:51:37 AM UTC 24	Aug 25 05:51:40 AM UTC 24	614517585 ps
T152	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2054376394	Aug 25 05:51:29 AM UTC 24	Aug 25 05:51:40 AM UTC 24	971452371 ps
T424	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_errors.3533451961	Aug 25 05:51:34 AM UTC 24	Aug 25 05:51:40 AM UTC 24	286507626 ps
T425	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3041754803	Aug 25 05:51:36 AM UTC 24	Aug 25 05:51:41 AM UTC 24	214347040 ps
T153	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1972985674	Aug 25 05:51:35 AM UTC 24	Aug 25 05:51:42 AM UTC 24	226767048 ps
T426	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.466822328	Aug 25 05:50:36 AM UTC 24	Aug 25 05:51:42 AM UTC 24	2432189672 ps
T427	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1296166021	Aug 25 05:50:16 AM UTC 24	Aug 25 05:51:43 AM UTC 24	3437255396 ps
T161	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_rw.3420941774	Aug 25 05:51:40 AM UTC 24	Aug 25 05:51:44 AM UTC 24	149216106 ps
T428	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3351033368	Aug 25 05:51:09 AM UTC 24	Aug 25 05:51:44 AM UTC 24	22912526619 ps
T429	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.366181431	Aug 25 05:51:26 AM UTC 24	Aug 25 05:51:44 AM UTC 24	5169899585 ps
T430	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2020566852	Aug 25 05:51:42 AM UTC 24	Aug 25 05:51:44 AM UTC 24	225682234 ps
T431	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3786985834	Aug 25 05:51:09 AM UTC 24	Aug 25 05:51:44 AM UTC 24	2098260328 ps
T432	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.494945868	Aug 25 05:51:41 AM UTC 24	Aug 25 05:51:46 AM UTC 24	1065904310 ps
T433	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_errors.3838790815	Aug 25 05:51:39 AM UTC 24	Aug 25 05:51:47 AM UTC 24	200971716 ps
T201	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3479050267	Aug 25 05:51:21 AM UTC 24	Aug 25 05:51:47 AM UTC 24	4988583765 ps
T434	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_rw.1809388314	Aug 25 05:51:44 AM UTC 24	Aug 25 05:51:48 AM UTC 24	61014365 ps
T435	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3790182536	Aug 25 05:51:45 AM UTC 24	Aug 25 05:51:48 AM UTC 24	247851934 ps
T198	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2098240839	Aug 25 05:51:27 AM UTC 24	Aug 25 05:51:49 AM UTC 24	4693459482 ps
T436	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.3792919993	Aug 25 05:51:33 AM UTC 24	Aug 25 05:51:50 AM UTC 24	3238602600 ps
T437	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3848672587	Aug 25 05:51:45 AM UTC 24	Aug 25 05:51:52 AM UTC 24	165872272 ps
T438	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_errors.1906663832	Aug 25 05:51:48 AM UTC 24	Aug 25 05:51:52 AM UTC 24	173893303 ps
T439	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_rw.3687178305	Aug 25 05:51:49 AM UTC 24	Aug 25 05:51:52 AM UTC 24	133463657 ps
T440	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.76054568	Aug 25 05:51:50 AM UTC 24	Aug 25 05:51:53 AM UTC 24	109762889 ps
T441	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_errors.4206387239	Aug 25 05:51:43 AM UTC 24	Aug 25 05:51:53 AM UTC 24	858058200 ps
T442	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2059739316	Aug 25 05:51:45 AM UTC 24	Aug 25 05:51:53 AM UTC 24	634630764 ps
T443	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1108201446	Aug 25 05:51:41 AM UTC 24	Aug 25 05:51:53 AM UTC 24	7589761127 ps
T106	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.2300478260	Aug 25 05:50:44 AM UTC 24	Aug 25 05:51:54 AM UTC 24	6794602119 ps
T444	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1215218012	Aug 25 05:51:42 AM UTC 24	Aug 25 05:51:54 AM UTC 24	5996765541 ps
T445	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3549526717	Aug 25 05:51:49 AM UTC 24	Aug 25 05:51:54 AM UTC 24	393969183 ps
T446	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1114421559	Aug 25 05:51:49 AM UTC 24	Aug 25 05:51:55 AM UTC 24	431495990 ps
T447	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_intg_err.862556475	Aug 25 05:51:34 AM UTC 24	Aug 25 05:51:55 AM UTC 24	2201832177 ps
T448	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3273975209	Aug 25 05:51:37 AM UTC 24	Aug 25 05:51:56 AM UTC 24	6128603366 ps
T449	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.903720287	Aug 25 05:51:55 AM UTC 24	Aug 25 05:51:57 AM UTC 24	124203494 ps
T450	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1313381884	Aug 25 05:51:44 AM UTC 24	Aug 25 05:51:57 AM UTC 24	2019095770 ps
T451	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_rw.2120528096	Aug 25 05:51:53 AM UTC 24	Aug 25 05:51:57 AM UTC 24	84851625 ps
T452	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3887266341	Aug 25 05:51:55 AM UTC 24	Aug 25 05:51:59 AM UTC 24	80704687 ps
T453	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_rw.1599982557	Aug 25 05:51:56 AM UTC 24	Aug 25 05:52:01 AM UTC 24	130588248 ps
T454	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2220894656	Aug 25 05:51:58 AM UTC 24	Aug 25 05:52:01 AM UTC 24	249559475 ps
T455	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_errors.1774934986	Aug 25 05:51:52 AM UTC 24	Aug 25 05:52:01 AM UTC 24	371993895 ps
T456	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1179131881	Aug 25 05:51:57 AM UTC 24	Aug 25 05:52:01 AM UTC 24	121823043 ps
T457	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.2947155764	Aug 25 05:51:52 AM UTC 24	Aug 25 05:52:02 AM UTC 24	10460706304 ps
T458	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_errors.923982473	Aug 25 05:51:56 AM UTC 24	Aug 25 05:52:02 AM UTC 24	261589081 ps
T112	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.1788947275	Aug 25 05:50:22 AM UTC 24	Aug 25 05:52:03 AM UTC 24	5086796827 ps
T459	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.270914906	Aug 25 05:51:43 AM UTC 24	Aug 25 05:52:05 AM UTC 24	8570406342 ps
T460	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1576923387	Aug 25 05:50:04 AM UTC 24	Aug 25 05:52:05 AM UTC 24	50315911185 ps
T461	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1207893576	Aug 25 05:51:55 AM UTC 24	Aug 25 05:52:05 AM UTC 24	1679535309 ps
T462	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3436415314	Aug 25 05:51:45 AM UTC 24	Aug 25 05:52:05 AM UTC 24	7001389580 ps
T463	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.4189650465	Aug 25 05:51:51 AM UTC 24	Aug 25 05:52:06 AM UTC 24	2226766757 ps
T158	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_rw.3934218130	Aug 25 05:52:02 AM UTC 24	Aug 25 05:52:06 AM UTC 24	438595540 ps
T464	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2788098464	Aug 25 05:51:54 AM UTC 24	Aug 25 05:52:06 AM UTC 24	2582724095 ps
T465	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_errors.2171597391	Aug 25 05:52:00 AM UTC 24	Aug 25 05:52:06 AM UTC 24	138350349 ps
T466	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3985055286	Aug 25 05:51:01 AM UTC 24	Aug 25 05:52:07 AM UTC 24	5134092486 ps
T467	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3620070887	Aug 25 05:51:56 AM UTC 24	Aug 25 05:52:07 AM UTC 24	399624969 ps
T468	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.454189699	Aug 25 05:52:03 AM UTC 24	Aug 25 05:52:08 AM UTC 24	64067388 ps
T469	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.4237232100	Aug 25 05:52:02 AM UTC 24	Aug 25 05:52:08 AM UTC 24	435195490 ps
T470	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1720701166	Aug 25 05:51:39 AM UTC 24	Aug 25 05:52:12 AM UTC 24	4794950058 ps
T471	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3748198176	Aug 25 05:51:56 AM UTC 24	Aug 25 05:52:13 AM UTC 24	2885559184 ps
T472	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2288041971	Aug 25 05:52:01 AM UTC 24	Aug 25 05:52:16 AM UTC 24	1910746538 ps
T473	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.755082630	Aug 25 05:51:58 AM UTC 24	Aug 25 05:52:16 AM UTC 24	5982855325 ps
T474	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.3567330221	Aug 25 05:51:58 AM UTC 24	Aug 25 05:52:17 AM UTC 24	5470982764 ps
T203	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.709809160	Aug 25 05:51:52 AM UTC 24	Aug 25 05:52:18 AM UTC 24	2862717013 ps
T475	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.4149162248	Aug 25 05:51:48 AM UTC 24	Aug 25 05:52:25 AM UTC 24	5146782209 ps
T110	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3593706507	Aug 25 05:50:04 AM UTC 24	Aug 25 05:52:37 AM UTC 24	12218189288 ps
T476	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1907223703	Aug 25 05:50:02 AM UTC 24	Aug 25 05:52:46 AM UTC 24	33196470168 ps
T477	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.4257151288	Aug 25 05:51:19 AM UTC 24	Aug 25 05:52:46 AM UTC 24	13581300939 ps
T478	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.316437194	Aug 25 05:50:52 AM UTC 24	Aug 25 05:53:13 AM UTC 24	3999196237 ps
T479	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.3094893678	Aug 25 05:51:47 AM UTC 24	Aug 25 05:53:26 AM UTC 24	87294659590 ps
T480	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.923910140	Aug 25 05:50:43 AM UTC 24	Aug 25 05:53:30 AM UTC 24	37611498740 ps
T481	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.15234641	Aug 25 05:51:55 AM UTC 24	Aug 25 05:53:39 AM UTC 24	18904415083 ps
T482	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1929753466	Aug 25 05:50:51 AM UTC 24	Aug 25 05:57:24 AM UTC 24	72233839773 ps
T483	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3263364840	Aug 25 05:51:38 AM UTC 24	Aug 25 05:57:52 AM UTC 24	67736354451 ps

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all.1338895452
Short name	T1
Test name
Test status
Simulation time	2632471771 ps
CPU time	3.63 seconds
Started	Aug 25 05:52:27 AM UTC 24
Finished	Aug 25 05:52:32 AM UTC 24
Peak memory	226384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338895452 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.1338895452
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/2.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.3953275785
Short name	T66
Test name
Test status
Simulation time	3768738202 ps
CPU time	43.99 seconds
Started	Aug 25 05:52:25 AM UTC 24
Finished	Aug 25 05:53:10 AM UTC 24
Peak memory	226512 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3953275785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stres s_all_with_rand_reset.3953275785
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.1245947270
Short name	T37
Test name
Test status
Simulation time	3118469359 ps
CPU time	9.6 seconds
Started	Aug 25 05:52:06 AM UTC 24
Finished	Aug 25 05:52:17 AM UTC 24
Peak memory	226568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245947270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.1245947270
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.3455560788
Short name	T30
Test name
Test status
Simulation time	4060019047 ps
CPU time	26.08 seconds
Started	Aug 25 05:52:15 AM UTC 24
Finished	Aug 25 05:52:42 AM UTC 24
Peak memory	216008 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455560788 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.3455560788
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1742434170
Short name	T85
Test name
Test status
Simulation time	15169185696 ps
CPU time	95.78 seconds
Started	Aug 25 05:48:31 AM UTC 24
Finished	Aug 25 05:50:10 AM UTC 24
Peak memory	229960 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1742434170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_re set.1742434170
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.570373970
Short name	T171
Test name
Test status
Simulation time	3910722241 ps
CPU time	29.32 seconds
Started	Aug 25 05:49:11 AM UTC 24
Finished	Aug 25 05:49:42 AM UTC 24
Peak memory	231968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570373970 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.570373970
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.1109187789
Short name	T86
Test name
Test status
Simulation time	7568604952 ps
CPU time	21.39 seconds
Started	Aug 25 05:52:03 AM UTC 24
Finished	Aug 25 05:52:26 AM UTC 24
Peak memory	216008 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109187789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.1109187789
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.3137181366
Short name	T22
Test name
Test status
Simulation time	12322412001 ps
CPU time	81.84 seconds
Started	Aug 25 05:53:09 AM UTC 24
Finished	Aug 25 05:54:33 AM UTC 24
Peak memory	243584 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3137181366 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stres s_all_with_rand_reset.3137181366
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/18.rv_dm_autoincr_sba_tl_access.2649126593
Short name	T332
Test name
Test status
Simulation time	28514582613 ps
CPU time	138.75 seconds
Started	Aug 25 05:53:50 AM UTC 24
Finished	Aug 25 05:56:11 AM UTC 24
Peak memory	226508 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649126593 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.2649126593
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/18.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.3371745816
Short name	T78
Test name
Test status
Simulation time	147917412 ps
CPU time	1.66 seconds
Started	Aug 25 05:52:27 AM UTC 24
Finished	Aug 25 05:52:30 AM UTC 24
Peak memory	252064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371745816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_buffered_enable.3371745816
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/2.rv_dm_buffered_enable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.2027476464
Short name	T107
Test name
Test status
Simulation time	2122554007 ps
CPU time	74.11 seconds
Started	Aug 25 05:52:56 AM UTC 24
Finished	Aug 25 05:54:13 AM UTC 24
Peak memory	233196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2027476464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stres s_all_with_rand_reset.2027476464
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.2786647215
Short name	T47
Test name
Test status
Simulation time	1272226726 ps
CPU time	5.76 seconds
Started	Aug 25 05:52:16 AM UTC 24
Finished	Aug 25 05:52:22 AM UTC 24
Peak memory	254760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786647215 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.2786647215
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.3215590359
Short name	T91
Test name
Test status
Simulation time	12920736 ps
CPU time	0.96 seconds
Started	Aug 25 05:52:14 AM UTC 24
Finished	Aug 25 05:52:17 AM UTC 24
Peak memory	213348 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215590359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_scanmode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 0.rv_dm_scanmode.3215590359
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_scanmode/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.1937796344
Short name	T80
Test name
Test status
Simulation time	260727729 ps
CPU time	1.92 seconds
Started	Aug 25 05:52:14 AM UTC 24
Finished	Aug 25 05:52:17 AM UTC 24
Peak memory	213464 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937796344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.1937796344
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_dmi_failed_op/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.3487838404
Short name	T39
Test name
Test status
Simulation time	290799008 ps
CPU time	1.22 seconds
Started	Aug 25 05:52:10 AM UTC 24
Finished	Aug 25 05:52:12 AM UTC 24
Peak memory	213452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487838404 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.3487838404
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_halt_resume_whereto/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.739667682
Short name	T184
Test name
Test status
Simulation time	19601674997 ps
CPU time	46.25 seconds
Started	Aug 25 05:52:30 AM UTC 24
Finished	Aug 25 05:53:18 AM UTC 24
Peak memory	226556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739667682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.739667682
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/3.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_aliasing.4171618479
Short name	T147
Test name
Test status
Simulation time	2148096055 ps
CPU time	33.47 seconds
Started	Aug 25 05:49:49 AM UTC 24
Finished	Aug 25 05:50:24 AM UTC 24
Peak memory	215524 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171618479 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_aliasing.4171618479
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/3.rv_dm_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.733609407
Short name	T114
Test name
Test status
Simulation time	4874068243 ps
CPU time	93.46 seconds
Started	Aug 25 05:49:05 AM UTC 24
Finished	Aug 25 05:50:41 AM UTC 24
Peak memory	230052 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=733609407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.733609407
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.3283597565
Short name	T108
Test name
Test status
Simulation time	867546342 ps
CPU time	22.55 seconds
Started	Aug 25 05:49:37 AM UTC 24
Finished	Aug 25 05:50:01 AM UTC 24
Peak memory	231936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3283597565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_re set.3283597565
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/2.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.901605082
Short name	T44
Test name
Test status
Simulation time	158644173 ps
CPU time	1.2 seconds
Started	Aug 25 05:52:17 AM UTC 24
Finished	Aug 25 05:52:19 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901605082 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.901605082
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.1846144463
Short name	T25
Test name
Test status
Simulation time	170662442 ps
CPU time	1.75 seconds
Started	Aug 25 05:52:07 AM UTC 24
Finished	Aug 25 05:52:10 AM UTC 24
Peak memory	215600 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846144463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.1846144463
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_cmderr_exception/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/4.rv_dm_autoincr_sba_tl_access.3413842179
Short name	T178
Test name
Test status
Simulation time	8387634259 ps
CPU time	31.83 seconds
Started	Aug 25 05:52:35 AM UTC 24
Finished	Aug 25 05:53:08 AM UTC 24
Peak memory	226564 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413842179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.3413842179
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/4.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.398662565
Short name	T317
Test name
Test status
Simulation time	1952577330 ps
CPU time	5.85 seconds
Started	Aug 25 05:54:16 AM UTC 24
Finished	Aug 25 05:54:23 AM UTC 24
Peak memory	215940 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398662565 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.398662565
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/46.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1122269995
Short name	T174
Test name
Test status
Simulation time	719886756 ps
CPU time	12.88 seconds
Started	Aug 25 05:48:35 AM UTC 24
Finished	Aug 25 05:48:49 AM UTC 24
Peak memory	225688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122269995 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.1122269995
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.2261878636
Short name	T63
Test name
Test status
Simulation time	147213067 ps
CPU time	1.39 seconds
Started	Aug 25 05:52:13 AM UTC 24
Finished	Aug 25 05:52:16 AM UTC 24
Peak memory	225796 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261878636 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_rom_read_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.2261878636
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_rom_read_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/16.rv_dm_autoincr_sba_tl_access.1732223248
Short name	T330
Test name
Test status
Simulation time	14648918223 ps
CPU time	67.76 seconds
Started	Aug 25 05:53:41 AM UTC 24
Finished	Aug 25 05:54:51 AM UTC 24
Peak memory	226476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732223248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.1732223248
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/16.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.3955140245
Short name	T54
Test name
Test status
Simulation time	3979677878 ps
CPU time	74.99 seconds
Started	Aug 25 05:52:43 AM UTC 24
Finished	Aug 25 05:54:00 AM UTC 24
Peak memory	230544 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3955140245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stres s_all_with_rand_reset.3955140245
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1791721876
Short name	T127
Test name
Test status
Simulation time	989369450 ps
CPU time	9.16 seconds
Started	Aug 25 05:48:49 AM UTC 24
Finished	Aug 25 05:49:00 AM UTC 24
Peak memory	215436 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791721876 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_csr_outstanding.1791721876
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2263821178
Short name	T193
Test name
Test status
Simulation time	1246749295 ps
CPU time	26.34 seconds
Started	Aug 25 05:50:07 AM UTC 24
Finished	Aug 25 05:50:35 AM UTC 24
Peak memory	225668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263821178 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.2263821178
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/3.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all.3954447197
Short name	T27
Test name
Test status
Simulation time	2492637030 ps
CPU time	5.4 seconds
Started	Aug 25 05:52:49 AM UTC 24
Finished	Aug 25 05:52:55 AM UTC 24
Peak memory	226404 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954447197 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.3954447197
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/6.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.3139046046
Short name	T15
Test name
Test status
Simulation time	819431669 ps
CPU time	4.14 seconds
Started	Aug 25 05:52:10 AM UTC 24
Finished	Aug 25 05:52:15 AM UTC 24
Peak memory	215948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139046046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.3139046046
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_sba_debug_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/14.rv_dm_stress_all.21394376
Short name	T68
Test name
Test status
Simulation time	1904296034 ps
CPU time	3.65 seconds
Started	Aug 25 05:53:34 AM UTC 24
Finished	Aug 25 05:53:39 AM UTC 24
Peak memory	216080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21394376 -assert nopostproc +UVM_TESTNAME=rv_ dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.21394376
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/14.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.1474232467
Short name	T185
Test name
Test status
Simulation time	3866308706 ps
CPU time	15.74 seconds
Started	Aug 25 05:52:41 AM UTC 24
Finished	Aug 25 05:52:58 AM UTC 24
Peak memory	228608 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474232467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.1474232467
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/5.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.3141444641
Short name	T40
Test name
Test status
Simulation time	152064656 ps
CPU time	1.32 seconds
Started	Aug 25 05:52:12 AM UTC 24
Finished	Aug 25 05:52:14 AM UTC 24
Peak memory	213456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141444641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_abstractcmd_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.3141444641
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_abstractcmd_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1508120499
Short name	T103
Test name
Test status
Simulation time	367703666 ps
CPU time	1.09 seconds
Started	Aug 25 05:48:23 AM UTC 24
Finished	Aug 25 05:48:25 AM UTC 24
Peak memory	214424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508120499 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_aliasing.1508120499
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1882435331
Short name	T138
Test name
Test status
Simulation time	9015146305 ps
CPU time	45.63 seconds
Started	Aug 25 05:48:26 AM UTC 24
Finished	Aug 25 05:49:13 AM UTC 24
Peak memory	215360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882435331 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_hw_reset.1882435331
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.1807683129
Short name	T35
Test name
Test status
Simulation time	333833127 ps
CPU time	3.14 seconds
Started	Aug 25 05:52:07 AM UTC 24
Finished	Aug 25 05:52:12 AM UTC 24
Peak memory	215804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807683129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.1807683129
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_cmderr_halt_resume/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2123660583
Short name	T200
Test name
Test status
Simulation time	2653587972 ps
CPU time	24.25 seconds
Started	Aug 25 05:50:53 AM UTC 24
Finished	Aug 25 05:51:18 AM UTC 24
Peak memory	225736 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123660583 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2123660583
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/7.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/12.rv_dm_bad_sba_tl_access.4040225370
Short name	T188
Test name
Test status
Simulation time	12396521851 ps
CPU time	32.65 seconds
Started	Aug 25 05:53:24 AM UTC 24
Finished	Aug 25 05:53:58 AM UTC 24
Peak memory	226548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040225370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.4040225370
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/12.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.1587364087
Short name	T58
Test name
Test status
Simulation time	5020290623 ps
CPU time	10.31 seconds
Started	Aug 25 05:52:36 AM UTC 24
Finished	Aug 25 05:52:48 AM UTC 24
Peak memory	226388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587364087 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.1587364087
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/4.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.3751831536
Short name	T43
Test name
Test status
Simulation time	335913771 ps
CPU time	1.75 seconds
Started	Aug 25 05:52:14 AM UTC 24
Finished	Aug 25 05:52:17 AM UTC 24
Peak memory	225764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751831536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sparse_lc_gate_fsm.3751831536
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_sparse_lc_gate_fsm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.1316188385
Short name	T48
Test name
Test status
Simulation time	52118435 ps
CPU time	1.4 seconds
Started	Aug 25 05:52:23 AM UTC 24
Finished	Aug 25 05:52:26 AM UTC 24
Peak memory	225856 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316188385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sparse_lc_gate_fsm.1316188385
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_sparse_lc_gate_fsm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2881131622
Short name	T128
Test name
Test status
Simulation time	9302367312 ps
CPU time	41.3 seconds
Started	Aug 25 05:48:22 AM UTC 24
Finished	Aug 25 05:49:05 AM UTC 24
Peak memory	225736 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881131622 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_aliasing.2881131622
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1392791291
Short name	T132
Test name
Test status
Simulation time	3751202803 ps
CPU time	57.1 seconds
Started	Aug 25 05:48:47 AM UTC 24
Finished	Aug 25 05:49:46 AM UTC 24
Peak memory	225768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392791291 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.1392791291
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.655012639
Short name	T125
Test name
Test status
Simulation time	142342884 ps
CPU time	2.11 seconds
Started	Aug 25 05:48:45 AM UTC 24
Finished	Aug 25 05:48:48 AM UTC 24
Peak memory	225624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655012639 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.655012639
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3339391174
Short name	T338
Test name
Test status
Simulation time	190804830 ps
CPU time	3.05 seconds
Started	Aug 25 05:48:50 AM UTC 24
Finished	Aug 25 05:48:55 AM UTC 24
Peak memory	229888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3339391174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_r and_reset.3339391174
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.1591281334
Short name	T126
Test name
Test status
Simulation time	681500696 ps
CPU time	2.77 seconds
Started	Aug 25 05:48:45 AM UTC 24
Finished	Aug 25 05:48:49 AM UTC 24
Peak memory	225692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591281334 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.1591281334
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1733974310
Short name	T349
Test name
Test status
Simulation time	28741194350 ps
CPU time	65.07 seconds
Started	Aug 25 05:48:29 AM UTC 24
Finished	Aug 25 05:49:36 AM UTC 24
Peak memory	215328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733974310 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_aliasing.1733974310
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2247995802
Short name	T333
Test name
Test status
Simulation time	51099497 ps
CPU time	1 seconds
Started	Aug 25 05:48:27 AM UTC 24
Finished	Aug 25 05:48:30 AM UTC 24
Peak memory	215144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247995802 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_bit_bash.2247995802
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.414888350
Short name	T334
Test name
Test status
Simulation time	1173226661 ps
CPU time	6.26 seconds
Started	Aug 25 05:48:26 AM UTC 24
Finished	Aug 25 05:48:34 AM UTC 24
Peak memory	215296 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414888350 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.414888350
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3286933911
Short name	T336
Test name
Test status
Simulation time	10218245277 ps
CPU time	19.92 seconds
Started	Aug 25 05:48:23 AM UTC 24
Finished	Aug 25 05:48:44 AM UTC 24
Peak memory	215324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286933911 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_bit_bash.3286933911
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2795218621
Short name	T105
Test name
Test status
Simulation time	310152688 ps
CPU time	2.66 seconds
Started	Aug 25 05:48:23 AM UTC 24
Finished	Aug 25 05:48:27 AM UTC 24
Peak memory	215072 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795218621 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_hw_reset.2795218621
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1833230647
Short name	T104
Test name
Test status
Simulation time	163575695 ps
CPU time	1.26 seconds
Started	Aug 25 05:48:23 AM UTC 24
Finished	Aug 25 05:48:25 AM UTC 24
Peak memory	215080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833230647 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.1833230647
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.424480425
Short name	T337
Test name
Test status
Simulation time	90056789 ps
CPU time	0.93 seconds
Started	Aug 25 05:48:44 AM UTC 24
Finished	Aug 25 05:48:46 AM UTC 24
Peak memory	215144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424480425 -assert nopostproc +UVM_ TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_partial_access.424480425
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.3137153737
Short name	T335
Test name
Test status
Simulation time	32545250 ps
CPU time	1.07 seconds
Started	Aug 25 05:48:42 AM UTC 24
Finished	Aug 25 05:48:44 AM UTC 24
Peak memory	215140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137153737 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.3137153737
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.272606505
Short name	T169
Test name
Test status
Simulation time	386132956 ps
CPU time	8.47 seconds
Started	Aug 25 05:48:31 AM UTC 24
Finished	Aug 25 05:48:41 AM UTC 24
Peak memory	225720 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272606505 -assert nopostproc +UVM_TESTNAME=rv_dm_base _test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.272606505
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.990264025
Short name	T149
Test name
Test status
Simulation time	10315699777 ps
CPU time	112.12 seconds
Started	Aug 25 05:48:50 AM UTC 24
Finished	Aug 25 05:50:45 AM UTC 24
Peak memory	225716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990264025 -asse rt nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_aliasing.990264025
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3238655014
Short name	T173
Test name
Test status
Simulation time	3334695123 ps
CPU time	48.32 seconds
Started	Aug 25 05:49:16 AM UTC 24
Finished	Aug 25 05:50:06 AM UTC 24
Peak memory	215464 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238655014 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.3238655014
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2664399032
Short name	T130
Test name
Test status
Simulation time	372097618 ps
CPU time	3.72 seconds
Started	Aug 25 05:49:15 AM UTC 24
Finished	Aug 25 05:49:19 AM UTC 24
Peak memory	225592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664399032 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2664399032
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3485999912
Short name	T170
Test name
Test status
Simulation time	108303739 ps
CPU time	2.97 seconds
Started	Aug 25 05:49:20 AM UTC 24
Finished	Aug 25 05:49:24 AM UTC 24
Peak memory	227880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3485999912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_r and_reset.3485999912
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.4156193765
Short name	T129
Test name
Test status
Simulation time	208980170 ps
CPU time	1.83 seconds
Started	Aug 25 05:49:15 AM UTC 24
Finished	Aug 25 05:49:18 AM UTC 24
Peak memory	225280 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156193765 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.4156193765
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1149690047
Short name	T368
Test name
Test status
Simulation time	26655071367 ps
CPU time	84.88 seconds
Started	Aug 25 05:49:02 AM UTC 24
Finished	Aug 25 05:50:29 AM UTC 24
Peak memory	215384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149690047 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_aliasing.1149690047
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3615201577
Short name	T342
Test name
Test status
Simulation time	4750956672 ps
CPU time	8.06 seconds
Started	Aug 25 05:49:01 AM UTC 24
Finished	Aug 25 05:49:10 AM UTC 24
Peak memory	215360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615201577 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_bit_bash.3615201577
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1041977036
Short name	T139
Test name
Test status
Simulation time	4482105440 ps
CPU time	26.3 seconds
Started	Aug 25 05:48:58 AM UTC 24
Finished	Aug 25 05:49:25 AM UTC 24
Peak memory	215500 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041977036 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_hw_reset.1041977036
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2643084921
Short name	T351
Test name
Test status
Simulation time	7269013870 ps
CPU time	41.82 seconds
Started	Aug 25 05:49:00 AM UTC 24
Finished	Aug 25 05:49:43 AM UTC 24
Peak memory	215384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643084921 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.2643084921
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.4088255426
Short name	T341
Test name
Test status
Simulation time	1180709481 ps
CPU time	2.46 seconds
Started	Aug 25 05:48:58 AM UTC 24
Finished	Aug 25 05:49:01 AM UTC 24
Peak memory	215148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088255426 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_aliasing.4088255426
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1515615658
Short name	T360
Test name
Test status
Simulation time	14512018817 ps
CPU time	74.37 seconds
Started	Aug 25 05:48:56 AM UTC 24
Finished	Aug 25 05:50:12 AM UTC 24
Peak memory	215396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515615658 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_bit_bash.1515615658
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1462895337
Short name	T340
Test name
Test status
Simulation time	1421280493 ps
CPU time	5.18 seconds
Started	Aug 25 05:48:52 AM UTC 24
Finished	Aug 25 05:48:59 AM UTC 24
Peak memory	215144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462895337 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_hw_reset.1462895337
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1872702779
Short name	T339
Test name
Test status
Simulation time	274921918 ps
CPU time	1.2 seconds
Started	Aug 25 05:48:55 AM UTC 24
Finished	Aug 25 05:48:57 AM UTC 24
Peak memory	215140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872702779 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.1872702779
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1179909639
Short name	T345
Test name
Test status
Simulation time	78848891 ps
CPU time	1.35 seconds
Started	Aug 25 05:49:13 AM UTC 24
Finished	Aug 25 05:49:15 AM UTC 24
Peak memory	215140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179909639 -assert nopostproc +UVM _TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_partial_access.1179909639
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.330760962
Short name	T344
Test name
Test status
Simulation time	71866080 ps
CPU time	1.32 seconds
Started	Aug 25 05:49:11 AM UTC 24
Finished	Aug 25 05:49:14 AM UTC 24
Peak memory	215140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330760962 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.330760962
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2668399898
Short name	T131
Test name
Test status
Simulation time	640085509 ps
CPU time	9.83 seconds
Started	Aug 25 05:49:19 AM UTC 24
Finished	Aug 25 05:49:30 AM UTC 24
Peak memory	215428 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668399898 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_csr_outstanding.2668399898
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.1782573961
Short name	T343
Test name
Test status
Simulation time	526725565 ps
CPU time	4.8 seconds
Started	Aug 25 05:49:05 AM UTC 24
Finished	Aug 25 05:49:11 AM UTC 24
Peak memory	225796 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782573961 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.1782573961
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3814732626
Short name	T409
Test name
Test status
Simulation time	200305818 ps
CPU time	4.92 seconds
Started	Aug 25 05:51:17 AM UTC 24
Finished	Aug 25 05:51:23 AM UTC 24
Peak memory	231988 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3814732626 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_ rand_reset.3814732626
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.3227656526
Short name	T157
Test name
Test status
Simulation time	157476935 ps
CPU time	2.31 seconds
Started	Aug 25 05:51:14 AM UTC 24
Finished	Aug 25 05:51:18 AM UTC 24
Peak memory	225592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227656526 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.3227656526
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/10.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.1579322104
Short name	T420
Test name
Test status
Simulation time	8606776304 ps
CPU time	22.92 seconds
Started	Aug 25 05:51:13 AM UTC 24
Finished	Aug 25 05:51:38 AM UTC 24
Peak memory	215292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579322104 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_bit_bash.1579322104
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3746850745
Short name	T407
Test name
Test status
Simulation time	7705913941 ps
CPU time	9.59 seconds
Started	Aug 25 05:51:11 AM UTC 24
Finished	Aug 25 05:51:22 AM UTC 24
Peak memory	215368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746850745 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.3746850745
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/10.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1917569766
Short name	T401
Test name
Test status
Simulation time	192014897 ps
CPU time	1.42 seconds
Started	Aug 25 05:51:11 AM UTC 24
Finished	Aug 25 05:51:14 AM UTC 24
Peak memory	215080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917569766 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.1917569766
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/10.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2877873439
Short name	T151
Test name
Test status
Simulation time	306028828 ps
CPU time	8.37 seconds
Started	Aug 25 05:51:15 AM UTC 24
Finished	Aug 25 05:51:25 AM UTC 24
Peak memory	215444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877873439 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_csr_outstanding.2877873439
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/10.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.2393223453
Short name	T405
Test name
Test status
Simulation time	49587104 ps
CPU time	3.31 seconds
Started	Aug 25 05:51:13 AM UTC 24
Finished	Aug 25 05:51:18 AM UTC 24
Peak memory	225728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393223453 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.2393223453
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/10.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1232156037
Short name	T202
Test name
Test status
Simulation time	1304827370 ps
CPU time	14.19 seconds
Started	Aug 25 05:51:14 AM UTC 24
Finished	Aug 25 05:51:30 AM UTC 24
Peak memory	225680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232156037 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.1232156037
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/10.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3101280497
Short name	T413
Test name
Test status
Simulation time	133530013 ps
CPU time	3.07 seconds
Started	Aug 25 05:51:23 AM UTC 24
Finished	Aug 25 05:51:27 AM UTC 24
Peak memory	227716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3101280497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_ rand_reset.3101280497
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_rw.2538646444
Short name	T412
Test name
Test status
Simulation time	127790693 ps
CPU time	3.61 seconds
Started	Aug 25 05:51:22 AM UTC 24
Finished	Aug 25 05:51:27 AM UTC 24
Peak memory	225824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538646444 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.2538646444
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/11.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.4257151288
Short name	T477
Test name
Test status
Simulation time	13581300939 ps
CPU time	84.66 seconds
Started	Aug 25 05:51:19 AM UTC 24
Finished	Aug 25 05:52:46 AM UTC 24
Peak memory	215364 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257151288 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_bit_bash.4257151288
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3866166984
Short name	T419
Test name
Test status
Simulation time	2963878499 ps
CPU time	16.28 seconds
Started	Aug 25 05:51:19 AM UTC 24
Finished	Aug 25 05:51:36 AM UTC 24
Peak memory	215492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866166984 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.3866166984
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/11.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2160020648
Short name	T406
Test name
Test status
Simulation time	703397421 ps
CPU time	2.18 seconds
Started	Aug 25 05:51:19 AM UTC 24
Finished	Aug 25 05:51:22 AM UTC 24
Peak memory	215072 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160020648 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.2160020648
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/11.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3592313016
Short name	T418
Test name
Test status
Simulation time	1626968471 ps
CPU time	10.53 seconds
Started	Aug 25 05:51:23 AM UTC 24
Finished	Aug 25 05:51:35 AM UTC 24
Peak memory	215456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592313016 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_csr_outstanding.3592313016
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/11.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_errors.3905211267
Short name	T411
Test name
Test status
Simulation time	225400602 ps
CPU time	6.5 seconds
Started	Aug 25 05:51:19 AM UTC 24
Finished	Aug 25 05:51:27 AM UTC 24
Peak memory	225724 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905211267 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.3905211267
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/11.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3479050267
Short name	T201
Test name
Test status
Simulation time	4988583765 ps
CPU time	23.84 seconds
Started	Aug 25 05:51:21 AM UTC 24
Finished	Aug 25 05:51:47 AM UTC 24
Peak memory	225664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479050267 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.3479050267
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/11.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.95742743
Short name	T417
Test name
Test status
Simulation time	52414399 ps
CPU time	4.37 seconds
Started	Aug 25 05:51:29 AM UTC 24
Finished	Aug 25 05:51:34 AM UTC 24
Peak memory	232036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=95742743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_ra nd_reset.95742743
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_rw.4206887603
Short name	T159
Test name
Test status
Simulation time	161209113 ps
CPU time	2.86 seconds
Started	Aug 25 05:51:27 AM UTC 24
Finished	Aug 25 05:51:31 AM UTC 24
Peak memory	225592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206887603 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.4206887603
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/12.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.366181431
Short name	T429
Test name
Test status
Simulation time	5169899585 ps
CPU time	16.45 seconds
Started	Aug 25 05:51:26 AM UTC 24
Finished	Aug 25 05:51:44 AM UTC 24
Peak memory	215516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366181431 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_bit_bash.366181431
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.4057577334
Short name	T414
Test name
Test status
Simulation time	2545684348 ps
CPU time	6.86 seconds
Started	Aug 25 05:51:24 AM UTC 24
Finished	Aug 25 05:51:32 AM UTC 24
Peak memory	215384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057577334 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.4057577334
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/12.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.4139753263
Short name	T410
Test name
Test status
Simulation time	259123782 ps
CPU time	1.48 seconds
Started	Aug 25 05:51:23 AM UTC 24
Finished	Aug 25 05:51:26 AM UTC 24
Peak memory	215080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139753263 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.4139753263
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/12.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2054376394
Short name	T152
Test name
Test status
Simulation time	971452371 ps
CPU time	10.33 seconds
Started	Aug 25 05:51:29 AM UTC 24
Finished	Aug 25 05:51:40 AM UTC 24
Peak memory	215572 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054376394 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same_csr_outstanding.2054376394
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/12.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_errors.123063740
Short name	T416
Test name
Test status
Simulation time	258129320 ps
CPU time	5.89 seconds
Started	Aug 25 05:51:26 AM UTC 24
Finished	Aug 25 05:51:34 AM UTC 24
Peak memory	225856 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123063740 -assert nopostproc +UVM_TESTNAME=rv_dm_base _test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.123063740
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/12.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2098240839
Short name	T198
Test name
Test status
Simulation time	4693459482 ps
CPU time	20 seconds
Started	Aug 25 05:51:27 AM UTC 24
Finished	Aug 25 05:51:49 AM UTC 24
Peak memory	225924 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098240839 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.2098240839
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/12.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3041754803
Short name	T425
Test name
Test status
Simulation time	214347040 ps
CPU time	3.1 seconds
Started	Aug 25 05:51:36 AM UTC 24
Finished	Aug 25 05:51:41 AM UTC 24
Peak memory	225756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3041754803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_ rand_reset.3041754803
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_rw.1805670702
Short name	T422
Test name
Test status
Simulation time	270084484 ps
CPU time	2.21 seconds
Started	Aug 25 05:51:35 AM UTC 24
Finished	Aug 25 05:51:39 AM UTC 24
Peak memory	225636 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805670702 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.1805670702
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/13.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.3792919993
Short name	T436
Test name
Test status
Simulation time	3238602600 ps
CPU time	15.49 seconds
Started	Aug 25 05:51:33 AM UTC 24
Finished	Aug 25 05:51:50 AM UTC 24
Peak memory	215428 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792919993 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_bit_bash.3792919993
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1146073213
Short name	T421
Test name
Test status
Simulation time	1986469455 ps
CPU time	4.61 seconds
Started	Aug 25 05:51:32 AM UTC 24
Finished	Aug 25 05:51:38 AM UTC 24
Peak memory	215232 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146073213 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.1146073213
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/13.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.181187965
Short name	T415
Test name
Test status
Simulation time	412015386 ps
CPU time	1.23 seconds
Started	Aug 25 05:51:31 AM UTC 24
Finished	Aug 25 05:51:33 AM UTC 24
Peak memory	215084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181187965 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.181187965
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/13.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1972985674
Short name	T153
Test name
Test status
Simulation time	226767048 ps
CPU time	5.67 seconds
Started	Aug 25 05:51:35 AM UTC 24
Finished	Aug 25 05:51:42 AM UTC 24
Peak memory	215528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972985674 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_csr_outstanding.1972985674
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/13.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_errors.3533451961
Short name	T424
Test name
Test status
Simulation time	286507626 ps
CPU time	4.86 seconds
Started	Aug 25 05:51:34 AM UTC 24
Finished	Aug 25 05:51:40 AM UTC 24
Peak memory	225764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533451961 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.3533451961
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/13.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_intg_err.862556475
Short name	T447
Test name
Test status
Simulation time	2201832177 ps
CPU time	19.43 seconds
Started	Aug 25 05:51:34 AM UTC 24
Finished	Aug 25 05:51:55 AM UTC 24
Peak memory	232584 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862556475 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.862556475
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/13.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.494945868
Short name	T432
Test name
Test status
Simulation time	1065904310 ps
CPU time	4.24 seconds
Started	Aug 25 05:51:41 AM UTC 24
Finished	Aug 25 05:51:46 AM UTC 24
Peak memory	232244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=494945868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_r and_reset.494945868
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_rw.3420941774
Short name	T161
Test name
Test status
Simulation time	149216106 ps
CPU time	2.99 seconds
Started	Aug 25 05:51:40 AM UTC 24
Finished	Aug 25 05:51:44 AM UTC 24
Peak memory	229760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420941774 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.3420941774
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/14.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3263364840
Short name	T483
Test name
Test status
Simulation time	67736354451 ps
CPU time	367.65 seconds
Started	Aug 25 05:51:38 AM UTC 24
Finished	Aug 25 05:57:52 AM UTC 24
Peak memory	215364 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263364840 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_bit_bash.3263364840
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3273975209
Short name	T448
Test name
Test status
Simulation time	6128603366 ps
CPU time	17.03 seconds
Started	Aug 25 05:51:37 AM UTC 24
Finished	Aug 25 05:51:56 AM UTC 24
Peak memory	215368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273975209 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.3273975209
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/14.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1688285860
Short name	T423
Test name
Test status
Simulation time	614517585 ps
CPU time	1.66 seconds
Started	Aug 25 05:51:37 AM UTC 24
Finished	Aug 25 05:51:40 AM UTC 24
Peak memory	215080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688285860 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.1688285860
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/14.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1108201446
Short name	T443
Test name
Test status
Simulation time	7589761127 ps
CPU time	11.54 seconds
Started	Aug 25 05:51:41 AM UTC 24
Finished	Aug 25 05:51:53 AM UTC 24
Peak memory	215696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108201446 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same_csr_outstanding.1108201446
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/14.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_errors.3838790815
Short name	T433
Test name
Test status
Simulation time	200971716 ps
CPU time	6.93 seconds
Started	Aug 25 05:51:39 AM UTC 24
Finished	Aug 25 05:51:47 AM UTC 24
Peak memory	225796 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838790815 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.3838790815
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/14.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1720701166
Short name	T470
Test name
Test status
Simulation time	4794950058 ps
CPU time	31.64 seconds
Started	Aug 25 05:51:39 AM UTC 24
Finished	Aug 25 05:52:12 AM UTC 24
Peak memory	232488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720701166 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.1720701166
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/14.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3848672587
Short name	T437
Test name
Test status
Simulation time	165872272 ps
CPU time	5.39 seconds
Started	Aug 25 05:51:45 AM UTC 24
Finished	Aug 25 05:51:52 AM UTC 24
Peak memory	232528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3848672587 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_ rand_reset.3848672587
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_rw.1809388314
Short name	T434
Test name
Test status
Simulation time	61014365 ps
CPU time	2.99 seconds
Started	Aug 25 05:51:44 AM UTC 24
Finished	Aug 25 05:51:48 AM UTC 24
Peak memory	229700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809388314 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.1809388314
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/15.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.270914906
Short name	T459
Test name
Test status
Simulation time	8570406342 ps
CPU time	20.35 seconds
Started	Aug 25 05:51:43 AM UTC 24
Finished	Aug 25 05:52:05 AM UTC 24
Peak memory	215452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270914906 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_bit_bash.270914906
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1215218012
Short name	T444
Test name
Test status
Simulation time	5996765541 ps
CPU time	11.33 seconds
Started	Aug 25 05:51:42 AM UTC 24
Finished	Aug 25 05:51:54 AM UTC 24
Peak memory	215456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215218012 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.1215218012
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/15.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2020566852
Short name	T430
Test name
Test status
Simulation time	225682234 ps
CPU time	1.34 seconds
Started	Aug 25 05:51:42 AM UTC 24
Finished	Aug 25 05:51:44 AM UTC 24
Peak memory	215080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020566852 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.2020566852
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/15.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2059739316
Short name	T442
Test name
Test status
Simulation time	634630764 ps
CPU time	6.82 seconds
Started	Aug 25 05:51:45 AM UTC 24
Finished	Aug 25 05:51:53 AM UTC 24
Peak memory	215572 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059739316 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_csr_outstanding.2059739316
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/15.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_errors.4206387239
Short name	T441
Test name
Test status
Simulation time	858058200 ps
CPU time	9.04 seconds
Started	Aug 25 05:51:43 AM UTC 24
Finished	Aug 25 05:51:53 AM UTC 24
Peak memory	225728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206387239 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.4206387239
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/15.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1313381884
Short name	T450
Test name
Test status
Simulation time	2019095770 ps
CPU time	11.65 seconds
Started	Aug 25 05:51:44 AM UTC 24
Finished	Aug 25 05:51:57 AM UTC 24
Peak memory	225792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313381884 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.1313381884
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/15.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3549526717
Short name	T445
Test name
Test status
Simulation time	393969183 ps
CPU time	4.45 seconds
Started	Aug 25 05:51:49 AM UTC 24
Finished	Aug 25 05:51:54 AM UTC 24
Peak memory	225800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3549526717 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_ rand_reset.3549526717
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_rw.3687178305
Short name	T439
Test name
Test status
Simulation time	133463657 ps
CPU time	2.45 seconds
Started	Aug 25 05:51:49 AM UTC 24
Finished	Aug 25 05:51:52 AM UTC 24
Peak memory	229792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687178305 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.3687178305
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/16.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.3094893678
Short name	T479
Test name
Test status
Simulation time	87294659590 ps
CPU time	96.83 seconds
Started	Aug 25 05:51:47 AM UTC 24
Finished	Aug 25 05:53:26 AM UTC 24
Peak memory	215364 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094893678 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_bit_bash.3094893678
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3436415314
Short name	T462
Test name
Test status
Simulation time	7001389580 ps
CPU time	18.55 seconds
Started	Aug 25 05:51:45 AM UTC 24
Finished	Aug 25 05:52:05 AM UTC 24
Peak memory	215368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436415314 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.3436415314
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/16.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3790182536
Short name	T435
Test name
Test status
Simulation time	247851934 ps
CPU time	1.83 seconds
Started	Aug 25 05:51:45 AM UTC 24
Finished	Aug 25 05:51:48 AM UTC 24
Peak memory	215080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790182536 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.3790182536
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/16.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1114421559
Short name	T446
Test name
Test status
Simulation time	431495990 ps
CPU time	5.26 seconds
Started	Aug 25 05:51:49 AM UTC 24
Finished	Aug 25 05:51:55 AM UTC 24
Peak memory	215372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114421559 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_csr_outstanding.1114421559
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/16.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_errors.1906663832
Short name	T438
Test name
Test status
Simulation time	173893303 ps
CPU time	3.33 seconds
Started	Aug 25 05:51:48 AM UTC 24
Finished	Aug 25 05:51:52 AM UTC 24
Peak memory	225884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906663832 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.1906663832
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/16.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.4149162248
Short name	T475
Test name
Test status
Simulation time	5146782209 ps
CPU time	36.1 seconds
Started	Aug 25 05:51:48 AM UTC 24
Finished	Aug 25 05:52:25 AM UTC 24
Peak memory	227880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149162248 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.4149162248
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/16.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3887266341
Short name	T452
Test name
Test status
Simulation time	80704687 ps
CPU time	3.32 seconds
Started	Aug 25 05:51:55 AM UTC 24
Finished	Aug 25 05:51:59 AM UTC 24
Peak memory	230032 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3887266341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_ rand_reset.3887266341
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_rw.2120528096
Short name	T451
Test name
Test status
Simulation time	84851625 ps
CPU time	2.66 seconds
Started	Aug 25 05:51:53 AM UTC 24
Finished	Aug 25 05:51:57 AM UTC 24
Peak memory	225672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120528096 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.2120528096
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/17.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.2947155764
Short name	T457
Test name
Test status
Simulation time	10460706304 ps
CPU time	8.26 seconds
Started	Aug 25 05:51:52 AM UTC 24
Finished	Aug 25 05:52:02 AM UTC 24
Peak memory	215292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947155764 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_bit_bash.2947155764
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.4189650465
Short name	T463
Test name
Test status
Simulation time	2226766757 ps
CPU time	13.41 seconds
Started	Aug 25 05:51:51 AM UTC 24
Finished	Aug 25 05:52:06 AM UTC 24
Peak memory	215364 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189650465 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.4189650465
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/17.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.76054568
Short name	T440
Test name
Test status
Simulation time	109762889 ps
CPU time	1.63 seconds
Started	Aug 25 05:51:50 AM UTC 24
Finished	Aug 25 05:51:53 AM UTC 24
Peak memory	215204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76054568 -assert nopostproc +UVM_TESTNAME=rv_dm_ba se_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.76054568
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/17.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2788098464
Short name	T464
Test name
Test status
Simulation time	2582724095 ps
CPU time	11.37 seconds
Started	Aug 25 05:51:54 AM UTC 24
Finished	Aug 25 05:52:06 AM UTC 24
Peak memory	215440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788098464 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same_csr_outstanding.2788098464
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/17.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_errors.1774934986
Short name	T455
Test name
Test status
Simulation time	371993895 ps
CPU time	7.43 seconds
Started	Aug 25 05:51:52 AM UTC 24
Finished	Aug 25 05:52:01 AM UTC 24
Peak memory	225692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774934986 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.1774934986
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/17.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.709809160
Short name	T203
Test name
Test status
Simulation time	2862717013 ps
CPU time	24.13 seconds
Started	Aug 25 05:51:52 AM UTC 24
Finished	Aug 25 05:52:18 AM UTC 24
Peak memory	225792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709809160 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.709809160
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/17.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1179131881
Short name	T456
Test name
Test status
Simulation time	121823043 ps
CPU time	3.08 seconds
Started	Aug 25 05:51:57 AM UTC 24
Finished	Aug 25 05:52:01 AM UTC 24
Peak memory	227848 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1179131881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_ rand_reset.1179131881
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_rw.1599982557
Short name	T453
Test name
Test status
Simulation time	130588248 ps
CPU time	3.6 seconds
Started	Aug 25 05:51:56 AM UTC 24
Finished	Aug 25 05:52:01 AM UTC 24
Peak memory	229856 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599982557 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.1599982557
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/18.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.15234641
Short name	T481
Test name
Test status
Simulation time	18904415083 ps
CPU time	102.29 seconds
Started	Aug 25 05:51:55 AM UTC 24
Finished	Aug 25 05:53:39 AM UTC 24
Peak memory	215368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15234641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_bit_bash.15234641
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1207893576
Short name	T461
Test name
Test status
Simulation time	1679535309 ps
CPU time	9.09 seconds
Started	Aug 25 05:51:55 AM UTC 24
Finished	Aug 25 05:52:05 AM UTC 24
Peak memory	215428 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207893576 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.1207893576
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/18.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.903720287
Short name	T449
Test name
Test status
Simulation time	124203494 ps
CPU time	1.16 seconds
Started	Aug 25 05:51:55 AM UTC 24
Finished	Aug 25 05:51:57 AM UTC 24
Peak memory	215084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903720287 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.903720287
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/18.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3620070887
Short name	T467
Test name
Test status
Simulation time	399624969 ps
CPU time	9.5 seconds
Started	Aug 25 05:51:56 AM UTC 24
Finished	Aug 25 05:52:07 AM UTC 24
Peak memory	215436 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620070887 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same_csr_outstanding.3620070887
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/18.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_errors.923982473
Short name	T458
Test name
Test status
Simulation time	261589081 ps
CPU time	4.9 seconds
Started	Aug 25 05:51:56 AM UTC 24
Finished	Aug 25 05:52:02 AM UTC 24
Peak memory	225792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923982473 -assert nopostproc +UVM_TESTNAME=rv_dm_base _test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.923982473
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/18.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3748198176
Short name	T471
Test name
Test status
Simulation time	2885559184 ps
CPU time	16.15 seconds
Started	Aug 25 05:51:56 AM UTC 24
Finished	Aug 25 05:52:13 AM UTC 24
Peak memory	232460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748198176 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3748198176
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/18.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.454189699
Short name	T468
Test name
Test status
Simulation time	64067388 ps
CPU time	3.9 seconds
Started	Aug 25 05:52:03 AM UTC 24
Finished	Aug 25 05:52:08 AM UTC 24
Peak memory	229828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=454189699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_r and_reset.454189699
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_rw.3934218130
Short name	T158
Test name
Test status
Simulation time	438595540 ps
CPU time	3.33 seconds
Started	Aug 25 05:52:02 AM UTC 24
Finished	Aug 25 05:52:06 AM UTC 24
Peak memory	225636 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934218130 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.3934218130
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/19.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.3567330221
Short name	T474
Test name
Test status
Simulation time	5470982764 ps
CPU time	17.69 seconds
Started	Aug 25 05:51:58 AM UTC 24
Finished	Aug 25 05:52:17 AM UTC 24
Peak memory	215456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567330221 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_bit_bash.3567330221
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.755082630
Short name	T473
Test name
Test status
Simulation time	5982855325 ps
CPU time	16.47 seconds
Started	Aug 25 05:51:58 AM UTC 24
Finished	Aug 25 05:52:16 AM UTC 24
Peak memory	215320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755082630 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.755082630
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/19.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2220894656
Short name	T454
Test name
Test status
Simulation time	249559475 ps
CPU time	1.5 seconds
Started	Aug 25 05:51:58 AM UTC 24
Finished	Aug 25 05:52:01 AM UTC 24
Peak memory	215080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220894656 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.2220894656
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/19.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.4237232100
Short name	T469
Test name
Test status
Simulation time	435195490 ps
CPU time	5.78 seconds
Started	Aug 25 05:52:02 AM UTC 24
Finished	Aug 25 05:52:08 AM UTC 24
Peak memory	215436 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237232100 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_csr_outstanding.4237232100
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/19.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_errors.2171597391
Short name	T465
Test name
Test status
Simulation time	138350349 ps
CPU time	4.9 seconds
Started	Aug 25 05:52:00 AM UTC 24
Finished	Aug 25 05:52:06 AM UTC 24
Peak memory	225728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171597391 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.2171597391
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/19.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2288041971
Short name	T472
Test name
Test status
Simulation time	1910746538 ps
CPU time	13.03 seconds
Started	Aug 25 05:52:01 AM UTC 24
Finished	Aug 25 05:52:16 AM UTC 24
Peak memory	232380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288041971 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.2288041971
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/19.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3174630771
Short name	T144
Test name
Test status
Simulation time	15176098823 ps
CPU time	43.65 seconds
Started	Aug 25 05:49:20 AM UTC 24
Finished	Aug 25 05:50:06 AM UTC 24
Peak memory	215528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174630771 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_aliasing.3174630771
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/2.rv_dm_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1887309615
Short name	T155
Test name
Test status
Simulation time	6366510014 ps
CPU time	48.83 seconds
Started	Aug 25 05:49:47 AM UTC 24
Finished	Aug 25 05:50:37 AM UTC 24
Peak memory	215460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887309615 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.1887309615
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/2.rv_dm_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.392737094
Short name	T133
Test name
Test status
Simulation time	288413459 ps
CPU time	2.48 seconds
Started	Aug 25 05:49:44 AM UTC 24
Finished	Aug 25 05:49:48 AM UTC 24
Peak memory	225760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392737094 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.392737094
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/2.rv_dm_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.2724008536
Short name	T354
Test name
Test status
Simulation time	264504633 ps
CPU time	2.77 seconds
Started	Aug 25 05:49:49 AM UTC 24
Finished	Aug 25 05:49:53 AM UTC 24
Peak memory	225800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2724008536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_r and_reset.2724008536
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_rw.3691634189
Short name	T134
Test name
Test status
Simulation time	56717697 ps
CPU time	2.44 seconds
Started	Aug 25 05:49:47 AM UTC 24
Finished	Aug 25 05:49:50 AM UTC 24
Peak memory	225576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691634189 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.3691634189
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/2.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.807428385
Short name	T391
Test name
Test status
Simulation time	25263765825 ps
CPU time	87.63 seconds
Started	Aug 25 05:49:35 AM UTC 24
Finished	Aug 25 05:51:05 AM UTC 24
Peak memory	215580 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807428385 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_aliasing.807428385
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.4024891990
Short name	T392
Test name
Test status
Simulation time	32128735589 ps
CPU time	92.33 seconds
Started	Aug 25 05:49:31 AM UTC 24
Finished	Aug 25 05:51:05 AM UTC 24
Peak memory	215516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024891990 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_bit_bash.4024891990
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2131240853
Short name	T140
Test name
Test status
Simulation time	10493963649 ps
CPU time	30.35 seconds
Started	Aug 25 05:49:27 AM UTC 24
Finished	Aug 25 05:49:58 AM UTC 24
Peak memory	215468 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131240853 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_hw_reset.2131240853
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1146453803
Short name	T358
Test name
Test status
Simulation time	6032874454 ps
CPU time	35.04 seconds
Started	Aug 25 05:49:31 AM UTC 24
Finished	Aug 25 05:50:08 AM UTC 24
Peak memory	215380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146453803 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1146453803
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2703316603
Short name	T348
Test name
Test status
Simulation time	265035252 ps
CPU time	2.43 seconds
Started	Aug 25 05:49:26 AM UTC 24
Finished	Aug 25 05:49:30 AM UTC 24
Peak memory	215080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703316603 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_aliasing.2703316603
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1853776848
Short name	T350
Test name
Test status
Simulation time	19360188368 ps
CPU time	13.68 seconds
Started	Aug 25 05:49:25 AM UTC 24
Finished	Aug 25 05:49:40 AM UTC 24
Peak memory	215396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853776848 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_bit_bash.1853776848
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1942062938
Short name	T346
Test name
Test status
Simulation time	198024670 ps
CPU time	1.22 seconds
Started	Aug 25 05:49:20 AM UTC 24
Finished	Aug 25 05:49:22 AM UTC 24
Peak memory	215144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942062938 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_hw_reset.1942062938
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.4255392322
Short name	T347
Test name
Test status
Simulation time	360033338 ps
CPU time	1.15 seconds
Started	Aug 25 05:49:23 AM UTC 24
Finished	Aug 25 05:49:26 AM UTC 24
Peak memory	215080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255392322 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.4255392322
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_partial_access.851674132
Short name	T353
Test name
Test status
Simulation time	71028313 ps
CPU time	1.05 seconds
Started	Aug 25 05:49:44 AM UTC 24
Finished	Aug 25 05:49:46 AM UTC 24
Peak memory	215144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851674132 -assert nopostproc +UVM_ TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_partial_access.851674132
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/2.rv_dm_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_walk.333748836
Short name	T352
Test name
Test status
Simulation time	76482848 ps
CPU time	1.07 seconds
Started	Aug 25 05:49:43 AM UTC 24
Finished	Aug 25 05:49:45 AM UTC 24
Peak memory	215140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333748836 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.333748836
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/2.rv_dm_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3678943696
Short name	T143
Test name
Test status
Simulation time	529861955 ps
CPU time	12.62 seconds
Started	Aug 25 05:49:48 AM UTC 24
Finished	Aug 25 05:50:01 AM UTC 24
Peak memory	215428 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678943696 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_csr_outstanding.3678943696
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/2.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_errors.1896859560
Short name	T172
Test name
Test status
Simulation time	431903164 ps
CPU time	6.25 seconds
Started	Aug 25 05:49:41 AM UTC 24
Finished	Aug 25 05:49:48 AM UTC 24
Peak memory	225820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896859560 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.1896859560
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/2.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.243114783
Short name	T175
Test name
Test status
Simulation time	4674123652 ps
CPU time	32.76 seconds
Started	Aug 25 05:49:42 AM UTC 24
Finished	Aug 25 05:50:16 AM UTC 24
Peak memory	232484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243114783 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.243114783
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/2.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2928171052
Short name	T380
Test name
Test status
Simulation time	783733760 ps
CPU time	34.57 seconds
Started	Aug 25 05:50:13 AM UTC 24
Finished	Aug 25 05:50:50 AM UTC 24
Peak memory	215340 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928171052 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.2928171052
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/3.rv_dm_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.874843599
Short name	T146
Test name
Test status
Simulation time	686582929 ps
CPU time	3.64 seconds
Started	Aug 25 05:50:11 AM UTC 24
Finished	Aug 25 05:50:16 AM UTC 24
Peak memory	225696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874843599 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.874843599
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/3.rv_dm_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.125651181
Short name	T109
Test name
Test status
Simulation time	89640308 ps
CPU time	2.62 seconds
Started	Aug 25 05:50:15 AM UTC 24
Finished	Aug 25 05:50:19 AM UTC 24
Peak memory	225804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=125651181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_ra nd_reset.125651181
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_rw.2282027581
Short name	T145
Test name
Test status
Simulation time	145116218 ps
CPU time	2.3 seconds
Started	Aug 25 05:50:12 AM UTC 24
Finished	Aug 25 05:50:16 AM UTC 24
Peak memory	225660 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282027581 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.2282027581
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/3.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1576923387
Short name	T460
Test name
Test status
Simulation time	50315911185 ps
CPU time	117.82 seconds
Started	Aug 25 05:50:04 AM UTC 24
Finished	Aug 25 05:52:05 AM UTC 24
Peak memory	215324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576923387 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_aliasing.1576923387
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1907223703
Short name	T476
Test name
Test status
Simulation time	33196470168 ps
CPU time	160.25 seconds
Started	Aug 25 05:50:02 AM UTC 24
Finished	Aug 25 05:52:46 AM UTC 24
Peak memory	215360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907223703 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_bit_bash.1907223703
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3452612638
Short name	T141
Test name
Test status
Simulation time	12622601492 ps
CPU time	10.46 seconds
Started	Aug 25 05:49:59 AM UTC 24
Finished	Aug 25 05:50:11 AM UTC 24
Peak memory	215464 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452612638 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_hw_reset.3452612638
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1939744377
Short name	T363
Test name
Test status
Simulation time	1837321269 ps
CPU time	13.52 seconds
Started	Aug 25 05:50:01 AM UTC 24
Finished	Aug 25 05:50:16 AM UTC 24
Peak memory	215360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939744377 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.1939744377
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1488967488
Short name	T357
Test name
Test status
Simulation time	2198178884 ps
CPU time	2.96 seconds
Started	Aug 25 05:49:59 AM UTC 24
Finished	Aug 25 05:50:03 AM UTC 24
Peak memory	215212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488967488 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_aliasing.1488967488
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1380641306
Short name	T364
Test name
Test status
Simulation time	8132283216 ps
CPU time	18.6 seconds
Started	Aug 25 05:49:56 AM UTC 24
Finished	Aug 25 05:50:16 AM UTC 24
Peak memory	215384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380641306 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_bit_bash.1380641306
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3815656393
Short name	T355
Test name
Test status
Simulation time	535661410 ps
CPU time	3.22 seconds
Started	Aug 25 05:49:51 AM UTC 24
Finished	Aug 25 05:49:56 AM UTC 24
Peak memory	215144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815656393 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_hw_reset.3815656393
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3768814651
Short name	T356
Test name
Test status
Simulation time	223354656 ps
CPU time	2.47 seconds
Started	Aug 25 05:49:54 AM UTC 24
Finished	Aug 25 05:49:58 AM UTC 24
Peak memory	215336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768814651 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.3768814651
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_partial_access.8721548
Short name	T361
Test name
Test status
Simulation time	45228351 ps
CPU time	1.17 seconds
Started	Aug 25 05:50:11 AM UTC 24
Finished	Aug 25 05:50:14 AM UTC 24
Peak memory	215148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8721548 -assert nopostproc +UVM_TE STNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_partial_access.8721548
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/3.rv_dm_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_walk.2217083831
Short name	T359
Test name
Test status
Simulation time	131683184 ps
CPU time	1.09 seconds
Started	Aug 25 05:50:08 AM UTC 24
Finished	Aug 25 05:50:10 AM UTC 24
Peak memory	215140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217083831 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.2217083831
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/3.rv_dm_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3922831294
Short name	T162
Test name
Test status
Simulation time	798420320 ps
CPU time	5.64 seconds
Started	Aug 25 05:50:14 AM UTC 24
Finished	Aug 25 05:50:21 AM UTC 24
Peak memory	215488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922831294 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_csr_outstanding.3922831294
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/3.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3593706507
Short name	T110
Test name
Test status
Simulation time	12218189288 ps
CPU time	150.02 seconds
Started	Aug 25 05:50:04 AM UTC 24
Finished	Aug 25 05:52:37 AM UTC 24
Peak memory	225784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3593706507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_re set.3593706507
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/3.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_errors.376622667
Short name	T362
Test name
Test status
Simulation time	83630460 ps
CPU time	7.03 seconds
Started	Aug 25 05:50:07 AM UTC 24
Finished	Aug 25 05:50:15 AM UTC 24
Peak memory	225704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376622667 -assert nopostproc +UVM_TESTNAME=rv_dm_base _test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.376622667
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/3.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1296166021
Short name	T427
Test name
Test status
Simulation time	3437255396 ps
CPU time	84.68 seconds
Started	Aug 25 05:50:16 AM UTC 24
Finished	Aug 25 05:51:43 AM UTC 24
Peak memory	229828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296166021 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_aliasing.1296166021
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/4.rv_dm_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.776568118
Short name	T160
Test name
Test status
Simulation time	1506379709 ps
CPU time	63.22 seconds
Started	Aug 25 05:50:33 AM UTC 24
Finished	Aug 25 05:51:38 AM UTC 24
Peak memory	215404 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776568118 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.776568118
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/4.rv_dm_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2377461035
Short name	T154
Test name
Test status
Simulation time	389708501 ps
CPU time	4.02 seconds
Started	Aug 25 05:50:30 AM UTC 24
Finished	Aug 25 05:50:36 AM UTC 24
Peak memory	225532 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377461035 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.2377461035
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/4.rv_dm_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3205598261
Short name	T113
Test name
Test status
Simulation time	213212355 ps
CPU time	3.92 seconds
Started	Aug 25 05:50:34 AM UTC 24
Finished	Aug 25 05:50:39 AM UTC 24
Peak memory	227912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3205598261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_r and_reset.3205598261
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_rw.1894824442
Short name	T374
Test name
Test status
Simulation time	444867599 ps
CPU time	3.32 seconds
Started	Aug 25 05:50:32 AM UTC 24
Finished	Aug 25 05:50:36 AM UTC 24
Peak memory	225704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894824442 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.1894824442
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/4.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.123424127
Short name	T404
Test name
Test status
Simulation time	19183627073 ps
CPU time	55.18 seconds
Started	Aug 25 05:50:21 AM UTC 24
Finished	Aug 25 05:51:18 AM UTC 24
Peak memory	215364 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123424127 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_aliasing.123424127
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.4085805032
Short name	T388
Test name
Test status
Simulation time	20706302009 ps
CPU time	37.2 seconds
Started	Aug 25 05:50:21 AM UTC 24
Finished	Aug 25 05:51:00 AM UTC 24
Peak memory	215360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085805032 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_bit_bash.4085805032
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2196180247
Short name	T142
Test name
Test status
Simulation time	20277930903 ps
CPU time	65.98 seconds
Started	Aug 25 05:50:20 AM UTC 24
Finished	Aug 25 05:51:28 AM UTC 24
Peak memory	215456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196180247 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_hw_reset.2196180247
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.370088606
Short name	T370
Test name
Test status
Simulation time	3619156768 ps
CPU time	10.3 seconds
Started	Aug 25 05:50:20 AM UTC 24
Finished	Aug 25 05:50:31 AM UTC 24
Peak memory	215452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370088606 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.370088606
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3072851456
Short name	T367
Test name
Test status
Simulation time	529184984 ps
CPU time	3.52 seconds
Started	Aug 25 05:50:18 AM UTC 24
Finished	Aug 25 05:50:22 AM UTC 24
Peak memory	215076 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072851456 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_aliasing.3072851456
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.766584743
Short name	T384
Test name
Test status
Simulation time	7106426762 ps
CPU time	33.39 seconds
Started	Aug 25 05:50:18 AM UTC 24
Finished	Aug 25 05:50:52 AM UTC 24
Peak memory	215452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766584743 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_bit_bash.766584743
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1212554405
Short name	T365
Test name
Test status
Simulation time	464113549 ps
CPU time	1.97 seconds
Started	Aug 25 05:50:16 AM UTC 24
Finished	Aug 25 05:50:20 AM UTC 24
Peak memory	215144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212554405 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_hw_reset.1212554405
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.893124409
Short name	T366
Test name
Test status
Simulation time	246788966 ps
CPU time	1.93 seconds
Started	Aug 25 05:50:18 AM UTC 24
Finished	Aug 25 05:50:20 AM UTC 24
Peak memory	215144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893124409 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.893124409
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_partial_access.935241690
Short name	T372
Test name
Test status
Simulation time	124525122 ps
CPU time	1.12 seconds
Started	Aug 25 05:50:30 AM UTC 24
Finished	Aug 25 05:50:32 AM UTC 24
Peak memory	215144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935241690 -assert nopostproc +UVM_ TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_partial_access.935241690
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/4.rv_dm_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_walk.2949457607
Short name	T369
Test name
Test status
Simulation time	144655001 ps
CPU time	1.18 seconds
Started	Aug 25 05:50:27 AM UTC 24
Finished	Aug 25 05:50:30 AM UTC 24
Peak memory	215140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949457607 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.2949457607
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/4.rv_dm_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1175838163
Short name	T163
Test name
Test status
Simulation time	539322649 ps
CPU time	10.8 seconds
Started	Aug 25 05:50:34 AM UTC 24
Finished	Aug 25 05:50:46 AM UTC 24
Peak memory	215484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175838163 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_csr_outstanding.1175838163
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/4.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.1788947275
Short name	T112
Test name
Test status
Simulation time	5086796827 ps
CPU time	98.85 seconds
Started	Aug 25 05:50:22 AM UTC 24
Finished	Aug 25 05:52:03 AM UTC 24
Peak memory	229828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1788947275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_re set.1788947275
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/4.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_errors.1727838489
Short name	T371
Test name
Test status
Simulation time	518501877 ps
CPU time	8.17 seconds
Started	Aug 25 05:50:23 AM UTC 24
Finished	Aug 25 05:50:32 AM UTC 24
Peak memory	225728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727838489 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.1727838489
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/4.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1750716366
Short name	T197
Test name
Test status
Simulation time	487113429 ps
CPU time	13.72 seconds
Started	Aug 25 05:50:24 AM UTC 24
Finished	Aug 25 05:50:39 AM UTC 24
Peak memory	232468 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750716366 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.1750716366
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/4.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3957396517
Short name	T379
Test name
Test status
Simulation time	986514787 ps
CPU time	4.73 seconds
Started	Aug 25 05:50:40 AM UTC 24
Finished	Aug 25 05:50:45 AM UTC 24
Peak memory	229960 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3957396517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_r and_reset.3957396517
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_rw.1336546686
Short name	T376
Test name
Test status
Simulation time	583982639 ps
CPU time	2.33 seconds
Started	Aug 25 05:50:38 AM UTC 24
Finished	Aug 25 05:50:42 AM UTC 24
Peak memory	225620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336546686 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.1336546686
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/5.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.4144862304
Short name	T375
Test name
Test status
Simulation time	71133010 ps
CPU time	1.35 seconds
Started	Aug 25 05:50:35 AM UTC 24
Finished	Aug 25 05:50:37 AM UTC 24
Peak memory	215144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144862304 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_bit_bash.4144862304
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3860374392
Short name	T393
Test name
Test status
Simulation time	4574492434 ps
CPU time	31.17 seconds
Started	Aug 25 05:50:35 AM UTC 24
Finished	Aug 25 05:51:08 AM UTC 24
Peak memory	215460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860374392 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.3860374392
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/5.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3580042097
Short name	T373
Test name
Test status
Simulation time	319788437 ps
CPU time	1.04 seconds
Started	Aug 25 05:50:34 AM UTC 24
Finished	Aug 25 05:50:36 AM UTC 24
Peak memory	215008 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580042097 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.3580042097
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/5.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1771759454
Short name	T148
Test name
Test status
Simulation time	353711342 ps
CPU time	4.7 seconds
Started	Aug 25 05:50:38 AM UTC 24
Finished	Aug 25 05:50:44 AM UTC 24
Peak memory	215552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771759454 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_csr_outstanding.1771759454
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/5.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.466822328
Short name	T426
Test name
Test status
Simulation time	2432189672 ps
CPU time	64.29 seconds
Started	Aug 25 05:50:36 AM UTC 24
Finished	Aug 25 05:51:42 AM UTC 24
Peak memory	228048 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=466822328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.466822328
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/5.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_errors.600545986
Short name	T378
Test name
Test status
Simulation time	745528255 ps
CPU time	6.87 seconds
Started	Aug 25 05:50:37 AM UTC 24
Finished	Aug 25 05:50:45 AM UTC 24
Peak memory	225708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600545986 -assert nopostproc +UVM_TESTNAME=rv_dm_base _test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.600545986
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/5.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1388779676
Short name	T194
Test name
Test status
Simulation time	866308490 ps
CPU time	13.52 seconds
Started	Aug 25 05:50:37 AM UTC 24
Finished	Aug 25 05:50:52 AM UTC 24
Peak memory	227808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388779676 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.1388779676
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/5.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2131659232
Short name	T382
Test name
Test status
Simulation time	695655401 ps
CPU time	2.68 seconds
Started	Aug 25 05:50:47 AM UTC 24
Finished	Aug 25 05:50:51 AM UTC 24
Peak memory	227748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2131659232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_r and_reset.2131659232
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_rw.3943306757
Short name	T381
Test name
Test status
Simulation time	294902996 ps
CPU time	3.73 seconds
Started	Aug 25 05:50:46 AM UTC 24
Finished	Aug 25 05:50:51 AM UTC 24
Peak memory	229620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943306757 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.3943306757
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/6.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.923910140
Short name	T480
Test name
Test status
Simulation time	37611498740 ps
CPU time	164.09 seconds
Started	Aug 25 05:50:43 AM UTC 24
Finished	Aug 25 05:53:30 AM UTC 24
Peak memory	215368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923910140 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_bit_bash.923910140
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2841899263
Short name	T396
Test name
Test status
Simulation time	8093757029 ps
CPU time	25.32 seconds
Started	Aug 25 05:50:42 AM UTC 24
Finished	Aug 25 05:51:08 AM UTC 24
Peak memory	215288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841899263 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.2841899263
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/6.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.866656072
Short name	T377
Test name
Test status
Simulation time	358728592 ps
CPU time	2.11 seconds
Started	Aug 25 05:50:40 AM UTC 24
Finished	Aug 25 05:50:43 AM UTC 24
Peak memory	215072 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866656072 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.866656072
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/6.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3356046658
Short name	T164
Test name
Test status
Simulation time	5443413842 ps
CPU time	9.78 seconds
Started	Aug 25 05:50:46 AM UTC 24
Finished	Aug 25 05:50:57 AM UTC 24
Peak memory	215620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356046658 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_csr_outstanding.3356046658
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/6.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.2300478260
Short name	T106
Test name
Test status
Simulation time	6794602119 ps
CPU time	67.66 seconds
Started	Aug 25 05:50:44 AM UTC 24
Finished	Aug 25 05:51:54 AM UTC 24
Peak memory	229896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2300478260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_re set.2300478260
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/6.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_errors.4080071511
Short name	T383
Test name
Test status
Simulation time	70707819 ps
CPU time	5.55 seconds
Started	Aug 25 05:50:45 AM UTC 24
Finished	Aug 25 05:50:52 AM UTC 24
Peak memory	225788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080071511 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.4080071511
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/6.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_intg_err.818574191
Short name	T199
Test name
Test status
Simulation time	3098107271 ps
CPU time	25.64 seconds
Started	Aug 25 05:50:46 AM UTC 24
Finished	Aug 25 05:51:13 AM UTC 24
Peak memory	227872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818574191 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.818574191
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/6.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2630441124
Short name	T115
Test name
Test status
Simulation time	48474941 ps
CPU time	4.18 seconds
Started	Aug 25 05:50:58 AM UTC 24
Finished	Aug 25 05:51:03 AM UTC 24
Peak memory	232176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2630441124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_r and_reset.2630441124
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_rw.1183477317
Short name	T387
Test name
Test status
Simulation time	46936810 ps
CPU time	2.18 seconds
Started	Aug 25 05:50:54 AM UTC 24
Finished	Aug 25 05:50:57 AM UTC 24
Peak memory	225600 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183477317 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.1183477317
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/7.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1929753466
Short name	T482
Test name
Test status
Simulation time	72233839773 ps
CPU time	386.9 seconds
Started	Aug 25 05:50:51 AM UTC 24
Finished	Aug 25 05:57:24 AM UTC 24
Peak memory	215552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929753466 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_bit_bash.1929753466
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3778768392
Short name	T389
Test name
Test status
Simulation time	4517073390 ps
CPU time	8.61 seconds
Started	Aug 25 05:50:51 AM UTC 24
Finished	Aug 25 05:51:01 AM UTC 24
Peak memory	215360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778768392 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.3778768392
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/7.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.25807843
Short name	T385
Test name
Test status
Simulation time	486578269 ps
CPU time	1.64 seconds
Started	Aug 25 05:50:50 AM UTC 24
Finished	Aug 25 05:50:53 AM UTC 24
Peak memory	215204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25807843 -assert nopostproc +UVM_TESTNAME=rv_dm_ba se_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.25807843
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/7.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2990066836
Short name	T150
Test name
Test status
Simulation time	424450976 ps
CPU time	8.5 seconds
Started	Aug 25 05:50:54 AM UTC 24
Finished	Aug 25 05:51:03 AM UTC 24
Peak memory	215428 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990066836 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_csr_outstanding.2990066836
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/7.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.316437194
Short name	T478
Test name
Test status
Simulation time	3999196237 ps
CPU time	137.89 seconds
Started	Aug 25 05:50:52 AM UTC 24
Finished	Aug 25 05:53:13 AM UTC 24
Peak memory	225984 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=316437194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.316437194
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/7.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_errors.3589283763
Short name	T386
Test name
Test status
Simulation time	393554336 ps
CPU time	3.08 seconds
Started	Aug 25 05:50:53 AM UTC 24
Finished	Aug 25 05:50:57 AM UTC 24
Peak memory	225728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589283763 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.3589283763
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/7.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2629792737
Short name	T400
Test name
Test status
Simulation time	324220001 ps
CPU time	3.73 seconds
Started	Aug 25 05:51:05 AM UTC 24
Finished	Aug 25 05:51:10 AM UTC 24
Peak memory	227808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2629792737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_r and_reset.2629792737
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_rw.682463120
Short name	T395
Test name
Test status
Simulation time	71157689 ps
CPU time	2.38 seconds
Started	Aug 25 05:51:04 AM UTC 24
Finished	Aug 25 05:51:08 AM UTC 24
Peak memory	225612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682463120 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.682463120
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/8.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1247883478
Short name	T394
Test name
Test status
Simulation time	8520637909 ps
CPU time	5.44 seconds
Started	Aug 25 05:51:01 AM UTC 24
Finished	Aug 25 05:51:08 AM UTC 24
Peak memory	215360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247883478 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_bit_bash.1247883478
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1684670898
Short name	T399
Test name
Test status
Simulation time	7214749252 ps
CPU time	10.36 seconds
Started	Aug 25 05:50:58 AM UTC 24
Finished	Aug 25 05:51:09 AM UTC 24
Peak memory	215456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684670898 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.1684670898
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/8.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1029659505
Short name	T390
Test name
Test status
Simulation time	350626765 ps
CPU time	2.7 seconds
Started	Aug 25 05:50:58 AM UTC 24
Finished	Aug 25 05:51:02 AM UTC 24
Peak memory	215072 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029659505 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.1029659505
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/8.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2274193969
Short name	T165
Test name
Test status
Simulation time	1547602453 ps
CPU time	6.36 seconds
Started	Aug 25 05:51:04 AM UTC 24
Finished	Aug 25 05:51:12 AM UTC 24
Peak memory	215496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274193969 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_csr_outstanding.2274193969
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/8.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3985055286
Short name	T466
Test name
Test status
Simulation time	5134092486 ps
CPU time	63.64 seconds
Started	Aug 25 05:51:01 AM UTC 24
Finished	Aug 25 05:52:07 AM UTC 24
Peak memory	229956 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3985055286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_re set.3985055286
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/8.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_errors.3654412716
Short name	T397
Test name
Test status
Simulation time	369084905 ps
CPU time	5.53 seconds
Started	Aug 25 05:51:02 AM UTC 24
Finished	Aug 25 05:51:09 AM UTC 24
Peak memory	225884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654412716 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.3654412716
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/8.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3867368845
Short name	T196
Test name
Test status
Simulation time	953069254 ps
CPU time	16.3 seconds
Started	Aug 25 05:51:02 AM UTC 24
Finished	Aug 25 05:51:20 AM UTC 24
Peak memory	232364 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867368845 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.3867368845
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/8.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2659196489
Short name	T403
Test name
Test status
Simulation time	320017373 ps
CPU time	4.56 seconds
Started	Aug 25 05:51:10 AM UTC 24
Finished	Aug 25 05:51:16 AM UTC 24
Peak memory	229896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2659196489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_r and_reset.2659196489
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_rw.711137671
Short name	T156
Test name
Test status
Simulation time	109314025 ps
CPU time	2.34 seconds
Started	Aug 25 05:51:10 AM UTC 24
Finished	Aug 25 05:51:13 AM UTC 24
Peak memory	225596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711137671 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.711137671
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/9.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3351033368
Short name	T428
Test name
Test status
Simulation time	22912526619 ps
CPU time	33.68 seconds
Started	Aug 25 05:51:09 AM UTC 24
Finished	Aug 25 05:51:44 AM UTC 24
Peak memory	215452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351033368 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_bit_bash.3351033368
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3122879918
Short name	T408
Test name
Test status
Simulation time	5990316507 ps
CPU time	14.8 seconds
Started	Aug 25 05:51:07 AM UTC 24
Finished	Aug 25 05:51:23 AM UTC 24
Peak memory	215288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122879918 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.3122879918
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/9.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2531484961
Short name	T398
Test name
Test status
Simulation time	178345853 ps
CPU time	1.74 seconds
Started	Aug 25 05:51:07 AM UTC 24
Finished	Aug 25 05:51:09 AM UTC 24
Peak memory	215044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531484961 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.2531484961
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/9.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2754108806
Short name	T166
Test name
Test status
Simulation time	2856579032 ps
CPU time	10.16 seconds
Started	Aug 25 05:51:10 AM UTC 24
Finished	Aug 25 05:51:21 AM UTC 24
Peak memory	215616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754108806 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_csr_outstanding.2754108806
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/9.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3786985834
Short name	T431
Test name
Test status
Simulation time	2098260328 ps
CPU time	33.97 seconds
Started	Aug 25 05:51:09 AM UTC 24
Finished	Aug 25 05:51:44 AM UTC 24
Peak memory	225796 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3786985834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_re set.3786985834
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/9.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_errors.2456679785
Short name	T402
Test name
Test status
Simulation time	279839111 ps
CPU time	4.72 seconds
Started	Aug 25 05:51:09 AM UTC 24
Finished	Aug 25 05:51:15 AM UTC 24
Peak memory	225764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456679785 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.2456679785
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/9.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_intg_err.648342981
Short name	T195
Test name
Test status
Simulation time	1826903204 ps
CPU time	24.66 seconds
Started	Aug 25 05:51:10 AM UTC 24
Finished	Aug 25 05:51:36 AM UTC 24
Peak memory	225732 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648342981 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.648342981
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/9.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.1684528211
Short name	T17
Test name
Test status
Simulation time	8994915782 ps
CPU time	18 seconds
Started	Aug 25 05:52:06 AM UTC 24
Finished	Aug 25 05:52:25 AM UTC 24
Peak memory	226572 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684528211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.1684528211
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.3135057668
Short name	T76
Test name
Test status
Simulation time	354179479 ps
CPU time	1.42 seconds
Started	Aug 25 05:52:14 AM UTC 24
Finished	Aug 25 05:52:17 AM UTC 24
Peak memory	258692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135057668 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_buffered_enable.3135057668
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_buffered_enable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_busy.691461472
Short name	T3
Test name
Test status
Simulation time	492472151 ps
CPU time	2.46 seconds
Started	Aug 25 05:52:06 AM UTC 24
Finished	Aug 25 05:52:10 AM UTC 24
Peak memory	215820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691461472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.691461472
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_cmderr_busy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.3583195312
Short name	T2
Test name
Test status
Simulation time	144857315 ps
CPU time	1.79 seconds
Started	Aug 25 05:52:06 AM UTC 24
Finished	Aug 25 05:52:09 AM UTC 24
Peak memory	215356 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583195312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.3583195312
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_cmderr_not_supported/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_dataaddr_rw_access.3932371683
Short name	T6
Test name
Test status
Simulation time	95856991 ps
CPU time	1.44 seconds
Started	Aug 25 05:52:08 AM UTC 24
Finished	Aug 25 05:52:11 AM UTC 24
Peak memory	213456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932371683 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.3932371683
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_dataaddr_rw_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_debug_disabled.3128039016
Short name	T92
Test name
Test status
Simulation time	279058933 ps
CPU time	1.28 seconds
Started	Aug 25 05:52:13 AM UTC 24
Finished	Aug 25 05:52:15 AM UTC 24
Peak memory	236048 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128039016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.3128039016
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_debug_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.3798354159
Short name	T14
Test name
Test status
Simulation time	3085291548 ps
CPU time	6.42 seconds
Started	Aug 25 05:52:06 AM UTC 24
Finished	Aug 25 05:52:13 AM UTC 24
Peak memory	216188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798354159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_tl_access.3798354159
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_hart_unavail.3867215533
Short name	T4
Test name
Test status
Simulation time	92852428 ps
CPU time	1.5 seconds
Started	Aug 25 05:52:07 AM UTC 24
Finished	Aug 25 05:52:10 AM UTC 24
Peak memory	213452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867215533 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.3867215533
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_hart_unavail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_hartsel_warl.4244407113
Short name	T23
Test name
Test status
Simulation time	148528011 ps
CPU time	1.55 seconds
Started	Aug 25 05:52:14 AM UTC 24
Finished	Aug 25 05:52:17 AM UTC 24
Peak memory	213300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244407113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.4244407113
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_hartsel_warl/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.298154295
Short name	T90
Test name
Test status
Simulation time	747491965 ps
CPU time	2.91 seconds
Started	Aug 25 05:52:12 AM UTC 24
Finished	Aug 25 05:52:16 AM UTC 24
Peak memory	215808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298154295 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.298154295
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1950810622
Short name	T7
Test name
Test status
Simulation time	296716256 ps
CPU time	1.62 seconds
Started	Aug 25 05:52:11 AM UTC 24
Finished	Aug 25 05:52:13 AM UTC 24
Peak memory	213460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950810622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.1950810622
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2021401916
Short name	T82
Test name
Test status
Simulation time	691990977 ps
CPU time	3.37 seconds
Started	Aug 25 05:52:12 AM UTC 24
Finished	Aug 25 05:52:16 AM UTC 24
Peak memory	215928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021401916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.2021401916
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_hard_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_idle_hint.879504273
Short name	T20
Test name
Test status
Simulation time	169965651 ps
CPU time	1.07 seconds
Started	Aug 25 05:52:11 AM UTC 24
Finished	Aug 25 05:52:13 AM UTC 24
Peak memory	213456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879504273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.879504273
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_idle_hint/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_halted.1372654216
Short name	T42
Test name
Test status
Simulation time	372992026 ps
CPU time	3.02 seconds
Started	Aug 25 05:52:07 AM UTC 24
Finished	Aug 25 05:52:11 AM UTC 24
Peak memory	215876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372654216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.1372654216
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_halted/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_resuming.1270084714
Short name	T5
Test name
Test status
Simulation time	706191222 ps
CPU time	2.95 seconds
Started	Aug 25 05:52:07 AM UTC 24
Finished	Aug 25 05:52:11 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270084714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.1270084714
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_resuming/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.3908087764
Short name	T10
Test name
Test status
Simulation time	290394970 ps
CPU time	2.02 seconds
Started	Aug 25 05:52:11 AM UTC 24
Finished	Aug 25 05:52:14 AM UTC 24
Peak memory	226172 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908087764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.3908087764
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_ndmreset_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.7573969
Short name	T41
Test name
Test status
Simulation time	665295058 ps
CPU time	4.69 seconds
Started	Aug 25 05:52:13 AM UTC 24
Finished	Aug 25 05:52:19 AM UTC 24
Peak memory	215808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7573969 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_ dm_progbuf_read_write_execute_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.7573969
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_progbuf_read_write_execute/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_tl_access.3115191406
Short name	T16
Test name
Test status
Simulation time	3536393448 ps
CPU time	10.41 seconds
Started	Aug 25 05:52:04 AM UTC 24
Finished	Aug 25 05:52:16 AM UTC 24
Peak memory	226492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115191406 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.3115191406
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_smoke.1174834216
Short name	T52
Test name
Test status
Simulation time	1331219592 ps
CPU time	8.99 seconds
Started	Aug 25 05:52:03 AM UTC 24
Finished	Aug 25 05:52:13 AM UTC 24
Peak memory	215864 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174834216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.1174834216
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.3765931797
Short name	T60
Test name
Test status
Simulation time	2045739710 ps
CPU time	28.76 seconds
Started	Aug 25 05:52:16 AM UTC 24
Finished	Aug 25 05:52:46 AM UTC 24
Peak memory	232648 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3765931797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stres s_all_with_rand_reset.3765931797
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_abstractcmd_status.3102706378
Short name	T61
Test name
Test status
Simulation time	96174573 ps
CPU time	1.26 seconds
Started	Aug 25 05:52:22 AM UTC 24
Finished	Aug 25 05:52:24 AM UTC 24
Peak memory	213336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102706378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_abstractcmd_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.3102706378
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_abstractcmd_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_alert_test.1703957913
Short name	T45
Test name
Test status
Simulation time	61798545 ps
CPU time	1.22 seconds
Started	Aug 25 05:52:26 AM UTC 24
Finished	Aug 25 05:52:28 AM UTC 24
Peak memory	215528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703957913 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.1703957913
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_autoincr_sba_tl_access.1075293599
Short name	T18
Test name
Test status
Simulation time	5825651184 ps
CPU time	11.19 seconds
Started	Aug 25 05:52:17 AM UTC 24
Finished	Aug 25 05:52:29 AM UTC 24
Peak memory	226692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075293599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.1075293599
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_bad_sba_tl_access.422491020
Short name	T38
Test name
Test status
Simulation time	4045751250 ps
CPU time	5.13 seconds
Started	Aug 25 05:52:17 AM UTC 24
Finished	Aug 25 05:52:23 AM UTC 24
Peak memory	226572 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422491020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.422491020
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_buffered_enable.2492882469
Short name	T62
Test name
Test status
Simulation time	133867093 ps
CPU time	1.77 seconds
Started	Aug 25 05:52:23 AM UTC 24
Finished	Aug 25 05:52:26 AM UTC 24
Peak memory	257836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492882469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_buffered_enable.2492882469
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_buffered_enable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_busy.1860176350
Short name	T33
Test name
Test status
Simulation time	1249273372 ps
CPU time	2.65 seconds
Started	Aug 25 05:52:17 AM UTC 24
Finished	Aug 25 05:52:21 AM UTC 24
Peak memory	215812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860176350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.1860176350
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_cmderr_busy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.1237986508
Short name	T26
Test name
Test status
Simulation time	290542942 ps
CPU time	2.44 seconds
Started	Aug 25 05:52:18 AM UTC 24
Finished	Aug 25 05:52:22 AM UTC 24
Peak memory	215808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237986508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.1237986508
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_cmderr_exception/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.332547998
Short name	T49
Test name
Test status
Simulation time	322029696 ps
CPU time	1.55 seconds
Started	Aug 25 05:52:18 AM UTC 24
Finished	Aug 25 05:52:21 AM UTC 24
Peak memory	213456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332547998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_cmderr_halt_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.332547998
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_cmderr_halt_resume/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_not_supported.3021611907
Short name	T50
Test name
Test status
Simulation time	310893773 ps
CPU time	2.94 seconds
Started	Aug 25 05:52:18 AM UTC 24
Finished	Aug 25 05:52:22 AM UTC 24
Peak memory	215808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021611907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.3021611907
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_cmderr_not_supported/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_dataaddr_rw_access.1246895419
Short name	T102
Test name
Test status
Simulation time	56636233 ps
CPU time	1.27 seconds
Started	Aug 25 05:52:19 AM UTC 24
Finished	Aug 25 05:52:21 AM UTC 24
Peak memory	213456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246895419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.1246895419
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_dataaddr_rw_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_debug_disabled.487683590
Short name	T89
Test name
Test status
Simulation time	44025781 ps
CPU time	1.41 seconds
Started	Aug 25 05:52:23 AM UTC 24
Finished	Aug 25 05:52:26 AM UTC 24
Peak memory	236172 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487683590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.487683590
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_debug_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.1803165335
Short name	T238
Test name
Test status
Simulation time	9976684861 ps
CPU time	46.64 seconds
Started	Aug 25 05:52:17 AM UTC 24
Finished	Aug 25 05:53:05 AM UTC 24
Peak memory	226568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803165335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_tl_access.1803165335
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.3892491725
Short name	T81
Test name
Test status
Simulation time	594204331 ps
CPU time	2.1 seconds
Started	Aug 25 05:52:23 AM UTC 24
Finished	Aug 25 05:52:26 AM UTC 24
Peak memory	215876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892491725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.3892491725
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_dmi_failed_op/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_halt_resume_whereto.771364058
Short name	T53
Test name
Test status
Simulation time	1014749641 ps
CPU time	2.54 seconds
Started	Aug 25 05:52:19 AM UTC 24
Finished	Aug 25 05:52:22 AM UTC 24
Peak memory	215800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771364058 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.771364058
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_halt_resume_whereto/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_hart_unavail.270143127
Short name	T94
Test name
Test status
Simulation time	384366660 ps
CPU time	1.24 seconds
Started	Aug 25 05:52:18 AM UTC 24
Finished	Aug 25 05:52:21 AM UTC 24
Peak memory	213456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270143127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.270143127
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_hart_unavail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.2710868195
Short name	T99
Test name
Test status
Simulation time	656698393 ps
CPU time	3.4 seconds
Started	Aug 25 05:52:22 AM UTC 24
Finished	Aug 25 05:52:26 AM UTC 24
Peak memory	215828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710868195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.2710868195
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1481952448
Short name	T100
Test name
Test status
Simulation time	795395441 ps
CPU time	4.06 seconds
Started	Aug 25 05:52:22 AM UTC 24
Finished	Aug 25 05:52:27 AM UTC 24
Peak memory	215808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481952448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.1481952448
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_hard_reset.2952868103
Short name	T83
Test name
Test status
Simulation time	793425743 ps
CPU time	5.49 seconds
Started	Aug 25 05:52:22 AM UTC 24
Finished	Aug 25 05:52:29 AM UTC 24
Peak memory	215864 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952868103 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.2952868103
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_hard_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1863927789
Short name	T84
Test name
Test status
Simulation time	302395559 ps
CPU time	2.94 seconds
Started	Aug 25 05:52:22 AM UTC 24
Finished	Aug 25 05:52:26 AM UTC 24
Peak memory	215804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863927789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.1863927789
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_idle_hint/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_halted.1573154900
Short name	T101
Test name
Test status
Simulation time	89595559 ps
CPU time	1.26 seconds
Started	Aug 25 05:52:18 AM UTC 24
Finished	Aug 25 05:52:21 AM UTC 24
Peak memory	213460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573154900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.1573154900
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_mem_tl_access_halted/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_resuming.2545309947
Short name	T24
Test name
Test status
Simulation time	178354936 ps
CPU time	1.34 seconds
Started	Aug 25 05:52:18 AM UTC 24
Finished	Aug 25 05:52:21 AM UTC 24
Peak memory	213460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545309947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.2545309947
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_mem_tl_access_resuming/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_ndmreset_req.558175025
Short name	T36
Test name
Test status
Simulation time	439483813 ps
CPU time	1.41 seconds
Started	Aug 25 05:52:20 AM UTC 24
Finished	Aug 25 05:52:22 AM UTC 24
Peak memory	225796 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558175025 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.558175025
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_ndmreset_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_progbuf_read_write_execute.585938009
Short name	T59
Test name
Test status
Simulation time	1006748936 ps
CPU time	2.37 seconds
Started	Aug 25 05:52:23 AM UTC 24
Finished	Aug 25 05:52:27 AM UTC 24
Peak memory	215936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585938009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_progbuf_read_write_execute_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.585938009
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_progbuf_read_write_execute/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_rom_read_access.1722097468
Short name	T64
Test name
Test status
Simulation time	42471260 ps
CPU time	1.45 seconds
Started	Aug 25 05:52:22 AM UTC 24
Finished	Aug 25 05:52:25 AM UTC 24
Peak memory	225796 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722097468 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_rom_read_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.1722097468
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_rom_read_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_debug_disabled.3665680887
Short name	T98
Test name
Test status
Simulation time	794471059 ps
CPU time	3.59 seconds
Started	Aug 25 05:52:20 AM UTC 24
Finished	Aug 25 05:52:24 AM UTC 24
Peak memory	216080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665680887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.3665680887
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_sba_debug_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_tl_access.4102907054
Short name	T97
Test name
Test status
Simulation time	2107282630 ps
CPU time	5.79 seconds
Started	Aug 25 05:52:17 AM UTC 24
Finished	Aug 25 05:52:24 AM UTC 24
Peak memory	216268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102907054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.4102907054
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_sec_cm.1183332535
Short name	T87
Test name
Test status
Simulation time	481062388 ps
CPU time	1.96 seconds
Started	Aug 25 05:52:25 AM UTC 24
Finished	Aug 25 05:52:28 AM UTC 24
Peak memory	253496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183332535 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.1183332535
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_smoke.2919145001
Short name	T75
Test name
Test status
Simulation time	1058277267 ps
CPU time	3.69 seconds
Started	Aug 25 05:52:17 AM UTC 24
Finished	Aug 25 05:52:22 AM UTC 24
Peak memory	216016 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919145001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.2919145001
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.660188932
Short name	T51
Test name
Test status
Simulation time	2229872348 ps
CPU time	8.39 seconds
Started	Aug 25 05:52:23 AM UTC 24
Finished	Aug 25 05:52:33 AM UTC 24
Peak memory	226308 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660188932 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.660188932
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/1.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/10.rv_dm_alert_test.2742653349
Short name	T210
Test name
Test status
Simulation time	63026508 ps
CPU time	1.27 seconds
Started	Aug 25 05:53:14 AM UTC 24
Finished	Aug 25 05:53:16 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742653349 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.2742653349
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/10.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/10.rv_dm_autoincr_sba_tl_access.3964751162
Short name	T245
Test name
Test status
Simulation time	16693428572 ps
CPU time	19.8 seconds
Started	Aug 25 05:53:12 AM UTC 24
Finished	Aug 25 05:53:33 AM UTC 24
Peak memory	226416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964751162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.3964751162
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/10.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/10.rv_dm_bad_sba_tl_access.792013656
Short name	T258
Test name
Test status
Simulation time	7526042201 ps
CPU time	42.5 seconds
Started	Aug 25 05:53:11 AM UTC 24
Finished	Aug 25 05:53:55 AM UTC 24
Peak memory	226544 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792013656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.792013656
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/10.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.2553565572
Short name	T250
Test name
Test status
Simulation time	4529770260 ps
CPU time	30.32 seconds
Started	Aug 25 05:53:10 AM UTC 24
Finished	Aug 25 05:53:42 AM UTC 24
Peak memory	216376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553565572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_tl_access.2553565572
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/10.rv_dm_sba_tl_access.94678485
Short name	T221
Test name
Test status
Simulation time	2977223450 ps
CPU time	18.98 seconds
Started	Aug 25 05:53:10 AM UTC 24
Finished	Aug 25 05:53:30 AM UTC 24
Peak memory	216312 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94678485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv _dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.94678485
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/10.rv_dm_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/10.rv_dm_stress_all.521881789
Short name	T34
Test name
Test status
Simulation time	2745625806 ps
CPU time	8.76 seconds
Started	Aug 25 05:53:14 AM UTC 24
Finished	Aug 25 05:53:23 AM UTC 24
Peak memory	226260 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521881789 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.521881789
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/10.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/11.rv_dm_alert_test.4216246745
Short name	T242
Test name
Test status
Simulation time	154563812 ps
CPU time	1.86 seconds
Started	Aug 25 05:53:19 AM UTC 24
Finished	Aug 25 05:53:22 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216246745 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.4216246745
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/11.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/11.rv_dm_autoincr_sba_tl_access.1302312157
Short name	T261
Test name
Test status
Simulation time	12450322948 ps
CPU time	39.3 seconds
Started	Aug 25 05:53:17 AM UTC 24
Finished	Aug 25 05:53:58 AM UTC 24
Peak memory	226496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302312157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.1302312157
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/11.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/11.rv_dm_bad_sba_tl_access.3965871768
Short name	T244
Test name
Test status
Simulation time	7902430040 ps
CPU time	16.05 seconds
Started	Aug 25 05:53:16 AM UTC 24
Finished	Aug 25 05:53:33 AM UTC 24
Peak memory	226608 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965871768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.3965871768
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/11.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.1891168395
Short name	T297
Test name
Test status
Simulation time	14676585239 ps
CPU time	56.16 seconds
Started	Aug 25 05:53:15 AM UTC 24
Finished	Aug 25 05:54:12 AM UTC 24
Peak memory	226432 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891168395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_tl_access.1891168395
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/11.rv_dm_sba_tl_access.3210368232
Short name	T191
Test name
Test status
Simulation time	2414526791 ps
CPU time	6.64 seconds
Started	Aug 25 05:53:15 AM UTC 24
Finished	Aug 25 05:53:22 AM UTC 24
Peak memory	216396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210368232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.3210368232
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/11.rv_dm_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/11.rv_dm_stress_all.1684841083
Short name	T67
Test name
Test status
Simulation time	1497923371 ps
CPU time	6.88 seconds
Started	Aug 25 05:53:19 AM UTC 24
Finished	Aug 25 05:53:27 AM UTC 24
Peak memory	216140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684841083 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.1684841083
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/11.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/12.rv_dm_alert_test.3103053609
Short name	T212
Test name
Test status
Simulation time	50844796 ps
CPU time	1.27 seconds
Started	Aug 25 05:53:27 AM UTC 24
Finished	Aug 25 05:53:29 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103053609 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.3103053609
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/12.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/12.rv_dm_autoincr_sba_tl_access.2202711582
Short name	T181
Test name
Test status
Simulation time	4115208494 ps
CPU time	4.97 seconds
Started	Aug 25 05:53:24 AM UTC 24
Finished	Aug 25 05:53:30 AM UTC 24
Peak memory	226612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202711582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.2202711582
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/12.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.79366951
Short name	T211
Test name
Test status
Simulation time	2219585464 ps
CPU time	7.64 seconds
Started	Aug 25 05:53:24 AM UTC 24
Finished	Aug 25 05:53:32 AM UTC 24
Peak memory	216260 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79366951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_tl_access.79366951
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/12.rv_dm_sba_tl_access.2571232624
Short name	T243
Test name
Test status
Simulation time	3088431886 ps
CPU time	4.5 seconds
Started	Aug 25 05:53:21 AM UTC 24
Finished	Aug 25 05:53:27 AM UTC 24
Peak memory	216464 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571232624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.2571232624
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/12.rv_dm_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/12.rv_dm_stress_all.3497690351
Short name	T179
Test name
Test status
Simulation time	5673694085 ps
CPU time	4.83 seconds
Started	Aug 25 05:53:25 AM UTC 24
Finished	Aug 25 05:53:31 AM UTC 24
Peak memory	226320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497690351 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.3497690351
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/12.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/13.rv_dm_alert_test.3049701537
Short name	T222
Test name
Test status
Simulation time	50890858 ps
CPU time	1.38 seconds
Started	Aug 25 05:53:32 AM UTC 24
Finished	Aug 25 05:53:34 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049701537 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.3049701537
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/13.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/13.rv_dm_autoincr_sba_tl_access.3912565250
Short name	T283
Test name
Test status
Simulation time	14718088627 ps
CPU time	36.39 seconds
Started	Aug 25 05:53:30 AM UTC 24
Finished	Aug 25 05:54:08 AM UTC 24
Peak memory	226552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912565250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.3912565250
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/13.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/13.rv_dm_bad_sba_tl_access.2062777323
Short name	T316
Test name
Test status
Simulation time	16443460416 ps
CPU time	50.27 seconds
Started	Aug 25 05:53:30 AM UTC 24
Finished	Aug 25 05:54:22 AM UTC 24
Peak memory	226484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062777323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.2062777323
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/13.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.1899822649
Short name	T186
Test name
Test status
Simulation time	1403770505 ps
CPU time	3.15 seconds
Started	Aug 25 05:53:28 AM UTC 24
Finished	Aug 25 05:53:32 AM UTC 24
Peak memory	216316 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899822649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_tl_access.1899822649
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/13.rv_dm_sba_tl_access.4252201071
Short name	T247
Test name
Test status
Simulation time	1335515490 ps
CPU time	5.97 seconds
Started	Aug 25 05:53:28 AM UTC 24
Finished	Aug 25 05:53:35 AM UTC 24
Peak memory	216260 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252201071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.4252201071
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/13.rv_dm_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/13.rv_dm_stress_all.2455483534
Short name	T12
Test name
Test status
Simulation time	918642121 ps
CPU time	2.8 seconds
Started	Aug 25 05:53:30 AM UTC 24
Finished	Aug 25 05:53:34 AM UTC 24
Peak memory	226316 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455483534 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.2455483534
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/13.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/14.rv_dm_alert_test.3993142523
Short name	T214
Test name
Test status
Simulation time	68214462 ps
CPU time	0.92 seconds
Started	Aug 25 05:53:34 AM UTC 24
Finished	Aug 25 05:53:36 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993142523 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.3993142523
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/14.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/14.rv_dm_autoincr_sba_tl_access.508954853
Short name	T254
Test name
Test status
Simulation time	1918189570 ps
CPU time	12.29 seconds
Started	Aug 25 05:53:34 AM UTC 24
Finished	Aug 25 05:53:48 AM UTC 24
Peak memory	226556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508954853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.508954853
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/14.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/14.rv_dm_bad_sba_tl_access.303868215
Short name	T239
Test name
Test status
Simulation time	3674416780 ps
CPU time	11.04 seconds
Started	Aug 25 05:53:33 AM UTC 24
Finished	Aug 25 05:53:45 AM UTC 24
Peak memory	216380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303868215 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.303868215
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/14.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.1082221090
Short name	T252
Test name
Test status
Simulation time	3381486391 ps
CPU time	10.64 seconds
Started	Aug 25 05:53:33 AM UTC 24
Finished	Aug 25 05:53:45 AM UTC 24
Peak memory	216300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082221090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_tl_access.1082221090
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/14.rv_dm_sba_tl_access.3460040644
Short name	T257
Test name
Test status
Simulation time	3516423748 ps
CPU time	19.01 seconds
Started	Aug 25 05:53:32 AM UTC 24
Finished	Aug 25 05:53:52 AM UTC 24
Peak memory	216272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460040644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.3460040644
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/14.rv_dm_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/15.rv_dm_alert_test.3702044374
Short name	T248
Test name
Test status
Simulation time	93521066 ps
CPU time	1.33 seconds
Started	Aug 25 05:53:38 AM UTC 24
Finished	Aug 25 05:53:40 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702044374 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.3702044374
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/15.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/15.rv_dm_autoincr_sba_tl_access.996097941
Short name	T325
Test name
Test status
Simulation time	11057681539 ps
CPU time	61.53 seconds
Started	Aug 25 05:53:36 AM UTC 24
Finished	Aug 25 05:54:39 AM UTC 24
Peak memory	226504 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996097941 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.996097941
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/15.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/15.rv_dm_bad_sba_tl_access.4096522614
Short name	T253
Test name
Test status
Simulation time	1762687400 ps
CPU time	8.62 seconds
Started	Aug 25 05:53:36 AM UTC 24
Finished	Aug 25 05:53:45 AM UTC 24
Peak memory	226472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096522614 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.4096522614
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/15.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.290414327
Short name	T319
Test name
Test status
Simulation time	11491377716 ps
CPU time	46.51 seconds
Started	Aug 25 05:53:36 AM UTC 24
Finished	Aug 25 05:54:24 AM UTC 24
Peak memory	226632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290414327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_tl_access.290414327
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/15.rv_dm_sba_tl_access.4059915086
Short name	T223
Test name
Test status
Simulation time	1902141115 ps
CPU time	12.84 seconds
Started	Aug 25 05:53:36 AM UTC 24
Finished	Aug 25 05:53:50 AM UTC 24
Peak memory	216272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059915086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.4059915086
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/15.rv_dm_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/15.rv_dm_stress_all.256166838
Short name	T11
Test name
Test status
Simulation time	4292299705 ps
CPU time	7.55 seconds
Started	Aug 25 05:53:37 AM UTC 24
Finished	Aug 25 05:53:45 AM UTC 24
Peak memory	216008 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256166838 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.256166838
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/15.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/16.rv_dm_alert_test.1060329160
Short name	T226
Test name
Test status
Simulation time	36121360 ps
CPU time	1.05 seconds
Started	Aug 25 05:53:43 AM UTC 24
Finished	Aug 25 05:53:45 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060329160 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.1060329160
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/16.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/16.rv_dm_bad_sba_tl_access.2086197950
Short name	T187
Test name
Test status
Simulation time	2577112495 ps
CPU time	6.59 seconds
Started	Aug 25 05:53:40 AM UTC 24
Finished	Aug 25 05:53:48 AM UTC 24
Peak memory	226492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086197950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.2086197950
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/16.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.3730283362
Short name	T251
Test name
Test status
Simulation time	1474056179 ps
CPU time	3.01 seconds
Started	Aug 25 05:53:40 AM UTC 24
Finished	Aug 25 05:53:44 AM UTC 24
Peak memory	216256 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730283362 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_tl_access.3730283362
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/16.rv_dm_sba_tl_access.544151014
Short name	T266
Test name
Test status
Simulation time	8281843983 ps
CPU time	18.18 seconds
Started	Aug 25 05:53:40 AM UTC 24
Finished	Aug 25 05:54:00 AM UTC 24
Peak memory	226500 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544151014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.544151014
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/16.rv_dm_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/16.rv_dm_stress_all.1697719253
Short name	T28
Test name
Test status
Simulation time	2422664235 ps
CPU time	5.03 seconds
Started	Aug 25 05:53:42 AM UTC 24
Finished	Aug 25 05:53:49 AM UTC 24
Peak memory	226440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697719253 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.1697719253
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/16.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/17.rv_dm_alert_test.3909269211
Short name	T255
Test name
Test status
Simulation time	148541705 ps
CPU time	1.74 seconds
Started	Aug 25 05:53:46 AM UTC 24
Finished	Aug 25 05:53:49 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909269211 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.3909269211
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/17.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/17.rv_dm_autoincr_sba_tl_access.2564110744
Short name	T182
Test name
Test status
Simulation time	4557953069 ps
CPU time	7.77 seconds
Started	Aug 25 05:53:46 AM UTC 24
Finished	Aug 25 05:53:55 AM UTC 24
Peak memory	216252 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564110744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.2564110744
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/17.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/17.rv_dm_bad_sba_tl_access.3099893280
Short name	T259
Test name
Test status
Simulation time	4764027337 ps
CPU time	9.81 seconds
Started	Aug 25 05:53:46 AM UTC 24
Finished	Aug 25 05:53:57 AM UTC 24
Peak memory	226428 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099893280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.3099893280
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/17.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.3594754139
Short name	T256
Test name
Test status
Simulation time	1459265665 ps
CPU time	3.94 seconds
Started	Aug 25 05:53:46 AM UTC 24
Finished	Aug 25 05:53:51 AM UTC 24
Peak memory	216128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594754139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_tl_access.3594754139
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/17.rv_dm_sba_tl_access.2465472590
Short name	T262
Test name
Test status
Simulation time	3558205825 ps
CPU time	12.21 seconds
Started	Aug 25 05:53:45 AM UTC 24
Finished	Aug 25 05:53:58 AM UTC 24
Peak memory	216272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465472590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.2465472590
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/17.rv_dm_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/17.rv_dm_stress_all.3180041349
Short name	T271
Test name
Test status
Simulation time	2748491841 ps
CPU time	15.21 seconds
Started	Aug 25 05:53:46 AM UTC 24
Finished	Aug 25 05:54:03 AM UTC 24
Peak memory	216136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180041349 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.3180041349
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/17.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/18.rv_dm_alert_test.3383544870
Short name	T213
Test name
Test status
Simulation time	63547931 ps
CPU time	1.2 seconds
Started	Aug 25 05:53:52 AM UTC 24
Finished	Aug 25 05:53:54 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383544870 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.3383544870
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/18.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/18.rv_dm_bad_sba_tl_access.852936811
Short name	T263
Test name
Test status
Simulation time	2336021100 ps
CPU time	7.71 seconds
Started	Aug 25 05:53:50 AM UTC 24
Finished	Aug 25 05:53:58 AM UTC 24
Peak memory	216272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852936811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.852936811
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/18.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.3427510828
Short name	T268
Test name
Test status
Simulation time	2187752010 ps
CPU time	10.51 seconds
Started	Aug 25 05:53:48 AM UTC 24
Finished	Aug 25 05:54:00 AM UTC 24
Peak memory	216388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427510828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_tl_access.3427510828
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/18.rv_dm_sba_tl_access.2687421911
Short name	T274
Test name
Test status
Simulation time	14932584353 ps
CPU time	13.93 seconds
Started	Aug 25 05:53:48 AM UTC 24
Finished	Aug 25 05:54:03 AM UTC 24
Peak memory	226508 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687421911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.2687421911
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/18.rv_dm_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/18.rv_dm_stress_all.680272682
Short name	T69
Test name
Test status
Simulation time	3789969220 ps
CPU time	7.01 seconds
Started	Aug 25 05:53:51 AM UTC 24
Finished	Aug 25 05:53:59 AM UTC 24
Peak memory	226256 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680272682 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.680272682
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/18.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/19.rv_dm_alert_test.1386444242
Short name	T264
Test name
Test status
Simulation time	111890972 ps
CPU time	1.24 seconds
Started	Aug 25 05:53:56 AM UTC 24
Finished	Aug 25 05:53:59 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386444242 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.1386444242
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/19.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.3358295993
Short name	T329
Test name
Test status
Simulation time	50135492153 ps
CPU time	51.75 seconds
Started	Aug 25 05:53:56 AM UTC 24
Finished	Aug 25 05:54:50 AM UTC 24
Peak memory	230720 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358295993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.3358295993
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/19.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/19.rv_dm_bad_sba_tl_access.2518317583
Short name	T267
Test name
Test status
Simulation time	1982028789 ps
CPU time	3.78 seconds
Started	Aug 25 05:53:55 AM UTC 24
Finished	Aug 25 05:54:00 AM UTC 24
Peak memory	226568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518317583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.2518317583
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/19.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.4056467865
Short name	T265
Test name
Test status
Simulation time	1324386995 ps
CPU time	2.93 seconds
Started	Aug 25 05:53:55 AM UTC 24
Finished	Aug 25 05:53:59 AM UTC 24
Peak memory	216196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056467865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_tl_access.4056467865
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/19.rv_dm_sba_tl_access.4205163516
Short name	T260
Test name
Test status
Simulation time	1502170418 ps
CPU time	3.78 seconds
Started	Aug 25 05:53:53 AM UTC 24
Finished	Aug 25 05:53:58 AM UTC 24
Peak memory	216248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205163516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.4205163516
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/19.rv_dm_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.625657124
Short name	T327
Test name
Test status
Simulation time	11331663414 ps
CPU time	47.97 seconds
Started	Aug 25 05:53:56 AM UTC 24
Finished	Aug 25 05:54:46 AM UTC 24
Peak memory	216000 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625657124 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.625657124
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/19.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.1243338693
Short name	T46
Test name
Test status
Simulation time	80689804 ps
CPU time	1.13 seconds
Started	Aug 25 05:52:27 AM UTC 24
Finished	Aug 25 05:52:30 AM UTC 24
Peak memory	215936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243338693 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.1243338693
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/2.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.292724812
Short name	T19
Test name
Test status
Simulation time	11778206822 ps
CPU time	21.86 seconds
Started	Aug 25 05:52:26 AM UTC 24
Finished	Aug 25 05:52:49 AM UTC 24
Peak memory	226684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292724812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.292724812
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/2.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.2562440543
Short name	T177
Test name
Test status
Simulation time	15795500655 ps
CPU time	45.29 seconds
Started	Aug 25 05:52:26 AM UTC 24
Finished	Aug 25 05:53:13 AM UTC 24
Peak memory	226492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562440543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.2562440543
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/2.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.3282173577
Short name	T117
Test name
Test status
Simulation time	2127992538 ps
CPU time	2.32 seconds
Started	Aug 25 05:52:26 AM UTC 24
Finished	Aug 25 05:52:29 AM UTC 24
Peak memory	216188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282173577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_tl_access.3282173577
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.75914581
Short name	T65
Test name
Test status
Simulation time	843789207 ps
CPU time	5.8 seconds
Started	Aug 25 05:52:27 AM UTC 24
Finished	Aug 25 05:52:34 AM UTC 24
Peak memory	215936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75914581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv _dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_halt_resume_whereto.75914581
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/2.rv_dm_halt_resume_whereto/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.3480778235
Short name	T228
Test name
Test status
Simulation time	65694147 ps
CPU time	1.08 seconds
Started	Aug 25 05:52:27 AM UTC 24
Finished	Aug 25 05:52:29 AM UTC 24
Peak memory	213452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480778235 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.3480778235
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/2.rv_dm_hart_unavail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.1613284151
Short name	T135
Test name
Test status
Simulation time	1785768428 ps
CPU time	3 seconds
Started	Aug 25 05:52:26 AM UTC 24
Finished	Aug 25 05:52:30 AM UTC 24
Peak memory	215852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613284151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.1613284151
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/2.rv_dm_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.724582456
Short name	T88
Test name
Test status
Simulation time	2222740474 ps
CPU time	5 seconds
Started	Aug 25 05:52:27 AM UTC 24
Finished	Aug 25 05:52:34 AM UTC 24
Peak memory	254744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724582456 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.724582456
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/2.rv_dm_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/2.rv_dm_sparse_lc_gate_fsm.804486392
Short name	T77
Test name
Test status
Simulation time	87086657 ps
CPU time	1.29 seconds
Started	Aug 25 05:52:27 AM UTC 24
Finished	Aug 25 05:52:30 AM UTC 24
Peak memory	225856 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804486392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sparse_lc_gate_fsm.804486392
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/2.rv_dm_sparse_lc_gate_fsm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.3031783291
Short name	T118
Test name
Test status
Simulation time	8763067774 ps
CPU time	114.89 seconds
Started	Aug 25 05:52:27 AM UTC 24
Finished	Aug 25 05:54:25 AM UTC 24
Peak memory	233220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3031783291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stres s_all_with_rand_reset.3031783291
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/20.rv_dm_alert_test.2021323830
Short name	T227
Test name
Test status
Simulation time	115786239 ps
CPU time	1.3 seconds
Started	Aug 25 05:53:59 AM UTC 24
Finished	Aug 25 05:54:01 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021323830 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.2021323830
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/20.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.2620931286
Short name	T280
Test name
Test status
Simulation time	3303735059 ps
CPU time	7.25 seconds
Started	Aug 25 05:53:58 AM UTC 24
Finished	Aug 25 05:54:06 AM UTC 24
Peak memory	216060 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620931286 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.2620931286
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/20.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/21.rv_dm_alert_test.758254015
Short name	T269
Test name
Test status
Simulation time	47385785 ps
CPU time	1.18 seconds
Started	Aug 25 05:53:59 AM UTC 24
Finished	Aug 25 05:54:01 AM UTC 24
Peak memory	215936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758254015 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.758254015
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/21.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/21.rv_dm_stress_all.3559186201
Short name	T278
Test name
Test status
Simulation time	7988974859 ps
CPU time	5.14 seconds
Started	Aug 25 05:53:59 AM UTC 24
Finished	Aug 25 05:54:05 AM UTC 24
Peak memory	216136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559186201 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.3559186201
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/21.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/22.rv_dm_alert_test.3075774079
Short name	T270
Test name
Test status
Simulation time	94533285 ps
CPU time	1.06 seconds
Started	Aug 25 05:53:59 AM UTC 24
Finished	Aug 25 05:54:01 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075774079 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.3075774079
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/22.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.3164872485
Short name	T285
Test name
Test status
Simulation time	3025378282 ps
CPU time	8.47 seconds
Started	Aug 25 05:53:59 AM UTC 24
Finished	Aug 25 05:54:09 AM UTC 24
Peak memory	216068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164872485 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.3164872485
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/22.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/23.rv_dm_alert_test.2928291216
Short name	T272
Test name
Test status
Simulation time	33164459 ps
CPU time	1.15 seconds
Started	Aug 25 05:54:00 AM UTC 24
Finished	Aug 25 05:54:03 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928291216 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.2928291216
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/23.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/23.rv_dm_stress_all.3621275973
Short name	T29
Test name
Test status
Simulation time	3889170870 ps
CPU time	5.61 seconds
Started	Aug 25 05:54:00 AM UTC 24
Finished	Aug 25 05:54:07 AM UTC 24
Peak memory	216208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621275973 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.3621275973
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/23.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/24.rv_dm_alert_test.2740817420
Short name	T273
Test name
Test status
Simulation time	171090942 ps
CPU time	1.49 seconds
Started	Aug 25 05:54:01 AM UTC 24
Finished	Aug 25 05:54:03 AM UTC 24
Peak memory	215412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740817420 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.2740817420
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/24.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/24.rv_dm_stress_all.1501519044
Short name	T287
Test name
Test status
Simulation time	4701537163 ps
CPU time	7.25 seconds
Started	Aug 25 05:54:00 AM UTC 24
Finished	Aug 25 05:54:09 AM UTC 24
Peak memory	216268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501519044 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.1501519044
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/24.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/25.rv_dm_alert_test.3052699292
Short name	T275
Test name
Test status
Simulation time	65817716 ps
CPU time	1.18 seconds
Started	Aug 25 05:54:02 AM UTC 24
Finished	Aug 25 05:54:05 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052699292 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.3052699292
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/25.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.1594945964
Short name	T21
Test name
Test status
Simulation time	4962377760 ps
CPU time	6.66 seconds
Started	Aug 25 05:54:01 AM UTC 24
Finished	Aug 25 05:54:08 AM UTC 24
Peak memory	226324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594945964 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.1594945964
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/25.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/26.rv_dm_alert_test.2110556706
Short name	T276
Test name
Test status
Simulation time	121192857 ps
CPU time	1.48 seconds
Started	Aug 25 05:54:02 AM UTC 24
Finished	Aug 25 05:54:05 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110556706 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.2110556706
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/26.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/26.rv_dm_stress_all.3693519112
Short name	T286
Test name
Test status
Simulation time	2462161520 ps
CPU time	5.23 seconds
Started	Aug 25 05:54:02 AM UTC 24
Finished	Aug 25 05:54:09 AM UTC 24
Peak memory	226352 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693519112 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.3693519112
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/26.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/27.rv_dm_alert_test.3200644520
Short name	T277
Test name
Test status
Simulation time	35708300 ps
CPU time	1.27 seconds
Started	Aug 25 05:54:02 AM UTC 24
Finished	Aug 25 05:54:05 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200644520 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.3200644520
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/27.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.2813451756
Short name	T284
Test name
Test status
Simulation time	2295541084 ps
CPU time	4.72 seconds
Started	Aug 25 05:54:02 AM UTC 24
Finished	Aug 25 05:54:09 AM UTC 24
Peak memory	216268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813451756 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.2813451756
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/27.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/28.rv_dm_alert_test.497626633
Short name	T279
Test name
Test status
Simulation time	132376416 ps
CPU time	1.26 seconds
Started	Aug 25 05:54:03 AM UTC 24
Finished	Aug 25 05:54:06 AM UTC 24
Peak memory	215936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497626633 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.497626633
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/28.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/28.rv_dm_stress_all.2688972056
Short name	T13
Test name
Test status
Simulation time	1715923513 ps
CPU time	9.35 seconds
Started	Aug 25 05:54:03 AM UTC 24
Finished	Aug 25 05:54:15 AM UTC 24
Peak memory	226248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688972056 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.2688972056
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/28.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/29.rv_dm_alert_test.1159269608
Short name	T281
Test name
Test status
Simulation time	78289292 ps
CPU time	1.11 seconds
Started	Aug 25 05:54:04 AM UTC 24
Finished	Aug 25 05:54:07 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159269608 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.1159269608
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/29.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/29.rv_dm_stress_all.163966347
Short name	T321
Test name
Test status
Simulation time	7410636747 ps
CPU time	19.56 seconds
Started	Aug 25 05:54:04 AM UTC 24
Finished	Aug 25 05:54:26 AM UTC 24
Peak memory	216084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163966347 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.163966347
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/29.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.4066508867
Short name	T167
Test name
Test status
Simulation time	268575258 ps
CPU time	1.02 seconds
Started	Aug 25 05:52:33 AM UTC 24
Finished	Aug 25 05:52:36 AM UTC 24
Peak memory	215936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066508867 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.4066508867
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/3.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.49376000
Short name	T136
Test name
Test status
Simulation time	900682868 ps
CPU time	5.62 seconds
Started	Aug 25 05:52:29 AM UTC 24
Finished	Aug 25 05:52:35 AM UTC 24
Peak memory	216212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49376000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv _dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.49376000
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/3.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.1196169995
Short name	T137
Test name
Test status
Simulation time	343710885 ps
CPU time	1.89 seconds
Started	Aug 25 05:52:31 AM UTC 24
Finished	Aug 25 05:52:34 AM UTC 24
Peak memory	256816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196169995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_buffered_enable.1196169995
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/3.rv_dm_buffered_enable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1814408744
Short name	T230
Test name
Test status
Simulation time	4672625320 ps
CPU time	7.09 seconds
Started	Aug 25 05:52:29 AM UTC 24
Finished	Aug 25 05:52:37 AM UTC 24
Peak memory	216188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814408744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_tl_access.1814408744
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.1174625593
Short name	T56
Test name
Test status
Simulation time	476734509 ps
CPU time	1.66 seconds
Started	Aug 25 05:52:31 AM UTC 24
Finished	Aug 25 05:52:34 AM UTC 24
Peak memory	213452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174625593 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_halt_resume_whereto.1174625593
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/3.rv_dm_halt_resume_whereto/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/3.rv_dm_hart_unavail.4068554803
Short name	T229
Test name
Test status
Simulation time	64579427 ps
CPU time	1.26 seconds
Started	Aug 25 05:52:30 AM UTC 24
Finished	Aug 25 05:52:32 AM UTC 24
Peak memory	213452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068554803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.4068554803
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/3.rv_dm_hart_unavail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.3085566033
Short name	T233
Test name
Test status
Simulation time	1639053792 ps
CPU time	11.86 seconds
Started	Aug 25 05:52:29 AM UTC 24
Finished	Aug 25 05:52:42 AM UTC 24
Peak memory	216192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085566033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.3085566033
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/3.rv_dm_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/3.rv_dm_sec_cm.2446102599
Short name	T95
Test name
Test status
Simulation time	828348531 ps
CPU time	4.42 seconds
Started	Aug 25 05:52:31 AM UTC 24
Finished	Aug 25 05:52:37 AM UTC 24
Peak memory	254620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446102599 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.2446102599
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/3.rv_dm_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.1548434940
Short name	T79
Test name
Test status
Simulation time	185817326 ps
CPU time	1.27 seconds
Started	Aug 25 05:52:31 AM UTC 24
Finished	Aug 25 05:52:34 AM UTC 24
Peak memory	225856 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548434940 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sparse_lc_gate_fsm.1548434940
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/3.rv_dm_sparse_lc_gate_fsm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.450318981
Short name	T8
Test name
Test status
Simulation time	2831306162 ps
CPU time	17.49 seconds
Started	Aug 25 05:52:31 AM UTC 24
Finished	Aug 25 05:52:50 AM UTC 24
Peak memory	226324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450318981 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.450318981
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/3.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.3989409814
Short name	T116
Test name
Test status
Simulation time	3970376010 ps
CPU time	126.12 seconds
Started	Aug 25 05:52:31 AM UTC 24
Finished	Aug 25 05:54:41 AM UTC 24
Peak memory	233184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3989409814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stres s_all_with_rand_reset.3989409814
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/30.rv_dm_alert_test.1646462546
Short name	T282
Test name
Test status
Simulation time	65334823 ps
CPU time	1.11 seconds
Started	Aug 25 05:54:06 AM UTC 24
Finished	Aug 25 05:54:08 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646462546 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.1646462546
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/30.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.3173764801
Short name	T291
Test name
Test status
Simulation time	1670495520 ps
CPU time	3.61 seconds
Started	Aug 25 05:54:06 AM UTC 24
Finished	Aug 25 05:54:11 AM UTC 24
Peak memory	226232 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173764801 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.3173764801
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/30.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/31.rv_dm_alert_test.1542191462
Short name	T288
Test name
Test status
Simulation time	71341406 ps
CPU time	1 seconds
Started	Aug 25 05:54:07 AM UTC 24
Finished	Aug 25 05:54:09 AM UTC 24
Peak memory	215812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542191462 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.1542191462
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/31.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/31.rv_dm_stress_all.2502246155
Short name	T320
Test name
Test status
Simulation time	3059589550 ps
CPU time	17.04 seconds
Started	Aug 25 05:54:06 AM UTC 24
Finished	Aug 25 05:54:24 AM UTC 24
Peak memory	216132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502246155 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.2502246155
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/31.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/32.rv_dm_alert_test.2003901632
Short name	T289
Test name
Test status
Simulation time	56338440 ps
CPU time	1.35 seconds
Started	Aug 25 05:54:07 AM UTC 24
Finished	Aug 25 05:54:10 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003901632 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.2003901632
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/32.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/32.rv_dm_stress_all.3721532036
Short name	T31
Test name
Test status
Simulation time	3805570669 ps
CPU time	13.13 seconds
Started	Aug 25 05:54:07 AM UTC 24
Finished	Aug 25 05:54:21 AM UTC 24
Peak memory	216068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721532036 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.3721532036
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/32.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/33.rv_dm_alert_test.1244259127
Short name	T292
Test name
Test status
Simulation time	101147392 ps
CPU time	1.19 seconds
Started	Aug 25 05:54:08 AM UTC 24
Finished	Aug 25 05:54:11 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244259127 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.1244259127
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/33.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.474223182
Short name	T55
Test name
Test status
Simulation time	5868290066 ps
CPU time	17.28 seconds
Started	Aug 25 05:54:07 AM UTC 24
Finished	Aug 25 05:54:26 AM UTC 24
Peak memory	216016 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474223182 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.474223182
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/33.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/34.rv_dm_alert_test.3896501786
Short name	T293
Test name
Test status
Simulation time	71816243 ps
CPU time	1.28 seconds
Started	Aug 25 05:54:08 AM UTC 24
Finished	Aug 25 05:54:11 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896501786 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.3896501786
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/34.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/34.rv_dm_stress_all.2725003220
Short name	T322
Test name
Test status
Simulation time	2744619589 ps
CPU time	18.16 seconds
Started	Aug 25 05:54:08 AM UTC 24
Finished	Aug 25 05:54:28 AM UTC 24
Peak memory	215992 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725003220 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.2725003220
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/34.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/35.rv_dm_alert_test.1144192770
Short name	T295
Test name
Test status
Simulation time	69083766 ps
CPU time	1.09 seconds
Started	Aug 25 05:54:10 AM UTC 24
Finished	Aug 25 05:54:12 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144192770 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.1144192770
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/35.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/35.rv_dm_stress_all.3786252823
Short name	T32
Test name
Test status
Simulation time	8057235851 ps
CPU time	27.56 seconds
Started	Aug 25 05:54:10 AM UTC 24
Finished	Aug 25 05:54:39 AM UTC 24
Peak memory	216080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786252823 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.3786252823
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/35.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/36.rv_dm_alert_test.1088958707
Short name	T220
Test name
Test status
Simulation time	32939558 ps
CPU time	1.11 seconds
Started	Aug 25 05:54:10 AM UTC 24
Finished	Aug 25 05:54:12 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088958707 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.1088958707
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/36.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/36.rv_dm_stress_all.2878187531
Short name	T308
Test name
Test status
Simulation time	5811837122 ps
CPU time	8.1 seconds
Started	Aug 25 05:54:10 AM UTC 24
Finished	Aug 25 05:54:19 AM UTC 24
Peak memory	216004 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878187531 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.2878187531
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/36.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/37.rv_dm_alert_test.2468766609
Short name	T298
Test name
Test status
Simulation time	111532890 ps
CPU time	1.16 seconds
Started	Aug 25 05:54:10 AM UTC 24
Finished	Aug 25 05:54:13 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468766609 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.2468766609
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/37.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/37.rv_dm_stress_all.4229348764
Short name	T328
Test name
Test status
Simulation time	6881205969 ps
CPU time	37.83 seconds
Started	Aug 25 05:54:10 AM UTC 24
Finished	Aug 25 05:54:50 AM UTC 24
Peak memory	216004 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229348764 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.4229348764
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/37.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/38.rv_dm_alert_test.1107193497
Short name	T296
Test name
Test status
Simulation time	55546546 ps
CPU time	1.04 seconds
Started	Aug 25 05:54:10 AM UTC 24
Finished	Aug 25 05:54:12 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107193497 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.1107193497
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/38.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/38.rv_dm_stress_all.198840676
Short name	T323
Test name
Test status
Simulation time	6304883720 ps
CPU time	18.19 seconds
Started	Aug 25 05:54:10 AM UTC 24
Finished	Aug 25 05:54:30 AM UTC 24
Peak memory	216084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198840676 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.198840676
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/38.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/39.rv_dm_alert_test.1612180272
Short name	T299
Test name
Test status
Simulation time	113424038 ps
CPU time	1.16 seconds
Started	Aug 25 05:54:12 AM UTC 24
Finished	Aug 25 05:54:14 AM UTC 24
Peak memory	215812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612180272 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.1612180272
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/39.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/39.rv_dm_stress_all.3501270677
Short name	T309
Test name
Test status
Simulation time	3364583640 ps
CPU time	7.28 seconds
Started	Aug 25 05:54:12 AM UTC 24
Finished	Aug 25 05:54:20 AM UTC 24
Peak memory	216132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501270677 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.3501270677
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/39.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/4.rv_dm_alert_test.2412100057
Short name	T168
Test name
Test status
Simulation time	58508608 ps
CPU time	1.06 seconds
Started	Aug 25 05:52:38 AM UTC 24
Finished	Aug 25 05:52:41 AM UTC 24
Peak memory	215936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412100057 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.2412100057
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/4.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/4.rv_dm_bad_sba_tl_access.2766117382
Short name	T176
Test name
Test status
Simulation time	4367804735 ps
CPU time	21.9 seconds
Started	Aug 25 05:52:35 AM UTC 24
Finished	Aug 25 05:52:58 AM UTC 24
Peak memory	226436 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766117382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.2766117382
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/4.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/4.rv_dm_buffered_enable.1838434154
Short name	T73
Test name
Test status
Simulation time	330505484 ps
CPU time	2.61 seconds
Started	Aug 25 05:52:36 AM UTC 24
Finished	Aug 25 05:52:40 AM UTC 24
Peak memory	258492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838434154 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_buffered_enable.1838434154
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/4.rv_dm_buffered_enable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.2781518497
Short name	T232
Test name
Test status
Simulation time	1786454224 ps
CPU time	4.43 seconds
Started	Aug 25 05:52:34 AM UTC 24
Finished	Aug 25 05:52:40 AM UTC 24
Peak memory	226560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781518497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_tl_access.2781518497
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.3537780208
Short name	T205
Test name
Test status
Simulation time	412248360 ps
CPU time	3.48 seconds
Started	Aug 25 05:52:36 AM UTC 24
Finished	Aug 25 05:52:41 AM UTC 24
Peak memory	215928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537780208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_halt_resume_whereto.3537780208
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/4.rv_dm_halt_resume_whereto/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.814214236
Short name	T231
Test name
Test status
Simulation time	83451289 ps
CPU time	1.51 seconds
Started	Aug 25 05:52:36 AM UTC 24
Finished	Aug 25 05:52:38 AM UTC 24
Peak memory	213456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814214236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.814214236
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/4.rv_dm_hart_unavail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/4.rv_dm_sba_tl_access.3629781111
Short name	T224
Test name
Test status
Simulation time	4137501156 ps
CPU time	23.25 seconds
Started	Aug 25 05:52:34 AM UTC 24
Finished	Aug 25 05:52:59 AM UTC 24
Peak memory	216332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629781111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.3629781111
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/4.rv_dm_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/4.rv_dm_sec_cm.127766017
Short name	T96
Test name
Test status
Simulation time	646527351 ps
CPU time	1.58 seconds
Started	Aug 25 05:52:37 AM UTC 24
Finished	Aug 25 05:52:40 AM UTC 24
Peak memory	253552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127766017 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.127766017
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/4.rv_dm_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.3909288218
Short name	T119
Test name
Test status
Simulation time	10505710696 ps
CPU time	122.85 seconds
Started	Aug 25 05:52:37 AM UTC 24
Finished	Aug 25 05:54:43 AM UTC 24
Peak memory	233196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3909288218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stres s_all_with_rand_reset.3909288218
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/40.rv_dm_alert_test.1836932814
Short name	T300
Test name
Test status
Simulation time	78436354 ps
CPU time	1.1 seconds
Started	Aug 25 05:54:12 AM UTC 24
Finished	Aug 25 05:54:14 AM UTC 24
Peak memory	215812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836932814 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.1836932814
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/40.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/40.rv_dm_stress_all.2929396798
Short name	T312
Test name
Test status
Simulation time	2893427434 ps
CPU time	7.96 seconds
Started	Aug 25 05:54:12 AM UTC 24
Finished	Aug 25 05:54:21 AM UTC 24
Peak memory	226388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929396798 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.2929396798
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/40.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/41.rv_dm_alert_test.4272927669
Short name	T302
Test name
Test status
Simulation time	120918189 ps
CPU time	1.65 seconds
Started	Aug 25 05:54:13 AM UTC 24
Finished	Aug 25 05:54:16 AM UTC 24
Peak memory	215812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272927669 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.4272927669
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/41.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/41.rv_dm_stress_all.651389316
Short name	T314
Test name
Test status
Simulation time	1367238281 ps
CPU time	9.11 seconds
Started	Aug 25 05:54:12 AM UTC 24
Finished	Aug 25 05:54:22 AM UTC 24
Peak memory	216072 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651389316 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.651389316
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/41.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/42.rv_dm_alert_test.3360074785
Short name	T301
Test name
Test status
Simulation time	127158049 ps
CPU time	1.22 seconds
Started	Aug 25 05:54:13 AM UTC 24
Finished	Aug 25 05:54:15 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360074785 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.3360074785
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/42.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/42.rv_dm_stress_all.1804185941
Short name	T324
Test name
Test status
Simulation time	3703791965 ps
CPU time	23.83 seconds
Started	Aug 25 05:54:13 AM UTC 24
Finished	Aug 25 05:54:38 AM UTC 24
Peak memory	216264 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804185941 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.1804185941
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/42.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/43.rv_dm_alert_test.2322180755
Short name	T304
Test name
Test status
Simulation time	53805062 ps
CPU time	1.18 seconds
Started	Aug 25 05:54:14 AM UTC 24
Finished	Aug 25 05:54:17 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322180755 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.2322180755
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/43.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/43.rv_dm_stress_all.1382780036
Short name	T310
Test name
Test status
Simulation time	1605171463 ps
CPU time	6.08 seconds
Started	Aug 25 05:54:13 AM UTC 24
Finished	Aug 25 05:54:20 AM UTC 24
Peak memory	226172 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382780036 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.1382780036
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/43.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/44.rv_dm_alert_test.3023995780
Short name	T303
Test name
Test status
Simulation time	53773291 ps
CPU time	1.05 seconds
Started	Aug 25 05:54:15 AM UTC 24
Finished	Aug 25 05:54:17 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023995780 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.3023995780
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/44.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.2977271247
Short name	T311
Test name
Test status
Simulation time	3664833278 ps
CPU time	5.07 seconds
Started	Aug 25 05:54:15 AM UTC 24
Finished	Aug 25 05:54:21 AM UTC 24
Peak memory	226244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977271247 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.2977271247
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/44.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/45.rv_dm_alert_test.1103541744
Short name	T305
Test name
Test status
Simulation time	123295188 ps
CPU time	1.2 seconds
Started	Aug 25 05:54:16 AM UTC 24
Finished	Aug 25 05:54:18 AM UTC 24
Peak memory	215864 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103541744 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.1103541744
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/45.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/45.rv_dm_stress_all.797645334
Short name	T294
Test name
Test status
Simulation time	1162595631 ps
CPU time	5.68 seconds
Started	Aug 25 05:54:15 AM UTC 24
Finished	Aug 25 05:54:22 AM UTC 24
Peak memory	215932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797645334 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.797645334
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/45.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/46.rv_dm_alert_test.2987375103
Short name	T306
Test name
Test status
Simulation time	154358756 ps
CPU time	1.28 seconds
Started	Aug 25 05:54:16 AM UTC 24
Finished	Aug 25 05:54:18 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987375103 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.2987375103
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/46.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/47.rv_dm_alert_test.3498204093
Short name	T307
Test name
Test status
Simulation time	78155644 ps
CPU time	1.14 seconds
Started	Aug 25 05:54:17 AM UTC 24
Finished	Aug 25 05:54:19 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498204093 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.3498204093
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/47.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/47.rv_dm_stress_all.1565758546
Short name	T190
Test name
Test status
Simulation time	4659715669 ps
CPU time	6.35 seconds
Started	Aug 25 05:54:17 AM UTC 24
Finished	Aug 25 05:54:25 AM UTC 24
Peak memory	216144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565758546 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.1565758546
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/47.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/48.rv_dm_alert_test.191887174
Short name	T313
Test name
Test status
Simulation time	37966656 ps
CPU time	1.21 seconds
Started	Aug 25 05:54:18 AM UTC 24
Finished	Aug 25 05:54:21 AM UTC 24
Peak memory	215936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191887174 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.191887174
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/48.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/48.rv_dm_stress_all.1217333347
Short name	T326
Test name
Test status
Simulation time	5006554766 ps
CPU time	24.02 seconds
Started	Aug 25 05:54:18 AM UTC 24
Finished	Aug 25 05:54:44 AM UTC 24
Peak memory	226444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217333347 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.1217333347
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/48.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/49.rv_dm_alert_test.1970484897
Short name	T315
Test name
Test status
Simulation time	66623438 ps
CPU time	1.09 seconds
Started	Aug 25 05:54:20 AM UTC 24
Finished	Aug 25 05:54:22 AM UTC 24
Peak memory	215724 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970484897 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.1970484897
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/49.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/49.rv_dm_stress_all.3388375623
Short name	T318
Test name
Test status
Simulation time	1459208856 ps
CPU time	2.68 seconds
Started	Aug 25 05:54:20 AM UTC 24
Finished	Aug 25 05:54:24 AM UTC 24
Peak memory	215644 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388375623 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.3388375623
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/49.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/5.rv_dm_alert_test.2877317726
Short name	T234
Test name
Test status
Simulation time	228954059 ps
CPU time	1 seconds
Started	Aug 25 05:52:43 AM UTC 24
Finished	Aug 25 05:52:45 AM UTC 24
Peak memory	215936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877317726 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.2877317726
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/5.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.414222958
Short name	T235
Test name
Test status
Simulation time	4635166986 ps
CPU time	14.01 seconds
Started	Aug 25 05:52:41 AM UTC 24
Finished	Aug 25 05:52:56 AM UTC 24
Peak memory	216332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414222958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.414222958
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/5.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/5.rv_dm_buffered_enable.31105517
Short name	T74
Test name
Test status
Simulation time	180251769 ps
CPU time	1.9 seconds
Started	Aug 25 05:52:42 AM UTC 24
Finished	Aug 25 05:52:45 AM UTC 24
Peak memory	251500 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31105517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv _dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_buffered_enable.31105517
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/5.rv_dm_buffered_enable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.3676768441
Short name	T122
Test name
Test status
Simulation time	4791230555 ps
CPU time	8.95 seconds
Started	Aug 25 05:52:39 AM UTC 24
Finished	Aug 25 05:52:50 AM UTC 24
Peak memory	216384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676768441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl_access.3676768441
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/5.rv_dm_halt_resume_whereto.533974657
Short name	T57
Test name
Test status
Simulation time	177229878 ps
CPU time	1.45 seconds
Started	Aug 25 05:52:42 AM UTC 24
Finished	Aug 25 05:52:44 AM UTC 24
Peak memory	213456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533974657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_halt_resume_whereto.533974657
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/5.rv_dm_halt_resume_whereto/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/5.rv_dm_sba_tl_access.1909844958
Short name	T120
Test name
Test status
Simulation time	1646976756 ps
CPU time	7.34 seconds
Started	Aug 25 05:52:38 AM UTC 24
Finished	Aug 25 05:52:48 AM UTC 24
Peak memory	216192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909844958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.1909844958
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/5.rv_dm_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.1159872206
Short name	T9
Test name
Test status
Simulation time	5424696317 ps
CPU time	12.47 seconds
Started	Aug 25 05:52:42 AM UTC 24
Finished	Aug 25 05:52:56 AM UTC 24
Peak memory	216140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159872206 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.1159872206
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/5.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/6.rv_dm_alert_test.2397529864
Short name	T124
Test name
Test status
Simulation time	209147563 ps
CPU time	1.31 seconds
Started	Aug 25 05:52:50 AM UTC 24
Finished	Aug 25 05:52:52 AM UTC 24
Peak memory	215936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397529864 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.2397529864
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/6.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/6.rv_dm_autoincr_sba_tl_access.340670760
Short name	T225
Test name
Test status
Simulation time	7425026349 ps
CPU time	7.62 seconds
Started	Aug 25 05:52:46 AM UTC 24
Finished	Aug 25 05:52:55 AM UTC 24
Peak memory	226492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340670760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.340670760
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/6.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/6.rv_dm_bad_sba_tl_access.724523130
Short name	T183
Test name
Test status
Simulation time	1729495074 ps
CPU time	11.35 seconds
Started	Aug 25 05:52:46 AM UTC 24
Finished	Aug 25 05:52:59 AM UTC 24
Peak memory	216212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724523130 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.724523130
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/6.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/6.rv_dm_buffered_enable.2015752437
Short name	T121
Test name
Test status
Simulation time	153862686 ps
CPU time	2.08 seconds
Started	Aug 25 05:52:46 AM UTC 24
Finished	Aug 25 05:52:50 AM UTC 24
Peak memory	258788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015752437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_buffered_enable.2015752437
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/6.rv_dm_buffered_enable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.266590833
Short name	T219
Test name
Test status
Simulation time	5338998254 ps
CPU time	16.56 seconds
Started	Aug 25 05:52:45 AM UTC 24
Finished	Aug 25 05:53:03 AM UTC 24
Peak memory	216188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266590833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_tl_access.266590833
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/6.rv_dm_halt_resume_whereto.3480627253
Short name	T72
Test name
Test status
Simulation time	266690166 ps
CPU time	2.89 seconds
Started	Aug 25 05:52:46 AM UTC 24
Finished	Aug 25 05:52:50 AM UTC 24
Peak memory	215800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480627253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_halt_resume_whereto.3480627253
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/6.rv_dm_halt_resume_whereto/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/6.rv_dm_sba_tl_access.3004747438
Short name	T123
Test name
Test status
Simulation time	1740413016 ps
CPU time	5.86 seconds
Started	Aug 25 05:52:45 AM UTC 24
Finished	Aug 25 05:52:52 AM UTC 24
Peak memory	216360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004747438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.3004747438
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/6.rv_dm_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all_with_rand_reset.1180289627
Short name	T111
Test name
Test status
Simulation time	3491543634 ps
CPU time	84.33 seconds
Started	Aug 25 05:52:49 AM UTC 24
Finished	Aug 25 05:54:15 AM UTC 24
Peak memory	233312 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1180289627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stres s_all_with_rand_reset.1180289627
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/7.rv_dm_alert_test.760239180
Short name	T236
Test name
Test status
Simulation time	112211356 ps
CPU time	1.53 seconds
Started	Aug 25 05:52:57 AM UTC 24
Finished	Aug 25 05:52:59 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760239180 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.760239180
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/7.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.2919295492
Short name	T331
Test name
Test status
Simulation time	21821579813 ps
CPU time	121.83 seconds
Started	Aug 25 05:52:51 AM UTC 24
Finished	Aug 25 05:54:56 AM UTC 24
Peak memory	228544 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919295492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.2919295492
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/7.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.3796579798
Short name	T216
Test name
Test status
Simulation time	7186915764 ps
CPU time	6.45 seconds
Started	Aug 25 05:52:51 AM UTC 24
Finished	Aug 25 05:52:59 AM UTC 24
Peak memory	226568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796579798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.3796579798
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/7.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/7.rv_dm_buffered_enable.2080259439
Short name	T206
Test name
Test status
Simulation time	92687900 ps
CPU time	1.55 seconds
Started	Aug 25 05:52:53 AM UTC 24
Finished	Aug 25 05:52:56 AM UTC 24
Peak memory	244524 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080259439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_buffered_enable.2080259439
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/7.rv_dm_buffered_enable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3738641382
Short name	T215
Test name
Test status
Simulation time	3156126415 ps
CPU time	20.23 seconds
Started	Aug 25 05:52:51 AM UTC 24
Finished	Aug 25 05:53:13 AM UTC 24
Peak memory	226688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738641382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_tl_access.3738641382
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.1275881607
Short name	T70
Test name
Test status
Simulation time	1343165737 ps
CPU time	8.22 seconds
Started	Aug 25 05:52:53 AM UTC 24
Finished	Aug 25 05:53:03 AM UTC 24
Peak memory	215928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275881607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_halt_resume_whereto.1275881607
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/7.rv_dm_halt_resume_whereto/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/7.rv_dm_sba_tl_access.1015312930
Short name	T249
Test name
Test status
Simulation time	13900956437 ps
CPU time	48.99 seconds
Started	Aug 25 05:52:51 AM UTC 24
Finished	Aug 25 05:53:42 AM UTC 24
Peak memory	226468 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015312930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.1015312930
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/7.rv_dm_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all.294687057
Short name	T189
Test name
Test status
Simulation time	4293892547 ps
CPU time	22.04 seconds
Started	Aug 25 05:52:56 AM UTC 24
Finished	Aug 25 05:53:20 AM UTC 24
Peak memory	226452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294687057 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.294687057
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/7.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/8.rv_dm_alert_test.2513983790
Short name	T209
Test name
Test status
Simulation time	254685625 ps
CPU time	1.12 seconds
Started	Aug 25 05:53:00 AM UTC 24
Finished	Aug 25 05:53:02 AM UTC 24
Peak memory	215936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513983790 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.2513983790
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/8.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.1462441449
Short name	T192
Test name
Test status
Simulation time	10272477235 ps
CPU time	53.3 seconds
Started	Aug 25 05:52:59 AM UTC 24
Finished	Aug 25 05:53:54 AM UTC 24
Peak memory	226496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462441449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.1462441449
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/8.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/8.rv_dm_bad_sba_tl_access.467822494
Short name	T237
Test name
Test status
Simulation time	2756571937 ps
CPU time	4.99 seconds
Started	Aug 25 05:52:59 AM UTC 24
Finished	Aug 25 05:53:05 AM UTC 24
Peak memory	226636 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467822494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.467822494
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/8.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/8.rv_dm_buffered_enable.3793710998
Short name	T218
Test name
Test status
Simulation time	152601200 ps
CPU time	1.56 seconds
Started	Aug 25 05:53:00 AM UTC 24
Finished	Aug 25 05:53:03 AM UTC 24
Peak memory	258164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793710998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_buffered_enable.3793710998
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/8.rv_dm_buffered_enable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.3449291246
Short name	T240
Test name
Test status
Simulation time	6844713753 ps
CPU time	14.89 seconds
Started	Aug 25 05:52:58 AM UTC 24
Finished	Aug 25 05:53:14 AM UTC 24
Peak memory	226428 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449291246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl_access.3449291246
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/8.rv_dm_sba_tl_access.1779802770
Short name	T208
Test name
Test status
Simulation time	12827619683 ps
CPU time	38.14 seconds
Started	Aug 25 05:52:57 AM UTC 24
Finished	Aug 25 05:53:36 AM UTC 24
Peak memory	226624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779802770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.1779802770
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/8.rv_dm_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.2489702838
Short name	T93
Test name
Test status
Simulation time	1697507918 ps
CPU time	7.67 seconds
Started	Aug 25 05:53:00 AM UTC 24
Finished	Aug 25 05:53:09 AM UTC 24
Peak memory	216076 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489702838 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.2489702838
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/8.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.788416721
Short name	T71
Test name
Test status
Simulation time	5178201913 ps
CPU time	53.65 seconds
Started	Aug 25 05:53:00 AM UTC 24
Finished	Aug 25 05:53:56 AM UTC 24
Peak memory	230616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=788416721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress _all_with_rand_reset.788416721
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.684361435
Short name	T217
Test name
Test status
Simulation time	62554760 ps
CPU time	1.08 seconds
Started	Aug 25 05:53:09 AM UTC 24
Finished	Aug 25 05:53:11 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684361435 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.684361435
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/9.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/9.rv_dm_autoincr_sba_tl_access.2361897019
Short name	T246
Test name
Test status
Simulation time	25349877870 ps
CPU time	29.26 seconds
Started	Aug 25 05:53:04 AM UTC 24
Finished	Aug 25 05:53:34 AM UTC 24
Peak memory	226560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361897019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.2361897019
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/9.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.62204521
Short name	T180
Test name
Test status
Simulation time	3179992372 ps
CPU time	17.75 seconds
Started	Aug 25 05:53:03 AM UTC 24
Finished	Aug 25 05:53:22 AM UTC 24
Peak memory	226452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62204521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv _dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.62204521
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/9.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/9.rv_dm_buffered_enable.1665631548
Short name	T204
Test name
Test status
Simulation time	731006597 ps
CPU time	2.2 seconds
Started	Aug 25 05:53:06 AM UTC 24
Finished	Aug 25 05:53:09 AM UTC 24
Peak memory	258740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665631548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_buffered_enable.1665631548
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/9.rv_dm_buffered_enable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.3863063425
Short name	T290
Test name
Test status
Simulation time	11054309784 ps
CPU time	64.42 seconds
Started	Aug 25 05:53:03 AM UTC 24
Finished	Aug 25 05:54:10 AM UTC 24
Peak memory	226492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863063425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_tl_access.3863063425
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.732903432
Short name	T241
Test name
Test status
Simulation time	2054255916 ps
CPU time	14.03 seconds
Started	Aug 25 05:53:03 AM UTC 24
Finished	Aug 25 05:53:19 AM UTC 24
Peak memory	216248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732903432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.732903432
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/9.rv_dm_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.975639898
Short name	T207
Test name
Test status
Simulation time	1989991710 ps
CPU time	8.31 seconds
Started	Aug 25 05:53:06 AM UTC 24
Finished	Aug 25 05:53:15 AM UTC 24
Peak memory	226192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975639898 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.975639898
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/9.rv_dm_stress_all/latest