Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.96 96.32 89.67 92.10 94.67 90.27 98.53 61.18


Total tests in report: 483
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
62.29 62.29 87.10 87.10 62.94 62.94 61.09 61.09 56.00 56.00 69.62 69.62 93.48 93.48 5.76 5.76 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all.1338895452
72.30 10.02 88.46 1.36 71.57 8.63 63.95 2.86 61.33 5.33 75.26 5.63 94.53 1.05 51.03 45.27 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.3953275785
79.13 6.82 92.14 3.68 77.23 5.66 82.94 18.99 72.00 10.67 81.74 6.48 96.00 1.47 51.85 0.82 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.1245947270
80.57 1.44 93.90 1.76 79.63 2.40 83.03 0.08 74.67 2.67 84.64 2.90 96.00 0.00 52.13 0.27 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.3455560788
81.86 1.29 93.90 0.00 79.92 0.28 83.40 0.38 82.67 8.00 84.98 0.34 96.00 0.00 52.13 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1742434170
82.81 0.96 94.01 0.10 81.47 1.56 84.16 0.76 82.67 0.00 85.49 0.51 96.21 0.21 55.69 3.57 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.570373970
83.45 0.64 94.06 0.05 81.47 0.00 85.59 1.43 85.33 2.67 85.67 0.17 96.21 0.00 55.83 0.14 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.1109187789
84.07 0.62 94.76 0.71 82.60 1.13 85.71 0.13 86.67 1.33 86.69 1.02 96.21 0.00 55.83 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.3137181366
84.59 0.53 94.76 0.00 82.60 0.00 88.57 2.86 86.67 0.00 86.69 0.00 96.21 0.00 56.65 0.82 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/18.rv_dm_autoincr_sba_tl_access.2649126593
85.11 0.51 95.37 0.60 83.31 0.71 88.70 0.13 88.00 1.33 87.37 0.68 96.21 0.00 56.79 0.14 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.3371745816
85.54 0.44 95.37 0.00 83.45 0.14 88.95 0.25 90.67 2.67 87.37 0.00 96.21 0.00 56.79 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.2027476464
85.88 0.33 95.37 0.00 84.16 0.71 89.79 0.84 90.67 0.00 87.37 0.00 96.32 0.11 57.48 0.69 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.2786647215
86.20 0.32 95.37 0.00 86.42 2.26 89.79 0.00 90.67 0.00 87.37 0.00 96.32 0.00 57.48 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.3215590359
86.48 0.28 95.42 0.05 86.85 0.42 89.79 0.00 92.00 1.33 87.54 0.17 96.32 0.00 57.48 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.1937796344
86.76 0.28 95.57 0.15 87.41 0.57 90.38 0.59 92.00 0.00 88.05 0.51 96.32 0.00 57.61 0.14 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.3487838404
87.01 0.24 95.62 0.05 87.55 0.14 90.71 0.34 92.00 0.00 88.40 0.34 96.32 0.00 58.44 0.82 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.739667682
87.20 0.20 95.62 0.00 87.55 0.00 90.71 0.00 92.00 0.00 88.40 0.00 97.69 1.37 58.44 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_aliasing.4171618479
87.39 0.19 95.62 0.00 87.55 0.00 90.71 0.00 93.33 1.33 88.40 0.00 97.69 0.00 58.44 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.733609407
87.58 0.19 95.62 0.00 87.55 0.00 90.71 0.00 94.67 1.33 88.40 0.00 97.69 0.00 58.44 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.3283597565
87.72 0.14 95.77 0.15 88.26 0.71 90.84 0.13 94.67 0.00 88.40 0.00 97.69 0.00 58.44 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.901605082
87.86 0.14 95.92 0.15 88.54 0.28 90.84 0.00 94.67 0.00 88.91 0.51 97.69 0.00 58.44 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.1846144463
87.99 0.13 95.92 0.00 88.68 0.14 90.92 0.08 94.67 0.00 88.91 0.00 97.69 0.00 59.12 0.69 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/4.rv_dm_autoincr_sba_tl_access.3413842179
88.12 0.13 96.12 0.20 88.97 0.28 91.01 0.08 94.67 0.00 89.25 0.34 97.69 0.00 59.12 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.398662565
88.22 0.10 96.12 0.00 88.97 0.00 91.01 0.00 94.67 0.00 89.25 0.00 97.69 0.00 59.81 0.69 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1122269995
88.31 0.09 96.17 0.05 89.11 0.14 91.13 0.13 94.67 0.00 89.59 0.34 97.69 0.00 59.81 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.2261878636
88.40 0.09 96.17 0.00 89.11 0.00 91.47 0.34 94.67 0.00 89.59 0.00 97.69 0.00 60.08 0.27 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/16.rv_dm_autoincr_sba_tl_access.1732223248
88.46 0.07 96.22 0.05 89.11 0.00 91.72 0.25 94.67 0.00 89.76 0.17 97.69 0.00 60.08 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.3955140245
88.52 0.06 96.22 0.00 89.11 0.00 91.72 0.00 94.67 0.00 89.76 0.00 98.11 0.42 60.08 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1791721876
88.58 0.06 96.22 0.00 89.11 0.00 91.72 0.00 94.67 0.00 89.76 0.00 98.11 0.00 60.49 0.41 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2263821178
88.63 0.05 96.22 0.00 89.11 0.00 91.81 0.08 94.67 0.00 89.76 0.00 98.11 0.00 60.77 0.27 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all.3954447197
88.68 0.04 96.22 0.00 89.25 0.14 91.81 0.00 94.67 0.00 89.93 0.17 98.11 0.00 60.77 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.3139046046
88.72 0.04 96.22 0.00 89.53 0.28 91.81 0.00 94.67 0.00 89.93 0.00 98.11 0.00 60.77 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/14.rv_dm_stress_all.21394376
88.76 0.04 96.22 0.00 89.53 0.00 91.93 0.13 94.67 0.00 89.93 0.00 98.11 0.00 60.91 0.14 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.1474232467
88.79 0.04 96.27 0.05 89.53 0.00 91.97 0.04 94.67 0.00 90.10 0.17 98.11 0.00 60.91 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.3141444641
88.83 0.03 96.32 0.05 89.53 0.00 91.97 0.00 94.67 0.00 90.27 0.17 98.11 0.00 60.91 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1508120499
88.86 0.03 96.32 0.00 89.53 0.00 91.97 0.00 94.67 0.00 90.27 0.00 98.32 0.21 60.91 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1882435331
88.88 0.02 96.32 0.00 89.67 0.14 91.97 0.00 94.67 0.00 90.27 0.00 98.32 0.00 60.91 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.1807683129
88.90 0.02 96.32 0.00 89.67 0.00 91.97 0.00 94.67 0.00 90.27 0.00 98.32 0.00 61.04 0.14 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2123660583
88.92 0.02 96.32 0.00 89.67 0.00 91.97 0.00 94.67 0.00 90.27 0.00 98.32 0.00 61.18 0.14 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/12.rv_dm_bad_sba_tl_access.4040225370
88.93 0.02 96.32 0.00 89.67 0.00 92.10 0.13 94.67 0.00 90.27 0.00 98.32 0.00 61.18 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.1587364087
88.95 0.02 96.32 0.00 89.67 0.00 92.10 0.00 94.67 0.00 90.27 0.00 98.42 0.11 61.18 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.3751831536
88.96 0.02 96.32 0.00 89.67 0.00 92.10 0.00 94.67 0.00 90.27 0.00 98.53 0.11 61.18 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.1316188385

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2881131622
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1392791291
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.655012639
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3339391174
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.1591281334
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1733974310
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2247995802
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.414888350
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3286933911
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2795218621
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1833230647
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.424480425
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.3137153737
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.272606505
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.990264025
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3238655014
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2664399032
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3485999912
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.4156193765
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1149690047
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3615201577
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1041977036
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2643084921
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.4088255426
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1515615658
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1462895337
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1872702779
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1179909639
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.330760962
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2668399898
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.1782573961
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3814732626
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.3227656526
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.1579322104
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3746850745
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1917569766
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2877873439
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.2393223453
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1232156037
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3101280497
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_rw.2538646444
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.4257151288
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3866166984
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2160020648
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3592313016
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_errors.3905211267
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3479050267
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.95742743
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_rw.4206887603
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.366181431
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.4057577334
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.4139753263
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2054376394
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_errors.123063740
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2098240839
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3041754803
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_rw.1805670702
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.3792919993
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1146073213
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.181187965
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1972985674
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_errors.3533451961
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_intg_err.862556475
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.494945868
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_rw.3420941774
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3263364840
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3273975209
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1688285860
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1108201446
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_errors.3838790815
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1720701166
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3848672587
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_rw.1809388314
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.270914906
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1215218012
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2020566852
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2059739316
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_errors.4206387239
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1313381884
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3549526717
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_rw.3687178305
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.3094893678
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3436415314
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3790182536
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1114421559
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_errors.1906663832
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.4149162248
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3887266341
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_rw.2120528096
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.2947155764
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.4189650465
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.76054568
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2788098464
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_errors.1774934986
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.709809160
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1179131881
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_rw.1599982557
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.15234641
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1207893576
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.903720287
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3620070887
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_errors.923982473
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3748198176
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.454189699
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_rw.3934218130
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.3567330221
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.755082630
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2220894656
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.4237232100
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_errors.2171597391
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2288041971
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3174630771
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1887309615
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.392737094
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.2724008536
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_rw.3691634189
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.807428385
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.4024891990
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2131240853
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1146453803
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2703316603
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1853776848
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1942062938
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.4255392322
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_partial_access.851674132
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_walk.333748836
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3678943696
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_errors.1896859560
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.243114783
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2928171052
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.874843599
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.125651181
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_rw.2282027581
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1576923387
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1907223703
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3452612638
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1939744377
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1488967488
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1380641306
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3815656393
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3768814651
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_partial_access.8721548
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_walk.2217083831
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3922831294
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3593706507
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_errors.376622667
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1296166021
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.776568118
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2377461035
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3205598261
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_rw.1894824442
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.123424127
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.4085805032
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2196180247
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.370088606
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3072851456
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.766584743
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1212554405
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.893124409
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_partial_access.935241690
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_walk.2949457607
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1175838163
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.1788947275
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_errors.1727838489
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1750716366
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3957396517
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_rw.1336546686
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.4144862304
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3860374392
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3580042097
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1771759454
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.466822328
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_errors.600545986
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1388779676
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2131659232
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_rw.3943306757
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.923910140
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2841899263
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.866656072
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3356046658
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.2300478260
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_errors.4080071511
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_intg_err.818574191
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2630441124
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_rw.1183477317
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1929753466
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3778768392
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.25807843
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2990066836
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.316437194
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_errors.3589283763
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2629792737
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_rw.682463120
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1247883478
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1684670898
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1029659505
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2274193969
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3985055286
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_errors.3654412716
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3867368845
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2659196489
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_rw.711137671
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3351033368
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3122879918
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2531484961
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2754108806
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3786985834
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_errors.2456679785
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_intg_err.648342981
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.1684528211
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.3135057668
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_busy.691461472
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.3583195312
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_dataaddr_rw_access.3932371683
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_debug_disabled.3128039016
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.3798354159
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_hart_unavail.3867215533
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_hartsel_warl.4244407113
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.298154295
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1950810622
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2021401916
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_idle_hint.879504273
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_halted.1372654216
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_resuming.1270084714
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.3908087764
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.7573969
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_tl_access.3115191406
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_smoke.1174834216
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.3765931797
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_abstractcmd_status.3102706378
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_alert_test.1703957913
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_autoincr_sba_tl_access.1075293599
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_bad_sba_tl_access.422491020
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_buffered_enable.2492882469
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_busy.1860176350
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.1237986508
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.332547998
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_not_supported.3021611907
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_dataaddr_rw_access.1246895419
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_debug_disabled.487683590
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.1803165335
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.3892491725
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_halt_resume_whereto.771364058
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_hart_unavail.270143127
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.2710868195
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1481952448
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_hard_reset.2952868103
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1863927789
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_halted.1573154900
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_resuming.2545309947
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_ndmreset_req.558175025
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_progbuf_read_write_execute.585938009
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_rom_read_access.1722097468
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_debug_disabled.3665680887
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_tl_access.4102907054
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_sec_cm.1183332535
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_smoke.2919145001
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.660188932
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/10.rv_dm_alert_test.2742653349
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/10.rv_dm_autoincr_sba_tl_access.3964751162
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/10.rv_dm_bad_sba_tl_access.792013656
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.2553565572
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/10.rv_dm_sba_tl_access.94678485
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/10.rv_dm_stress_all.521881789
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/11.rv_dm_alert_test.4216246745
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/11.rv_dm_autoincr_sba_tl_access.1302312157
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/11.rv_dm_bad_sba_tl_access.3965871768
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.1891168395
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/11.rv_dm_sba_tl_access.3210368232
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/11.rv_dm_stress_all.1684841083
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/12.rv_dm_alert_test.3103053609
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/12.rv_dm_autoincr_sba_tl_access.2202711582
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.79366951
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/12.rv_dm_sba_tl_access.2571232624
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/12.rv_dm_stress_all.3497690351
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/13.rv_dm_alert_test.3049701537
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/13.rv_dm_autoincr_sba_tl_access.3912565250
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/13.rv_dm_bad_sba_tl_access.2062777323
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.1899822649
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/13.rv_dm_sba_tl_access.4252201071
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/13.rv_dm_stress_all.2455483534
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/14.rv_dm_alert_test.3993142523
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/14.rv_dm_autoincr_sba_tl_access.508954853
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/14.rv_dm_bad_sba_tl_access.303868215
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.1082221090
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/14.rv_dm_sba_tl_access.3460040644
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/15.rv_dm_alert_test.3702044374
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/15.rv_dm_autoincr_sba_tl_access.996097941
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/15.rv_dm_bad_sba_tl_access.4096522614
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.290414327
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/15.rv_dm_sba_tl_access.4059915086
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/15.rv_dm_stress_all.256166838
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/16.rv_dm_alert_test.1060329160
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/16.rv_dm_bad_sba_tl_access.2086197950
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.3730283362
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/16.rv_dm_sba_tl_access.544151014
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/16.rv_dm_stress_all.1697719253
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/17.rv_dm_alert_test.3909269211
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/17.rv_dm_autoincr_sba_tl_access.2564110744
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/17.rv_dm_bad_sba_tl_access.3099893280
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.3594754139
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/17.rv_dm_sba_tl_access.2465472590
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/17.rv_dm_stress_all.3180041349
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/18.rv_dm_alert_test.3383544870
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/18.rv_dm_bad_sba_tl_access.852936811
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.3427510828
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/18.rv_dm_sba_tl_access.2687421911
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/18.rv_dm_stress_all.680272682
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/19.rv_dm_alert_test.1386444242
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.3358295993
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/19.rv_dm_bad_sba_tl_access.2518317583
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.4056467865
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/19.rv_dm_sba_tl_access.4205163516
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.625657124
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.1243338693
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.292724812
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.2562440543
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.3282173577
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.75914581
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.3480778235
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.1613284151
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.724582456
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/2.rv_dm_sparse_lc_gate_fsm.804486392
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.3031783291
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/20.rv_dm_alert_test.2021323830
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.2620931286
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/21.rv_dm_alert_test.758254015
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/21.rv_dm_stress_all.3559186201
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/22.rv_dm_alert_test.3075774079
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.3164872485
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/23.rv_dm_alert_test.2928291216
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/23.rv_dm_stress_all.3621275973
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/24.rv_dm_alert_test.2740817420
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/24.rv_dm_stress_all.1501519044
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/25.rv_dm_alert_test.3052699292
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.1594945964
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/26.rv_dm_alert_test.2110556706
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/26.rv_dm_stress_all.3693519112
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/27.rv_dm_alert_test.3200644520
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.2813451756
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/28.rv_dm_alert_test.497626633
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/28.rv_dm_stress_all.2688972056
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/29.rv_dm_alert_test.1159269608
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/29.rv_dm_stress_all.163966347
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.4066508867
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.49376000
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.1196169995
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1814408744
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.1174625593
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/3.rv_dm_hart_unavail.4068554803
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.3085566033
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/3.rv_dm_sec_cm.2446102599
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.1548434940
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.450318981
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.3989409814
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/30.rv_dm_alert_test.1646462546
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.3173764801
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/31.rv_dm_alert_test.1542191462
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/31.rv_dm_stress_all.2502246155
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/32.rv_dm_alert_test.2003901632
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/32.rv_dm_stress_all.3721532036
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/33.rv_dm_alert_test.1244259127
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.474223182
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/34.rv_dm_alert_test.3896501786
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/34.rv_dm_stress_all.2725003220
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/35.rv_dm_alert_test.1144192770
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/35.rv_dm_stress_all.3786252823
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/36.rv_dm_alert_test.1088958707
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/36.rv_dm_stress_all.2878187531
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/37.rv_dm_alert_test.2468766609
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/37.rv_dm_stress_all.4229348764
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/38.rv_dm_alert_test.1107193497
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/38.rv_dm_stress_all.198840676
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/39.rv_dm_alert_test.1612180272
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/39.rv_dm_stress_all.3501270677
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/4.rv_dm_alert_test.2412100057
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/4.rv_dm_bad_sba_tl_access.2766117382
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/4.rv_dm_buffered_enable.1838434154
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.2781518497
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.3537780208
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.814214236
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/4.rv_dm_sba_tl_access.3629781111
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/4.rv_dm_sec_cm.127766017
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.3909288218
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/40.rv_dm_alert_test.1836932814
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/40.rv_dm_stress_all.2929396798
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/41.rv_dm_alert_test.4272927669
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/41.rv_dm_stress_all.651389316
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/42.rv_dm_alert_test.3360074785
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/42.rv_dm_stress_all.1804185941
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/43.rv_dm_alert_test.2322180755
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/43.rv_dm_stress_all.1382780036
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/44.rv_dm_alert_test.3023995780
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.2977271247
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/45.rv_dm_alert_test.1103541744
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/45.rv_dm_stress_all.797645334
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/46.rv_dm_alert_test.2987375103
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/47.rv_dm_alert_test.3498204093
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/47.rv_dm_stress_all.1565758546
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/48.rv_dm_alert_test.191887174
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/48.rv_dm_stress_all.1217333347
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/49.rv_dm_alert_test.1970484897
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/49.rv_dm_stress_all.3388375623
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/5.rv_dm_alert_test.2877317726
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.414222958
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/5.rv_dm_buffered_enable.31105517
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.3676768441
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/5.rv_dm_halt_resume_whereto.533974657
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/5.rv_dm_sba_tl_access.1909844958
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.1159872206
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/6.rv_dm_alert_test.2397529864
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/6.rv_dm_autoincr_sba_tl_access.340670760
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/6.rv_dm_bad_sba_tl_access.724523130
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/6.rv_dm_buffered_enable.2015752437
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.266590833
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/6.rv_dm_halt_resume_whereto.3480627253
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/6.rv_dm_sba_tl_access.3004747438
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all_with_rand_reset.1180289627
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/7.rv_dm_alert_test.760239180
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.2919295492
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.3796579798
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/7.rv_dm_buffered_enable.2080259439
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3738641382
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.1275881607
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/7.rv_dm_sba_tl_access.1015312930
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all.294687057
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/8.rv_dm_alert_test.2513983790
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.1462441449
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/8.rv_dm_bad_sba_tl_access.467822494
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/8.rv_dm_buffered_enable.3793710998
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.3449291246
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/8.rv_dm_sba_tl_access.1779802770
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.2489702838
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.788416721
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.684361435
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/9.rv_dm_autoincr_sba_tl_access.2361897019
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.62204521
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/9.rv_dm_buffered_enable.1665631548
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.3863063425
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.732903432
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.975639898



Total test records in report: 483
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all.1338895452 Aug 25 05:52:27 AM UTC 24 Aug 25 05:52:32 AM UTC 24 2632471771 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.3583195312 Aug 25 05:52:06 AM UTC 24 Aug 25 05:52:09 AM UTC 24 144857315 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_busy.691461472 Aug 25 05:52:06 AM UTC 24 Aug 25 05:52:10 AM UTC 24 492472151 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_hart_unavail.3867215533 Aug 25 05:52:07 AM UTC 24 Aug 25 05:52:10 AM UTC 24 92852428 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.1846144463 Aug 25 05:52:07 AM UTC 24 Aug 25 05:52:10 AM UTC 24 170662442 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_dataaddr_rw_access.3932371683 Aug 25 05:52:08 AM UTC 24 Aug 25 05:52:11 AM UTC 24 95856991 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_resuming.1270084714 Aug 25 05:52:07 AM UTC 24 Aug 25 05:52:11 AM UTC 24 706191222 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_halted.1372654216 Aug 25 05:52:07 AM UTC 24 Aug 25 05:52:11 AM UTC 24 372992026 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.1807683129 Aug 25 05:52:07 AM UTC 24 Aug 25 05:52:12 AM UTC 24 333833127 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.3487838404 Aug 25 05:52:10 AM UTC 24 Aug 25 05:52:12 AM UTC 24 290799008 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_idle_hint.879504273 Aug 25 05:52:11 AM UTC 24 Aug 25 05:52:13 AM UTC 24 169965651 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_smoke.1174834216 Aug 25 05:52:03 AM UTC 24 Aug 25 05:52:13 AM UTC 24 1331219592 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1950810622 Aug 25 05:52:11 AM UTC 24 Aug 25 05:52:13 AM UTC 24 296716256 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.3798354159 Aug 25 05:52:06 AM UTC 24 Aug 25 05:52:13 AM UTC 24 3085291548 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.3908087764 Aug 25 05:52:11 AM UTC 24 Aug 25 05:52:14 AM UTC 24 290394970 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.3141444641 Aug 25 05:52:12 AM UTC 24 Aug 25 05:52:14 AM UTC 24 152064656 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.3139046046 Aug 25 05:52:10 AM UTC 24 Aug 25 05:52:15 AM UTC 24 819431669 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_debug_disabled.3128039016 Aug 25 05:52:13 AM UTC 24 Aug 25 05:52:15 AM UTC 24 279058933 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_tl_access.3115191406 Aug 25 05:52:04 AM UTC 24 Aug 25 05:52:16 AM UTC 24 3536393448 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.2261878636 Aug 25 05:52:13 AM UTC 24 Aug 25 05:52:16 AM UTC 24 147213067 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.298154295 Aug 25 05:52:12 AM UTC 24 Aug 25 05:52:16 AM UTC 24 747491965 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2021401916 Aug 25 05:52:12 AM UTC 24 Aug 25 05:52:16 AM UTC 24 691990977 ps
T91 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.3215590359 Aug 25 05:52:14 AM UTC 24 Aug 25 05:52:17 AM UTC 24 12920736 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.1245947270 Aug 25 05:52:06 AM UTC 24 Aug 25 05:52:17 AM UTC 24 3118469359 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.3135057668 Aug 25 05:52:14 AM UTC 24 Aug 25 05:52:17 AM UTC 24 354179479 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_hartsel_warl.4244407113 Aug 25 05:52:14 AM UTC 24 Aug 25 05:52:17 AM UTC 24 148528011 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.3751831536 Aug 25 05:52:14 AM UTC 24 Aug 25 05:52:17 AM UTC 24 335913771 ps
T80 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.1937796344 Aug 25 05:52:14 AM UTC 24 Aug 25 05:52:17 AM UTC 24 260727729 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.7573969 Aug 25 05:52:13 AM UTC 24 Aug 25 05:52:19 AM UTC 24 665295058 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.901605082 Aug 25 05:52:17 AM UTC 24 Aug 25 05:52:19 AM UTC 24 158644173 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_halted.1573154900 Aug 25 05:52:18 AM UTC 24 Aug 25 05:52:21 AM UTC 24 89595559 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_hart_unavail.270143127 Aug 25 05:52:18 AM UTC 24 Aug 25 05:52:21 AM UTC 24 384366660 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_resuming.2545309947 Aug 25 05:52:18 AM UTC 24 Aug 25 05:52:21 AM UTC 24 178354936 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_busy.1860176350 Aug 25 05:52:17 AM UTC 24 Aug 25 05:52:21 AM UTC 24 1249273372 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_dataaddr_rw_access.1246895419 Aug 25 05:52:19 AM UTC 24 Aug 25 05:52:21 AM UTC 24 56636233 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.332547998 Aug 25 05:52:18 AM UTC 24 Aug 25 05:52:21 AM UTC 24 322029696 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_smoke.2919145001 Aug 25 05:52:17 AM UTC 24 Aug 25 05:52:22 AM UTC 24 1058277267 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.1237986508 Aug 25 05:52:18 AM UTC 24 Aug 25 05:52:22 AM UTC 24 290542942 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_ndmreset_req.558175025 Aug 25 05:52:20 AM UTC 24 Aug 25 05:52:22 AM UTC 24 439483813 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_halt_resume_whereto.771364058 Aug 25 05:52:19 AM UTC 24 Aug 25 05:52:22 AM UTC 24 1014749641 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_not_supported.3021611907 Aug 25 05:52:18 AM UTC 24 Aug 25 05:52:22 AM UTC 24 310893773 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.2786647215 Aug 25 05:52:16 AM UTC 24 Aug 25 05:52:22 AM UTC 24 1272226726 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_bad_sba_tl_access.422491020 Aug 25 05:52:17 AM UTC 24 Aug 25 05:52:23 AM UTC 24 4045751250 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_tl_access.4102907054 Aug 25 05:52:17 AM UTC 24 Aug 25 05:52:24 AM UTC 24 2107282630 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_debug_disabled.3665680887 Aug 25 05:52:20 AM UTC 24 Aug 25 05:52:24 AM UTC 24 794471059 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_abstractcmd_status.3102706378 Aug 25 05:52:22 AM UTC 24 Aug 25 05:52:24 AM UTC 24 96174573 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_rom_read_access.1722097468 Aug 25 05:52:22 AM UTC 24 Aug 25 05:52:25 AM UTC 24 42471260 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.1684528211 Aug 25 05:52:06 AM UTC 24 Aug 25 05:52:25 AM UTC 24 8994915782 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_debug_disabled.487683590 Aug 25 05:52:23 AM UTC 24 Aug 25 05:52:26 AM UTC 24 44025781 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.1109187789 Aug 25 05:52:03 AM UTC 24 Aug 25 05:52:26 AM UTC 24 7568604952 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.1316188385 Aug 25 05:52:23 AM UTC 24 Aug 25 05:52:26 AM UTC 24 52118435 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1863927789 Aug 25 05:52:22 AM UTC 24 Aug 25 05:52:26 AM UTC 24 302395559 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_buffered_enable.2492882469 Aug 25 05:52:23 AM UTC 24 Aug 25 05:52:26 AM UTC 24 133867093 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.2710868195 Aug 25 05:52:22 AM UTC 24 Aug 25 05:52:26 AM UTC 24 656698393 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.3892491725 Aug 25 05:52:23 AM UTC 24 Aug 25 05:52:26 AM UTC 24 594204331 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_progbuf_read_write_execute.585938009 Aug 25 05:52:23 AM UTC 24 Aug 25 05:52:27 AM UTC 24 1006748936 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1481952448 Aug 25 05:52:22 AM UTC 24 Aug 25 05:52:27 AM UTC 24 795395441 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_sec_cm.1183332535 Aug 25 05:52:25 AM UTC 24 Aug 25 05:52:28 AM UTC 24 481062388 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_alert_test.1703957913 Aug 25 05:52:26 AM UTC 24 Aug 25 05:52:28 AM UTC 24 61798545 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_hard_reset.2952868103 Aug 25 05:52:22 AM UTC 24 Aug 25 05:52:29 AM UTC 24 793425743 ps
T228 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.3480778235 Aug 25 05:52:27 AM UTC 24 Aug 25 05:52:29 AM UTC 24 65694147 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_autoincr_sba_tl_access.1075293599 Aug 25 05:52:17 AM UTC 24 Aug 25 05:52:29 AM UTC 24 5825651184 ps
T117 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.3282173577 Aug 25 05:52:26 AM UTC 24 Aug 25 05:52:29 AM UTC 24 2127992538 ps
T77 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/2.rv_dm_sparse_lc_gate_fsm.804486392 Aug 25 05:52:27 AM UTC 24 Aug 25 05:52:30 AM UTC 24 87086657 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.1243338693 Aug 25 05:52:27 AM UTC 24 Aug 25 05:52:30 AM UTC 24 80689804 ps
T78 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.3371745816 Aug 25 05:52:27 AM UTC 24 Aug 25 05:52:30 AM UTC 24 147917412 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.1613284151 Aug 25 05:52:26 AM UTC 24 Aug 25 05:52:30 AM UTC 24 1785768428 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/3.rv_dm_hart_unavail.4068554803 Aug 25 05:52:30 AM UTC 24 Aug 25 05:52:32 AM UTC 24 64579427 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.660188932 Aug 25 05:52:23 AM UTC 24 Aug 25 05:52:33 AM UTC 24 2229872348 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.724582456 Aug 25 05:52:27 AM UTC 24 Aug 25 05:52:34 AM UTC 24 2222740474 ps
T79 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.1548434940 Aug 25 05:52:31 AM UTC 24 Aug 25 05:52:34 AM UTC 24 185817326 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.1174625593 Aug 25 05:52:31 AM UTC 24 Aug 25 05:52:34 AM UTC 24 476734509 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.75914581 Aug 25 05:52:27 AM UTC 24 Aug 25 05:52:34 AM UTC 24 843789207 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.1196169995 Aug 25 05:52:31 AM UTC 24 Aug 25 05:52:34 AM UTC 24 343710885 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.49376000 Aug 25 05:52:29 AM UTC 24 Aug 25 05:52:35 AM UTC 24 900682868 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.4066508867 Aug 25 05:52:33 AM UTC 24 Aug 25 05:52:36 AM UTC 24 268575258 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1814408744 Aug 25 05:52:29 AM UTC 24 Aug 25 05:52:37 AM UTC 24 4672625320 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/3.rv_dm_sec_cm.2446102599 Aug 25 05:52:31 AM UTC 24 Aug 25 05:52:37 AM UTC 24 828348531 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/4.rv_dm_sec_cm.127766017 Aug 25 05:52:37 AM UTC 24 Aug 25 05:52:40 AM UTC 24 646527351 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.814214236 Aug 25 05:52:36 AM UTC 24 Aug 25 05:52:38 AM UTC 24 83451289 ps
T232 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.2781518497 Aug 25 05:52:34 AM UTC 24 Aug 25 05:52:40 AM UTC 24 1786454224 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/4.rv_dm_buffered_enable.1838434154 Aug 25 05:52:36 AM UTC 24 Aug 25 05:52:40 AM UTC 24 330505484 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.3537780208 Aug 25 05:52:36 AM UTC 24 Aug 25 05:52:41 AM UTC 24 412248360 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/4.rv_dm_alert_test.2412100057 Aug 25 05:52:38 AM UTC 24 Aug 25 05:52:41 AM UTC 24 58508608 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.3085566033 Aug 25 05:52:29 AM UTC 24 Aug 25 05:52:42 AM UTC 24 1639053792 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.3455560788 Aug 25 05:52:15 AM UTC 24 Aug 25 05:52:42 AM UTC 24 4060019047 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/5.rv_dm_halt_resume_whereto.533974657 Aug 25 05:52:42 AM UTC 24 Aug 25 05:52:44 AM UTC 24 177229878 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/5.rv_dm_buffered_enable.31105517 Aug 25 05:52:42 AM UTC 24 Aug 25 05:52:45 AM UTC 24 180251769 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/5.rv_dm_alert_test.2877317726 Aug 25 05:52:43 AM UTC 24 Aug 25 05:52:45 AM UTC 24 228954059 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.3765931797 Aug 25 05:52:16 AM UTC 24 Aug 25 05:52:46 AM UTC 24 2045739710 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.1587364087 Aug 25 05:52:36 AM UTC 24 Aug 25 05:52:48 AM UTC 24 5020290623 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/5.rv_dm_sba_tl_access.1909844958 Aug 25 05:52:38 AM UTC 24 Aug 25 05:52:48 AM UTC 24 1646976756 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.292724812 Aug 25 05:52:26 AM UTC 24 Aug 25 05:52:49 AM UTC 24 11778206822 ps
T121 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/6.rv_dm_buffered_enable.2015752437 Aug 25 05:52:46 AM UTC 24 Aug 25 05:52:50 AM UTC 24 153862686 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.3676768441 Aug 25 05:52:39 AM UTC 24 Aug 25 05:52:50 AM UTC 24 4791230555 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.450318981 Aug 25 05:52:31 AM UTC 24 Aug 25 05:52:50 AM UTC 24 2831306162 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/6.rv_dm_halt_resume_whereto.3480627253 Aug 25 05:52:46 AM UTC 24 Aug 25 05:52:50 AM UTC 24 266690166 ps
T123 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/6.rv_dm_sba_tl_access.3004747438 Aug 25 05:52:45 AM UTC 24 Aug 25 05:52:52 AM UTC 24 1740413016 ps
T124 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/6.rv_dm_alert_test.2397529864 Aug 25 05:52:50 AM UTC 24 Aug 25 05:52:52 AM UTC 24 209147563 ps
T225 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/6.rv_dm_autoincr_sba_tl_access.340670760 Aug 25 05:52:46 AM UTC 24 Aug 25 05:52:55 AM UTC 24 7425026349 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all.3954447197 Aug 25 05:52:49 AM UTC 24 Aug 25 05:52:55 AM UTC 24 2492637030 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.1159872206 Aug 25 05:52:42 AM UTC 24 Aug 25 05:52:56 AM UTC 24 5424696317 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/7.rv_dm_buffered_enable.2080259439 Aug 25 05:52:53 AM UTC 24 Aug 25 05:52:56 AM UTC 24 92687900 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.414222958 Aug 25 05:52:41 AM UTC 24 Aug 25 05:52:56 AM UTC 24 4635166986 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.1474232467 Aug 25 05:52:41 AM UTC 24 Aug 25 05:52:58 AM UTC 24 3866308706 ps
T176 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/4.rv_dm_bad_sba_tl_access.2766117382 Aug 25 05:52:35 AM UTC 24 Aug 25 05:52:58 AM UTC 24 4367804735 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.3796579798 Aug 25 05:52:51 AM UTC 24 Aug 25 05:52:59 AM UTC 24 7186915764 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/4.rv_dm_sba_tl_access.3629781111 Aug 25 05:52:34 AM UTC 24 Aug 25 05:52:59 AM UTC 24 4137501156 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/6.rv_dm_bad_sba_tl_access.724523130 Aug 25 05:52:46 AM UTC 24 Aug 25 05:52:59 AM UTC 24 1729495074 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/7.rv_dm_alert_test.760239180 Aug 25 05:52:57 AM UTC 24 Aug 25 05:52:59 AM UTC 24 112211356 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/8.rv_dm_alert_test.2513983790 Aug 25 05:53:00 AM UTC 24 Aug 25 05:53:02 AM UTC 24 254685625 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.1275881607 Aug 25 05:52:53 AM UTC 24 Aug 25 05:53:03 AM UTC 24 1343165737 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/8.rv_dm_buffered_enable.3793710998 Aug 25 05:53:00 AM UTC 24 Aug 25 05:53:03 AM UTC 24 152601200 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.266590833 Aug 25 05:52:45 AM UTC 24 Aug 25 05:53:03 AM UTC 24 5338998254 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/8.rv_dm_bad_sba_tl_access.467822494 Aug 25 05:52:59 AM UTC 24 Aug 25 05:53:05 AM UTC 24 2756571937 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.1803165335 Aug 25 05:52:17 AM UTC 24 Aug 25 05:53:05 AM UTC 24 9976684861 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/4.rv_dm_autoincr_sba_tl_access.3413842179 Aug 25 05:52:35 AM UTC 24 Aug 25 05:53:08 AM UTC 24 8387634259 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/9.rv_dm_buffered_enable.1665631548 Aug 25 05:53:06 AM UTC 24 Aug 25 05:53:09 AM UTC 24 731006597 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.2489702838 Aug 25 05:53:00 AM UTC 24 Aug 25 05:53:09 AM UTC 24 1697507918 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.3953275785 Aug 25 05:52:25 AM UTC 24 Aug 25 05:53:10 AM UTC 24 3768738202 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.684361435 Aug 25 05:53:09 AM UTC 24 Aug 25 05:53:11 AM UTC 24 62554760 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3738641382 Aug 25 05:52:51 AM UTC 24 Aug 25 05:53:13 AM UTC 24 3156126415 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.2562440543 Aug 25 05:52:26 AM UTC 24 Aug 25 05:53:13 AM UTC 24 15795500655 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/14.rv_dm_bad_sba_tl_access.303868215 Aug 25 05:53:33 AM UTC 24 Aug 25 05:53:45 AM UTC 24 3674416780 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.3449291246 Aug 25 05:52:58 AM UTC 24 Aug 25 05:53:14 AM UTC 24 6844713753 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.975639898 Aug 25 05:53:06 AM UTC 24 Aug 25 05:53:15 AM UTC 24 1989991710 ps
T210 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/10.rv_dm_alert_test.2742653349 Aug 25 05:53:14 AM UTC 24 Aug 25 05:53:16 AM UTC 24 63026508 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.739667682 Aug 25 05:52:30 AM UTC 24 Aug 25 05:53:18 AM UTC 24 19601674997 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.732903432 Aug 25 05:53:03 AM UTC 24 Aug 25 05:53:19 AM UTC 24 2054255916 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all.294687057 Aug 25 05:52:56 AM UTC 24 Aug 25 05:53:20 AM UTC 24 4293892547 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/11.rv_dm_alert_test.4216246745 Aug 25 05:53:19 AM UTC 24 Aug 25 05:53:22 AM UTC 24 154563812 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.62204521 Aug 25 05:53:03 AM UTC 24 Aug 25 05:53:22 AM UTC 24 3179992372 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/11.rv_dm_sba_tl_access.3210368232 Aug 25 05:53:15 AM UTC 24 Aug 25 05:53:22 AM UTC 24 2414526791 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/10.rv_dm_stress_all.521881789 Aug 25 05:53:14 AM UTC 24 Aug 25 05:53:23 AM UTC 24 2745625806 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/12.rv_dm_sba_tl_access.2571232624 Aug 25 05:53:21 AM UTC 24 Aug 25 05:53:27 AM UTC 24 3088431886 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/11.rv_dm_stress_all.1684841083 Aug 25 05:53:19 AM UTC 24 Aug 25 05:53:27 AM UTC 24 1497923371 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/12.rv_dm_alert_test.3103053609 Aug 25 05:53:27 AM UTC 24 Aug 25 05:53:29 AM UTC 24 50844796 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/12.rv_dm_autoincr_sba_tl_access.2202711582 Aug 25 05:53:24 AM UTC 24 Aug 25 05:53:30 AM UTC 24 4115208494 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/10.rv_dm_sba_tl_access.94678485 Aug 25 05:53:10 AM UTC 24 Aug 25 05:53:30 AM UTC 24 2977223450 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/12.rv_dm_stress_all.3497690351 Aug 25 05:53:25 AM UTC 24 Aug 25 05:53:31 AM UTC 24 5673694085 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.1899822649 Aug 25 05:53:28 AM UTC 24 Aug 25 05:53:32 AM UTC 24 1403770505 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.79366951 Aug 25 05:53:24 AM UTC 24 Aug 25 05:53:32 AM UTC 24 2219585464 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/11.rv_dm_bad_sba_tl_access.3965871768 Aug 25 05:53:16 AM UTC 24 Aug 25 05:53:33 AM UTC 24 7902430040 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/16.rv_dm_alert_test.1060329160 Aug 25 05:53:43 AM UTC 24 Aug 25 05:53:45 AM UTC 24 36121360 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/15.rv_dm_stress_all.256166838 Aug 25 05:53:37 AM UTC 24 Aug 25 05:53:45 AM UTC 24 4292299705 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/10.rv_dm_autoincr_sba_tl_access.3964751162 Aug 25 05:53:12 AM UTC 24 Aug 25 05:53:33 AM UTC 24 16693428572 ps
T222 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/13.rv_dm_alert_test.3049701537 Aug 25 05:53:32 AM UTC 24 Aug 25 05:53:34 AM UTC 24 50890858 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/9.rv_dm_autoincr_sba_tl_access.2361897019 Aug 25 05:53:04 AM UTC 24 Aug 25 05:53:34 AM UTC 24 25349877870 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/13.rv_dm_stress_all.2455483534 Aug 25 05:53:30 AM UTC 24 Aug 25 05:53:34 AM UTC 24 918642121 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/13.rv_dm_sba_tl_access.4252201071 Aug 25 05:53:28 AM UTC 24 Aug 25 05:53:35 AM UTC 24 1335515490 ps
T214 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/14.rv_dm_alert_test.3993142523 Aug 25 05:53:34 AM UTC 24 Aug 25 05:53:36 AM UTC 24 68214462 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/8.rv_dm_sba_tl_access.1779802770 Aug 25 05:52:57 AM UTC 24 Aug 25 05:53:36 AM UTC 24 12827619683 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/14.rv_dm_stress_all.21394376 Aug 25 05:53:34 AM UTC 24 Aug 25 05:53:39 AM UTC 24 1904296034 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/15.rv_dm_alert_test.3702044374 Aug 25 05:53:38 AM UTC 24 Aug 25 05:53:40 AM UTC 24 93521066 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/7.rv_dm_sba_tl_access.1015312930 Aug 25 05:52:51 AM UTC 24 Aug 25 05:53:42 AM UTC 24 13900956437 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.2553565572 Aug 25 05:53:10 AM UTC 24 Aug 25 05:53:42 AM UTC 24 4529770260 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.3730283362 Aug 25 05:53:40 AM UTC 24 Aug 25 05:53:44 AM UTC 24 1474056179 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/16.rv_dm_stress_all.1697719253 Aug 25 05:53:42 AM UTC 24 Aug 25 05:53:49 AM UTC 24 2422664235 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.1082221090 Aug 25 05:53:33 AM UTC 24 Aug 25 05:53:45 AM UTC 24 3381486391 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/15.rv_dm_bad_sba_tl_access.4096522614 Aug 25 05:53:36 AM UTC 24 Aug 25 05:53:45 AM UTC 24 1762687400 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/14.rv_dm_autoincr_sba_tl_access.508954853 Aug 25 05:53:34 AM UTC 24 Aug 25 05:53:48 AM UTC 24 1918189570 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/16.rv_dm_bad_sba_tl_access.2086197950 Aug 25 05:53:40 AM UTC 24 Aug 25 05:53:48 AM UTC 24 2577112495 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/17.rv_dm_alert_test.3909269211 Aug 25 05:53:46 AM UTC 24 Aug 25 05:53:49 AM UTC 24 148541705 ps
T223 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/15.rv_dm_sba_tl_access.4059915086 Aug 25 05:53:36 AM UTC 24 Aug 25 05:53:50 AM UTC 24 1902141115 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.3594754139 Aug 25 05:53:46 AM UTC 24 Aug 25 05:53:51 AM UTC 24 1459265665 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/14.rv_dm_sba_tl_access.3460040644 Aug 25 05:53:32 AM UTC 24 Aug 25 05:53:52 AM UTC 24 3516423748 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/18.rv_dm_alert_test.3383544870 Aug 25 05:53:52 AM UTC 24 Aug 25 05:53:54 AM UTC 24 63547931 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.1462441449 Aug 25 05:52:59 AM UTC 24 Aug 25 05:53:54 AM UTC 24 10272477235 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/17.rv_dm_autoincr_sba_tl_access.2564110744 Aug 25 05:53:46 AM UTC 24 Aug 25 05:53:55 AM UTC 24 4557953069 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/10.rv_dm_bad_sba_tl_access.792013656 Aug 25 05:53:11 AM UTC 24 Aug 25 05:53:55 AM UTC 24 7526042201 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.788416721 Aug 25 05:53:00 AM UTC 24 Aug 25 05:53:56 AM UTC 24 5178201913 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/17.rv_dm_bad_sba_tl_access.3099893280 Aug 25 05:53:46 AM UTC 24 Aug 25 05:53:57 AM UTC 24 4764027337 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/12.rv_dm_bad_sba_tl_access.4040225370 Aug 25 05:53:24 AM UTC 24 Aug 25 05:53:58 AM UTC 24 12396521851 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/19.rv_dm_sba_tl_access.4205163516 Aug 25 05:53:53 AM UTC 24 Aug 25 05:53:58 AM UTC 24 1502170418 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/11.rv_dm_autoincr_sba_tl_access.1302312157 Aug 25 05:53:17 AM UTC 24 Aug 25 05:53:58 AM UTC 24 12450322948 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/17.rv_dm_sba_tl_access.2465472590 Aug 25 05:53:45 AM UTC 24 Aug 25 05:53:58 AM UTC 24 3558205825 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/18.rv_dm_bad_sba_tl_access.852936811 Aug 25 05:53:50 AM UTC 24 Aug 25 05:53:58 AM UTC 24 2336021100 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/18.rv_dm_stress_all.680272682 Aug 25 05:53:51 AM UTC 24 Aug 25 05:53:59 AM UTC 24 3789969220 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/19.rv_dm_alert_test.1386444242 Aug 25 05:53:56 AM UTC 24 Aug 25 05:53:59 AM UTC 24 111890972 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.4056467865 Aug 25 05:53:55 AM UTC 24 Aug 25 05:53:59 AM UTC 24 1324386995 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/16.rv_dm_sba_tl_access.544151014 Aug 25 05:53:40 AM UTC 24 Aug 25 05:54:00 AM UTC 24 8281843983 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/19.rv_dm_bad_sba_tl_access.2518317583 Aug 25 05:53:55 AM UTC 24 Aug 25 05:54:00 AM UTC 24 1982028789 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.3427510828 Aug 25 05:53:48 AM UTC 24 Aug 25 05:54:00 AM UTC 24 2187752010 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.3955140245 Aug 25 05:52:43 AM UTC 24 Aug 25 05:54:00 AM UTC 24 3979677878 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/21.rv_dm_alert_test.758254015 Aug 25 05:53:59 AM UTC 24 Aug 25 05:54:01 AM UTC 24 47385785 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/22.rv_dm_alert_test.3075774079 Aug 25 05:53:59 AM UTC 24 Aug 25 05:54:01 AM UTC 24 94533285 ps
T227 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/20.rv_dm_alert_test.2021323830 Aug 25 05:53:59 AM UTC 24 Aug 25 05:54:01 AM UTC 24 115786239 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/17.rv_dm_stress_all.3180041349 Aug 25 05:53:46 AM UTC 24 Aug 25 05:54:03 AM UTC 24 2748491841 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/23.rv_dm_alert_test.2928291216 Aug 25 05:54:00 AM UTC 24 Aug 25 05:54:03 AM UTC 24 33164459 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/24.rv_dm_alert_test.2740817420 Aug 25 05:54:01 AM UTC 24 Aug 25 05:54:03 AM UTC 24 171090942 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/18.rv_dm_sba_tl_access.2687421911 Aug 25 05:53:48 AM UTC 24 Aug 25 05:54:03 AM UTC 24 14932584353 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/25.rv_dm_alert_test.3052699292 Aug 25 05:54:02 AM UTC 24 Aug 25 05:54:05 AM UTC 24 65817716 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/26.rv_dm_alert_test.2110556706 Aug 25 05:54:02 AM UTC 24 Aug 25 05:54:05 AM UTC 24 121192857 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/27.rv_dm_alert_test.3200644520 Aug 25 05:54:02 AM UTC 24 Aug 25 05:54:05 AM UTC 24 35708300 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/21.rv_dm_stress_all.3559186201 Aug 25 05:53:59 AM UTC 24 Aug 25 05:54:05 AM UTC 24 7988974859 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/28.rv_dm_alert_test.497626633 Aug 25 05:54:03 AM UTC 24 Aug 25 05:54:06 AM UTC 24 132376416 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.2620931286 Aug 25 05:53:58 AM UTC 24 Aug 25 05:54:06 AM UTC 24 3303735059 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/29.rv_dm_alert_test.1159269608 Aug 25 05:54:04 AM UTC 24 Aug 25 05:54:07 AM UTC 24 78289292 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/23.rv_dm_stress_all.3621275973 Aug 25 05:54:00 AM UTC 24 Aug 25 05:54:07 AM UTC 24 3889170870 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/30.rv_dm_alert_test.1646462546 Aug 25 05:54:06 AM UTC 24 Aug 25 05:54:08 AM UTC 24 65334823 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/13.rv_dm_autoincr_sba_tl_access.3912565250 Aug 25 05:53:30 AM UTC 24 Aug 25 05:54:08 AM UTC 24 14718088627 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.1594945964 Aug 25 05:54:01 AM UTC 24 Aug 25 05:54:08 AM UTC 24 4962377760 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.2813451756 Aug 25 05:54:02 AM UTC 24 Aug 25 05:54:09 AM UTC 24 2295541084 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.3164872485 Aug 25 05:53:59 AM UTC 24 Aug 25 05:54:09 AM UTC 24 3025378282 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/26.rv_dm_stress_all.3693519112 Aug 25 05:54:02 AM UTC 24 Aug 25 05:54:09 AM UTC 24 2462161520 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/24.rv_dm_stress_all.1501519044 Aug 25 05:54:00 AM UTC 24 Aug 25 05:54:09 AM UTC 24 4701537163 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/31.rv_dm_alert_test.1542191462 Aug 25 05:54:07 AM UTC 24 Aug 25 05:54:09 AM UTC 24 71341406 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/32.rv_dm_alert_test.2003901632 Aug 25 05:54:07 AM UTC 24 Aug 25 05:54:10 AM UTC 24 56338440 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.3863063425 Aug 25 05:53:03 AM UTC 24 Aug 25 05:54:10 AM UTC 24 11054309784 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.3173764801 Aug 25 05:54:06 AM UTC 24 Aug 25 05:54:11 AM UTC 24 1670495520 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/33.rv_dm_alert_test.1244259127 Aug 25 05:54:08 AM UTC 24 Aug 25 05:54:11 AM UTC 24 101147392 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/34.rv_dm_alert_test.3896501786 Aug 25 05:54:08 AM UTC 24 Aug 25 05:54:11 AM UTC 24 71816243 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/45.rv_dm_stress_all.797645334 Aug 25 05:54:15 AM UTC 24 Aug 25 05:54:22 AM UTC 24 1162595631 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/35.rv_dm_alert_test.1144192770 Aug 25 05:54:10 AM UTC 24 Aug 25 05:54:12 AM UTC 24 69083766 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/36.rv_dm_alert_test.1088958707 Aug 25 05:54:10 AM UTC 24 Aug 25 05:54:12 AM UTC 24 32939558 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/38.rv_dm_alert_test.1107193497 Aug 25 05:54:10 AM UTC 24 Aug 25 05:54:12 AM UTC 24 55546546 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.1891168395 Aug 25 05:53:15 AM UTC 24 Aug 25 05:54:12 AM UTC 24 14676585239 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/37.rv_dm_alert_test.2468766609 Aug 25 05:54:10 AM UTC 24 Aug 25 05:54:13 AM UTC 24 111532890 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.2027476464 Aug 25 05:52:56 AM UTC 24 Aug 25 05:54:13 AM UTC 24 2122554007 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/39.rv_dm_alert_test.1612180272 Aug 25 05:54:12 AM UTC 24 Aug 25 05:54:14 AM UTC 24 113424038 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/40.rv_dm_alert_test.1836932814 Aug 25 05:54:12 AM UTC 24 Aug 25 05:54:14 AM UTC 24 78436354 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/28.rv_dm_stress_all.2688972056 Aug 25 05:54:03 AM UTC 24 Aug 25 05:54:15 AM UTC 24 1715923513 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/42.rv_dm_alert_test.3360074785 Aug 25 05:54:13 AM UTC 24 Aug 25 05:54:15 AM UTC 24 127158049 ps
T111 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all_with_rand_reset.1180289627 Aug 25 05:52:49 AM UTC 24 Aug 25 05:54:15 AM UTC 24 3491543634 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/41.rv_dm_alert_test.4272927669 Aug 25 05:54:13 AM UTC 24 Aug 25 05:54:16 AM UTC 24 120918189 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/44.rv_dm_alert_test.3023995780 Aug 25 05:54:15 AM UTC 24 Aug 25 05:54:17 AM UTC 24 53773291 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/43.rv_dm_alert_test.2322180755 Aug 25 05:54:14 AM UTC 24 Aug 25 05:54:17 AM UTC 24 53805062 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/45.rv_dm_alert_test.1103541744 Aug 25 05:54:16 AM UTC 24 Aug 25 05:54:18 AM UTC 24 123295188 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/46.rv_dm_alert_test.2987375103 Aug 25 05:54:16 AM UTC 24 Aug 25 05:54:18 AM UTC 24 154358756 ps
T307 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/47.rv_dm_alert_test.3498204093 Aug 25 05:54:17 AM UTC 24 Aug 25 05:54:19 AM UTC 24 78155644 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/36.rv_dm_stress_all.2878187531 Aug 25 05:54:10 AM UTC 24 Aug 25 05:54:19 AM UTC 24 5811837122 ps
T309 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/39.rv_dm_stress_all.3501270677 Aug 25 05:54:12 AM UTC 24 Aug 25 05:54:20 AM UTC 24 3364583640 ps
T310 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/43.rv_dm_stress_all.1382780036 Aug 25 05:54:13 AM UTC 24 Aug 25 05:54:20 AM UTC 24 1605171463 ps
T311 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.2977271247 Aug 25 05:54:15 AM UTC 24 Aug 25 05:54:21 AM UTC 24 3664833278 ps
T312 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/40.rv_dm_stress_all.2929396798 Aug 25 05:54:12 AM UTC 24 Aug 25 05:54:21 AM UTC 24 2893427434 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/48.rv_dm_alert_test.191887174 Aug 25 05:54:18 AM UTC 24 Aug 25 05:54:21 AM UTC 24 37966656 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/32.rv_dm_stress_all.3721532036 Aug 25 05:54:07 AM UTC 24 Aug 25 05:54:21 AM UTC 24 3805570669 ps
T314 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/41.rv_dm_stress_all.651389316 Aug 25 05:54:12 AM UTC 24 Aug 25 05:54:22 AM UTC 24 1367238281 ps
T315 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/49.rv_dm_alert_test.1970484897 Aug 25 05:54:20 AM UTC 24 Aug 25 05:54:22 AM UTC 24 66623438 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/13.rv_dm_bad_sba_tl_access.2062777323 Aug 25 05:53:30 AM UTC 24 Aug 25 05:54:22 AM UTC 24 16443460416 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.398662565 Aug 25 05:54:16 AM UTC 24 Aug 25 05:54:23 AM UTC 24 1952577330 ps
T318 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/49.rv_dm_stress_all.3388375623 Aug 25 05:54:20 AM UTC 24 Aug 25 05:54:24 AM UTC 24 1459208856 ps
T319 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.290414327 Aug 25 05:53:36 AM UTC 24 Aug 25 05:54:24 AM UTC 24 11491377716 ps
T320 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/31.rv_dm_stress_all.2502246155 Aug 25 05:54:06 AM UTC 24 Aug 25 05:54:24 AM UTC 24 3059589550 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/47.rv_dm_stress_all.1565758546 Aug 25 05:54:17 AM UTC 24 Aug 25 05:54:25 AM UTC 24 4659715669 ps
T118 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.3031783291 Aug 25 05:52:27 AM UTC 24 Aug 25 05:54:25 AM UTC 24 8763067774 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.474223182 Aug 25 05:54:07 AM UTC 24 Aug 25 05:54:26 AM UTC 24 5868290066 ps
T321 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/29.rv_dm_stress_all.163966347 Aug 25 05:54:04 AM UTC 24 Aug 25 05:54:26 AM UTC 24 7410636747 ps
T322 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/34.rv_dm_stress_all.2725003220 Aug 25 05:54:08 AM UTC 24 Aug 25 05:54:28 AM UTC 24 2744619589 ps
T323 /workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/coverage/default/38.rv_dm_stress_all.198840676 Aug 25 05:54:10 AM UTC 24 Aug 25 05:54:30 AM UTC 24 6304883720 ps
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