Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.80	96.32	89.67	92.10	93.33	90.44	98.53	61.18

Total test records in report: 483

T82	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.2234912143	Aug 27 07:02:19 AM UTC 24	Aug 27 07:03:05 AM UTC 24	11077616456 ps
T81	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.3799744192	Aug 27 07:02:06 AM UTC 24	Aug 27 07:03:06 AM UTC 24	8429754277 ps
T334	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.4287163336	Aug 27 07:02:37 AM UTC 24	Aug 27 07:03:06 AM UTC 24	10871393865 ps
T335	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/12.rv_dm_autoincr_sba_tl_access.4004937877	Aug 27 07:02:24 AM UTC 24	Aug 27 07:03:07 AM UTC 24	77936138795 ps
T77	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.1116314822	Aug 27 07:02:12 AM UTC 24	Aug 27 07:03:12 AM UTC 24	50064620652 ps
T119	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.2144700056	Aug 27 07:02:17 AM UTC 24	Aug 27 07:03:16 AM UTC 24	3441710344 ps
T336	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.3852286672	Aug 27 07:01:54 AM UTC 24	Aug 27 07:03:19 AM UTC 24	48181420552 ps
T337	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_autoincr_sba_tl_access.2011531324	Aug 27 07:02:01 AM UTC 24	Aug 27 07:03:19 AM UTC 24	26232289347 ps
T338	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/9.rv_dm_autoincr_sba_tl_access.3133181272	Aug 27 07:02:18 AM UTC 24	Aug 27 07:03:40 AM UTC 24	32484442722 ps
T120	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.385031103	Aug 27 07:02:10 AM UTC 24	Aug 27 07:03:41 AM UTC 24	4116167273 ps
T339	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/18.rv_dm_autoincr_sba_tl_access.3573984890	Aug 27 07:02:34 AM UTC 24	Aug 27 07:04:36 AM UTC 24	41089120754 ps
T340	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/13.rv_dm_autoincr_sba_tl_access.513208788	Aug 27 07:02:25 AM UTC 24	Aug 27 07:07:52 AM UTC 24	100574339861 ps
T341	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/6.rv_dm_autoincr_sba_tl_access.928511547	Aug 27 07:02:13 AM UTC 24	Aug 27 07:10:49 AM UTC 24	187002641093 ps
T101	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2535478125	Aug 27 07:00:35 AM UTC 24	Aug 27 07:00:38 AM UTC 24	487821083 ps
T102	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1001583521	Aug 27 07:00:35 AM UTC 24	Aug 27 07:00:39 AM UTC 24	852237003 ps
T342	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.2117041026	Aug 27 07:00:37 AM UTC 24	Aug 27 07:00:39 AM UTC 24	73262256 ps
T343	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.4052857698	Aug 27 07:00:37 AM UTC 24	Aug 27 07:00:40 AM UTC 24	36066722 ps
T103	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1339806317	Aug 27 07:00:38 AM UTC 24	Aug 27 07:00:40 AM UTC 24	561243850 ps
T344	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3289290552	Aug 27 07:00:38 AM UTC 24	Aug 27 07:00:40 AM UTC 24	425437575 ps
T345	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.4226433155	Aug 27 07:00:35 AM UTC 24	Aug 27 07:00:40 AM UTC 24	1132396309 ps
T129	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.496858076	Aug 27 07:00:37 AM UTC 24	Aug 27 07:00:41 AM UTC 24	215778532 ps
T346	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1274969338	Aug 27 07:00:35 AM UTC 24	Aug 27 07:00:41 AM UTC 24	3903966484 ps
T347	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2551378559	Aug 27 07:00:35 AM UTC 24	Aug 27 07:00:41 AM UTC 24	2155661681 ps
T130	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3381286394	Aug 27 07:00:37 AM UTC 24	Aug 27 07:00:41 AM UTC 24	307914019 ps
T348	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1485441950	Aug 27 07:00:38 AM UTC 24	Aug 27 07:00:42 AM UTC 24	157671503 ps
T349	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2560843808	Aug 27 07:00:41 AM UTC 24	Aug 27 07:00:43 AM UTC 24	207402591 ps
T350	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.4289892775	Aug 27 07:00:41 AM UTC 24	Aug 27 07:00:43 AM UTC 24	76884728 ps
T351	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1753549292	Aug 27 07:00:41 AM UTC 24	Aug 27 07:00:43 AM UTC 24	125261642 ps
T352	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.2036603005	Aug 27 07:00:37 AM UTC 24	Aug 27 07:00:43 AM UTC 24	968628909 ps
T353	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2263035032	Aug 27 07:00:41 AM UTC 24	Aug 27 07:00:44 AM UTC 24	343224618 ps
T131	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2382347485	Aug 27 07:00:41 AM UTC 24	Aug 27 07:00:44 AM UTC 24	177719939 ps
T132	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.3761453816	Aug 27 07:00:41 AM UTC 24	Aug 27 07:00:44 AM UTC 24	106666689 ps
T354	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.150361253	Aug 27 07:00:42 AM UTC 24	Aug 27 07:00:45 AM UTC 24	376434966 ps
T106	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3648104625	Aug 27 07:00:41 AM UTC 24	Aug 27 07:00:46 AM UTC 24	150497250 ps
T355	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2187870676	Aug 27 07:00:44 AM UTC 24	Aug 27 07:00:46 AM UTC 24	42475669 ps
T356	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_walk.1233452442	Aug 27 07:00:44 AM UTC 24	Aug 27 07:00:46 AM UTC 24	35379461 ps
T133	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1209915906	Aug 27 07:00:38 AM UTC 24	Aug 27 07:00:46 AM UTC 24	385103537 ps
T194	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1191815713	Aug 27 07:00:37 AM UTC 24	Aug 27 07:00:47 AM UTC 24	1170098212 ps
T357	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.2224596303	Aug 27 07:00:41 AM UTC 24	Aug 27 07:00:48 AM UTC 24	1162675575 ps
T358	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1155706442	Aug 27 07:00:42 AM UTC 24	Aug 27 07:00:48 AM UTC 24	2625243856 ps
T134	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1872736669	Aug 27 07:00:45 AM UTC 24	Aug 27 07:00:48 AM UTC 24	454841227 ps
T359	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_errors.3387012192	Aug 27 07:00:44 AM UTC 24	Aug 27 07:00:48 AM UTC 24	154507792 ps
T360	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1812439721	Aug 27 07:00:46 AM UTC 24	Aug 27 07:00:49 AM UTC 24	208807575 ps
T178	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1596170573	Aug 27 07:00:46 AM UTC 24	Aug 27 07:00:49 AM UTC 24	153527712 ps
T135	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_rw.158472827	Aug 27 07:00:45 AM UTC 24	Aug 27 07:00:49 AM UTC 24	53251400 ps
T361	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1693013507	Aug 27 07:00:41 AM UTC 24	Aug 27 07:00:49 AM UTC 24	2928484788 ps
T362	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1734098604	Aug 27 07:00:46 AM UTC 24	Aug 27 07:00:50 AM UTC 24	421594427 ps
T136	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.4005801584	Aug 27 07:00:41 AM UTC 24	Aug 27 07:00:50 AM UTC 24	3276585197 ps
T363	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3639665640	Aug 27 07:00:38 AM UTC 24	Aug 27 07:01:08 AM UTC 24	40475824281 ps
T364	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1521862009	Aug 27 07:00:41 AM UTC 24	Aug 27 07:00:52 AM UTC 24	5758850722 ps
T365	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_walk.3649066056	Aug 27 07:00:50 AM UTC 24	Aug 27 07:00:52 AM UTC 24	106404118 ps
T366	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1017848082	Aug 27 07:00:50 AM UTC 24	Aug 27 07:00:52 AM UTC 24	34511880 ps
T137	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.968911893	Aug 27 07:00:46 AM UTC 24	Aug 27 07:00:53 AM UTC 24	308623540 ps
T367	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_errors.3984138851	Aug 27 07:01:03 AM UTC 24	Aug 27 07:01:10 AM UTC 24	325882066 ps
T138	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3580308640	Aug 27 07:00:50 AM UTC 24	Aug 27 07:00:53 AM UTC 24	163805669 ps
T368	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.540540781	Aug 27 07:00:48 AM UTC 24	Aug 27 07:00:54 AM UTC 24	623707527 ps
T369	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_errors.4066476393	Aug 27 07:00:50 AM UTC 24	Aug 27 07:00:54 AM UTC 24	371680812 ps
T146	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_rw.3770218897	Aug 27 07:00:50 AM UTC 24	Aug 27 07:00:54 AM UTC 24	88233876 ps
T370	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3922707492	Aug 27 07:00:53 AM UTC 24	Aug 27 07:00:55 AM UTC 24	188030559 ps
T371	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.204583729	Aug 27 07:00:53 AM UTC 24	Aug 27 07:00:55 AM UTC 24	368620447 ps
T179	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.212047561	Aug 27 07:00:44 AM UTC 24	Aug 27 07:00:56 AM UTC 24	1641050010 ps
T195	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1242561675	Aug 27 07:00:41 AM UTC 24	Aug 27 07:00:56 AM UTC 24	2481598554 ps
T372	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.671195507	Aug 27 07:00:53 AM UTC 24	Aug 27 07:00:57 AM UTC 24	146850457 ps
T373	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.331655417	Aug 27 07:00:41 AM UTC 24	Aug 27 07:00:57 AM UTC 24	23382457992 ps
T374	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3293053970	Aug 27 07:00:55 AM UTC 24	Aug 27 07:00:58 AM UTC 24	1619057231 ps
T142	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2350693436	Aug 27 07:00:35 AM UTC 24	Aug 27 07:00:59 AM UTC 24	10345459433 ps
T375	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.441713769	Aug 27 07:00:55 AM UTC 24	Aug 27 07:00:59 AM UTC 24	988616846 ps
T376	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.2297239451	Aug 27 07:00:43 AM UTC 24	Aug 27 07:00:59 AM UTC 24	4924113804 ps
T377	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3654754610	Aug 27 07:00:57 AM UTC 24	Aug 27 07:01:00 AM UTC 24	175943235 ps
T378	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_walk.1717310450	Aug 27 07:00:57 AM UTC 24	Aug 27 07:01:00 AM UTC 24	79245902 ps
T147	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.663436965	Aug 27 07:00:52 AM UTC 24	Aug 27 07:01:02 AM UTC 24	1220518729 ps
T379	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2399583438	Aug 27 07:01:00 AM UTC 24	Aug 27 07:01:03 AM UTC 24	273525888 ps
T380	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_rw.2591999442	Aug 27 07:01:00 AM UTC 24	Aug 27 07:01:03 AM UTC 24	439157140 ps
T148	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3885053147	Aug 27 07:01:00 AM UTC 24	Aug 27 07:01:03 AM UTC 24	169128044 ps
T180	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1206977561	Aug 27 07:00:50 AM UTC 24	Aug 27 07:01:04 AM UTC 24	3584435521 ps
T181	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_errors.4000376647	Aug 27 07:00:56 AM UTC 24	Aug 27 07:01:04 AM UTC 24	1102803707 ps
T381	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2047011062	Aug 27 07:01:00 AM UTC 24	Aug 27 07:01:04 AM UTC 24	75004297 ps
T107	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.2755136919	Aug 27 07:00:50 AM UTC 24	Aug 27 07:01:06 AM UTC 24	2418706138 ps
T143	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1043924237	Aug 27 07:00:48 AM UTC 24	Aug 27 07:01:07 AM UTC 24	4351021748 ps
T382	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.139264455	Aug 27 07:01:02 AM UTC 24	Aug 27 07:01:07 AM UTC 24	7574843639 ps
T149	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_rw.2419787213	Aug 27 07:01:04 AM UTC 24	Aug 27 07:01:08 AM UTC 24	184763759 ps
T383	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2053867191	Aug 27 07:00:50 AM UTC 24	Aug 27 07:01:08 AM UTC 24	15775990667 ps
T150	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3345417310	Aug 27 07:01:04 AM UTC 24	Aug 27 07:01:09 AM UTC 24	307885882 ps
T159	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_rw.3375335213	Aug 27 07:01:09 AM UTC 24	Aug 27 07:01:12 AM UTC 24	37891906 ps
T384	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.619204271	Aug 27 07:00:48 AM UTC 24	Aug 27 07:01:09 AM UTC 24	7107529422 ps
T385	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2742511972	Aug 27 07:01:06 AM UTC 24	Aug 27 07:01:09 AM UTC 24	319363788 ps
T172	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1034906620	Aug 27 07:00:41 AM UTC 24	Aug 27 07:01:09 AM UTC 24	2969532670 ps
T144	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2707553447	Aug 27 07:00:55 AM UTC 24	Aug 27 07:01:09 AM UTC 24	5270783698 ps
T217	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1731544443	Aug 27 07:00:57 AM UTC 24	Aug 27 07:01:10 AM UTC 24	1340473937 ps
T112	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3884850844	Aug 27 07:00:37 AM UTC 24	Aug 27 07:01:10 AM UTC 24	6230692190 ps
T145	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.340948998	Aug 27 07:00:42 AM UTC 24	Aug 27 07:01:10 AM UTC 24	17495648445 ps
T151	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2011147638	Aug 27 07:01:00 AM UTC 24	Aug 27 07:01:10 AM UTC 24	415408725 ps
T386	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2052006241	Aug 27 07:01:05 AM UTC 24	Aug 27 07:01:11 AM UTC 24	93159397 ps
T387	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1792971824	Aug 27 07:00:55 AM UTC 24	Aug 27 07:01:11 AM UTC 24	18463794816 ps
T388	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.753029806	Aug 27 07:01:10 AM UTC 24	Aug 27 07:01:13 AM UTC 24	181148762 ps
T160	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_rw.3866918449	Aug 27 07:01:11 AM UTC 24	Aug 27 07:01:14 AM UTC 24	137515645 ps
T182	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.508490020	Aug 27 07:01:10 AM UTC 24	Aug 27 07:01:14 AM UTC 24	853852868 ps
T389	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.91906400	Aug 27 07:01:12 AM UTC 24	Aug 27 07:01:14 AM UTC 24	869178736 ps
T390	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3626425040	Aug 27 07:01:10 AM UTC 24	Aug 27 07:01:15 AM UTC 24	2682388265 ps
T391	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2575138434	Aug 27 07:01:12 AM UTC 24	Aug 27 07:01:15 AM UTC 24	209039987 ps
T183	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_errors.3032337208	Aug 27 07:01:09 AM UTC 24	Aug 27 07:01:15 AM UTC 24	274678606 ps
T392	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.4078704140	Aug 27 07:01:12 AM UTC 24	Aug 27 07:01:15 AM UTC 24	1408064824 ps
T169	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.271421899	Aug 27 07:01:10 AM UTC 24	Aug 27 07:01:16 AM UTC 24	161617850 ps
T393	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.4255288955	Aug 27 07:00:48 AM UTC 24	Aug 27 07:01:16 AM UTC 24	20581147990 ps
T394	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.515823781	Aug 27 07:01:13 AM UTC 24	Aug 27 07:01:18 AM UTC 24	3949868512 ps
T395	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1020833153	Aug 27 07:01:16 AM UTC 24	Aug 27 07:01:18 AM UTC 24	140170384 ps
T184	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_errors.2871717413	Aug 27 07:01:11 AM UTC 24	Aug 27 07:01:19 AM UTC 24	229145161 ps
T396	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1924926944	Aug 27 07:01:08 AM UTC 24	Aug 27 07:01:19 AM UTC 24	2466117831 ps
T161	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_rw.1966818903	Aug 27 07:01:16 AM UTC 24	Aug 27 07:01:19 AM UTC 24	297832099 ps
T397	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_errors.3825948551	Aug 27 07:01:16 AM UTC 24	Aug 27 07:01:19 AM UTC 24	173022323 ps
T398	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1789396281	Aug 27 07:01:16 AM UTC 24	Aug 27 07:01:20 AM UTC 24	79417922 ps
T399	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.79578182	Aug 27 07:00:41 AM UTC 24	Aug 27 07:01:20 AM UTC 24	27829613756 ps
T167	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3405368124	Aug 27 07:00:38 AM UTC 24	Aug 27 07:01:20 AM UTC 24	13313957576 ps
T400	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3488855240	Aug 27 07:01:16 AM UTC 24	Aug 27 07:01:20 AM UTC 24	1356375790 ps
T170	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3555651169	Aug 27 07:01:12 AM UTC 24	Aug 27 07:01:22 AM UTC 24	582085535 ps
T401	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.848285376	Aug 27 07:00:45 AM UTC 24	Aug 27 07:01:22 AM UTC 24	8366600926 ps
T220	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2909932523	Aug 27 07:01:11 AM UTC 24	Aug 27 07:01:23 AM UTC 24	843509688 ps
T402	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3097535038	Aug 27 07:00:42 AM UTC 24	Aug 27 07:01:23 AM UTC 24	8833778781 ps
T403	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_rw.712440723	Aug 27 07:01:19 AM UTC 24	Aug 27 07:01:23 AM UTC 24	151057851 ps
T162	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3129765241	Aug 27 07:00:53 AM UTC 24	Aug 27 07:01:24 AM UTC 24	1714621260 ps
T404	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2614845162	Aug 27 07:01:21 AM UTC 24	Aug 27 07:01:24 AM UTC 24	54115465 ps
T171	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1956210495	Aug 27 07:01:16 AM UTC 24	Aug 27 07:01:25 AM UTC 24	997340223 ps
T405	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1786860245	Aug 27 07:01:21 AM UTC 24	Aug 27 07:01:25 AM UTC 24	1011557917 ps
T163	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.1632447764	Aug 27 07:01:22 AM UTC 24	Aug 27 07:01:26 AM UTC 24	143604161 ps
T406	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.1326396007	Aug 27 07:01:32 AM UTC 24	Aug 27 07:01:46 AM UTC 24	12343886889 ps
T407	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_errors.2580294157	Aug 27 07:01:17 AM UTC 24	Aug 27 07:01:26 AM UTC 24	714746872 ps
T408	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3036477873	Aug 27 07:01:23 AM UTC 24	Aug 27 07:01:27 AM UTC 24	254096163 ps
T409	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.704327933	Aug 27 07:01:21 AM UTC 24	Aug 27 07:01:27 AM UTC 24	355141392 ps
T152	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.50987588	Aug 27 07:01:22 AM UTC 24	Aug 27 07:01:28 AM UTC 24	101934673 ps
T164	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_rw.2762164362	Aug 27 07:01:26 AM UTC 24	Aug 27 07:01:28 AM UTC 24	66487148 ps
T109	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2038128062	Aug 27 07:01:23 AM UTC 24	Aug 27 07:01:29 AM UTC 24	100521889 ps
T410	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2425640751	Aug 27 07:01:26 AM UTC 24	Aug 27 07:01:30 AM UTC 24	651045840 ps
T218	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_intg_err.657263777	Aug 27 07:01:04 AM UTC 24	Aug 27 07:01:30 AM UTC 24	1884217700 ps
T411	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1035366334	Aug 27 07:01:26 AM UTC 24	Aug 27 07:01:31 AM UTC 24	250766419 ps
T214	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2297706889	Aug 27 07:01:16 AM UTC 24	Aug 27 07:01:32 AM UTC 24	4905855571 ps
T412	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1103027019	Aug 27 07:01:26 AM UTC 24	Aug 27 07:01:33 AM UTC 24	714121932 ps
T215	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_intg_err.4262377451	Aug 27 07:01:22 AM UTC 24	Aug 27 07:01:33 AM UTC 24	4503587863 ps
T153	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_rw.1536085322	Aug 27 07:01:29 AM UTC 24	Aug 27 07:01:33 AM UTC 24	141319745 ps
T413	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_errors.1449277054	Aug 27 07:01:24 AM UTC 24	Aug 27 07:01:34 AM UTC 24	601438571 ps
T216	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2903506758	Aug 27 07:01:24 AM UTC 24	Aug 27 07:01:34 AM UTC 24	2109171420 ps
T414	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_errors.2560143294	Aug 27 07:01:28 AM UTC 24	Aug 27 07:01:34 AM UTC 24	297015158 ps
T415	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1018871253	Aug 27 07:01:30 AM UTC 24	Aug 27 07:01:34 AM UTC 24	368868066 ps
T221	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_intg_err.144152323	Aug 27 07:01:09 AM UTC 24	Aug 27 07:01:34 AM UTC 24	1737152953 ps
T154	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2867790951	Aug 27 07:01:21 AM UTC 24	Aug 27 07:01:35 AM UTC 24	1127569028 ps
T416	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.118283615	Aug 27 07:01:30 AM UTC 24	Aug 27 07:01:36 AM UTC 24	247870917 ps
T155	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3830747841	Aug 27 07:01:29 AM UTC 24	Aug 27 07:01:36 AM UTC 24	136465214 ps
T417	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2311787718	Aug 27 07:01:21 AM UTC 24	Aug 27 07:01:36 AM UTC 24	2816627198 ps
T165	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_rw.2572931764	Aug 27 07:01:33 AM UTC 24	Aug 27 07:01:36 AM UTC 24	119042860 ps
T418	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.3739010247	Aug 27 07:01:35 AM UTC 24	Aug 27 07:01:38 AM UTC 24	256724493 ps
T419	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1390970960	Aug 27 07:01:31 AM UTC 24	Aug 27 07:01:39 AM UTC 24	1092315312 ps
T420	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_errors.1173297937	Aug 27 07:01:33 AM UTC 24	Aug 27 07:01:40 AM UTC 24	703497414 ps
T421	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2201327893	Aug 27 07:01:38 AM UTC 24	Aug 27 07:01:40 AM UTC 24	388945822 ps
T156	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_rw.1528864523	Aug 27 07:01:36 AM UTC 24	Aug 27 07:01:40 AM UTC 24	98432682 ps
T116	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3980758223	Aug 27 07:01:08 AM UTC 24	Aug 27 07:01:40 AM UTC 24	7629472441 ps
T422	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1120330415	Aug 27 07:01:35 AM UTC 24	Aug 27 07:01:40 AM UTC 24	3250536150 ps
T423	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.1367424220	Aug 27 07:01:17 AM UTC 24	Aug 27 07:01:40 AM UTC 24	14884364980 ps
T424	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2350267161	Aug 27 07:01:21 AM UTC 24	Aug 27 07:01:41 AM UTC 24	5711318249 ps
T425	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1585301612	Aug 27 07:01:36 AM UTC 24	Aug 27 07:01:41 AM UTC 24	117926143 ps
T108	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2054635064	Aug 27 07:01:35 AM UTC 24	Aug 27 07:01:41 AM UTC 24	257343075 ps
T426	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_errors.2519377650	Aug 27 07:01:40 AM UTC 24	Aug 27 07:01:47 AM UTC 24	344214517 ps
T427	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_intg_err.437140130	Aug 27 07:01:18 AM UTC 24	Aug 27 07:01:42 AM UTC 24	5369758840 ps
T113	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2303159360	Aug 27 07:00:44 AM UTC 24	Aug 27 07:01:42 AM UTC 24	4798982451 ps
T428	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_errors.1912739668	Aug 27 07:01:35 AM UTC 24	Aug 27 07:01:43 AM UTC 24	117537807 ps
T429	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3770205648	Aug 27 07:01:35 AM UTC 24	Aug 27 07:01:44 AM UTC 24	570333371 ps
T430	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3659646759	Aug 27 07:01:41 AM UTC 24	Aug 27 07:01:45 AM UTC 24	376864867 ps
T431	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_rw.2666775046	Aug 27 07:01:41 AM UTC 24	Aug 27 07:01:45 AM UTC 24	333305222 ps
T168	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1931454614	Aug 27 07:00:38 AM UTC 24	Aug 27 07:01:45 AM UTC 24	1993057443 ps
T432	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.951666894	Aug 27 07:01:02 AM UTC 24	Aug 27 07:01:45 AM UTC 24	20559845467 ps
T157	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.684742179	Aug 27 07:01:36 AM UTC 24	Aug 27 07:01:46 AM UTC 24	380700575 ps
T433	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_rw.3374822249	Aug 27 07:01:42 AM UTC 24	Aug 27 07:01:46 AM UTC 24	913358313 ps
T434	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_errors.1272483340	Aug 27 07:01:42 AM UTC 24	Aug 27 07:01:46 AM UTC 24	298032368 ps
T435	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.4051641340	Aug 27 07:01:41 AM UTC 24	Aug 27 07:01:49 AM UTC 24	3486133816 ps
T114	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2828129409	Aug 27 07:01:41 AM UTC 24	Aug 27 07:01:46 AM UTC 24	97000450 ps
T436	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1318904622	Aug 27 07:01:43 AM UTC 24	Aug 27 07:01:47 AM UTC 24	267009203 ps
T437	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1230666884	Aug 27 07:01:42 AM UTC 24	Aug 27 07:01:47 AM UTC 24	2838478453 ps
T158	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3070086401	Aug 27 07:01:41 AM UTC 24	Aug 27 07:01:48 AM UTC 24	869384275 ps
T105	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1569334106	Aug 27 07:01:11 AM UTC 24	Aug 27 07:01:48 AM UTC 24	3914809326 ps
T222	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1410901145	Aug 27 07:01:35 AM UTC 24	Aug 27 07:01:49 AM UTC 24	1477300045 ps
T438	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2232466845	Aug 27 07:01:45 AM UTC 24	Aug 27 07:01:49 AM UTC 24	373241616 ps
T439	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.244220507	Aug 27 07:01:27 AM UTC 24	Aug 27 07:01:50 AM UTC 24	13732130917 ps
T440	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.786055080	Aug 27 07:01:47 AM UTC 24	Aug 27 07:01:50 AM UTC 24	278197839 ps
T441	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2648784728	Aug 27 07:00:35 AM UTC 24	Aug 27 07:01:50 AM UTC 24	8698514057 ps
T442	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1851410822	Aug 27 07:01:43 AM UTC 24	Aug 27 07:01:51 AM UTC 24	623549114 ps
T443	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_rw.345985354	Aug 27 07:01:47 AM UTC 24	Aug 27 07:01:52 AM UTC 24	368817929 ps
T444	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_rw.4250573960	Aug 27 07:01:48 AM UTC 24	Aug 27 07:01:52 AM UTC 24	144885824 ps
T445	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_errors.296103925	Aug 27 07:01:47 AM UTC 24	Aug 27 07:01:52 AM UTC 24	126477320 ps
T446	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3842955352	Aug 27 07:01:45 AM UTC 24	Aug 27 07:01:52 AM UTC 24	6079975284 ps
T447	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.739826581	Aug 27 07:01:50 AM UTC 24	Aug 27 07:01:53 AM UTC 24	389000834 ps
T448	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_errors.874396923	Aug 27 07:01:48 AM UTC 24	Aug 27 07:01:53 AM UTC 24	174833498 ps
T449	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3358173655	Aug 27 07:01:24 AM UTC 24	Aug 27 07:01:53 AM UTC 24	5345204808 ps
T450	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2435525707	Aug 27 07:01:47 AM UTC 24	Aug 27 07:01:53 AM UTC 24	177667687 ps
T451	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1323108401	Aug 27 07:01:50 AM UTC 24	Aug 27 07:01:54 AM UTC 24	120651708 ps
T452	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1109599324	Aug 27 07:01:50 AM UTC 24	Aug 27 07:01:54 AM UTC 24	1517154458 ps
T453	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_rw.361297508	Aug 27 07:01:51 AM UTC 24	Aug 27 07:01:54 AM UTC 24	340506466 ps
T454	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_errors.2970284520	Aug 27 07:01:51 AM UTC 24	Aug 27 07:01:55 AM UTC 24	77215127 ps
T455	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.4115981239	Aug 27 07:01:47 AM UTC 24	Aug 27 07:01:56 AM UTC 24	337199099 ps
T219	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1222073771	Aug 27 07:01:28 AM UTC 24	Aug 27 07:01:56 AM UTC 24	6525652390 ps
T224	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1194513340	Aug 27 07:01:42 AM UTC 24	Aug 27 07:01:56 AM UTC 24	2193113430 ps
T110	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2919914797	Aug 27 07:01:53 AM UTC 24	Aug 27 07:01:57 AM UTC 24	246730897 ps
T456	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.362104244	Aug 27 07:01:47 AM UTC 24	Aug 27 07:01:57 AM UTC 24	5152332810 ps
T166	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2961901294	Aug 27 07:00:41 AM UTC 24	Aug 27 07:01:57 AM UTC 24	6737274310 ps
T457	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.995867163	Aug 27 07:01:53 AM UTC 24	Aug 27 07:01:58 AM UTC 24	240575950 ps
T458	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.3140651381	Aug 27 07:01:27 AM UTC 24	Aug 27 07:01:58 AM UTC 24	21795065800 ps
T459	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.3630322160	Aug 27 07:01:10 AM UTC 24	Aug 27 07:01:58 AM UTC 24	14374567972 ps
T111	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.2273015983	Aug 27 07:01:14 AM UTC 24	Aug 27 07:01:59 AM UTC 24	2205860882 ps
T460	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3327252910	Aug 27 07:01:49 AM UTC 24	Aug 27 07:01:59 AM UTC 24	598129982 ps
T461	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_intg_err.983365067	Aug 27 07:01:33 AM UTC 24	Aug 27 07:02:00 AM UTC 24	1629544306 ps
T462	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1458610267	Aug 27 07:00:46 AM UTC 24	Aug 27 07:02:00 AM UTC 24	17041368831 ps
T463	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.567741229	Aug 27 07:00:41 AM UTC 24	Aug 27 07:02:00 AM UTC 24	17109203183 ps
T115	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2904811121	Aug 27 07:01:02 AM UTC 24	Aug 27 07:02:03 AM UTC 24	3846019863 ps
T464	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_intg_err.69772213	Aug 27 07:01:41 AM UTC 24	Aug 27 07:02:03 AM UTC 24	14264119429 ps
T225	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.1147953173	Aug 27 07:01:47 AM UTC 24	Aug 27 07:02:05 AM UTC 24	6421296768 ps
T465	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.4093849084	Aug 27 07:01:38 AM UTC 24	Aug 27 07:02:05 AM UTC 24	9008147672 ps
T466	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3529565107	Aug 27 07:01:48 AM UTC 24	Aug 27 07:02:07 AM UTC 24	10268935574 ps
T467	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3961941702	Aug 27 07:01:35 AM UTC 24	Aug 27 07:02:07 AM UTC 24	16642870489 ps
T468	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3732218859	Aug 27 07:00:56 AM UTC 24	Aug 27 07:02:08 AM UTC 24	28733813028 ps
T469	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.709314590	Aug 27 07:01:48 AM UTC 24	Aug 27 07:02:08 AM UTC 24	20045112778 ps
T470	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.773656141	Aug 27 07:00:35 AM UTC 24	Aug 27 07:02:09 AM UTC 24	26874807051 ps
T223	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_intg_err.126759913	Aug 27 07:01:51 AM UTC 24	Aug 27 07:02:10 AM UTC 24	3022522658 ps
T471	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3597115241	Aug 27 07:01:00 AM UTC 24	Aug 27 07:02:10 AM UTC 24	8071435435 ps
T472	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.61844497	Aug 27 07:01:24 AM UTC 24	Aug 27 07:02:12 AM UTC 24	18748111892 ps
T473	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.3741087559	Aug 27 07:01:51 AM UTC 24	Aug 27 07:02:13 AM UTC 24	21421940355 ps
T104	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.526913011	Aug 27 07:00:56 AM UTC 24	Aug 27 07:02:17 AM UTC 24	9857632042 ps
T474	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.446940724	Aug 27 07:00:55 AM UTC 24	Aug 27 07:02:19 AM UTC 24	41709114889 ps
T475	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.95471616	Aug 27 07:00:52 AM UTC 24	Aug 27 07:02:22 AM UTC 24	25287919233 ps
T476	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2406843739	Aug 27 07:00:43 AM UTC 24	Aug 27 07:02:25 AM UTC 24	33510288949 ps
T477	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.1174458830	Aug 27 07:01:39 AM UTC 24	Aug 27 07:02:27 AM UTC 24	14858502092 ps
T478	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2822599578	Aug 27 07:00:50 AM UTC 24	Aug 27 07:02:30 AM UTC 24	33682037397 ps
T479	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.343053028	Aug 27 07:01:08 AM UTC 24	Aug 27 07:02:30 AM UTC 24	46180624174 ps
T480	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2937069950	Aug 27 07:01:17 AM UTC 24	Aug 27 07:02:43 AM UTC 24	41365899357 ps
T481	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.416746301	Aug 27 07:00:43 AM UTC 24	Aug 27 07:03:35 AM UTC 24	56402795047 ps
T482	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.587057549	Aug 27 07:00:35 AM UTC 24	Aug 27 07:03:44 AM UTC 24	105112523703 ps
T483	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3839971039	Aug 27 07:01:45 AM UTC 24	Aug 27 07:04:32 AM UTC 24	53286573611 ps

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.3691935093
Short name	T18
Test name
Test status
Simulation time	2551705539 ps
CPU time	4.01 seconds
Started	Aug 27 07:01:54 AM UTC 24
Finished	Aug 27 07:01:59 AM UTC 24
Peak memory	226564 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691935093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.3691935093
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.2234912143
Short name	T82
Test name
Test status
Simulation time	11077616456 ps
CPU time	44 seconds
Started	Aug 27 07:02:19 AM UTC 24
Finished	Aug 27 07:03:05 AM UTC 24
Peak memory	243520 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2234912143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stres s_all_with_rand_reset.2234912143
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.3937934731
Short name	T45
Test name
Test status
Simulation time	774944666 ps
CPU time	1.68 seconds
Started	Aug 27 07:01:57 AM UTC 24
Finished	Aug 27 07:02:00 AM UTC 24
Peak memory	213392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937934731 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.3937934731
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_halt_resume_whereto/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.3643562403
Short name	T49
Test name
Test status
Simulation time	8674656787 ps
CPU time	6.11 seconds
Started	Aug 27 07:01:53 AM UTC 24
Finished	Aug 27 07:02:00 AM UTC 24
Peak memory	215996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643562403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.3643562403
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.1506988820
Short name	T32
Test name
Test status
Simulation time	2195560251 ps
CPU time	2.78 seconds
Started	Aug 27 07:02:11 AM UTC 24
Finished	Aug 27 07:02:15 AM UTC 24
Peak memory	226384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506988820 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.1506988820
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/5.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1191815713
Short name	T194
Test name
Test status
Simulation time	1170098212 ps
CPU time	8.39 seconds
Started	Aug 27 07:00:37 AM UTC 24
Finished	Aug 27 07:00:47 AM UTC 24
Peak memory	225628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191815713 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.1191815713
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.3656027746
Short name	T9
Test name
Test status
Simulation time	4361576954 ps
CPU time	20.05 seconds
Started	Aug 27 07:02:07 AM UTC 24
Finished	Aug 27 07:02:29 AM UTC 24
Peak memory	230604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3656027746 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stres s_all_with_rand_reset.3656027746
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.3818565123
Short name	T44
Test name
Test status
Simulation time	747020104 ps
CPU time	2.85 seconds
Started	Aug 27 07:01:59 AM UTC 24
Finished	Aug 27 07:02:03 AM UTC 24
Peak memory	252604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818565123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_buffered_enable.3818565123
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_buffered_enable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.325383587
Short name	T75
Test name
Test status
Simulation time	214634170 ps
CPU time	1.37 seconds
Started	Aug 27 07:01:59 AM UTC 24
Finished	Aug 27 07:02:01 AM UTC 24
Peak memory	213312 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325383587 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_dmi_failed_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.325383587
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_dmi_failed_op/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.885253560
Short name	T53
Test name
Test status
Simulation time	164273204 ps
CPU time	1.12 seconds
Started	Aug 27 07:02:06 AM UTC 24
Finished	Aug 27 07:02:08 AM UTC 24
Peak memory	215988 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885253560 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.885253560
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/2.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/9.rv_dm_autoincr_sba_tl_access.3133181272
Short name	T338
Test name
Test status
Simulation time	32484442722 ps
CPU time	80 seconds
Started	Aug 27 07:02:18 AM UTC 24
Finished	Aug 27 07:03:40 AM UTC 24
Peak memory	226564 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133181272 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.3133181272
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/9.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.3928692034
Short name	T36
Test name
Test status
Simulation time	3943703901 ps
CPU time	50.83 seconds
Started	Aug 27 07:02:00 AM UTC 24
Finished	Aug 27 07:02:52 AM UTC 24
Peak memory	233328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3928692034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stres s_all_with_rand_reset.3928692034
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.2755136919
Short name	T107
Test name
Test status
Simulation time	2418706138 ps
CPU time	15.43 seconds
Started	Aug 27 07:00:50 AM UTC 24
Finished	Aug 27 07:01:06 AM UTC 24
Peak memory	228000 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2755136919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_re set.2755136919
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/3.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.2158594046
Short name	T99
Test name
Test status
Simulation time	14676365 ps
CPU time	0.98 seconds
Started	Aug 27 07:01:59 AM UTC 24
Finished	Aug 27 07:02:01 AM UTC 24
Peak memory	213336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158594046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_scanmode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 0.rv_dm_scanmode.2158594046
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_scanmode/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/29.rv_dm_stress_all.2828708779
Short name	T333
Test name
Test status
Simulation time	11012555868 ps
CPU time	23.29 seconds
Started	Aug 27 07:02:40 AM UTC 24
Finished	Aug 27 07:03:05 AM UTC 24
Peak memory	226448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828708779 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.2828708779
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/29.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.2357565840
Short name	T2
Test name
Test status
Simulation time	200234154 ps
CPU time	1.44 seconds
Started	Aug 27 07:01:54 AM UTC 24
Finished	Aug 27 07:01:56 AM UTC 24
Peak memory	215940 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357565840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.2357565840
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_cmderr_exception/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/15.rv_dm_autoincr_sba_tl_access.973612838
Short name	T203
Test name
Test status
Simulation time	4569820713 ps
CPU time	5.32 seconds
Started	Aug 27 07:02:29 AM UTC 24
Finished	Aug 27 07:02:35 AM UTC 24
Peak memory	226488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973612838 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.973612838
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/15.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2038128062
Short name	T109
Test name
Test status
Simulation time	100521889 ps
CPU time	4.44 seconds
Started	Aug 27 07:01:23 AM UTC 24
Finished	Aug 27 07:01:29 AM UTC 24
Peak memory	229936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2038128062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_ rand_reset.2038128062
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.241188201
Short name	T25
Test name
Test status
Simulation time	2018230898 ps
CPU time	6.52 seconds
Started	Aug 27 07:02:18 AM UTC 24
Finished	Aug 27 07:02:26 AM UTC 24
Peak memory	226264 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241188201 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.241188201
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/9.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.2405941330
Short name	T54
Test name
Test status
Simulation time	479638583 ps
CPU time	3.91 seconds
Started	Aug 27 07:02:00 AM UTC 24
Finished	Aug 27 07:02:05 AM UTC 24
Peak memory	252564 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405941330 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.2405941330
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/26.rv_dm_stress_all.493249243
Short name	T16
Test name
Test status
Simulation time	3262360787 ps
CPU time	3.28 seconds
Started	Aug 27 07:02:40 AM UTC 24
Finished	Aug 27 07:02:44 AM UTC 24
Peak memory	215756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493249243 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.493249243
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/26.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1222073771
Short name	T219
Test name
Test status
Simulation time	6525652390 ps
CPU time	26.64 seconds
Started	Aug 27 07:01:28 AM UTC 24
Finished	Aug 27 07:01:56 AM UTC 24
Peak memory	232328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222073771 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.1222073771
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/12.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3381286394
Short name	T130
Test name
Test status
Simulation time	307914019 ps
CPU time	2.53 seconds
Started	Aug 27 07:00:37 AM UTC 24
Finished	Aug 27 07:00:41 AM UTC 24
Peak memory	225604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381286394 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.3381286394
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.775974078
Short name	T118
Test name
Test status
Simulation time	3507735597 ps
CPU time	4.58 seconds
Started	Aug 27 07:02:06 AM UTC 24
Finished	Aug 27 07:02:11 AM UTC 24
Peak memory	226516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775974078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.775974078
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/2.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.1227799408
Short name	T66
Test name
Test status
Simulation time	87198204 ps
CPU time	0.87 seconds
Started	Aug 27 07:01:59 AM UTC 24
Finished	Aug 27 07:02:01 AM UTC 24
Peak memory	225860 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227799408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_rom_read_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.1227799408
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_rom_read_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_ndmreset_req.2788432233
Short name	T42
Test name
Test status
Simulation time	348948345 ps
CPU time	2.38 seconds
Started	Aug 27 07:02:02 AM UTC 24
Finished	Aug 27 07:02:06 AM UTC 24
Peak memory	226176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788432233 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.2788432233
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_ndmreset_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.1324207543
Short name	T87
Test name
Test status
Simulation time	2584815410 ps
CPU time	5.78 seconds
Started	Aug 27 07:02:05 AM UTC 24
Finished	Aug 27 07:02:11 AM UTC 24
Peak memory	226440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324207543 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.1324207543
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all_with_rand_reset.693719702
Short name	T80
Test name
Test status
Simulation time	12268744661 ps
CPU time	46.6 seconds
Started	Aug 27 07:02:13 AM UTC 24
Finished	Aug 27 07:03:01 AM UTC 24
Peak memory	233260 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=693719702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress _all_with_rand_reset.693719702
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2961901294
Short name	T166
Test name
Test status
Simulation time	6737274310 ps
CPU time	74.46 seconds
Started	Aug 27 07:00:41 AM UTC 24
Finished	Aug 27 07:01:57 AM UTC 24
Peak memory	215488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961901294 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_aliasing.2961901294
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/2.rv_dm_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2011147638
Short name	T151
Test name
Test status
Simulation time	415408725 ps
CPU time	9.16 seconds
Started	Aug 27 07:01:00 AM UTC 24
Finished	Aug 27 07:01:10 AM UTC 24
Peak memory	215492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011147638 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_csr_outstanding.2011147638
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/4.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/16.rv_dm_bad_sba_tl_access.321385009
Short name	T206
Test name
Test status
Simulation time	1852886876 ps
CPU time	4.05 seconds
Started	Aug 27 07:02:30 AM UTC 24
Finished	Aug 27 07:02:35 AM UTC 24
Peak memory	226508 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321385009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.321385009
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/16.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1194513340
Short name	T224
Test name
Test status
Simulation time	2193113430 ps
CPU time	12.63 seconds
Started	Aug 27 07:01:42 AM UTC 24
Finished	Aug 27 07:01:56 AM UTC 24
Peak memory	225732 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194513340 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.1194513340
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/16.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.2829416490
Short name	T43
Test name
Test status
Simulation time	2138603897 ps
CPU time	4.05 seconds
Started	Aug 27 07:01:57 AM UTC 24
Finished	Aug 27 07:02:03 AM UTC 24
Peak memory	216076 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829416490 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.2829416490
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_sba_debug_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.1605579716
Short name	T69
Test name
Test status
Simulation time	612391276 ps
CPU time	1.54 seconds
Started	Aug 27 07:02:02 AM UTC 24
Finished	Aug 27 07:02:04 AM UTC 24
Peak memory	213408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605579716 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.1605579716
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_cmderr_halt_resume/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_intg_err.126759913
Short name	T223
Test name
Test status
Simulation time	3022522658 ps
CPU time	17.64 seconds
Started	Aug 27 07:01:51 AM UTC 24
Finished	Aug 27 07:02:10 AM UTC 24
Peak memory	229832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126759913 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.126759913
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/19.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/17.rv_dm_autoincr_sba_tl_access.243665250
Short name	T212
Test name
Test status
Simulation time	7499130518 ps
CPU time	15.06 seconds
Started	Aug 27 07:02:33 AM UTC 24
Finished	Aug 27 07:02:49 AM UTC 24
Peak memory	226480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243665250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.243665250
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/17.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.4226433155
Short name	T345
Test name
Test status
Simulation time	1132396309 ps
CPU time	3.85 seconds
Started	Aug 27 07:00:35 AM UTC 24
Finished	Aug 27 07:00:40 AM UTC 24
Peak memory	215076 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226433155 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_aliasing.4226433155
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.1398442500
Short name	T47
Test name
Test status
Simulation time	189284102 ps
CPU time	1.11 seconds
Started	Aug 27 07:01:58 AM UTC 24
Finished	Aug 27 07:02:00 AM UTC 24
Peak memory	213456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398442500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_abstractcmd_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.1398442500
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_abstractcmd_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2350693436
Short name	T142
Test name
Test status
Simulation time	10345459433 ps
CPU time	21.84 seconds
Started	Aug 27 07:00:35 AM UTC 24
Finished	Aug 27 07:00:59 AM UTC 24
Peak memory	214924 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350693436 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_hw_reset.2350693436
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3980758223
Short name	T116
Test name
Test status
Simulation time	7629472441 ps
CPU time	30.97 seconds
Started	Aug 27 07:01:08 AM UTC 24
Finished	Aug 27 07:01:40 AM UTC 24
Peak memory	229892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3980758223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_re set.3980758223
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/6.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3208932703
Short name	T278
Test name
Test status
Simulation time	13073684441 ps
CPU time	7.7 seconds
Started	Aug 27 07:02:13 AM UTC 24
Finished	Aug 27 07:02:22 AM UTC 24
Peak memory	226504 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208932703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_tl_access.3208932703
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.1824526967
Short name	T50
Test name
Test status
Simulation time	112088975 ps
CPU time	1 seconds
Started	Aug 27 07:01:59 AM UTC 24
Finished	Aug 27 07:02:01 AM UTC 24
Peak memory	225796 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824526967 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sparse_lc_gate_fsm.1824526967
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_sparse_lc_gate_fsm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/2.rv_dm_sparse_lc_gate_fsm.3428904668
Short name	T83
Test name
Test status
Simulation time	131156251 ps
CPU time	0.86 seconds
Started	Aug 27 07:02:06 AM UTC 24
Finished	Aug 27 07:02:08 AM UTC 24
Peak memory	225796 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428904668 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sparse_lc_gate_fsm.3428904668
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/2.rv_dm_sparse_lc_gate_fsm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1485441950
Short name	T348
Test name
Test status
Simulation time	157671503 ps
CPU time	3.11 seconds
Started	Aug 27 07:00:38 AM UTC 24
Finished	Aug 27 07:00:42 AM UTC 24
Peak memory	229832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1485441950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_r and_reset.1485441950
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2648784728
Short name	T441
Test name
Test status
Simulation time	8698514057 ps
CPU time	72.86 seconds
Started	Aug 27 07:00:35 AM UTC 24
Finished	Aug 27 07:01:50 AM UTC 24
Peak memory	213320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648784728 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_aliasing.2648784728
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3405368124
Short name	T167
Test name
Test status
Simulation time	13313957576 ps
CPU time	41.12 seconds
Started	Aug 27 07:00:38 AM UTC 24
Finished	Aug 27 07:01:20 AM UTC 24
Peak memory	225696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405368124 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.3405368124
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.496858076
Short name	T129
Test name
Test status
Simulation time	215778532 ps
CPU time	1.92 seconds
Started	Aug 27 07:00:37 AM UTC 24
Finished	Aug 27 07:00:41 AM UTC 24
Peak memory	228488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496858076 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.496858076
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.587057549
Short name	T482
Test name
Test status
Simulation time	105112523703 ps
CPU time	185.47 seconds
Started	Aug 27 07:00:35 AM UTC 24
Finished	Aug 27 07:03:44 AM UTC 24
Peak memory	214900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587057549 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_aliasing.587057549
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2551378559
Short name	T347
Test name
Test status
Simulation time	2155661681 ps
CPU time	4.42 seconds
Started	Aug 27 07:00:35 AM UTC 24
Finished	Aug 27 07:00:41 AM UTC 24
Peak memory	215516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551378559 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_bit_bash.2551378559
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1274969338
Short name	T346
Test name
Test status
Simulation time	3903966484 ps
CPU time	4.11 seconds
Started	Aug 27 07:00:35 AM UTC 24
Finished	Aug 27 07:00:41 AM UTC 24
Peak memory	215460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274969338 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.1274969338
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.773656141
Short name	T470
Test name
Test status
Simulation time	26874807051 ps
CPU time	91.27 seconds
Started	Aug 27 07:00:35 AM UTC 24
Finished	Aug 27 07:02:09 AM UTC 24
Peak memory	215288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773656141 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_bit_bash.773656141
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2535478125
Short name	T101
Test name
Test status
Simulation time	487821083 ps
CPU time	1.56 seconds
Started	Aug 27 07:00:35 AM UTC 24
Finished	Aug 27 07:00:38 AM UTC 24
Peak memory	212776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535478125 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_hw_reset.2535478125
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1001583521
Short name	T102
Test name
Test status
Simulation time	852237003 ps
CPU time	2.06 seconds
Started	Aug 27 07:00:35 AM UTC 24
Finished	Aug 27 07:00:39 AM UTC 24
Peak memory	215076 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001583521 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.1001583521
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.4052857698
Short name	T343
Test name
Test status
Simulation time	36066722 ps
CPU time	0.93 seconds
Started	Aug 27 07:00:37 AM UTC 24
Finished	Aug 27 07:00:40 AM UTC 24
Peak memory	215140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052857698 -assert nopostproc +UVM _TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_partial_access.4052857698
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.2117041026
Short name	T342
Test name
Test status
Simulation time	73262256 ps
CPU time	0.8 seconds
Started	Aug 27 07:00:37 AM UTC 24
Finished	Aug 27 07:00:39 AM UTC 24
Peak memory	215140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117041026 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.2117041026
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1209915906
Short name	T133
Test name
Test status
Simulation time	385103537 ps
CPU time	7.49 seconds
Started	Aug 27 07:00:38 AM UTC 24
Finished	Aug 27 07:00:46 AM UTC 24
Peak memory	215124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209915906 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_csr_outstanding.1209915906
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3884850844
Short name	T112
Test name
Test status
Simulation time	6230692190 ps
CPU time	30.97 seconds
Started	Aug 27 07:00:37 AM UTC 24
Finished	Aug 27 07:01:10 AM UTC 24
Peak memory	229964 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3884850844 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_re set.3884850844
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.2036603005
Short name	T352
Test name
Test status
Simulation time	968628909 ps
CPU time	4.83 seconds
Started	Aug 27 07:00:37 AM UTC 24
Finished	Aug 27 07:00:43 AM UTC 24
Peak memory	225808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036603005 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.2036603005
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1931454614
Short name	T168
Test name
Test status
Simulation time	1993057443 ps
CPU time	65.8 seconds
Started	Aug 27 07:00:38 AM UTC 24
Finished	Aug 27 07:01:45 AM UTC 24
Peak memory	229700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931454614 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_aliasing.1931454614
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1034906620
Short name	T172
Test name
Test status
Simulation time	2969532670 ps
CPU time	27.07 seconds
Started	Aug 27 07:00:41 AM UTC 24
Finished	Aug 27 07:01:09 AM UTC 24
Peak memory	225596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034906620 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.1034906620
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2382347485
Short name	T131
Test name
Test status
Simulation time	177719939 ps
CPU time	1.87 seconds
Started	Aug 27 07:00:41 AM UTC 24
Finished	Aug 27 07:00:44 AM UTC 24
Peak memory	225200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382347485 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2382347485
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3648104625
Short name	T106
Test name
Test status
Simulation time	150497250 ps
CPU time	3.45 seconds
Started	Aug 27 07:00:41 AM UTC 24
Finished	Aug 27 07:00:46 AM UTC 24
Peak memory	225744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3648104625 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_r and_reset.3648104625
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.3761453816
Short name	T132
Test name
Test status
Simulation time	106666689 ps
CPU time	2.11 seconds
Started	Aug 27 07:00:41 AM UTC 24
Finished	Aug 27 07:00:44 AM UTC 24
Peak memory	225680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761453816 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.3761453816
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.79578182
Short name	T399
Test name
Test status
Simulation time	27829613756 ps
CPU time	37.94 seconds
Started	Aug 27 07:00:41 AM UTC 24
Finished	Aug 27 07:01:20 AM UTC 24
Peak memory	215428 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79578182 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_aliasing.79578182
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.331655417
Short name	T373
Test name
Test status
Simulation time	23382457992 ps
CPU time	15.24 seconds
Started	Aug 27 07:00:41 AM UTC 24
Finished	Aug 27 07:00:57 AM UTC 24
Peak memory	215360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331655417 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_bit_bash.331655417
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1521862009
Short name	T364
Test name
Test status
Simulation time	5758850722 ps
CPU time	9.97 seconds
Started	Aug 27 07:00:41 AM UTC 24
Finished	Aug 27 07:00:52 AM UTC 24
Peak memory	215288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521862009 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_hw_reset.1521862009
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1693013507
Short name	T361
Test name
Test status
Simulation time	2928484788 ps
CPU time	7.75 seconds
Started	Aug 27 07:00:41 AM UTC 24
Finished	Aug 27 07:00:49 AM UTC 24
Peak memory	215404 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693013507 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.1693013507
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2560843808
Short name	T349
Test name
Test status
Simulation time	207402591 ps
CPU time	1.16 seconds
Started	Aug 27 07:00:41 AM UTC 24
Finished	Aug 27 07:00:43 AM UTC 24
Peak memory	215084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560843808 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_aliasing.2560843808
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3639665640
Short name	T363
Test name
Test status
Simulation time	40475824281 ps
CPU time	28.94 seconds
Started	Aug 27 07:00:38 AM UTC 24
Finished	Aug 27 07:01:08 AM UTC 24
Peak memory	215392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639665640 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_bit_bash.3639665640
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1339806317
Short name	T103
Test name
Test status
Simulation time	561243850 ps
CPU time	1.24 seconds
Started	Aug 27 07:00:38 AM UTC 24
Finished	Aug 27 07:00:40 AM UTC 24
Peak memory	215144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339806317 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_hw_reset.1339806317
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3289290552
Short name	T344
Test name
Test status
Simulation time	425437575 ps
CPU time	1.43 seconds
Started	Aug 27 07:00:38 AM UTC 24
Finished	Aug 27 07:00:40 AM UTC 24
Peak memory	215084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289290552 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.3289290552
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1753549292
Short name	T351
Test name
Test status
Simulation time	125261642 ps
CPU time	1.13 seconds
Started	Aug 27 07:00:41 AM UTC 24
Finished	Aug 27 07:00:43 AM UTC 24
Peak memory	215140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753549292 -assert nopostproc +UVM _TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_partial_access.1753549292
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.4289892775
Short name	T350
Test name
Test status
Simulation time	76884728 ps
CPU time	1.14 seconds
Started	Aug 27 07:00:41 AM UTC 24
Finished	Aug 27 07:00:43 AM UTC 24
Peak memory	215080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289892775 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.4289892775
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.4005801584
Short name	T136
Test name
Test status
Simulation time	3276585197 ps
CPU time	8.14 seconds
Started	Aug 27 07:00:41 AM UTC 24
Finished	Aug 27 07:00:50 AM UTC 24
Peak memory	215404 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005801584 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_csr_outstanding.4005801584
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.567741229
Short name	T463
Test name
Test status
Simulation time	17109203183 ps
CPU time	77.79 seconds
Started	Aug 27 07:00:41 AM UTC 24
Finished	Aug 27 07:02:00 AM UTC 24
Peak memory	230020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=567741229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.567741229
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.2224596303
Short name	T357
Test name
Test status
Simulation time	1162675575 ps
CPU time	5.72 seconds
Started	Aug 27 07:00:41 AM UTC 24
Finished	Aug 27 07:00:48 AM UTC 24
Peak memory	225824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224596303 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.2224596303
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1242561675
Short name	T195
Test name
Test status
Simulation time	2481598554 ps
CPU time	14.46 seconds
Started	Aug 27 07:00:41 AM UTC 24
Finished	Aug 27 07:00:56 AM UTC 24
Peak memory	225836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242561675 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.1242561675
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.1632447764
Short name	T163
Test name
Test status
Simulation time	143604161 ps
CPU time	2.05 seconds
Started	Aug 27 07:01:22 AM UTC 24
Finished	Aug 27 07:01:26 AM UTC 24
Peak memory	225640 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632447764 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.1632447764
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/10.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2311787718
Short name	T417
Test name
Test status
Simulation time	2816627198 ps
CPU time	13.58 seconds
Started	Aug 27 07:01:21 AM UTC 24
Finished	Aug 27 07:01:36 AM UTC 24
Peak memory	215368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311787718 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_bit_bash.2311787718
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2350267161
Short name	T424
Test name
Test status
Simulation time	5711318249 ps
CPU time	18.34 seconds
Started	Aug 27 07:01:21 AM UTC 24
Finished	Aug 27 07:01:41 AM UTC 24
Peak memory	215288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350267161 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.2350267161
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/10.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1786860245
Short name	T405
Test name
Test status
Simulation time	1011557917 ps
CPU time	2.52 seconds
Started	Aug 27 07:01:21 AM UTC 24
Finished	Aug 27 07:01:25 AM UTC 24
Peak memory	215140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786860245 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.1786860245
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/10.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.50987588
Short name	T152
Test name
Test status
Simulation time	101934673 ps
CPU time	3.98 seconds
Started	Aug 27 07:01:22 AM UTC 24
Finished	Aug 27 07:01:28 AM UTC 24
Peak memory	215392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50987588 -assert nopostproc +UVM _TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_csr_outstanding.50987588
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/10.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.704327933
Short name	T409
Test name
Test status
Simulation time	355141392 ps
CPU time	4.38 seconds
Started	Aug 27 07:01:21 AM UTC 24
Finished	Aug 27 07:01:27 AM UTC 24
Peak memory	225660 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704327933 -assert nopostproc +UVM_TESTNAME=rv_dm_base _test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.704327933
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/10.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_intg_err.4262377451
Short name	T215
Test name
Test status
Simulation time	4503587863 ps
CPU time	8.94 seconds
Started	Aug 27 07:01:22 AM UTC 24
Finished	Aug 27 07:01:33 AM UTC 24
Peak memory	225820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262377451 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.4262377451
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/10.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1035366334
Short name	T411
Test name
Test status
Simulation time	250766419 ps
CPU time	4.72 seconds
Started	Aug 27 07:01:26 AM UTC 24
Finished	Aug 27 07:01:31 AM UTC 24
Peak memory	230000 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1035366334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_ rand_reset.1035366334
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_rw.2762164362
Short name	T164
Test name
Test status
Simulation time	66487148 ps
CPU time	1.76 seconds
Started	Aug 27 07:01:26 AM UTC 24
Finished	Aug 27 07:01:28 AM UTC 24
Peak memory	225020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762164362 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.2762164362
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/11.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.61844497
Short name	T472
Test name
Test status
Simulation time	18748111892 ps
CPU time	45.96 seconds
Started	Aug 27 07:01:24 AM UTC 24
Finished	Aug 27 07:02:12 AM UTC 24
Peak memory	215528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61844497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_bit_bash.61844497
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3358173655
Short name	T449
Test name
Test status
Simulation time	5345204808 ps
CPU time	27.43 seconds
Started	Aug 27 07:01:24 AM UTC 24
Finished	Aug 27 07:01:53 AM UTC 24
Peak memory	215428 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358173655 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.3358173655
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/11.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3036477873
Short name	T408
Test name
Test status
Simulation time	254096163 ps
CPU time	2.42 seconds
Started	Aug 27 07:01:23 AM UTC 24
Finished	Aug 27 07:01:27 AM UTC 24
Peak memory	215072 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036477873 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.3036477873
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/11.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1103027019
Short name	T412
Test name
Test status
Simulation time	714121932 ps
CPU time	6.09 seconds
Started	Aug 27 07:01:26 AM UTC 24
Finished	Aug 27 07:01:33 AM UTC 24
Peak memory	215328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103027019 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_csr_outstanding.1103027019
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/11.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_errors.1449277054
Short name	T413
Test name
Test status
Simulation time	601438571 ps
CPU time	7.95 seconds
Started	Aug 27 07:01:24 AM UTC 24
Finished	Aug 27 07:01:34 AM UTC 24
Peak memory	225660 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449277054 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.1449277054
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/11.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2903506758
Short name	T216
Test name
Test status
Simulation time	2109171420 ps
CPU time	8.01 seconds
Started	Aug 27 07:01:24 AM UTC 24
Finished	Aug 27 07:01:34 AM UTC 24
Peak memory	225760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903506758 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.2903506758
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/11.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.118283615
Short name	T416
Test name
Test status
Simulation time	247870917 ps
CPU time	4.45 seconds
Started	Aug 27 07:01:30 AM UTC 24
Finished	Aug 27 07:01:36 AM UTC 24
Peak memory	231952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=118283615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_r and_reset.118283615
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_rw.1536085322
Short name	T153
Test name
Test status
Simulation time	141319745 ps
CPU time	2.71 seconds
Started	Aug 27 07:01:29 AM UTC 24
Finished	Aug 27 07:01:33 AM UTC 24
Peak memory	225608 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536085322 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.1536085322
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/12.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.3140651381
Short name	T458
Test name
Test status
Simulation time	21795065800 ps
CPU time	29.7 seconds
Started	Aug 27 07:01:27 AM UTC 24
Finished	Aug 27 07:01:58 AM UTC 24
Peak memory	215432 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140651381 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_bit_bash.3140651381
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.244220507
Short name	T439
Test name
Test status
Simulation time	13732130917 ps
CPU time	21.33 seconds
Started	Aug 27 07:01:27 AM UTC 24
Finished	Aug 27 07:01:50 AM UTC 24
Peak memory	215428 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244220507 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.244220507
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/12.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2425640751
Short name	T410
Test name
Test status
Simulation time	651045840 ps
CPU time	2.83 seconds
Started	Aug 27 07:01:26 AM UTC 24
Finished	Aug 27 07:01:30 AM UTC 24
Peak memory	215140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425640751 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.2425640751
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/12.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3830747841
Short name	T155
Test name
Test status
Simulation time	136465214 ps
CPU time	5.64 seconds
Started	Aug 27 07:01:29 AM UTC 24
Finished	Aug 27 07:01:36 AM UTC 24
Peak memory	215436 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830747841 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same_csr_outstanding.3830747841
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/12.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_errors.2560143294
Short name	T414
Test name
Test status
Simulation time	297015158 ps
CPU time	4.79 seconds
Started	Aug 27 07:01:28 AM UTC 24
Finished	Aug 27 07:01:34 AM UTC 24
Peak memory	227788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560143294 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.2560143294
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/12.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2054635064
Short name	T108
Test name
Test status
Simulation time	257343075 ps
CPU time	4.83 seconds
Started	Aug 27 07:01:35 AM UTC 24
Finished	Aug 27 07:01:41 AM UTC 24
Peak memory	232256 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2054635064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_ rand_reset.2054635064
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_rw.2572931764
Short name	T165
Test name
Test status
Simulation time	119042860 ps
CPU time	1.8 seconds
Started	Aug 27 07:01:33 AM UTC 24
Finished	Aug 27 07:01:36 AM UTC 24
Peak memory	229236 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572931764 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.2572931764
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/13.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.1326396007
Short name	T406
Test name
Test status
Simulation time	12343886889 ps
CPU time	12.99 seconds
Started	Aug 27 07:01:32 AM UTC 24
Finished	Aug 27 07:01:46 AM UTC 24
Peak memory	215460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326396007 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_bit_bash.1326396007
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1390970960
Short name	T419
Test name
Test status
Simulation time	1092315312 ps
CPU time	6.77 seconds
Started	Aug 27 07:01:31 AM UTC 24
Finished	Aug 27 07:01:39 AM UTC 24
Peak memory	215296 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390970960 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.1390970960
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/13.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1018871253
Short name	T415
Test name
Test status
Simulation time	368868066 ps
CPU time	3.07 seconds
Started	Aug 27 07:01:30 AM UTC 24
Finished	Aug 27 07:01:34 AM UTC 24
Peak memory	215076 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018871253 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.1018871253
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/13.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3770205648
Short name	T429
Test name
Test status
Simulation time	570333371 ps
CPU time	7.76 seconds
Started	Aug 27 07:01:35 AM UTC 24
Finished	Aug 27 07:01:44 AM UTC 24
Peak memory	215412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770205648 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_csr_outstanding.3770205648
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/13.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_errors.1173297937
Short name	T420
Test name
Test status
Simulation time	703497414 ps
CPU time	5.22 seconds
Started	Aug 27 07:01:33 AM UTC 24
Finished	Aug 27 07:01:40 AM UTC 24
Peak memory	225856 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173297937 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.1173297937
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/13.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_intg_err.983365067
Short name	T461
Test name
Test status
Simulation time	1629544306 ps
CPU time	25.05 seconds
Started	Aug 27 07:01:33 AM UTC 24
Finished	Aug 27 07:02:00 AM UTC 24
Peak memory	225732 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983365067 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.983365067
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/13.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1585301612
Short name	T425
Test name
Test status
Simulation time	117926143 ps
CPU time	3.29 seconds
Started	Aug 27 07:01:36 AM UTC 24
Finished	Aug 27 07:01:41 AM UTC 24
Peak memory	225876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1585301612 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_ rand_reset.1585301612
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_rw.1528864523
Short name	T156
Test name
Test status
Simulation time	98432682 ps
CPU time	2.26 seconds
Started	Aug 27 07:01:36 AM UTC 24
Finished	Aug 27 07:01:40 AM UTC 24
Peak memory	225536 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528864523 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.1528864523
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/14.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3961941702
Short name	T467
Test name
Test status
Simulation time	16642870489 ps
CPU time	30.57 seconds
Started	Aug 27 07:01:35 AM UTC 24
Finished	Aug 27 07:02:07 AM UTC 24
Peak memory	215460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961941702 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_bit_bash.3961941702
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1120330415
Short name	T422
Test name
Test status
Simulation time	3250536150 ps
CPU time	3.5 seconds
Started	Aug 27 07:01:35 AM UTC 24
Finished	Aug 27 07:01:40 AM UTC 24
Peak memory	215288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120330415 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.1120330415
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/14.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.3739010247
Short name	T418
Test name
Test status
Simulation time	256724493 ps
CPU time	1.24 seconds
Started	Aug 27 07:01:35 AM UTC 24
Finished	Aug 27 07:01:38 AM UTC 24
Peak memory	215056 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739010247 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.3739010247
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/14.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.684742179
Short name	T157
Test name
Test status
Simulation time	380700575 ps
CPU time	7.9 seconds
Started	Aug 27 07:01:36 AM UTC 24
Finished	Aug 27 07:01:46 AM UTC 24
Peak memory	215424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684742179 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same_csr_outstanding.684742179
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/14.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_errors.1912739668
Short name	T428
Test name
Test status
Simulation time	117537807 ps
CPU time	5.87 seconds
Started	Aug 27 07:01:35 AM UTC 24
Finished	Aug 27 07:01:43 AM UTC 24
Peak memory	225724 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912739668 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.1912739668
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/14.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1410901145
Short name	T222
Test name
Test status
Simulation time	1477300045 ps
CPU time	12.27 seconds
Started	Aug 27 07:01:35 AM UTC 24
Finished	Aug 27 07:01:49 AM UTC 24
Peak memory	225792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410901145 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.1410901145
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/14.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2828129409
Short name	T114
Test name
Test status
Simulation time	97000450 ps
CPU time	4.22 seconds
Started	Aug 27 07:01:41 AM UTC 24
Finished	Aug 27 07:01:46 AM UTC 24
Peak memory	231852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2828129409 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_ rand_reset.2828129409
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_rw.2666775046
Short name	T431
Test name
Test status
Simulation time	333305222 ps
CPU time	2.7 seconds
Started	Aug 27 07:01:41 AM UTC 24
Finished	Aug 27 07:01:45 AM UTC 24
Peak memory	231844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666775046 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.2666775046
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/15.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.1174458830
Short name	T477
Test name
Test status
Simulation time	14858502092 ps
CPU time	46.38 seconds
Started	Aug 27 07:01:39 AM UTC 24
Finished	Aug 27 07:02:27 AM UTC 24
Peak memory	215460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174458830 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_bit_bash.1174458830
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.4093849084
Short name	T465
Test name
Test status
Simulation time	9008147672 ps
CPU time	26.54 seconds
Started	Aug 27 07:01:38 AM UTC 24
Finished	Aug 27 07:02:05 AM UTC 24
Peak memory	215360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093849084 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.4093849084
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/15.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2201327893
Short name	T421
Test name
Test status
Simulation time	388945822 ps
CPU time	1.39 seconds
Started	Aug 27 07:01:38 AM UTC 24
Finished	Aug 27 07:01:40 AM UTC 24
Peak memory	215140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201327893 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.2201327893
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/15.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3070086401
Short name	T158
Test name
Test status
Simulation time	869384275 ps
CPU time	5.74 seconds
Started	Aug 27 07:01:41 AM UTC 24
Finished	Aug 27 07:01:48 AM UTC 24
Peak memory	215552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070086401 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_csr_outstanding.3070086401
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/15.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_errors.2519377650
Short name	T426
Test name
Test status
Simulation time	344214517 ps
CPU time	5.86 seconds
Started	Aug 27 07:01:40 AM UTC 24
Finished	Aug 27 07:01:47 AM UTC 24
Peak memory	225732 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519377650 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.2519377650
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/15.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_intg_err.69772213
Short name	T464
Test name
Test status
Simulation time	14264119429 ps
CPU time	21.11 seconds
Started	Aug 27 07:01:41 AM UTC 24
Finished	Aug 27 07:02:03 AM UTC 24
Peak memory	225664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69772213 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.69772213
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/15.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1318904622
Short name	T436
Test name
Test status
Simulation time	267009203 ps
CPU time	2.4 seconds
Started	Aug 27 07:01:43 AM UTC 24
Finished	Aug 27 07:01:47 AM UTC 24
Peak memory	227864 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1318904622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_ rand_reset.1318904622
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_rw.3374822249
Short name	T433
Test name
Test status
Simulation time	913358313 ps
CPU time	2.12 seconds
Started	Aug 27 07:01:42 AM UTC 24
Finished	Aug 27 07:01:46 AM UTC 24
Peak memory	225676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374822249 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.3374822249
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/16.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1230666884
Short name	T437
Test name
Test status
Simulation time	2838478453 ps
CPU time	3.34 seconds
Started	Aug 27 07:01:42 AM UTC 24
Finished	Aug 27 07:01:47 AM UTC 24
Peak memory	215388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230666884 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_bit_bash.1230666884
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.4051641340
Short name	T435
Test name
Test status
Simulation time	3486133816 ps
CPU time	6.26 seconds
Started	Aug 27 07:01:41 AM UTC 24
Finished	Aug 27 07:01:49 AM UTC 24
Peak memory	215392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051641340 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.4051641340
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/16.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3659646759
Short name	T430
Test name
Test status
Simulation time	376864867 ps
CPU time	2.25 seconds
Started	Aug 27 07:01:41 AM UTC 24
Finished	Aug 27 07:01:45 AM UTC 24
Peak memory	215304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659646759 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.3659646759
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/16.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1851410822
Short name	T442
Test name
Test status
Simulation time	623549114 ps
CPU time	6.82 seconds
Started	Aug 27 07:01:43 AM UTC 24
Finished	Aug 27 07:01:51 AM UTC 24
Peak memory	215500 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851410822 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_csr_outstanding.1851410822
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/16.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_errors.1272483340
Short name	T434
Test name
Test status
Simulation time	298032368 ps
CPU time	2.4 seconds
Started	Aug 27 07:01:42 AM UTC 24
Finished	Aug 27 07:01:46 AM UTC 24
Peak memory	225824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272483340 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.1272483340
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/16.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2435525707
Short name	T450
Test name
Test status
Simulation time	177667687 ps
CPU time	4.95 seconds
Started	Aug 27 07:01:47 AM UTC 24
Finished	Aug 27 07:01:53 AM UTC 24
Peak memory	229844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2435525707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_ rand_reset.2435525707
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_rw.345985354
Short name	T443
Test name
Test status
Simulation time	368817929 ps
CPU time	3.28 seconds
Started	Aug 27 07:01:47 AM UTC 24
Finished	Aug 27 07:01:52 AM UTC 24
Peak memory	225672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345985354 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.345985354
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/17.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3839971039
Short name	T483
Test name
Test status
Simulation time	53286573611 ps
CPU time	163.79 seconds
Started	Aug 27 07:01:45 AM UTC 24
Finished	Aug 27 07:04:32 AM UTC 24
Peak memory	215368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839971039 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_bit_bash.3839971039
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3842955352
Short name	T446
Test name
Test status
Simulation time	6079975284 ps
CPU time	5.48 seconds
Started	Aug 27 07:01:45 AM UTC 24
Finished	Aug 27 07:01:52 AM UTC 24
Peak memory	215360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842955352 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.3842955352
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/17.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2232466845
Short name	T438
Test name
Test status
Simulation time	373241616 ps
CPU time	2.89 seconds
Started	Aug 27 07:01:45 AM UTC 24
Finished	Aug 27 07:01:49 AM UTC 24
Peak memory	215208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232466845 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.2232466845
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/17.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.4115981239
Short name	T455
Test name
Test status
Simulation time	337199099 ps
CPU time	7.66 seconds
Started	Aug 27 07:01:47 AM UTC 24
Finished	Aug 27 07:01:56 AM UTC 24
Peak memory	215428 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115981239 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same_csr_outstanding.4115981239
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/17.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_errors.296103925
Short name	T445
Test name
Test status
Simulation time	126477320 ps
CPU time	3.74 seconds
Started	Aug 27 07:01:47 AM UTC 24
Finished	Aug 27 07:01:52 AM UTC 24
Peak memory	225848 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296103925 -assert nopostproc +UVM_TESTNAME=rv_dm_base _test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.296103925
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/17.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.1147953173
Short name	T225
Test name
Test status
Simulation time	6421296768 ps
CPU time	16.39 seconds
Started	Aug 27 07:01:47 AM UTC 24
Finished	Aug 27 07:02:05 AM UTC 24
Peak memory	227820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147953173 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.1147953173
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/17.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1323108401
Short name	T451
Test name
Test status
Simulation time	120651708 ps
CPU time	3.35 seconds
Started	Aug 27 07:01:50 AM UTC 24
Finished	Aug 27 07:01:54 AM UTC 24
Peak memory	232048 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1323108401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_ rand_reset.1323108401
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_rw.4250573960
Short name	T444
Test name
Test status
Simulation time	144885824 ps
CPU time	3.4 seconds
Started	Aug 27 07:01:48 AM UTC 24
Finished	Aug 27 07:01:52 AM UTC 24
Peak memory	225628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250573960 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.4250573960
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/18.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.709314590
Short name	T469
Test name
Test status
Simulation time	20045112778 ps
CPU time	19.75 seconds
Started	Aug 27 07:01:48 AM UTC 24
Finished	Aug 27 07:02:08 AM UTC 24
Peak memory	215364 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709314590 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_bit_bash.709314590
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.362104244
Short name	T456
Test name
Test status
Simulation time	5152332810 ps
CPU time	7.6 seconds
Started	Aug 27 07:01:47 AM UTC 24
Finished	Aug 27 07:01:57 AM UTC 24
Peak memory	215432 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362104244 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.362104244
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/18.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.786055080
Short name	T440
Test name
Test status
Simulation time	278197839 ps
CPU time	1.27 seconds
Started	Aug 27 07:01:47 AM UTC 24
Finished	Aug 27 07:01:50 AM UTC 24
Peak memory	215084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786055080 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.786055080
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/18.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3327252910
Short name	T460
Test name
Test status
Simulation time	598129982 ps
CPU time	9.41 seconds
Started	Aug 27 07:01:49 AM UTC 24
Finished	Aug 27 07:01:59 AM UTC 24
Peak memory	215520 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327252910 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same_csr_outstanding.3327252910
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/18.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_errors.874396923
Short name	T448
Test name
Test status
Simulation time	174833498 ps
CPU time	4.35 seconds
Started	Aug 27 07:01:48 AM UTC 24
Finished	Aug 27 07:01:53 AM UTC 24
Peak memory	225816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874396923 -assert nopostproc +UVM_TESTNAME=rv_dm_base _test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.874396923
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/18.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3529565107
Short name	T466
Test name
Test status
Simulation time	10268935574 ps
CPU time	18.43 seconds
Started	Aug 27 07:01:48 AM UTC 24
Finished	Aug 27 07:02:07 AM UTC 24
Peak memory	227768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529565107 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3529565107
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/18.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2919914797
Short name	T110
Test name
Test status
Simulation time	246730897 ps
CPU time	2.98 seconds
Started	Aug 27 07:01:53 AM UTC 24
Finished	Aug 27 07:01:57 AM UTC 24
Peak memory	227920 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2919914797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_ rand_reset.2919914797
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_rw.361297508
Short name	T453
Test name
Test status
Simulation time	340506466 ps
CPU time	2.42 seconds
Started	Aug 27 07:01:51 AM UTC 24
Finished	Aug 27 07:01:54 AM UTC 24
Peak memory	225568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361297508 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.361297508
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/19.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.3741087559
Short name	T473
Test name
Test status
Simulation time	21421940355 ps
CPU time	21.3 seconds
Started	Aug 27 07:01:51 AM UTC 24
Finished	Aug 27 07:02:13 AM UTC 24
Peak memory	215136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741087559 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_bit_bash.3741087559
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1109599324
Short name	T452
Test name
Test status
Simulation time	1517154458 ps
CPU time	3.71 seconds
Started	Aug 27 07:01:50 AM UTC 24
Finished	Aug 27 07:01:54 AM UTC 24
Peak memory	215296 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109599324 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.1109599324
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/19.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.739826581
Short name	T447
Test name
Test status
Simulation time	389000834 ps
CPU time	2.06 seconds
Started	Aug 27 07:01:50 AM UTC 24
Finished	Aug 27 07:01:53 AM UTC 24
Peak memory	215216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739826581 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.739826581
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/19.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.995867163
Short name	T457
Test name
Test status
Simulation time	240575950 ps
CPU time	4.46 seconds
Started	Aug 27 07:01:53 AM UTC 24
Finished	Aug 27 07:01:58 AM UTC 24
Peak memory	215424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995867163 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_csr_outstanding.995867163
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/19.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_errors.2970284520
Short name	T454
Test name
Test status
Simulation time	77215127 ps
CPU time	2.68 seconds
Started	Aug 27 07:01:51 AM UTC 24
Finished	Aug 27 07:01:55 AM UTC 24
Peak memory	225856 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970284520 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.2970284520
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/19.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.848285376
Short name	T401
Test name
Test status
Simulation time	8366600926 ps
CPU time	35.59 seconds
Started	Aug 27 07:00:45 AM UTC 24
Finished	Aug 27 07:01:22 AM UTC 24
Peak memory	225704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848285376 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.848285376
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/2.rv_dm_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1872736669
Short name	T134
Test name
Test status
Simulation time	454841227 ps
CPU time	1.98 seconds
Started	Aug 27 07:00:45 AM UTC 24
Finished	Aug 27 07:00:48 AM UTC 24
Peak memory	225200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872736669 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.1872736669
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/2.rv_dm_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1596170573
Short name	T178
Test name
Test status
Simulation time	153527712 ps
CPU time	1.82 seconds
Started	Aug 27 07:00:46 AM UTC 24
Finished	Aug 27 07:00:49 AM UTC 24
Peak memory	227196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1596170573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_r and_reset.1596170573
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_rw.158472827
Short name	T135
Test name
Test status
Simulation time	53251400 ps
CPU time	3.14 seconds
Started	Aug 27 07:00:45 AM UTC 24
Finished	Aug 27 07:00:49 AM UTC 24
Peak memory	225728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158472827 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.158472827
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/2.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.416746301
Short name	T481
Test name
Test status
Simulation time	56402795047 ps
CPU time	169.76 seconds
Started	Aug 27 07:00:43 AM UTC 24
Finished	Aug 27 07:03:35 AM UTC 24
Peak memory	215420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416746301 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_aliasing.416746301
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2406843739
Short name	T476
Test name
Test status
Simulation time	33510288949 ps
CPU time	100.84 seconds
Started	Aug 27 07:00:43 AM UTC 24
Finished	Aug 27 07:02:25 AM UTC 24
Peak memory	215424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406843739 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_bit_bash.2406843739
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.340948998
Short name	T145
Test name
Test status
Simulation time	17495648445 ps
CPU time	26.07 seconds
Started	Aug 27 07:00:42 AM UTC 24
Finished	Aug 27 07:01:10 AM UTC 24
Peak memory	215388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340948998 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_hw_reset.340948998
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.2297239451
Short name	T376
Test name
Test status
Simulation time	4924113804 ps
CPU time	15.24 seconds
Started	Aug 27 07:00:43 AM UTC 24
Finished	Aug 27 07:00:59 AM UTC 24
Peak memory	215432 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297239451 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.2297239451
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1155706442
Short name	T358
Test name
Test status
Simulation time	2625243856 ps
CPU time	4.31 seconds
Started	Aug 27 07:00:42 AM UTC 24
Finished	Aug 27 07:00:48 AM UTC 24
Peak memory	215140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155706442 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_aliasing.1155706442
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3097535038
Short name	T402
Test name
Test status
Simulation time	8833778781 ps
CPU time	39.06 seconds
Started	Aug 27 07:00:42 AM UTC 24
Finished	Aug 27 07:01:23 AM UTC 24
Peak memory	215396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097535038 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_bit_bash.3097535038
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2263035032
Short name	T353
Test name
Test status
Simulation time	343224618 ps
CPU time	1.57 seconds
Started	Aug 27 07:00:41 AM UTC 24
Finished	Aug 27 07:00:44 AM UTC 24
Peak memory	215092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263035032 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_hw_reset.2263035032
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.150361253
Short name	T354
Test name
Test status
Simulation time	376434966 ps
CPU time	2.02 seconds
Started	Aug 27 07:00:42 AM UTC 24
Finished	Aug 27 07:00:45 AM UTC 24
Peak memory	215204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150361253 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.150361253
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2187870676
Short name	T355
Test name
Test status
Simulation time	42475669 ps
CPU time	0.93 seconds
Started	Aug 27 07:00:44 AM UTC 24
Finished	Aug 27 07:00:46 AM UTC 24
Peak memory	215140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187870676 -assert nopostproc +UVM _TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_partial_access.2187870676
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/2.rv_dm_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_walk.1233452442
Short name	T356
Test name
Test status
Simulation time	35379461 ps
CPU time	1.02 seconds
Started	Aug 27 07:00:44 AM UTC 24
Finished	Aug 27 07:00:46 AM UTC 24
Peak memory	215140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233452442 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.1233452442
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/2.rv_dm_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.968911893
Short name	T137
Test name
Test status
Simulation time	308623540 ps
CPU time	5.24 seconds
Started	Aug 27 07:00:46 AM UTC 24
Finished	Aug 27 07:00:53 AM UTC 24
Peak memory	215428 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968911893 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_csr_outstanding.968911893
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/2.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2303159360
Short name	T113
Test name
Test status
Simulation time	4798982451 ps
CPU time	56.63 seconds
Started	Aug 27 07:00:44 AM UTC 24
Finished	Aug 27 07:01:42 AM UTC 24
Peak memory	229884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2303159360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_re set.2303159360
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/2.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_errors.3387012192
Short name	T359
Test name
Test status
Simulation time	154507792 ps
CPU time	3.62 seconds
Started	Aug 27 07:00:44 AM UTC 24
Finished	Aug 27 07:00:48 AM UTC 24
Peak memory	225824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387012192 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.3387012192
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/2.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.212047561
Short name	T179
Test name
Test status
Simulation time	1641050010 ps
CPU time	10.64 seconds
Started	Aug 27 07:00:44 AM UTC 24
Finished	Aug 27 07:00:56 AM UTC 24
Peak memory	232432 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212047561 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.212047561
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/2.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1458610267
Short name	T462
Test name
Test status
Simulation time	17041368831 ps
CPU time	71.86 seconds
Started	Aug 27 07:00:46 AM UTC 24
Finished	Aug 27 07:02:00 AM UTC 24
Peak memory	225760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458610267 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_aliasing.1458610267
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/3.rv_dm_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.95471616
Short name	T475
Test name
Test status
Simulation time	25287919233 ps
CPU time	88.5 seconds
Started	Aug 27 07:00:52 AM UTC 24
Finished	Aug 27 07:02:22 AM UTC 24
Peak memory	225708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95471616 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.95471616
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/3.rv_dm_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3580308640
Short name	T138
Test name
Test status
Simulation time	163805669 ps
CPU time	2.29 seconds
Started	Aug 27 07:00:50 AM UTC 24
Finished	Aug 27 07:00:53 AM UTC 24
Peak memory	225604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580308640 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.3580308640
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/3.rv_dm_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.671195507
Short name	T372
Test name
Test status
Simulation time	146850457 ps
CPU time	2.88 seconds
Started	Aug 27 07:00:53 AM UTC 24
Finished	Aug 27 07:00:57 AM UTC 24
Peak memory	225800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=671195507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_ra nd_reset.671195507
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_rw.3770218897
Short name	T146
Test name
Test status
Simulation time	88233876 ps
CPU time	3.06 seconds
Started	Aug 27 07:00:50 AM UTC 24
Finished	Aug 27 07:00:54 AM UTC 24
Peak memory	231844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770218897 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.3770218897
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/3.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2822599578
Short name	T478
Test name
Test status
Simulation time	33682037397 ps
CPU time	97.95 seconds
Started	Aug 27 07:00:50 AM UTC 24
Finished	Aug 27 07:02:30 AM UTC 24
Peak memory	215420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822599578 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_aliasing.2822599578
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2053867191
Short name	T383
Test name
Test status
Simulation time	15775990667 ps
CPU time	17.19 seconds
Started	Aug 27 07:00:50 AM UTC 24
Finished	Aug 27 07:01:08 AM UTC 24
Peak memory	215488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053867191 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_bit_bash.2053867191
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1043924237
Short name	T143
Test name
Test status
Simulation time	4351021748 ps
CPU time	17.53 seconds
Started	Aug 27 07:00:48 AM UTC 24
Finished	Aug 27 07:01:07 AM UTC 24
Peak memory	215524 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043924237 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_hw_reset.1043924237
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.619204271
Short name	T384
Test name
Test status
Simulation time	7107529422 ps
CPU time	20.16 seconds
Started	Aug 27 07:00:48 AM UTC 24
Finished	Aug 27 07:01:09 AM UTC 24
Peak memory	215356 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619204271 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.619204271
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.540540781
Short name	T368
Test name
Test status
Simulation time	623707527 ps
CPU time	5.13 seconds
Started	Aug 27 07:00:48 AM UTC 24
Finished	Aug 27 07:00:54 AM UTC 24
Peak memory	215208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540540781 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_aliasing.540540781
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.4255288955
Short name	T393
Test name
Test status
Simulation time	20581147990 ps
CPU time	27.23 seconds
Started	Aug 27 07:00:48 AM UTC 24
Finished	Aug 27 07:01:16 AM UTC 24
Peak memory	215292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255288955 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_bit_bash.4255288955
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1812439721
Short name	T360
Test name
Test status
Simulation time	208807575 ps
CPU time	1.14 seconds
Started	Aug 27 07:00:46 AM UTC 24
Finished	Aug 27 07:00:49 AM UTC 24
Peak memory	215144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812439721 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_hw_reset.1812439721
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1734098604
Short name	T362
Test name
Test status
Simulation time	421594427 ps
CPU time	1.94 seconds
Started	Aug 27 07:00:46 AM UTC 24
Finished	Aug 27 07:00:50 AM UTC 24
Peak memory	215084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734098604 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.1734098604
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1017848082
Short name	T366
Test name
Test status
Simulation time	34511880 ps
CPU time	1.09 seconds
Started	Aug 27 07:00:50 AM UTC 24
Finished	Aug 27 07:00:52 AM UTC 24
Peak memory	215140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017848082 -assert nopostproc +UVM _TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_partial_access.1017848082
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/3.rv_dm_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_walk.3649066056
Short name	T365
Test name
Test status
Simulation time	106404118 ps
CPU time	1.05 seconds
Started	Aug 27 07:00:50 AM UTC 24
Finished	Aug 27 07:00:52 AM UTC 24
Peak memory	215140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649066056 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.3649066056
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/3.rv_dm_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.663436965
Short name	T147
Test name
Test status
Simulation time	1220518729 ps
CPU time	8.82 seconds
Started	Aug 27 07:00:52 AM UTC 24
Finished	Aug 27 07:01:02 AM UTC 24
Peak memory	215500 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663436965 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_csr_outstanding.663436965
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/3.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_errors.4066476393
Short name	T369
Test name
Test status
Simulation time	371680812 ps
CPU time	3.23 seconds
Started	Aug 27 07:00:50 AM UTC 24
Finished	Aug 27 07:00:54 AM UTC 24
Peak memory	225716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066476393 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.4066476393
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/3.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1206977561
Short name	T180
Test name
Test status
Simulation time	3584435521 ps
CPU time	12.51 seconds
Started	Aug 27 07:00:50 AM UTC 24
Finished	Aug 27 07:01:04 AM UTC 24
Peak memory	225688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206977561 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.1206977561
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/3.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3129765241
Short name	T162
Test name
Test status
Simulation time	1714621260 ps
CPU time	29.5 seconds
Started	Aug 27 07:00:53 AM UTC 24
Finished	Aug 27 07:01:24 AM UTC 24
Peak memory	215356 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129765241 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_aliasing.3129765241
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/4.rv_dm_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3597115241
Short name	T471
Test name
Test status
Simulation time	8071435435 ps
CPU time	68.42 seconds
Started	Aug 27 07:01:00 AM UTC 24
Finished	Aug 27 07:02:10 AM UTC 24
Peak memory	215524 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597115241 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.3597115241
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/4.rv_dm_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3885053147
Short name	T148
Test name
Test status
Simulation time	169128044 ps
CPU time	2.41 seconds
Started	Aug 27 07:01:00 AM UTC 24
Finished	Aug 27 07:01:03 AM UTC 24
Peak memory	225624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885053147 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.3885053147
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/4.rv_dm_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2047011062
Short name	T381
Test name
Test status
Simulation time	75004297 ps
CPU time	3.26 seconds
Started	Aug 27 07:01:00 AM UTC 24
Finished	Aug 27 07:01:04 AM UTC 24
Peak memory	230000 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2047011062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_r and_reset.2047011062
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_rw.2591999442
Short name	T380
Test name
Test status
Simulation time	439157140 ps
CPU time	2.16 seconds
Started	Aug 27 07:01:00 AM UTC 24
Finished	Aug 27 07:01:03 AM UTC 24
Peak memory	225668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591999442 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.2591999442
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/4.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3732218859
Short name	T468
Test name
Test status
Simulation time	28733813028 ps
CPU time	70.68 seconds
Started	Aug 27 07:00:56 AM UTC 24
Finished	Aug 27 07:02:08 AM UTC 24
Peak memory	215428 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732218859 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_aliasing.3732218859
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.446940724
Short name	T474
Test name
Test status
Simulation time	41709114889 ps
CPU time	82.31 seconds
Started	Aug 27 07:00:55 AM UTC 24
Finished	Aug 27 07:02:19 AM UTC 24
Peak memory	215388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446940724 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_bit_bash.446940724
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2707553447
Short name	T144
Test name
Test status
Simulation time	5270783698 ps
CPU time	13.4 seconds
Started	Aug 27 07:00:55 AM UTC 24
Finished	Aug 27 07:01:09 AM UTC 24
Peak memory	215560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707553447 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_hw_reset.2707553447
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3293053970
Short name	T374
Test name
Test status
Simulation time	1619057231 ps
CPU time	2.43 seconds
Started	Aug 27 07:00:55 AM UTC 24
Finished	Aug 27 07:00:58 AM UTC 24
Peak memory	215204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293053970 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.3293053970
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.441713769
Short name	T375
Test name
Test status
Simulation time	988616846 ps
CPU time	2.85 seconds
Started	Aug 27 07:00:55 AM UTC 24
Finished	Aug 27 07:00:59 AM UTC 24
Peak memory	214948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441713769 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_aliasing.441713769
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1792971824
Short name	T387
Test name
Test status
Simulation time	18463794816 ps
CPU time	14.94 seconds
Started	Aug 27 07:00:55 AM UTC 24
Finished	Aug 27 07:01:11 AM UTC 24
Peak memory	215368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792971824 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_bit_bash.1792971824
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3922707492
Short name	T370
Test name
Test status
Simulation time	188030559 ps
CPU time	1.1 seconds
Started	Aug 27 07:00:53 AM UTC 24
Finished	Aug 27 07:00:55 AM UTC 24
Peak memory	215144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922707492 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_hw_reset.3922707492
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.204583729
Short name	T371
Test name
Test status
Simulation time	368620447 ps
CPU time	1.3 seconds
Started	Aug 27 07:00:53 AM UTC 24
Finished	Aug 27 07:00:55 AM UTC 24
Peak memory	215204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204583729 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.204583729
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3654754610
Short name	T377
Test name
Test status
Simulation time	175943235 ps
CPU time	1.19 seconds
Started	Aug 27 07:00:57 AM UTC 24
Finished	Aug 27 07:01:00 AM UTC 24
Peak memory	215140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654754610 -assert nopostproc +UVM _TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_partial_access.3654754610
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/4.rv_dm_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_walk.1717310450
Short name	T378
Test name
Test status
Simulation time	79245902 ps
CPU time	1.42 seconds
Started	Aug 27 07:00:57 AM UTC 24
Finished	Aug 27 07:01:00 AM UTC 24
Peak memory	215140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717310450 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.1717310450
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/4.rv_dm_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.526913011
Short name	T104
Test name
Test status
Simulation time	9857632042 ps
CPU time	78.79 seconds
Started	Aug 27 07:00:56 AM UTC 24
Finished	Aug 27 07:02:17 AM UTC 24
Peak memory	229836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=526913011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.526913011
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/4.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_errors.4000376647
Short name	T181
Test name
Test status
Simulation time	1102803707 ps
CPU time	6.71 seconds
Started	Aug 27 07:00:56 AM UTC 24
Finished	Aug 27 07:01:04 AM UTC 24
Peak memory	225800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000376647 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.4000376647
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/4.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1731544443
Short name	T217
Test name
Test status
Simulation time	1340473937 ps
CPU time	11.23 seconds
Started	Aug 27 07:00:57 AM UTC 24
Finished	Aug 27 07:01:10 AM UTC 24
Peak memory	225696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731544443 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.1731544443
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/4.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2052006241
Short name	T386
Test name
Test status
Simulation time	93159397 ps
CPU time	5.32 seconds
Started	Aug 27 07:01:05 AM UTC 24
Finished	Aug 27 07:01:11 AM UTC 24
Peak memory	225876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2052006241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_r and_reset.2052006241
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_rw.2419787213
Short name	T149
Test name
Test status
Simulation time	184763759 ps
CPU time	2.6 seconds
Started	Aug 27 07:01:04 AM UTC 24
Finished	Aug 27 07:01:08 AM UTC 24
Peak memory	225640 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419787213 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.2419787213
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/5.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.951666894
Short name	T432
Test name
Test status
Simulation time	20559845467 ps
CPU time	41.79 seconds
Started	Aug 27 07:01:02 AM UTC 24
Finished	Aug 27 07:01:45 AM UTC 24
Peak memory	215380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951666894 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_bit_bash.951666894
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.139264455
Short name	T382
Test name
Test status
Simulation time	7574843639 ps
CPU time	4.07 seconds
Started	Aug 27 07:01:02 AM UTC 24
Finished	Aug 27 07:01:07 AM UTC 24
Peak memory	215224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139264455 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.139264455
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/5.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2399583438
Short name	T379
Test name
Test status
Simulation time	273525888 ps
CPU time	1.58 seconds
Started	Aug 27 07:01:00 AM UTC 24
Finished	Aug 27 07:01:03 AM UTC 24
Peak memory	215084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399583438 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.2399583438
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/5.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3345417310
Short name	T150
Test name
Test status
Simulation time	307885882 ps
CPU time	3.77 seconds
Started	Aug 27 07:01:04 AM UTC 24
Finished	Aug 27 07:01:09 AM UTC 24
Peak memory	215436 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345417310 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_csr_outstanding.3345417310
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/5.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2904811121
Short name	T115
Test name
Test status
Simulation time	3846019863 ps
CPU time	58.99 seconds
Started	Aug 27 07:01:02 AM UTC 24
Finished	Aug 27 07:02:03 AM UTC 24
Peak memory	229924 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2904811121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_re set.2904811121
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/5.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_errors.3984138851
Short name	T367
Test name
Test status
Simulation time	325882066 ps
CPU time	6.07 seconds
Started	Aug 27 07:01:03 AM UTC 24
Finished	Aug 27 07:01:10 AM UTC 24
Peak memory	225740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984138851 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.3984138851
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/5.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_intg_err.657263777
Short name	T218
Test name
Test status
Simulation time	1884217700 ps
CPU time	24.3 seconds
Started	Aug 27 07:01:04 AM UTC 24
Finished	Aug 27 07:01:30 AM UTC 24
Peak memory	232556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657263777 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.657263777
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/5.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.508490020
Short name	T182
Test name
Test status
Simulation time	853852868 ps
CPU time	2.84 seconds
Started	Aug 27 07:01:10 AM UTC 24
Finished	Aug 27 07:01:14 AM UTC 24
Peak memory	227876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=508490020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_ra nd_reset.508490020
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_rw.3375335213
Short name	T159
Test name
Test status
Simulation time	37891906 ps
CPU time	1.73 seconds
Started	Aug 27 07:01:09 AM UTC 24
Finished	Aug 27 07:01:12 AM UTC 24
Peak memory	225260 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375335213 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.3375335213
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/6.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.343053028
Short name	T479
Test name
Test status
Simulation time	46180624174 ps
CPU time	80.72 seconds
Started	Aug 27 07:01:08 AM UTC 24
Finished	Aug 27 07:02:30 AM UTC 24
Peak memory	215360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343053028 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_bit_bash.343053028
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1924926944
Short name	T396
Test name
Test status
Simulation time	2466117831 ps
CPU time	10.3 seconds
Started	Aug 27 07:01:08 AM UTC 24
Finished	Aug 27 07:01:19 AM UTC 24
Peak memory	215496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924926944 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.1924926944
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/6.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2742511972
Short name	T385
Test name
Test status
Simulation time	319363788 ps
CPU time	2.77 seconds
Started	Aug 27 07:01:06 AM UTC 24
Finished	Aug 27 07:01:09 AM UTC 24
Peak memory	215084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742511972 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.2742511972
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/6.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.271421899
Short name	T169
Test name
Test status
Simulation time	161617850 ps
CPU time	4.92 seconds
Started	Aug 27 07:01:10 AM UTC 24
Finished	Aug 27 07:01:16 AM UTC 24
Peak memory	215496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271421899 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_csr_outstanding.271421899
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/6.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_errors.3032337208
Short name	T183
Test name
Test status
Simulation time	274678606 ps
CPU time	5.26 seconds
Started	Aug 27 07:01:09 AM UTC 24
Finished	Aug 27 07:01:15 AM UTC 24
Peak memory	225800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032337208 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.3032337208
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/6.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_intg_err.144152323
Short name	T221
Test name
Test status
Simulation time	1737152953 ps
CPU time	24.23 seconds
Started	Aug 27 07:01:09 AM UTC 24
Finished	Aug 27 07:01:34 AM UTC 24
Peak memory	231824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144152323 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.144152323
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/6.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2575138434
Short name	T391
Test name
Test status
Simulation time	209039987 ps
CPU time	1.93 seconds
Started	Aug 27 07:01:12 AM UTC 24
Finished	Aug 27 07:01:15 AM UTC 24
Peak memory	227192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2575138434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_r and_reset.2575138434
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_rw.3866918449
Short name	T160
Test name
Test status
Simulation time	137515645 ps
CPU time	2.14 seconds
Started	Aug 27 07:01:11 AM UTC 24
Finished	Aug 27 07:01:14 AM UTC 24
Peak memory	229764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866918449 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.3866918449
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/7.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.3630322160
Short name	T459
Test name
Test status
Simulation time	14374567972 ps
CPU time	46.28 seconds
Started	Aug 27 07:01:10 AM UTC 24
Finished	Aug 27 07:01:58 AM UTC 24
Peak memory	215376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630322160 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_bit_bash.3630322160
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3626425040
Short name	T390
Test name
Test status
Simulation time	2682388265 ps
CPU time	3.14 seconds
Started	Aug 27 07:01:10 AM UTC 24
Finished	Aug 27 07:01:15 AM UTC 24
Peak memory	215368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626425040 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.3626425040
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/7.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.753029806
Short name	T388
Test name
Test status
Simulation time	181148762 ps
CPU time	1.49 seconds
Started	Aug 27 07:01:10 AM UTC 24
Finished	Aug 27 07:01:13 AM UTC 24
Peak memory	215204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753029806 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.753029806
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/7.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3555651169
Short name	T170
Test name
Test status
Simulation time	582085535 ps
CPU time	8.77 seconds
Started	Aug 27 07:01:12 AM UTC 24
Finished	Aug 27 07:01:22 AM UTC 24
Peak memory	215428 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555651169 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_csr_outstanding.3555651169
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/7.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1569334106
Short name	T105
Test name
Test status
Simulation time	3914809326 ps
CPU time	36.53 seconds
Started	Aug 27 07:01:11 AM UTC 24
Finished	Aug 27 07:01:48 AM UTC 24
Peak memory	229956 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1569334106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_re set.1569334106
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/7.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_errors.2871717413
Short name	T184
Test name
Test status
Simulation time	229145161 ps
CPU time	7.18 seconds
Started	Aug 27 07:01:11 AM UTC 24
Finished	Aug 27 07:01:19 AM UTC 24
Peak memory	225796 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871717413 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.2871717413
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/7.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2909932523
Short name	T220
Test name
Test status
Simulation time	843509688 ps
CPU time	11.18 seconds
Started	Aug 27 07:01:11 AM UTC 24
Finished	Aug 27 07:01:23 AM UTC 24
Peak memory	232300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909932523 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2909932523
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/7.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1789396281
Short name	T398
Test name
Test status
Simulation time	79417922 ps
CPU time	2.94 seconds
Started	Aug 27 07:01:16 AM UTC 24
Finished	Aug 27 07:01:20 AM UTC 24
Peak memory	232440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1789396281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_r and_reset.1789396281
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_rw.1966818903
Short name	T161
Test name
Test status
Simulation time	297832099 ps
CPU time	2.41 seconds
Started	Aug 27 07:01:16 AM UTC 24
Finished	Aug 27 07:01:19 AM UTC 24
Peak memory	225632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966818903 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.1966818903
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/8.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.515823781
Short name	T394
Test name
Test status
Simulation time	3949868512 ps
CPU time	3.83 seconds
Started	Aug 27 07:01:13 AM UTC 24
Finished	Aug 27 07:01:18 AM UTC 24
Peak memory	215360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515823781 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_bit_bash.515823781
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.4078704140
Short name	T392
Test name
Test status
Simulation time	1408064824 ps
CPU time	2.45 seconds
Started	Aug 27 07:01:12 AM UTC 24
Finished	Aug 27 07:01:15 AM UTC 24
Peak memory	215396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078704140 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.4078704140
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/8.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.91906400
Short name	T389
Test name
Test status
Simulation time	869178736 ps
CPU time	1.52 seconds
Started	Aug 27 07:01:12 AM UTC 24
Finished	Aug 27 07:01:14 AM UTC 24
Peak memory	215264 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91906400 -assert nopostproc +UVM_TESTNAME=rv_dm_ba se_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.91906400
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/8.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1956210495
Short name	T171
Test name
Test status
Simulation time	997340223 ps
CPU time	7.99 seconds
Started	Aug 27 07:01:16 AM UTC 24
Finished	Aug 27 07:01:25 AM UTC 24
Peak memory	215616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956210495 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_csr_outstanding.1956210495
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/8.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.2273015983
Short name	T111
Test name
Test status
Simulation time	2205860882 ps
CPU time	43.07 seconds
Started	Aug 27 07:01:14 AM UTC 24
Finished	Aug 27 07:01:59 AM UTC 24
Peak memory	225884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2273015983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_re set.2273015983
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/8.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_errors.3825948551
Short name	T397
Test name
Test status
Simulation time	173022323 ps
CPU time	2.49 seconds
Started	Aug 27 07:01:16 AM UTC 24
Finished	Aug 27 07:01:19 AM UTC 24
Peak memory	227840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825948551 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.3825948551
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/8.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2297706889
Short name	T214
Test name
Test status
Simulation time	4905855571 ps
CPU time	15.25 seconds
Started	Aug 27 07:01:16 AM UTC 24
Finished	Aug 27 07:01:32 AM UTC 24
Peak memory	227708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297706889 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.2297706889
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/8.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2614845162
Short name	T404
Test name
Test status
Simulation time	54115465 ps
CPU time	1.98 seconds
Started	Aug 27 07:01:21 AM UTC 24
Finished	Aug 27 07:01:24 AM UTC 24
Peak memory	225108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2614845162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_r and_reset.2614845162
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_rw.712440723
Short name	T403
Test name
Test status
Simulation time	151057851 ps
CPU time	2.71 seconds
Started	Aug 27 07:01:19 AM UTC 24
Finished	Aug 27 07:01:23 AM UTC 24
Peak memory	225728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712440723 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.712440723
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/9.rv_dm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.1367424220
Short name	T423
Test name
Test status
Simulation time	14884364980 ps
CPU time	22.07 seconds
Started	Aug 27 07:01:17 AM UTC 24
Finished	Aug 27 07:01:40 AM UTC 24
Peak memory	215452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367424220 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_bit_bash.1367424220
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3488855240
Short name	T400
Test name
Test status
Simulation time	1356375790 ps
CPU time	3.37 seconds
Started	Aug 27 07:01:16 AM UTC 24
Finished	Aug 27 07:01:20 AM UTC 24
Peak memory	215264 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488855240 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.3488855240
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/9.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1020833153
Short name	T395
Test name
Test status
Simulation time	140170384 ps
CPU time	1.16 seconds
Started	Aug 27 07:01:16 AM UTC 24
Finished	Aug 27 07:01:18 AM UTC 24
Peak memory	215084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020833153 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.1020833153
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/9.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2867790951
Short name	T154
Test name
Test status
Simulation time	1127569028 ps
CPU time	12.61 seconds
Started	Aug 27 07:01:21 AM UTC 24
Finished	Aug 27 07:01:35 AM UTC 24
Peak memory	215480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867790951 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_csr_outstanding.2867790951
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/9.rv_dm_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2937069950
Short name	T480
Test name
Test status
Simulation time	41365899357 ps
CPU time	84.07 seconds
Started	Aug 27 07:01:17 AM UTC 24
Finished	Aug 27 07:02:43 AM UTC 24
Peak memory	231792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2937069950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_re set.2937069950
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/9.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_errors.2580294157
Short name	T407
Test name
Test status
Simulation time	714746872 ps
CPU time	8.16 seconds
Started	Aug 27 07:01:17 AM UTC 24
Finished	Aug 27 07:01:26 AM UTC 24
Peak memory	225796 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580294157 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.2580294157
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/9.rv_dm_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_intg_err.437140130
Short name	T427
Test name
Test status
Simulation time	5369758840 ps
CPU time	22.02 seconds
Started	Aug 27 07:01:18 AM UTC 24
Finished	Aug 27 07:01:42 AM UTC 24
Peak memory	225876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437140130 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.437140130
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/9.rv_dm_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.2191791410
Short name	T51
Test name
Test status
Simulation time	131455660 ps
CPU time	1.02 seconds
Started	Aug 27 07:02:00 AM UTC 24
Finished	Aug 27 07:02:02 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191791410 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.2191791410
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.3852286672
Short name	T336
Test name
Test status
Simulation time	48181420552 ps
CPU time	82.98 seconds
Started	Aug 27 07:01:54 AM UTC 24
Finished	Aug 27 07:03:19 AM UTC 24
Peak memory	226088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852286672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.3852286672
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_busy.1082304179
Short name	T12
Test name
Test status
Simulation time	176068175 ps
CPU time	2.04 seconds
Started	Aug 27 07:01:54 AM UTC 24
Finished	Aug 27 07:01:57 AM UTC 24
Peak memory	215360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082304179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.1082304179
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_cmderr_busy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.542423282
Short name	T5
Test name
Test status
Simulation time	610856457 ps
CPU time	2.83 seconds
Started	Aug 27 07:01:55 AM UTC 24
Finished	Aug 27 07:01:59 AM UTC 24
Peak memory	215804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542423282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_cmderr_halt_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.542423282
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_cmderr_halt_resume/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.1013573426
Short name	T3
Test name
Test status
Simulation time	139546935 ps
CPU time	1.53 seconds
Started	Aug 27 07:01:54 AM UTC 24
Finished	Aug 27 07:01:56 AM UTC 24
Peak memory	213340 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013573426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1013573426
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_cmderr_not_supported/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_dataaddr_rw_access.1862384399
Short name	T6
Test name
Test status
Simulation time	230481950 ps
CPU time	1.2 seconds
Started	Aug 27 07:01:56 AM UTC 24
Finished	Aug 27 07:01:58 AM UTC 24
Peak memory	213456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862384399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.1862384399
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_dataaddr_rw_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_debug_disabled.2163868139
Short name	T86
Test name
Test status
Simulation time	130511759 ps
CPU time	1.07 seconds
Started	Aug 27 07:01:59 AM UTC 24
Finished	Aug 27 07:02:01 AM UTC 24
Peak memory	236056 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163868139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.2163868139
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_debug_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2850581544
Short name	T20
Test name
Test status
Simulation time	5511838951 ps
CPU time	7.19 seconds
Started	Aug 27 07:01:53 AM UTC 24
Finished	Aug 27 07:02:01 AM UTC 24
Peak memory	233272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850581544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_tl_access.2850581544
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_hart_unavail.140878139
Short name	T4
Test name
Test status
Simulation time	128511528 ps
CPU time	1.2 seconds
Started	Aug 27 07:01:55 AM UTC 24
Finished	Aug 27 07:01:57 AM UTC 24
Peak memory	213396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140878139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.140878139
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_hart_unavail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_hartsel_warl.4156575512
Short name	T27
Test name
Test status
Simulation time	114699397 ps
CPU time	0.84 seconds
Started	Aug 27 07:01:59 AM UTC 24
Finished	Aug 27 07:02:01 AM UTC 24
Peak memory	213308 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156575512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.4156575512
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_hartsel_warl/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.3820083855
Short name	T8
Test name
Test status
Simulation time	176409558 ps
CPU time	0.99 seconds
Started	Aug 27 07:01:58 AM UTC 24
Finished	Aug 27 07:02:00 AM UTC 24
Peak memory	213456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820083855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.3820083855
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1986467713
Short name	T15
Test name
Test status
Simulation time	2168371343 ps
CPU time	2.76 seconds
Started	Aug 27 07:01:58 AM UTC 24
Finished	Aug 27 07:02:01 AM UTC 24
Peak memory	215940 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986467713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.1986467713
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_hard_reset.3099136794
Short name	T7
Test name
Test status
Simulation time	130836270 ps
CPU time	1.01 seconds
Started	Aug 27 07:01:58 AM UTC 24
Finished	Aug 27 07:02:00 AM UTC 24
Peak memory	213160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099136794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.3099136794
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_hard_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_idle_hint.1932671640
Short name	T24
Test name
Test status
Simulation time	111960477 ps
CPU time	1.3 seconds
Started	Aug 27 07:01:58 AM UTC 24
Finished	Aug 27 07:02:00 AM UTC 24
Peak memory	213396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932671640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.1932671640
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_idle_hint/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_halted.1061595333
Short name	T13
Test name
Test status
Simulation time	197296781 ps
CPU time	1.1 seconds
Started	Aug 27 07:01:55 AM UTC 24
Finished	Aug 27 07:01:57 AM UTC 24
Peak memory	213460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061595333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.1061595333
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_halted/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_resuming.579898720
Short name	T26
Test name
Test status
Simulation time	241269996 ps
CPU time	2.36 seconds
Started	Aug 27 07:01:55 AM UTC 24
Finished	Aug 27 07:01:58 AM UTC 24
Peak memory	215864 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579898720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.579898720
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_resuming/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.1137493631
Short name	T14
Test name
Test status
Simulation time	123722149 ps
CPU time	1.09 seconds
Started	Aug 27 07:01:57 AM UTC 24
Finished	Aug 27 07:02:00 AM UTC 24
Peak memory	225852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137493631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.1137493631
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_ndmreset_req/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.4055166059
Short name	T48
Test name
Test status
Simulation time	353769414 ps
CPU time	1.26 seconds
Started	Aug 27 07:01:59 AM UTC 24
Finished	Aug 27 07:02:01 AM UTC 24
Peak memory	213460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055166059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_progbuf_read_write_execute_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_d m-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.4055166059
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_progbuf_read_write_execute/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_tl_access.3947691392
Short name	T19
Test name
Test status
Simulation time	1778829648 ps
CPU time	7.25 seconds
Started	Aug 27 07:01:53 AM UTC 24
Finished	Aug 27 07:02:01 AM UTC 24
Peak memory	216140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947691392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.3947691392
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_smoke.2445092147
Short name	T1
Test name
Test status
Simulation time	922294035 ps
CPU time	2.01 seconds
Started	Aug 27 07:01:53 AM UTC 24
Finished	Aug 27 07:01:56 AM UTC 24
Peak memory	215460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445092147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.2445092147
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.2549441049
Short name	T41
Test name
Test status
Simulation time	3465160279 ps
CPU time	3.88 seconds
Started	Aug 27 07:02:00 AM UTC 24
Finished	Aug 27 07:02:05 AM UTC 24
Peak memory	226268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549441049 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.2549441049
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/0.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_abstractcmd_status.2081161134
Short name	T64
Test name
Test status
Simulation time	197429131 ps
CPU time	1.15 seconds
Started	Aug 27 07:02:03 AM UTC 24
Finished	Aug 27 07:02:05 AM UTC 24
Peak memory	213456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081161134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_abstractcmd_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.2081161134
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_abstractcmd_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_alert_test.747044604
Short name	T52
Test name
Test status
Simulation time	115834506 ps
CPU time	0.95 seconds
Started	Aug 27 07:02:05 AM UTC 24
Finished	Aug 27 07:02:07 AM UTC 24
Peak memory	215992 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747044604 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.747044604
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_autoincr_sba_tl_access.2011531324
Short name	T337
Test name
Test status
Simulation time	26232289347 ps
CPU time	77.25 seconds
Started	Aug 27 07:02:01 AM UTC 24
Finished	Aug 27 07:03:19 AM UTC 24
Peak memory	228500 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011531324 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.2011531324
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_bad_sba_tl_access.741600894
Short name	T95
Test name
Test status
Simulation time	1011828244 ps
CPU time	4.61 seconds
Started	Aug 27 07:02:00 AM UTC 24
Finished	Aug 27 07:02:06 AM UTC 24
Peak memory	216328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741600894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.741600894
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_buffered_enable.316696086
Short name	T84
Test name
Test status
Simulation time	210936661 ps
CPU time	0.95 seconds
Started	Aug 27 07:02:04 AM UTC 24
Finished	Aug 27 07:02:06 AM UTC 24
Peak memory	251672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316696086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_buffered_enable.316696086
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_buffered_enable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_busy.208639429
Short name	T34
Test name
Test status
Simulation time	599679827 ps
CPU time	2 seconds
Started	Aug 27 07:02:01 AM UTC 24
Finished	Aug 27 07:02:04 AM UTC 24
Peak memory	213456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208639429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.208639429
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_cmderr_busy/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.3092103443
Short name	T29
Test name
Test status
Simulation time	372181781 ps
CPU time	2.46 seconds
Started	Aug 27 07:02:02 AM UTC 24
Finished	Aug 27 07:02:05 AM UTC 24
Peak memory	216004 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092103443 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.3092103443
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_cmderr_exception/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_not_supported.55110229
Short name	T56
Test name
Test status
Simulation time	188852506 ps
CPU time	1.04 seconds
Started	Aug 27 07:02:02 AM UTC 24
Finished	Aug 27 07:02:04 AM UTC 24
Peak memory	213456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55110229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv _dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.55110229
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_cmderr_not_supported/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_dataaddr_rw_access.1939204067
Short name	T40
Test name
Test status
Simulation time	134644727 ps
CPU time	0.89 seconds
Started	Aug 27 07:02:02 AM UTC 24
Finished	Aug 27 07:02:04 AM UTC 24
Peak memory	213384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939204067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.1939204067
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_dataaddr_rw_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_debug_disabled.2364676323
Short name	T90
Test name
Test status
Simulation time	111404114 ps
CPU time	1.33 seconds
Started	Aug 27 07:02:03 AM UTC 24
Finished	Aug 27 07:02:06 AM UTC 24
Peak memory	236056 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364676323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.2364676323
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_debug_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.3017944910
Short name	T100
Test name
Test status
Simulation time	1062462592 ps
CPU time	1.9 seconds
Started	Aug 27 07:02:00 AM UTC 24
Finished	Aug 27 07:02:03 AM UTC 24
Peak memory	215616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017944910 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_tl_access.3017944910
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.827128873
Short name	T76
Test name
Test status
Simulation time	117956186 ps
CPU time	1.14 seconds
Started	Aug 27 07:02:04 AM UTC 24
Finished	Aug 27 07:02:07 AM UTC 24
Peak memory	213460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827128873 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_dmi_failed_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.827128873
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_dmi_failed_op/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_halt_resume_whereto.1562536431
Short name	T46
Test name
Test status
Simulation time	244197176 ps
CPU time	0.98 seconds
Started	Aug 27 07:02:02 AM UTC 24
Finished	Aug 27 07:02:04 AM UTC 24
Peak memory	213316 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562536431 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.1562536431
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_halt_resume_whereto/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_hart_unavail.1453811906
Short name	T277
Test name
Test status
Simulation time	64194125 ps
CPU time	1.29 seconds
Started	Aug 27 07:02:02 AM UTC 24
Finished	Aug 27 07:02:04 AM UTC 24
Peak memory	213452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453811906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.1453811906
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_hart_unavail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.3914660679
Short name	T193
Test name
Test status
Simulation time	436073648 ps
CPU time	1.45 seconds
Started	Aug 27 07:02:02 AM UTC 24
Finished	Aug 27 07:02:05 AM UTC 24
Peak memory	213456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914660679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.3914660679
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1416264595
Short name	T280
Test name
Test status
Simulation time	336585845 ps
CPU time	1.51 seconds
Started	Aug 27 07:02:02 AM UTC 24
Finished	Aug 27 07:02:05 AM UTC 24
Peak memory	213340 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416264595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.1416264595
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_hard_reset.516196212
Short name	T78
Test name
Test status
Simulation time	335048260 ps
CPU time	1.42 seconds
Started	Aug 27 07:02:02 AM UTC 24
Finished	Aug 27 07:02:05 AM UTC 24
Peak memory	213456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516196212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.516196212
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_hard_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_idle_hint.2200466026
Short name	T79
Test name
Test status
Simulation time	156830376 ps
CPU time	1.16 seconds
Started	Aug 27 07:02:02 AM UTC 24
Finished	Aug 27 07:02:04 AM UTC 24
Peak memory	213456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200466026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.2200466026
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_idle_hint/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_halted.2885959942
Short name	T174
Test name
Test status
Simulation time	146504113 ps
CPU time	1.14 seconds
Started	Aug 27 07:02:02 AM UTC 24
Finished	Aug 27 07:02:04 AM UTC 24
Peak memory	213460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885959942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.2885959942
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_mem_tl_access_halted/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_resuming.2593220148
Short name	T28
Test name
Test status
Simulation time	127822666 ps
CPU time	1.35 seconds
Started	Aug 27 07:02:02 AM UTC 24
Finished	Aug 27 07:02:04 AM UTC 24
Peak memory	215944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593220148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.2593220148
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_mem_tl_access_resuming/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_progbuf_read_write_execute.3424083386
Short name	T62
Test name
Test status
Simulation time	207685685 ps
CPU time	1.42 seconds
Started	Aug 27 07:02:03 AM UTC 24
Finished	Aug 27 07:02:06 AM UTC 24
Peak memory	213460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424083386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_progbuf_read_write_execute_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_d m-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.3424083386
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_progbuf_read_write_execute/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_rom_read_access.2056587179
Short name	T67
Test name
Test status
Simulation time	93027875 ps
CPU time	1.38 seconds
Started	Aug 27 07:02:03 AM UTC 24
Finished	Aug 27 07:02:06 AM UTC 24
Peak memory	225860 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056587179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_rom_read_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.2056587179
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_rom_read_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_debug_disabled.477023829
Short name	T94
Test name
Test status
Simulation time	988564281 ps
CPU time	3.02 seconds
Started	Aug 27 07:02:02 AM UTC 24
Finished	Aug 27 07:02:06 AM UTC 24
Peak memory	216040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477023829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sba_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.477023829
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_sba_debug_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_tl_access.278909424
Short name	T124
Test name
Test status
Simulation time	6855379231 ps
CPU time	17.97 seconds
Started	Aug 27 07:02:00 AM UTC 24
Finished	Aug 27 07:02:20 AM UTC 24
Peak memory	216260 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278909424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.278909424
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_sec_cm.3750045979
Short name	T88
Test name
Test status
Simulation time	830866503 ps
CPU time	1.92 seconds
Started	Aug 27 07:02:05 AM UTC 24
Finished	Aug 27 07:02:08 AM UTC 24
Peak memory	253560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750045979 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.3750045979
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_smoke.1834516355
Short name	T93
Test name
Test status
Simulation time	705975705 ps
CPU time	3.79 seconds
Started	Aug 27 07:02:00 AM UTC 24
Finished	Aug 27 07:02:05 AM UTC 24
Peak memory	215808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834516355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.1834516355
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.2683598715
Short name	T55
Test name
Test status
Simulation time	253146246 ps
CPU time	1.24 seconds
Started	Aug 27 07:02:05 AM UTC 24
Finished	Aug 27 07:02:07 AM UTC 24
Peak memory	225796 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683598715 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sparse_lc_gate_fsm.2683598715
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_sparse_lc_gate_fsm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.3979894657
Short name	T63
Test name
Test status
Simulation time	1119963665 ps
CPU time	12.7 seconds
Started	Aug 27 07:02:05 AM UTC 24
Finished	Aug 27 07:02:18 AM UTC 24
Peak memory	233168 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3979894657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stres s_all_with_rand_reset.3979894657
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/10.rv_dm_alert_test.2621435976
Short name	T243
Test name
Test status
Simulation time	41470707 ps
CPU time	1.22 seconds
Started	Aug 27 07:02:21 AM UTC 24
Finished	Aug 27 07:02:23 AM UTC 24
Peak memory	215876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621435976 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.2621435976
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/10.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/10.rv_dm_autoincr_sba_tl_access.1022665779
Short name	T188
Test name
Test status
Simulation time	7947497981 ps
CPU time	8 seconds
Started	Aug 27 07:02:21 AM UTC 24
Finished	Aug 27 07:02:30 AM UTC 24
Peak memory	226452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022665779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.1022665779
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/10.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/10.rv_dm_bad_sba_tl_access.284407348
Short name	T262
Test name
Test status
Simulation time	5836403893 ps
CPU time	17.87 seconds
Started	Aug 27 07:02:20 AM UTC 24
Finished	Aug 27 07:02:39 AM UTC 24
Peak memory	216200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284407348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.284407348
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/10.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.2022419910
Short name	T279
Test name
Test status
Simulation time	1820302524 ps
CPU time	2.85 seconds
Started	Aug 27 07:02:20 AM UTC 24
Finished	Aug 27 07:02:23 AM UTC 24
Peak memory	226344 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022419910 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_tl_access.2022419910
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/10.rv_dm_sba_tl_access.993176557
Short name	T289
Test name
Test status
Simulation time	9046552685 ps
CPU time	12.62 seconds
Started	Aug 27 07:02:20 AM UTC 24
Finished	Aug 27 07:02:33 AM UTC 24
Peak memory	216392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993176557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.993176557
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/10.rv_dm_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/10.rv_dm_stress_all.3948313824
Short name	T35
Test name
Test status
Simulation time	1247986052 ps
CPU time	1.8 seconds
Started	Aug 27 07:02:21 AM UTC 24
Finished	Aug 27 07:02:23 AM UTC 24
Peak memory	215944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948313824 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.3948313824
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/10.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/11.rv_dm_alert_test.1140186446
Short name	T284
Test name
Test status
Simulation time	180253445 ps
CPU time	1.04 seconds
Started	Aug 27 07:02:23 AM UTC 24
Finished	Aug 27 07:02:25 AM UTC 24
Peak memory	213516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140186446 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.1140186446
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/11.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/11.rv_dm_autoincr_sba_tl_access.1500980101
Short name	T244
Test name
Test status
Simulation time	1912391642 ps
CPU time	4.32 seconds
Started	Aug 27 07:02:23 AM UTC 24
Finished	Aug 27 07:02:28 AM UTC 24
Peak memory	216256 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500980101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.1500980101
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/11.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/11.rv_dm_bad_sba_tl_access.1688931801
Short name	T248
Test name
Test status
Simulation time	7605429066 ps
CPU time	11.89 seconds
Started	Aug 27 07:02:23 AM UTC 24
Finished	Aug 27 07:02:36 AM UTC 24
Peak memory	216392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688931801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.1688931801
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/11.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.1562011794
Short name	T302
Test name
Test status
Simulation time	10934740827 ps
CPU time	16.89 seconds
Started	Aug 27 07:02:23 AM UTC 24
Finished	Aug 27 07:02:41 AM UTC 24
Peak memory	226556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562011794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_tl_access.1562011794
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/11.rv_dm_sba_tl_access.371708225
Short name	T249
Test name
Test status
Simulation time	9033359989 ps
CPU time	10.35 seconds
Started	Aug 27 07:02:21 AM UTC 24
Finished	Aug 27 07:02:32 AM UTC 24
Peak memory	216260 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371708225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.371708225
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/11.rv_dm_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/11.rv_dm_stress_all.4198129845
Short name	T205
Test name
Test status
Simulation time	5747676514 ps
CPU time	15.57 seconds
Started	Aug 27 07:02:23 AM UTC 24
Finished	Aug 27 07:02:39 AM UTC 24
Peak memory	226444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198129845 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.4198129845
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/11.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/12.rv_dm_alert_test.3584346085
Short name	T286
Test name
Test status
Simulation time	38740331 ps
CPU time	1.04 seconds
Started	Aug 27 07:02:24 AM UTC 24
Finished	Aug 27 07:02:26 AM UTC 24
Peak memory	215876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584346085 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.3584346085
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/12.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/12.rv_dm_autoincr_sba_tl_access.4004937877
Short name	T335
Test name
Test status
Simulation time	77936138795 ps
CPU time	42.07 seconds
Started	Aug 27 07:02:24 AM UTC 24
Finished	Aug 27 07:03:07 AM UTC 24
Peak memory	226560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004937877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.4004937877
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/12.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/12.rv_dm_bad_sba_tl_access.3922286731
Short name	T287
Test name
Test status
Simulation time	843988955 ps
CPU time	2.3 seconds
Started	Aug 27 07:02:23 AM UTC 24
Finished	Aug 27 07:02:26 AM UTC 24
Peak memory	216248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922286731 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.3922286731
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/12.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.1776819965
Short name	T288
Test name
Test status
Simulation time	4560569634 ps
CPU time	8.44 seconds
Started	Aug 27 07:02:23 AM UTC 24
Finished	Aug 27 07:02:32 AM UTC 24
Peak memory	216304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776819965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_tl_access.1776819965
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/12.rv_dm_sba_tl_access.1381977561
Short name	T186
Test name
Test status
Simulation time	3533499042 ps
CPU time	5.19 seconds
Started	Aug 27 07:02:23 AM UTC 24
Finished	Aug 27 07:02:29 AM UTC 24
Peak memory	214164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381977561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.1381977561
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/12.rv_dm_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/12.rv_dm_stress_all.828289840
Short name	T31
Test name
Test status
Simulation time	3076112737 ps
CPU time	5.71 seconds
Started	Aug 27 07:02:24 AM UTC 24
Finished	Aug 27 07:02:31 AM UTC 24
Peak memory	226316 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828289840 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.828289840
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/12.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/13.rv_dm_alert_test.4025093525
Short name	T260
Test name
Test status
Simulation time	59793338 ps
CPU time	0.98 seconds
Started	Aug 27 07:02:25 AM UTC 24
Finished	Aug 27 07:02:27 AM UTC 24
Peak memory	215876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025093525 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.4025093525
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/13.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/13.rv_dm_autoincr_sba_tl_access.513208788
Short name	T340
Test name
Test status
Simulation time	100574339861 ps
CPU time	322.69 seconds
Started	Aug 27 07:02:25 AM UTC 24
Finished	Aug 27 07:07:52 AM UTC 24
Peak memory	227968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513208788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.513208788
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/13.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/13.rv_dm_bad_sba_tl_access.839145756
Short name	T190
Test name
Test status
Simulation time	1140944776 ps
CPU time	6.14 seconds
Started	Aug 27 07:02:24 AM UTC 24
Finished	Aug 27 07:02:31 AM UTC 24
Peak memory	216136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839145756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.839145756
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/13.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.3660884980
Short name	T293
Test name
Test status
Simulation time	2581405920 ps
CPU time	9.33 seconds
Started	Aug 27 07:02:24 AM UTC 24
Finished	Aug 27 07:02:35 AM UTC 24
Peak memory	216248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660884980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_tl_access.3660884980
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/13.rv_dm_sba_tl_access.1774997647
Short name	T273
Test name
Test status
Simulation time	1534113688 ps
CPU time	2.36 seconds
Started	Aug 27 07:02:24 AM UTC 24
Finished	Aug 27 07:02:27 AM UTC 24
Peak memory	216128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774997647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.1774997647
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/13.rv_dm_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/13.rv_dm_stress_all.3492410264
Short name	T33
Test name
Test status
Simulation time	2592531723 ps
CPU time	9.68 seconds
Started	Aug 27 07:02:25 AM UTC 24
Finished	Aug 27 07:02:36 AM UTC 24
Peak memory	226380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492410264 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.3492410264
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/13.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/14.rv_dm_alert_test.257328814
Short name	T189
Test name
Test status
Simulation time	104455144 ps
CPU time	1.56 seconds
Started	Aug 27 07:02:28 AM UTC 24
Finished	Aug 27 07:02:30 AM UTC 24
Peak memory	215876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257328814 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.257328814
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/14.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/14.rv_dm_autoincr_sba_tl_access.2712711977
Short name	T305
Test name
Test status
Simulation time	15140490195 ps
CPU time	14.21 seconds
Started	Aug 27 07:02:27 AM UTC 24
Finished	Aug 27 07:02:42 AM UTC 24
Peak memory	226560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712711977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.2712711977
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/14.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/14.rv_dm_bad_sba_tl_access.392713521
Short name	T295
Test name
Test status
Simulation time	2805641780 ps
CPU time	7.44 seconds
Started	Aug 27 07:02:27 AM UTC 24
Finished	Aug 27 07:02:35 AM UTC 24
Peak memory	226564 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392713521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.392713521
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/14.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.3456806392
Short name	T296
Test name
Test status
Simulation time	1987855721 ps
CPU time	8.06 seconds
Started	Aug 27 07:02:26 AM UTC 24
Finished	Aug 27 07:02:36 AM UTC 24
Peak memory	216184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456806392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_tl_access.3456806392
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/14.rv_dm_sba_tl_access.4216787918
Short name	T185
Test name
Test status
Simulation time	2183266782 ps
CPU time	2.44 seconds
Started	Aug 27 07:02:25 AM UTC 24
Finished	Aug 27 07:02:29 AM UTC 24
Peak memory	226552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216787918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.4216787918
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/14.rv_dm_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/14.rv_dm_stress_all.2039374341
Short name	T58
Test name
Test status
Simulation time	5514279680 ps
CPU time	6.76 seconds
Started	Aug 27 07:02:27 AM UTC 24
Finished	Aug 27 07:02:34 AM UTC 24
Peak memory	216188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039374341 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.2039374341
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/14.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/15.rv_dm_alert_test.3982228333
Short name	T192
Test name
Test status
Simulation time	54077160 ps
CPU time	1.03 seconds
Started	Aug 27 07:02:30 AM UTC 24
Finished	Aug 27 07:02:32 AM UTC 24
Peak memory	215876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982228333 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.3982228333
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/15.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/15.rv_dm_bad_sba_tl_access.4109818444
Short name	T250
Test name
Test status
Simulation time	1734042602 ps
CPU time	2.63 seconds
Started	Aug 27 07:02:29 AM UTC 24
Finished	Aug 27 07:02:32 AM UTC 24
Peak memory	216248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109818444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.4109818444
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/15.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.1698781770
Short name	T272
Test name
Test status
Simulation time	5819965229 ps
CPU time	11.9 seconds
Started	Aug 27 07:02:29 AM UTC 24
Finished	Aug 27 07:02:42 AM UTC 24
Peak memory	216304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698781770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_tl_access.1698781770
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/15.rv_dm_sba_tl_access.2714592479
Short name	T292
Test name
Test status
Simulation time	1783987388 ps
CPU time	5.71 seconds
Started	Aug 27 07:02:28 AM UTC 24
Finished	Aug 27 07:02:34 AM UTC 24
Peak memory	216196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714592479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.2714592479
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/15.rv_dm_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/15.rv_dm_stress_all.2004704864
Short name	T208
Test name
Test status
Simulation time	4278315712 ps
CPU time	14.46 seconds
Started	Aug 27 07:02:29 AM UTC 24
Finished	Aug 27 07:02:45 AM UTC 24
Peak memory	216068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004704864 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.2004704864
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/15.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/16.rv_dm_alert_test.3101624571
Short name	T290
Test name
Test status
Simulation time	61826612 ps
CPU time	0.94 seconds
Started	Aug 27 07:02:31 AM UTC 24
Finished	Aug 27 07:02:33 AM UTC 24
Peak memory	215876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101624571 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.3101624571
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/16.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/16.rv_dm_autoincr_sba_tl_access.2291706244
Short name	T236
Test name
Test status
Simulation time	5561503168 ps
CPU time	5.26 seconds
Started	Aug 27 07:02:31 AM UTC 24
Finished	Aug 27 07:02:38 AM UTC 24
Peak memory	216320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291706244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.2291706244
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/16.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.599151261
Short name	T310
Test name
Test status
Simulation time	5902694477 ps
CPU time	11.28 seconds
Started	Aug 27 07:02:30 AM UTC 24
Finished	Aug 27 07:02:43 AM UTC 24
Peak memory	226568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599151261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_tl_access.599151261
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/16.rv_dm_sba_tl_access.897200083
Short name	T297
Test name
Test status
Simulation time	14074261702 ps
CPU time	8.14 seconds
Started	Aug 27 07:02:30 AM UTC 24
Finished	Aug 27 07:02:39 AM UTC 24
Peak memory	226628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897200083 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.897200083
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/16.rv_dm_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/16.rv_dm_stress_all.3174958010
Short name	T234
Test name
Test status
Simulation time	4471490857 ps
CPU time	5.1 seconds
Started	Aug 27 07:02:31 AM UTC 24
Finished	Aug 27 07:02:37 AM UTC 24
Peak memory	216008 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174958010 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.3174958010
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/16.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/17.rv_dm_alert_test.3405681200
Short name	T263
Test name
Test status
Simulation time	121637980 ps
CPU time	1.4 seconds
Started	Aug 27 07:02:33 AM UTC 24
Finished	Aug 27 07:02:35 AM UTC 24
Peak memory	215876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405681200 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.3405681200
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/17.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/17.rv_dm_bad_sba_tl_access.2625982208
Short name	T210
Test name
Test status
Simulation time	6309239000 ps
CPU time	9.22 seconds
Started	Aug 27 07:02:33 AM UTC 24
Finished	Aug 27 07:02:43 AM UTC 24
Peak memory	226560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625982208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.2625982208
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/17.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.978406326
Short name	T204
Test name
Test status
Simulation time	2496702700 ps
CPU time	5.53 seconds
Started	Aug 27 07:02:32 AM UTC 24
Finished	Aug 27 07:02:38 AM UTC 24
Peak memory	216264 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978406326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_tl_access.978406326
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/17.rv_dm_sba_tl_access.2989616783
Short name	T314
Test name
Test status
Simulation time	3738708667 ps
CPU time	11.01 seconds
Started	Aug 27 07:02:31 AM UTC 24
Finished	Aug 27 07:02:44 AM UTC 24
Peak memory	216248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989616783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.2989616783
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/17.rv_dm_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/17.rv_dm_stress_all.865329554
Short name	T37
Test name
Test status
Simulation time	6893670687 ps
CPU time	5.62 seconds
Started	Aug 27 07:02:33 AM UTC 24
Finished	Aug 27 07:02:39 AM UTC 24
Peak memory	226436 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865329554 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.865329554
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/17.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/18.rv_dm_alert_test.161356103
Short name	T257
Test name
Test status
Simulation time	57932828 ps
CPU time	1.09 seconds
Started	Aug 27 07:02:35 AM UTC 24
Finished	Aug 27 07:02:37 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161356103 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.161356103
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/18.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/18.rv_dm_autoincr_sba_tl_access.3573984890
Short name	T339
Test name
Test status
Simulation time	41089120754 ps
CPU time	120.06 seconds
Started	Aug 27 07:02:34 AM UTC 24
Finished	Aug 27 07:04:36 AM UTC 24
Peak memory	230592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573984890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.3573984890
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/18.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/18.rv_dm_bad_sba_tl_access.3885721055
Short name	T265
Test name
Test status
Simulation time	3070852917 ps
CPU time	3.53 seconds
Started	Aug 27 07:02:34 AM UTC 24
Finished	Aug 27 07:02:38 AM UTC 24
Peak memory	226616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885721055 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.3885721055
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/18.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.262305500
Short name	T311
Test name
Test status
Simulation time	4282514529 ps
CPU time	8.86 seconds
Started	Aug 27 07:02:33 AM UTC 24
Finished	Aug 27 07:02:43 AM UTC 24
Peak memory	226496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262305500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_tl_access.262305500
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/18.rv_dm_sba_tl_access.3372608245
Short name	T301
Test name
Test status
Simulation time	1879900383 ps
CPU time	6.71 seconds
Started	Aug 27 07:02:33 AM UTC 24
Finished	Aug 27 07:02:41 AM UTC 24
Peak memory	216316 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372608245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.3372608245
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/18.rv_dm_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/18.rv_dm_stress_all.2947370733
Short name	T68
Test name
Test status
Simulation time	4534504874 ps
CPU time	11.93 seconds
Started	Aug 27 07:02:34 AM UTC 24
Finished	Aug 27 07:02:47 AM UTC 24
Peak memory	216268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947370733 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.2947370733
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/18.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/19.rv_dm_alert_test.2923693644
Short name	T246
Test name
Test status
Simulation time	71529536 ps
CPU time	1.07 seconds
Started	Aug 27 07:02:37 AM UTC 24
Finished	Aug 27 07:02:39 AM UTC 24
Peak memory	215288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923693644 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.2923693644
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/19.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.3315645180
Short name	T308
Test name
Test status
Simulation time	4197501139 ps
CPU time	5.79 seconds
Started	Aug 27 07:02:35 AM UTC 24
Finished	Aug 27 07:02:42 AM UTC 24
Peak memory	226516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315645180 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.3315645180
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/19.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/19.rv_dm_bad_sba_tl_access.2825550147
Short name	T245
Test name
Test status
Simulation time	5313170405 ps
CPU time	5.79 seconds
Started	Aug 27 07:02:35 AM UTC 24
Finished	Aug 27 07:02:42 AM UTC 24
Peak memory	226560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825550147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.2825550147
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/19.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2357795562
Short name	T303
Test name
Test status
Simulation time	1737227436 ps
CPU time	4.66 seconds
Started	Aug 27 07:02:35 AM UTC 24
Finished	Aug 27 07:02:41 AM UTC 24
Peak memory	216316 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357795562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_tl_access.2357795562
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/19.rv_dm_sba_tl_access.1029585608
Short name	T304
Test name
Test status
Simulation time	1158345500 ps
CPU time	4.97 seconds
Started	Aug 27 07:02:35 AM UTC 24
Finished	Aug 27 07:02:41 AM UTC 24
Peak memory	216140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029585608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.1029585608
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/19.rv_dm_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.2519387540
Short name	T11
Test name
Test status
Simulation time	4035545123 ps
CPU time	13.83 seconds
Started	Aug 27 07:02:37 AM UTC 24
Finished	Aug 27 07:02:52 AM UTC 24
Peak memory	226292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519387540 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.2519387540
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/19.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.997877193
Short name	T21
Test name
Test status
Simulation time	2001007837 ps
CPU time	2.39 seconds
Started	Aug 27 07:02:06 AM UTC 24
Finished	Aug 27 07:02:09 AM UTC 24
Peak memory	216240 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997877193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.997877193
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/2.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.3946535725
Short name	T117
Test name
Test status
Simulation time	627847206 ps
CPU time	3.76 seconds
Started	Aug 27 07:02:06 AM UTC 24
Finished	Aug 27 07:02:11 AM UTC 24
Peak memory	258868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946535725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_buffered_enable.3946535725
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/2.rv_dm_buffered_enable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.2687829803
Short name	T97
Test name
Test status
Simulation time	988017030 ps
CPU time	2.76 seconds
Started	Aug 27 07:02:05 AM UTC 24
Finished	Aug 27 07:02:08 AM UTC 24
Peak memory	226376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687829803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_tl_access.2687829803
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.937431252
Short name	T57
Test name
Test status
Simulation time	230858143 ps
CPU time	1.62 seconds
Started	Aug 27 07:02:06 AM UTC 24
Finished	Aug 27 07:02:09 AM UTC 24
Peak memory	213456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937431252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_halt_resume_whereto.937431252
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/2.rv_dm_halt_resume_whereto/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.3808581264
Short name	T96
Test name
Test status
Simulation time	73155267 ps
CPU time	1.06 seconds
Started	Aug 27 07:02:06 AM UTC 24
Finished	Aug 27 07:02:08 AM UTC 24
Peak memory	213452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808581264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.3808581264
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/2.rv_dm_hart_unavail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.2347474575
Short name	T187
Test name
Test status
Simulation time	8940503850 ps
CPU time	23.16 seconds
Started	Aug 27 07:02:05 AM UTC 24
Finished	Aug 27 07:02:29 AM UTC 24
Peak memory	216404 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347474575 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.2347474575
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/2.rv_dm_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.1496709152
Short name	T89
Test name
Test status
Simulation time	1398786998 ps
CPU time	2.32 seconds
Started	Aug 27 07:02:06 AM UTC 24
Finished	Aug 27 07:02:09 AM UTC 24
Peak memory	254684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496709152 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.1496709152
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/2.rv_dm_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all.399169429
Short name	T71
Test name
Test status
Simulation time	5438804209 ps
CPU time	8.45 seconds
Started	Aug 27 07:02:06 AM UTC 24
Finished	Aug 27 07:02:16 AM UTC 24
Peak memory	216088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399169429 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.399169429
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/2.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.3799744192
Short name	T81
Test name
Test status
Simulation time	8429754277 ps
CPU time	58.06 seconds
Started	Aug 27 07:02:06 AM UTC 24
Finished	Aug 27 07:03:06 AM UTC 24
Peak memory	233332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3799744192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stres s_all_with_rand_reset.3799744192
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/20.rv_dm_alert_test.203158283
Short name	T238
Test name
Test status
Simulation time	29983230 ps
CPU time	0.89 seconds
Started	Aug 27 07:02:37 AM UTC 24
Finished	Aug 27 07:02:39 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203158283 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.203158283
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/20.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.3135937846
Short name	T312
Test name
Test status
Simulation time	1110715970 ps
CPU time	5.05 seconds
Started	Aug 27 07:02:37 AM UTC 24
Finished	Aug 27 07:02:43 AM UTC 24
Peak memory	216020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135937846 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.3135937846
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/20.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/21.rv_dm_alert_test.2734557100
Short name	T298
Test name
Test status
Simulation time	37862656 ps
CPU time	1.11 seconds
Started	Aug 27 07:02:37 AM UTC 24
Finished	Aug 27 07:02:39 AM UTC 24
Peak memory	215368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734557100 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.2734557100
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/21.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/21.rv_dm_stress_all.2577216603
Short name	T232
Test name
Test status
Simulation time	2358629557 ps
CPU time	5.05 seconds
Started	Aug 27 07:02:37 AM UTC 24
Finished	Aug 27 07:02:43 AM UTC 24
Peak memory	226332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577216603 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.2577216603
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/21.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/22.rv_dm_alert_test.3124412402
Short name	T299
Test name
Test status
Simulation time	60233594 ps
CPU time	1.25 seconds
Started	Aug 27 07:02:37 AM UTC 24
Finished	Aug 27 07:02:40 AM UTC 24
Peak memory	215876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124412402 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.3124412402
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/22.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.4287163336
Short name	T334
Test name
Test status
Simulation time	10871393865 ps
CPU time	27.41 seconds
Started	Aug 27 07:02:37 AM UTC 24
Finished	Aug 27 07:03:06 AM UTC 24
Peak memory	226304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287163336 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.4287163336
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/22.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/23.rv_dm_alert_test.3775149732
Short name	T275
Test name
Test status
Simulation time	123269863 ps
CPU time	0.85 seconds
Started	Aug 27 07:02:39 AM UTC 24
Finished	Aug 27 07:02:40 AM UTC 24
Peak memory	215876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775149732 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.3775149732
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/23.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/23.rv_dm_stress_all.2077391962
Short name	T322
Test name
Test status
Simulation time	3134860661 ps
CPU time	9.1 seconds
Started	Aug 27 07:02:37 AM UTC 24
Finished	Aug 27 07:02:48 AM UTC 24
Peak memory	216212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077391962 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.2077391962
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/23.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/24.rv_dm_alert_test.2961833256
Short name	T229
Test name
Test status
Simulation time	165821212 ps
CPU time	1.11 seconds
Started	Aug 27 07:02:39 AM UTC 24
Finished	Aug 27 07:02:41 AM UTC 24
Peak memory	215876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961833256 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.2961833256
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/24.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/24.rv_dm_stress_all.4054542902
Short name	T315
Test name
Test status
Simulation time	1188396455 ps
CPU time	4.75 seconds
Started	Aug 27 07:02:39 AM UTC 24
Finished	Aug 27 07:02:44 AM UTC 24
Peak memory	216012 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054542902 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.4054542902
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/24.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/25.rv_dm_alert_test.4113072900
Short name	T309
Test name
Test status
Simulation time	154934574 ps
CPU time	1.29 seconds
Started	Aug 27 07:02:40 AM UTC 24
Finished	Aug 27 07:02:42 AM UTC 24
Peak memory	215480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113072900 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.4113072900
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/25.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.2842578806
Short name	T10
Test name
Test status
Simulation time	7968141437 ps
CPU time	7.69 seconds
Started	Aug 27 07:02:39 AM UTC 24
Finished	Aug 27 07:02:47 AM UTC 24
Peak memory	216076 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842578806 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.2842578806
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/25.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/26.rv_dm_alert_test.3028563269
Short name	T306
Test name
Test status
Simulation time	51317432 ps
CPU time	1.03 seconds
Started	Aug 27 07:02:40 AM UTC 24
Finished	Aug 27 07:02:42 AM UTC 24
Peak memory	215772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028563269 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.3028563269
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/26.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/27.rv_dm_alert_test.3795240365
Short name	T274
Test name
Test status
Simulation time	76777858 ps
CPU time	1.04 seconds
Started	Aug 27 07:02:40 AM UTC 24
Finished	Aug 27 07:02:42 AM UTC 24
Peak memory	215876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795240365 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.3795240365
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/27.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.352600508
Short name	T321
Test name
Test status
Simulation time	1615573124 ps
CPU time	6.43 seconds
Started	Aug 27 07:02:40 AM UTC 24
Finished	Aug 27 07:02:47 AM UTC 24
Peak memory	226268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352600508 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.352600508
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/27.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/28.rv_dm_alert_test.1961535908
Short name	T307
Test name
Test status
Simulation time	40932981 ps
CPU time	1.02 seconds
Started	Aug 27 07:02:40 AM UTC 24
Finished	Aug 27 07:02:42 AM UTC 24
Peak memory	215876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961535908 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.1961535908
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/28.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/28.rv_dm_stress_all.2699055929
Short name	T198
Test name
Test status
Simulation time	1912789630 ps
CPU time	4.1 seconds
Started	Aug 27 07:02:40 AM UTC 24
Finished	Aug 27 07:02:45 AM UTC 24
Peak memory	226252 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699055929 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.2699055929
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/28.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/29.rv_dm_alert_test.4084216640
Short name	T253
Test name
Test status
Simulation time	35276132 ps
CPU time	1.05 seconds
Started	Aug 27 07:02:41 AM UTC 24
Finished	Aug 27 07:02:43 AM UTC 24
Peak memory	215876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084216640 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.4084216640
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/29.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.1676434242
Short name	T98
Test name
Test status
Simulation time	57852836 ps
CPU time	0.91 seconds
Started	Aug 27 07:02:08 AM UTC 24
Finished	Aug 27 07:02:10 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676434242 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.1676434242
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/3.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.1749935715
Short name	T23
Test name
Test status
Simulation time	2799814523 ps
CPU time	5.8 seconds
Started	Aug 27 07:02:07 AM UTC 24
Finished	Aug 27 07:02:14 AM UTC 24
Peak memory	226432 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749935715 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.1749935715
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/3.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.3875166013
Short name	T139
Test name
Test status
Simulation time	6774104496 ps
CPU time	4.98 seconds
Started	Aug 27 07:02:06 AM UTC 24
Finished	Aug 27 07:02:12 AM UTC 24
Peak memory	226512 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875166013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.3875166013
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/3.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.2684376148
Short name	T73
Test name
Test status
Simulation time	213380841 ps
CPU time	1.2 seconds
Started	Aug 27 07:02:07 AM UTC 24
Finished	Aug 27 07:02:10 AM UTC 24
Peak memory	252360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684376148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_buffered_enable.2684376148
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/3.rv_dm_buffered_enable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.756697543
Short name	T121
Test name
Test status
Simulation time	3900965959 ps
CPU time	11.83 seconds
Started	Aug 27 07:02:06 AM UTC 24
Finished	Aug 27 07:02:19 AM UTC 24
Peak memory	216200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756697543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_tl_access.756697543
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.1033490940
Short name	T70
Test name
Test status
Simulation time	756632524 ps
CPU time	1.34 seconds
Started	Aug 27 07:02:07 AM UTC 24
Finished	Aug 27 07:02:10 AM UTC 24
Peak memory	213452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033490940 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_halt_resume_whereto.1033490940
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/3.rv_dm_halt_resume_whereto/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/3.rv_dm_hart_unavail.1156053553
Short name	T173
Test name
Test status
Simulation time	54775676 ps
CPU time	0.98 seconds
Started	Aug 27 07:02:07 AM UTC 24
Finished	Aug 27 07:02:09 AM UTC 24
Peak memory	213452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156053553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.1156053553
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/3.rv_dm_hart_unavail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.483255255
Short name	T282
Test name
Test status
Simulation time	2299422240 ps
CPU time	7.86 seconds
Started	Aug 27 07:02:06 AM UTC 24
Finished	Aug 27 07:02:15 AM UTC 24
Peak memory	216260 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483255255 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.483255255
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/3.rv_dm_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/3.rv_dm_sec_cm.308233839
Short name	T91
Test name
Test status
Simulation time	570215818 ps
CPU time	3.16 seconds
Started	Aug 27 07:02:08 AM UTC 24
Finished	Aug 27 07:02:12 AM UTC 24
Peak memory	254556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308233839 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.308233839
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/3.rv_dm_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.1544643920
Short name	T85
Test name
Test status
Simulation time	250176870 ps
CPU time	1.48 seconds
Started	Aug 27 07:02:07 AM UTC 24
Finished	Aug 27 07:02:10 AM UTC 24
Peak memory	225308 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544643920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sparse_lc_gate_fsm.1544643920
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/3.rv_dm_sparse_lc_gate_fsm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.3721621539
Short name	T30
Test name
Test status
Simulation time	6171434047 ps
CPU time	19.58 seconds
Started	Aug 27 07:02:07 AM UTC 24
Finished	Aug 27 07:02:28 AM UTC 24
Peak memory	226384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721621539 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.3721621539
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/3.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/30.rv_dm_alert_test.4211072080
Short name	T242
Test name
Test status
Simulation time	54234982 ps
CPU time	1 seconds
Started	Aug 27 07:02:41 AM UTC 24
Finished	Aug 27 07:02:43 AM UTC 24
Peak memory	215876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211072080 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.4211072080
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/30.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.1989321541
Short name	T17
Test name
Test status
Simulation time	2511912332 ps
CPU time	8.8 seconds
Started	Aug 27 07:02:41 AM UTC 24
Finished	Aug 27 07:02:51 AM UTC 24
Peak memory	216128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989321541 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.1989321541
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/30.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/31.rv_dm_alert_test.120751859
Short name	T313
Test name
Test status
Simulation time	32319536 ps
CPU time	1.04 seconds
Started	Aug 27 07:02:41 AM UTC 24
Finished	Aug 27 07:02:43 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120751859 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.120751859
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/31.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/31.rv_dm_stress_all.560849305
Short name	T201
Test name
Test status
Simulation time	2207752906 ps
CPU time	2.35 seconds
Started	Aug 27 07:02:41 AM UTC 24
Finished	Aug 27 07:02:45 AM UTC 24
Peak memory	215996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560849305 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.560849305
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/31.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/32.rv_dm_alert_test.3741409644
Short name	T237
Test name
Test status
Simulation time	54685955 ps
CPU time	0.99 seconds
Started	Aug 27 07:02:41 AM UTC 24
Finished	Aug 27 07:02:43 AM UTC 24
Peak memory	215876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741409644 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.3741409644
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/32.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/32.rv_dm_stress_all.3169044891
Short name	T231
Test name
Test status
Simulation time	3703470660 ps
CPU time	12.5 seconds
Started	Aug 27 07:02:41 AM UTC 24
Finished	Aug 27 07:02:55 AM UTC 24
Peak memory	216080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169044891 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.3169044891
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/32.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/33.rv_dm_alert_test.2670729574
Short name	T316
Test name
Test status
Simulation time	56245600 ps
CPU time	1.1 seconds
Started	Aug 27 07:02:43 AM UTC 24
Finished	Aug 27 07:02:45 AM UTC 24
Peak memory	215864 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670729574 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.2670729574
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/33.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.586254555
Short name	T330
Test name
Test status
Simulation time	4904640188 ps
CPU time	16.55 seconds
Started	Aug 27 07:02:43 AM UTC 24
Finished	Aug 27 07:03:00 AM UTC 24
Peak memory	216072 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586254555 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.586254555
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/33.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/34.rv_dm_alert_test.519701585
Short name	T267
Test name
Test status
Simulation time	42676117 ps
CPU time	1.14 seconds
Started	Aug 27 07:02:43 AM UTC 24
Finished	Aug 27 07:02:45 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519701585 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.519701585
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/34.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/34.rv_dm_stress_all.1864777315
Short name	T39
Test name
Test status
Simulation time	3628917622 ps
CPU time	3.04 seconds
Started	Aug 27 07:02:43 AM UTC 24
Finished	Aug 27 07:02:47 AM UTC 24
Peak memory	216128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864777315 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.1864777315
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/34.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/35.rv_dm_alert_test.1579728299
Short name	T258
Test name
Test status
Simulation time	39385394 ps
CPU time	0.82 seconds
Started	Aug 27 07:02:43 AM UTC 24
Finished	Aug 27 07:02:45 AM UTC 24
Peak memory	215876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579728299 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.1579728299
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/35.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/35.rv_dm_stress_all.1875789951
Short name	T38
Test name
Test status
Simulation time	7488927089 ps
CPU time	6.91 seconds
Started	Aug 27 07:02:43 AM UTC 24
Finished	Aug 27 07:02:51 AM UTC 24
Peak memory	226392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875789951 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.1875789951
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/35.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/36.rv_dm_alert_test.2547303832
Short name	T251
Test name
Test status
Simulation time	219581474 ps
CPU time	0.79 seconds
Started	Aug 27 07:02:43 AM UTC 24
Finished	Aug 27 07:02:45 AM UTC 24
Peak memory	215876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547303832 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.2547303832
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/36.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/36.rv_dm_stress_all.2036101813
Short name	T328
Test name
Test status
Simulation time	8890990743 ps
CPU time	8.61 seconds
Started	Aug 27 07:02:43 AM UTC 24
Finished	Aug 27 07:02:52 AM UTC 24
Peak memory	216084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036101813 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.2036101813
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/36.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/37.rv_dm_alert_test.1031516529
Short name	T318
Test name
Test status
Simulation time	29014983 ps
CPU time	1.07 seconds
Started	Aug 27 07:02:44 AM UTC 24
Finished	Aug 27 07:02:46 AM UTC 24
Peak memory	215876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031516529 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.1031516529
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/37.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/37.rv_dm_stress_all.413284169
Short name	T266
Test name
Test status
Simulation time	3481590553 ps
CPU time	5.15 seconds
Started	Aug 27 07:02:43 AM UTC 24
Finished	Aug 27 07:02:49 AM UTC 24
Peak memory	226380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413284169 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.413284169
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/37.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/38.rv_dm_alert_test.1651286898
Short name	T317
Test name
Test status
Simulation time	129182874 ps
CPU time	0.9 seconds
Started	Aug 27 07:02:44 AM UTC 24
Finished	Aug 27 07:02:46 AM UTC 24
Peak memory	215660 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651286898 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.1651286898
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/38.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/38.rv_dm_stress_all.3004319620
Short name	T326
Test name
Test status
Simulation time	2120852741 ps
CPU time	4.58 seconds
Started	Aug 27 07:02:44 AM UTC 24
Finished	Aug 27 07:02:50 AM UTC 24
Peak memory	216140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004319620 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.3004319620
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/38.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/39.rv_dm_alert_test.1679153297
Short name	T271
Test name
Test status
Simulation time	52588815 ps
CPU time	0.76 seconds
Started	Aug 27 07:02:44 AM UTC 24
Finished	Aug 27 07:02:46 AM UTC 24
Peak memory	215876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679153297 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.1679153297
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/39.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/39.rv_dm_stress_all.1139815081
Short name	T230
Test name
Test status
Simulation time	3321448151 ps
CPU time	7.19 seconds
Started	Aug 27 07:02:44 AM UTC 24
Finished	Aug 27 07:02:52 AM UTC 24
Peak memory	226176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139815081 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.1139815081
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/39.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/4.rv_dm_alert_test.2740199906
Short name	T175
Test name
Test status
Simulation time	101985090 ps
CPU time	0.98 seconds
Started	Aug 27 07:02:10 AM UTC 24
Finished	Aug 27 07:02:12 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740199906 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.2740199906
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/4.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/4.rv_dm_autoincr_sba_tl_access.3011913905
Short name	T22
Test name
Test status
Simulation time	3296427880 ps
CPU time	2.33 seconds
Started	Aug 27 07:02:09 AM UTC 24
Finished	Aug 27 07:02:12 AM UTC 24
Peak memory	226504 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011913905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.3011913905
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/4.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/4.rv_dm_bad_sba_tl_access.466993913
Short name	T199
Test name
Test status
Simulation time	2646861343 ps
CPU time	2.8 seconds
Started	Aug 27 07:02:09 AM UTC 24
Finished	Aug 27 07:02:13 AM UTC 24
Peak memory	216208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466993913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.466993913
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/4.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/4.rv_dm_buffered_enable.3440065922
Short name	T140
Test name
Test status
Simulation time	113321474 ps
CPU time	1.14 seconds
Started	Aug 27 07:02:10 AM UTC 24
Finished	Aug 27 07:02:12 AM UTC 24
Peak memory	259932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440065922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_buffered_enable.3440065922
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/4.rv_dm_buffered_enable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3736032886
Short name	T254
Test name
Test status
Simulation time	4038208674 ps
CPU time	5.46 seconds
Started	Aug 27 07:02:09 AM UTC 24
Finished	Aug 27 07:02:15 AM UTC 24
Peak memory	226492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736032886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_tl_access.3736032886
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.501449990
Short name	T59
Test name
Test status
Simulation time	290774074 ps
CPU time	1.38 seconds
Started	Aug 27 07:02:09 AM UTC 24
Finished	Aug 27 07:02:11 AM UTC 24
Peak memory	213456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501449990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_halt_resume_whereto.501449990
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/4.rv_dm_halt_resume_whereto/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.3257460841
Short name	T281
Test name
Test status
Simulation time	348593194 ps
CPU time	1.3 seconds
Started	Aug 27 07:02:09 AM UTC 24
Finished	Aug 27 07:02:11 AM UTC 24
Peak memory	215932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257460841 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.3257460841
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/4.rv_dm_hart_unavail/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/4.rv_dm_sba_tl_access.641343636
Short name	T200
Test name
Test status
Simulation time	12908558402 ps
CPU time	17.8 seconds
Started	Aug 27 07:02:09 AM UTC 24
Finished	Aug 27 07:02:28 AM UTC 24
Peak memory	216272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641343636 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.641343636
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/4.rv_dm_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/4.rv_dm_sec_cm.476832616
Short name	T92
Test name
Test status
Simulation time	300267642 ps
CPU time	1.39 seconds
Started	Aug 27 07:02:10 AM UTC 24
Finished	Aug 27 07:02:13 AM UTC 24
Peak memory	251516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476832616 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.476832616
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/4.rv_dm_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.1143386921
Short name	T211
Test name
Test status
Simulation time	2429075581 ps
CPU time	5.3 seconds
Started	Aug 27 07:02:10 AM UTC 24
Finished	Aug 27 07:02:17 AM UTC 24
Peak memory	216128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143386921 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.1143386921
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/4.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.385031103
Short name	T120
Test name
Test status
Simulation time	4116167273 ps
CPU time	88.59 seconds
Started	Aug 27 07:02:10 AM UTC 24
Finished	Aug 27 07:03:41 AM UTC 24
Peak memory	233332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=385031103 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress _all_with_rand_reset.385031103
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/40.rv_dm_alert_test.881204458
Short name	T319
Test name
Test status
Simulation time	73432000 ps
CPU time	0.96 seconds
Started	Aug 27 07:02:44 AM UTC 24
Finished	Aug 27 07:02:46 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881204458 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.881204458
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/40.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/40.rv_dm_stress_all.1094890063
Short name	T327
Test name
Test status
Simulation time	775437672 ps
CPU time	4.85 seconds
Started	Aug 27 07:02:44 AM UTC 24
Finished	Aug 27 07:02:50 AM UTC 24
Peak memory	215868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094890063 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.1094890063
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/40.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/41.rv_dm_alert_test.628461359
Short name	T320
Test name
Test status
Simulation time	57320342 ps
CPU time	0.96 seconds
Started	Aug 27 07:02:44 AM UTC 24
Finished	Aug 27 07:02:46 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628461359 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.628461359
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/41.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/41.rv_dm_stress_all.2168123718
Short name	T269
Test name
Test status
Simulation time	3233364800 ps
CPU time	4.08 seconds
Started	Aug 27 07:02:44 AM UTC 24
Finished	Aug 27 07:02:49 AM UTC 24
Peak memory	216088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168123718 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.2168123718
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/41.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/42.rv_dm_alert_test.1164135789
Short name	T241
Test name
Test status
Simulation time	30784678 ps
CPU time	1.08 seconds
Started	Aug 27 07:02:44 AM UTC 24
Finished	Aug 27 07:02:47 AM UTC 24
Peak memory	215876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164135789 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.1164135789
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/42.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/42.rv_dm_stress_all.3100785605
Short name	T207
Test name
Test status
Simulation time	4379750204 ps
CPU time	4.38 seconds
Started	Aug 27 07:02:44 AM UTC 24
Finished	Aug 27 07:02:50 AM UTC 24
Peak memory	226380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100785605 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.3100785605
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/42.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/43.rv_dm_alert_test.3293441870
Short name	T252
Test name
Test status
Simulation time	120608062 ps
CPU time	1.13 seconds
Started	Aug 27 07:02:46 AM UTC 24
Finished	Aug 27 07:02:48 AM UTC 24
Peak memory	215876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293441870 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.3293441870
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/43.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/43.rv_dm_stress_all.2007531059
Short name	T268
Test name
Test status
Simulation time	2917366282 ps
CPU time	10.56 seconds
Started	Aug 27 07:02:46 AM UTC 24
Finished	Aug 27 07:02:58 AM UTC 24
Peak memory	226304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007531059 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.2007531059
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/43.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/44.rv_dm_alert_test.1087026974
Short name	T261
Test name
Test status
Simulation time	81803584 ps
CPU time	1.02 seconds
Started	Aug 27 07:02:46 AM UTC 24
Finished	Aug 27 07:02:48 AM UTC 24
Peak memory	215804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087026974 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.1087026974
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/44.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.3831054076
Short name	T259
Test name
Test status
Simulation time	2555081167 ps
CPU time	1.57 seconds
Started	Aug 27 07:02:46 AM UTC 24
Finished	Aug 27 07:02:49 AM UTC 24
Peak memory	215996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831054076 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.3831054076
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/44.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/45.rv_dm_alert_test.1724759865
Short name	T324
Test name
Test status
Simulation time	62107523 ps
CPU time	1.11 seconds
Started	Aug 27 07:02:46 AM UTC 24
Finished	Aug 27 07:02:48 AM UTC 24
Peak memory	215876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724759865 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.1724759865
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/45.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/45.rv_dm_stress_all.1285013610
Short name	T213
Test name
Test status
Simulation time	3148637335 ps
CPU time	9.27 seconds
Started	Aug 27 07:02:46 AM UTC 24
Finished	Aug 27 07:02:57 AM UTC 24
Peak memory	226312 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285013610 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.1285013610
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/45.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/46.rv_dm_alert_test.3370045028
Short name	T323
Test name
Test status
Simulation time	150902803 ps
CPU time	1.06 seconds
Started	Aug 27 07:02:46 AM UTC 24
Finished	Aug 27 07:02:48 AM UTC 24
Peak memory	215796 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370045028 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3370045028
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/46.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.3604880537
Short name	T256
Test name
Test status
Simulation time	1275797948 ps
CPU time	2.24 seconds
Started	Aug 27 07:02:46 AM UTC 24
Finished	Aug 27 07:02:49 AM UTC 24
Peak memory	216012 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604880537 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.3604880537
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/46.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/47.rv_dm_alert_test.831819723
Short name	T233
Test name
Test status
Simulation time	53552521 ps
CPU time	0.87 seconds
Started	Aug 27 07:02:46 AM UTC 24
Finished	Aug 27 07:02:48 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831819723 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.831819723
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/47.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/47.rv_dm_stress_all.1615545128
Short name	T332
Test name
Test status
Simulation time	5904991865 ps
CPU time	15.17 seconds
Started	Aug 27 07:02:46 AM UTC 24
Finished	Aug 27 07:03:02 AM UTC 24
Peak memory	216136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615545128 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.1615545128
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/47.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/48.rv_dm_alert_test.364230192
Short name	T325
Test name
Test status
Simulation time	116868790 ps
CPU time	1.06 seconds
Started	Aug 27 07:02:47 AM UTC 24
Finished	Aug 27 07:02:49 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364230192 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.364230192
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/48.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/48.rv_dm_stress_all.3522560815
Short name	T331
Test name
Test status
Simulation time	10855305081 ps
CPU time	13.39 seconds
Started	Aug 27 07:02:47 AM UTC 24
Finished	Aug 27 07:03:02 AM UTC 24
Peak memory	216144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522560815 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.3522560815
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/48.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/49.rv_dm_alert_test.1317309908
Short name	T240
Test name
Test status
Simulation time	33236901 ps
CPU time	0.85 seconds
Started	Aug 27 07:02:47 AM UTC 24
Finished	Aug 27 07:02:49 AM UTC 24
Peak memory	215876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317309908 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.1317309908
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/49.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/49.rv_dm_stress_all.4256101214
Short name	T329
Test name
Test status
Simulation time	4212168260 ps
CPU time	5.3 seconds
Started	Aug 27 07:02:47 AM UTC 24
Finished	Aug 27 07:02:54 AM UTC 24
Peak memory	216012 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256101214 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.4256101214
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/49.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/5.rv_dm_alert_test.1727263063
Short name	T176
Test name
Test status
Simulation time	27169545 ps
CPU time	1.03 seconds
Started	Aug 27 07:02:12 AM UTC 24
Finished	Aug 27 07:02:14 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727263063 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.1727263063
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/5.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.644904637
Short name	T300
Test name
Test status
Simulation time	15785469479 ps
CPU time	28.27 seconds
Started	Aug 27 07:02:10 AM UTC 24
Finished	Aug 27 07:02:40 AM UTC 24
Peak memory	233328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644904637 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.644904637
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/5.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.3857882645
Short name	T197
Test name
Test status
Simulation time	13796889582 ps
CPU time	20.67 seconds
Started	Aug 27 07:02:10 AM UTC 24
Finished	Aug 27 07:02:32 AM UTC 24
Peak memory	216260 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857882645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.3857882645
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/5.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/5.rv_dm_buffered_enable.1229730633
Short name	T226
Test name
Test status
Simulation time	589598103 ps
CPU time	1.46 seconds
Started	Aug 27 07:02:11 AM UTC 24
Finished	Aug 27 07:02:14 AM UTC 24
Peak memory	256816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229730633 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_buffered_enable.1229730633
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/5.rv_dm_buffered_enable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.65340445
Short name	T235
Test name
Test status
Simulation time	2457994043 ps
CPU time	3.6 seconds
Started	Aug 27 07:02:10 AM UTC 24
Finished	Aug 27 07:02:15 AM UTC 24
Peak memory	216236 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65340445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl_access.65340445
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/5.rv_dm_halt_resume_whereto.899214037
Short name	T228
Test name
Test status
Simulation time	866521651 ps
CPU time	3.09 seconds
Started	Aug 27 07:02:10 AM UTC 24
Finished	Aug 27 07:02:15 AM UTC 24
Peak memory	215932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899214037 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_halt_resume_whereto.899214037
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/5.rv_dm_halt_resume_whereto/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/5.rv_dm_sba_tl_access.3310429164
Short name	T239
Test name
Test status
Simulation time	1217698514 ps
CPU time	2.06 seconds
Started	Aug 27 07:02:10 AM UTC 24
Finished	Aug 27 07:02:13 AM UTC 24
Peak memory	216204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310429164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.3310429164
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/5.rv_dm_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.1116314822
Short name	T77
Test name
Test status
Simulation time	50064620652 ps
CPU time	59.24 seconds
Started	Aug 27 07:02:12 AM UTC 24
Finished	Aug 27 07:03:12 AM UTC 24
Peak memory	233124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1116314822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stres s_all_with_rand_reset.1116314822
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/6.rv_dm_alert_test.3099695380
Short name	T177
Test name
Test status
Simulation time	43643128 ps
CPU time	1.07 seconds
Started	Aug 27 07:02:13 AM UTC 24
Finished	Aug 27 07:02:15 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099695380 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.3099695380
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/6.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/6.rv_dm_autoincr_sba_tl_access.928511547
Short name	T341
Test name
Test status
Simulation time	187002641093 ps
CPU time	510.44 seconds
Started	Aug 27 07:02:13 AM UTC 24
Finished	Aug 27 07:10:49 AM UTC 24
Peak memory	228116 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928511547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.928511547
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/6.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/6.rv_dm_bad_sba_tl_access.3962375084
Short name	T202
Test name
Test status
Simulation time	1100708330 ps
CPU time	2.12 seconds
Started	Aug 27 07:02:13 AM UTC 24
Finished	Aug 27 07:02:16 AM UTC 24
Peak memory	216324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962375084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.3962375084
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/6.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/6.rv_dm_buffered_enable.2410708665
Short name	T141
Test name
Test status
Simulation time	584061638 ps
CPU time	3.02 seconds
Started	Aug 27 07:02:13 AM UTC 24
Finished	Aug 27 07:02:17 AM UTC 24
Peak memory	258824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410708665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_buffered_enable.2410708665
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/6.rv_dm_buffered_enable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.3108286045
Short name	T122
Test name
Test status
Simulation time	1858052542 ps
CPU time	6.65 seconds
Started	Aug 27 07:02:12 AM UTC 24
Finished	Aug 27 07:02:19 AM UTC 24
Peak memory	226428 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108286045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_tl_access.3108286045
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/6.rv_dm_halt_resume_whereto.4042350144
Short name	T60
Test name
Test status
Simulation time	1219273540 ps
CPU time	5.25 seconds
Started	Aug 27 07:02:13 AM UTC 24
Finished	Aug 27 07:02:19 AM UTC 24
Peak memory	215804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042350144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_halt_resume_whereto.4042350144
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/6.rv_dm_halt_resume_whereto/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/6.rv_dm_sba_tl_access.1623148688
Short name	T276
Test name
Test status
Simulation time	13277560780 ps
CPU time	37.42 seconds
Started	Aug 27 07:02:12 AM UTC 24
Finished	Aug 27 07:02:50 AM UTC 24
Peak memory	226512 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623148688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.1623148688
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/6.rv_dm_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all.132330847
Short name	T61
Test name
Test status
Simulation time	2805030380 ps
CPU time	9.82 seconds
Started	Aug 27 07:02:13 AM UTC 24
Finished	Aug 27 07:02:24 AM UTC 24
Peak memory	216216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132330847 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.132330847
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/6.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/7.rv_dm_alert_test.3939275016
Short name	T264
Test name
Test status
Simulation time	57402913 ps
CPU time	1.07 seconds
Started	Aug 27 07:02:16 AM UTC 24
Finished	Aug 27 07:02:18 AM UTC 24
Peak memory	215872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939275016 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.3939275016
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/7.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.1039523847
Short name	T294
Test name
Test status
Simulation time	22084209055 ps
CPU time	19.5 seconds
Started	Aug 27 07:02:14 AM UTC 24
Finished	Aug 27 07:02:35 AM UTC 24
Peak memory	233176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039523847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.1039523847
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/7.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.1900677487
Short name	T283
Test name
Test status
Simulation time	4337516295 ps
CPU time	8.94 seconds
Started	Aug 27 07:02:14 AM UTC 24
Finished	Aug 27 07:02:24 AM UTC 24
Peak memory	226560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900677487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.1900677487
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/7.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/7.rv_dm_buffered_enable.1836352550
Short name	T196
Test name
Test status
Simulation time	496303663 ps
CPU time	2.46 seconds
Started	Aug 27 07:02:14 AM UTC 24
Finished	Aug 27 07:02:18 AM UTC 24
Peak memory	252600 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836352550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_buffered_enable.1836352550
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/7.rv_dm_buffered_enable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.843792416
Short name	T227
Test name
Test status
Simulation time	194166570 ps
CPU time	1.13 seconds
Started	Aug 27 07:02:14 AM UTC 24
Finished	Aug 27 07:02:16 AM UTC 24
Peak memory	213456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843792416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_halt_resume_whereto.843792416
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/7.rv_dm_halt_resume_whereto/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/7.rv_dm_sba_tl_access.2591946832
Short name	T209
Test name
Test status
Simulation time	10615721609 ps
CPU time	9.31 seconds
Started	Aug 27 07:02:13 AM UTC 24
Finished	Aug 27 07:02:23 AM UTC 24
Peak memory	226444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591946832 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.2591946832
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/7.rv_dm_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all.3619438408
Short name	T125
Test name
Test status
Simulation time	1518840384 ps
CPU time	4.08 seconds
Started	Aug 27 07:02:14 AM UTC 24
Finished	Aug 27 07:02:20 AM UTC 24
Peak memory	226056 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619438408 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.3619438408
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/7.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.4218560304
Short name	T72
Test name
Test status
Simulation time	1194587368 ps
CPU time	17.32 seconds
Started	Aug 27 07:02:16 AM UTC 24
Finished	Aug 27 07:02:34 AM UTC 24
Peak memory	228564 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=4218560304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stres s_all_with_rand_reset.4218560304
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/8.rv_dm_alert_test.2404787895
Short name	T123
Test name
Test status
Simulation time	144951717 ps
CPU time	1.49 seconds
Started	Aug 27 07:02:17 AM UTC 24
Finished	Aug 27 07:02:19 AM UTC 24
Peak memory	215876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404787895 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.2404787895
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/8.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.775028328
Short name	T127
Test name
Test status
Simulation time	4592172974 ps
CPU time	4.76 seconds
Started	Aug 27 07:02:16 AM UTC 24
Finished	Aug 27 07:02:22 AM UTC 24
Peak memory	226564 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775028328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.775028328
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/8.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/8.rv_dm_bad_sba_tl_access.3873088136
Short name	T247
Test name
Test status
Simulation time	4923037528 ps
CPU time	5.6 seconds
Started	Aug 27 07:02:16 AM UTC 24
Finished	Aug 27 07:02:22 AM UTC 24
Peak memory	226632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873088136 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.3873088136
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/8.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/8.rv_dm_buffered_enable.2758768132
Short name	T65
Test name
Test status
Simulation time	290796337 ps
CPU time	1.42 seconds
Started	Aug 27 07:02:16 AM UTC 24
Finished	Aug 27 07:02:18 AM UTC 24
Peak memory	258792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758768132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_buffered_enable.2758768132
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/8.rv_dm_buffered_enable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.805624046
Short name	T285
Test name
Test status
Simulation time	10101965214 ps
CPU time	8.2 seconds
Started	Aug 27 07:02:16 AM UTC 24
Finished	Aug 27 07:02:25 AM UTC 24
Peak memory	216180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805624046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl_access.805624046
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/8.rv_dm_sba_tl_access.1195394169
Short name	T291
Test name
Test status
Simulation time	10892929953 ps
CPU time	17.55 seconds
Started	Aug 27 07:02:16 AM UTC 24
Finished	Aug 27 07:02:34 AM UTC 24
Peak memory	226512 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195394169 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.1195394169
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/8.rv_dm_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.2108848232
Short name	T128
Test name
Test status
Simulation time	2316178545 ps
CPU time	3.72 seconds
Started	Aug 27 07:02:17 AM UTC 24
Finished	Aug 27 07:02:22 AM UTC 24
Peak memory	226328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108848232 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.2108848232
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/8.rv_dm_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.2144700056
Short name	T119
Test name
Test status
Simulation time	3441710344 ps
CPU time	57.77 seconds
Started	Aug 27 07:02:17 AM UTC 24
Finished	Aug 27 07:03:16 AM UTC 24
Peak memory	233332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2144700056 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stres s_all_with_rand_reset.2144700056
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.635972304
Short name	T126
Test name
Test status
Simulation time	80745933 ps
CPU time	1.04 seconds
Started	Aug 27 07:02:19 AM UTC 24
Finished	Aug 27 07:02:21 AM UTC 24
Peak memory	215996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635972304 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.635972304
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/9.rv_dm_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.3289168412
Short name	T255
Test name
Test status
Simulation time	2166897065 ps
CPU time	2.73 seconds
Started	Aug 27 07:02:18 AM UTC 24
Finished	Aug 27 07:02:22 AM UTC 24
Peak memory	226436 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289168412 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.3289168412
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/9.rv_dm_bad_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/9.rv_dm_buffered_enable.3799796600
Short name	T74
Test name
Test status
Simulation time	782425760 ps
CPU time	2.35 seconds
Started	Aug 27 07:02:18 AM UTC 24
Finished	Aug 27 07:02:22 AM UTC 24
Peak memory	252700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799796600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_buffered_enable.3799796600
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/9.rv_dm_buffered_enable/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.2010681023
Short name	T191
Test name
Test status
Simulation time	2694787166 ps
CPU time	13.23 seconds
Started	Aug 27 07:02:17 AM UTC 24
Finished	Aug 27 07:02:32 AM UTC 24
Peak memory	216384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010681023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_tl_access.2010681023
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.3890257020
Short name	T270
Test name
Test status
Simulation time	1415875693 ps
CPU time	4.06 seconds
Started	Aug 27 07:02:17 AM UTC 24
Finished	Aug 27 07:02:22 AM UTC 24
Peak memory	216268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890257020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.3890257020
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/9.rv_dm_sba_tl_access/latest