| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 88.80 | 96.32 | 89.67 | 92.10 | 93.33 | 90.44 | 98.53 | 61.18 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 54.75 | 54.75 | 84.79 | 84.79 | 50.50 | 50.50 | 32.56 | 32.56 | 53.33 | 53.33 | 65.36 | 65.36 | 93.59 | 93.59 | 3.16 | 3.16 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.3691935093 |
| 63.93 | 9.18 | 85.54 | 0.76 | 57.28 | 6.79 | 33.91 | 1.34 | 58.67 | 5.33 | 69.45 | 4.10 | 94.64 | 1.05 | 48.01 | 44.86 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.2234912143 |
| 72.58 | 8.65 | 89.82 | 4.28 | 69.17 | 11.88 | 59.24 | 25.34 | 65.33 | 6.67 | 77.99 | 8.53 | 95.90 | 1.26 | 50.62 | 2.61 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.3937934731 |
| 78.62 | 6.03 | 90.78 | 0.96 | 74.68 | 5.52 | 83.15 | 23.91 | 74.67 | 9.33 | 80.38 | 2.39 | 95.90 | 0.00 | 50.75 | 0.14 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.3643562403 |
| 81.02 | 2.41 | 92.44 | 1.66 | 78.36 | 3.68 | 84.08 | 0.92 | 81.33 | 6.67 | 83.79 | 3.41 | 96.00 | 0.11 | 51.17 | 0.41 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.1506988820 |
| 82.08 | 1.06 | 92.54 | 0.10 | 79.92 | 1.56 | 86.01 | 1.93 | 81.33 | 0.00 | 84.30 | 0.51 | 96.00 | 0.00 | 54.46 | 3.29 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1191815713 |
| 82.90 | 0.82 | 92.75 | 0.20 | 80.62 | 0.71 | 86.01 | 0.00 | 85.33 | 4.00 | 84.64 | 0.34 | 96.21 | 0.21 | 54.73 | 0.27 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.3656027746 |
| 83.47 | 0.57 | 93.45 | 0.71 | 81.47 | 0.85 | 86.13 | 0.13 | 86.67 | 1.33 | 85.49 | 0.85 | 96.21 | 0.00 | 54.87 | 0.14 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.3818565123 |
| 83.98 | 0.51 | 93.95 | 0.50 | 82.32 | 0.85 | 86.18 | 0.04 | 88.00 | 1.33 | 86.35 | 0.85 | 96.21 | 0.00 | 54.87 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.325383587 |
| 84.44 | 0.45 | 94.41 | 0.45 | 83.31 | 0.99 | 86.85 | 0.67 | 88.00 | 0.00 | 86.86 | 0.51 | 96.21 | 0.00 | 55.42 | 0.55 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.885253560 |
| 84.88 | 0.45 | 94.41 | 0.00 | 83.31 | 0.00 | 89.71 | 2.86 | 88.00 | 0.00 | 86.86 | 0.00 | 96.21 | 0.00 | 55.69 | 0.27 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/9.rv_dm_autoincr_sba_tl_access.3133181272 |
| 85.32 | 0.43 | 94.66 | 0.25 | 83.73 | 0.42 | 90.38 | 0.67 | 89.33 | 1.33 | 87.20 | 0.34 | 96.21 | 0.00 | 55.69 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.3928692034 |
| 85.70 | 0.38 | 94.66 | 0.00 | 83.73 | 0.00 | 90.38 | 0.00 | 92.00 | 2.67 | 87.20 | 0.00 | 96.21 | 0.00 | 55.69 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.2755136919 |
| 86.02 | 0.32 | 94.66 | 0.00 | 86.00 | 2.26 | 90.38 | 0.00 | 92.00 | 0.00 | 87.20 | 0.00 | 96.21 | 0.00 | 55.69 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.2158594046 |
| 86.31 | 0.29 | 95.21 | 0.55 | 86.56 | 0.57 | 90.38 | 0.00 | 92.00 | 0.00 | 87.54 | 0.34 | 96.21 | 0.00 | 56.24 | 0.55 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/29.rv_dm_stress_all.2828708779 |
| 86.58 | 0.28 | 95.47 | 0.25 | 87.27 | 0.71 | 90.84 | 0.46 | 92.00 | 0.00 | 88.05 | 0.51 | 96.21 | 0.00 | 56.24 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.2357565840 |
| 86.79 | 0.20 | 95.52 | 0.05 | 87.41 | 0.14 | 91.05 | 0.21 | 92.00 | 0.00 | 88.40 | 0.34 | 96.21 | 0.00 | 56.93 | 0.69 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/15.rv_dm_autoincr_sba_tl_access.973612838 |
| 86.98 | 0.19 | 95.52 | 0.00 | 87.41 | 0.00 | 91.05 | 0.00 | 93.33 | 1.33 | 88.40 | 0.00 | 96.21 | 0.00 | 56.93 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2038128062 |
| 87.17 | 0.19 | 95.67 | 0.15 | 87.98 | 0.57 | 91.22 | 0.17 | 93.33 | 0.00 | 88.57 | 0.17 | 96.21 | 0.00 | 57.20 | 0.27 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.241188201 |
| 87.31 | 0.14 | 95.67 | 0.00 | 88.40 | 0.42 | 91.39 | 0.17 | 93.33 | 0.00 | 88.57 | 0.00 | 96.32 | 0.11 | 57.48 | 0.27 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.2405941330 |
| 87.45 | 0.14 | 95.87 | 0.20 | 88.83 | 0.42 | 91.39 | 0.00 | 93.33 | 0.00 | 88.91 | 0.34 | 96.32 | 0.00 | 57.48 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/26.rv_dm_stress_all.493249243 |
| 87.58 | 0.14 | 95.87 | 0.00 | 88.83 | 0.00 | 91.39 | 0.00 | 93.33 | 0.00 | 88.91 | 0.00 | 96.32 | 0.00 | 58.44 | 0.96 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1222073771 |
| 87.72 | 0.14 | 95.87 | 0.00 | 88.83 | 0.00 | 91.39 | 0.00 | 93.33 | 0.00 | 88.91 | 0.00 | 97.27 | 0.95 | 58.44 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3381286394 |
| 87.85 | 0.13 | 95.97 | 0.10 | 88.97 | 0.14 | 91.47 | 0.08 | 93.33 | 0.00 | 89.08 | 0.17 | 97.27 | 0.00 | 58.85 | 0.41 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.775974078 |
| 87.96 | 0.12 | 96.02 | 0.05 | 89.11 | 0.14 | 91.47 | 0.00 | 93.33 | 0.00 | 89.42 | 0.34 | 97.27 | 0.00 | 59.12 | 0.27 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.1227799408 |
| 88.08 | 0.12 | 96.17 | 0.15 | 89.11 | 0.00 | 91.68 | 0.21 | 93.33 | 0.00 | 89.59 | 0.17 | 97.27 | 0.00 | 59.40 | 0.27 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_ndmreset_req.2788432233 |
| 88.16 | 0.08 | 96.17 | 0.00 | 89.11 | 0.00 | 91.81 | 0.13 | 93.33 | 0.00 | 89.76 | 0.17 | 97.27 | 0.00 | 59.67 | 0.27 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.1324207543 |
| 88.23 | 0.07 | 96.22 | 0.05 | 89.25 | 0.14 | 91.81 | 0.00 | 93.33 | 0.00 | 89.93 | 0.17 | 97.27 | 0.00 | 59.81 | 0.14 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all_with_rand_reset.693719702 |
| 88.29 | 0.06 | 96.22 | 0.00 | 89.25 | 0.00 | 91.81 | 0.00 | 93.33 | 0.00 | 89.93 | 0.00 | 97.69 | 0.42 | 59.81 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2961901294 |
| 88.35 | 0.06 | 96.22 | 0.00 | 89.25 | 0.00 | 91.81 | 0.00 | 93.33 | 0.00 | 89.93 | 0.00 | 98.11 | 0.42 | 59.81 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2011147638 |
| 88.41 | 0.06 | 96.22 | 0.00 | 89.25 | 0.00 | 91.81 | 0.00 | 93.33 | 0.00 | 89.93 | 0.00 | 98.11 | 0.00 | 60.22 | 0.41 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/16.rv_dm_bad_sba_tl_access.321385009 |
| 88.46 | 0.05 | 96.22 | 0.00 | 89.25 | 0.00 | 91.89 | 0.08 | 93.33 | 0.00 | 89.93 | 0.00 | 98.11 | 0.00 | 60.49 | 0.27 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1194513340 |
| 88.51 | 0.04 | 96.22 | 0.00 | 89.39 | 0.14 | 91.89 | 0.00 | 93.33 | 0.00 | 90.10 | 0.17 | 98.11 | 0.00 | 60.49 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.2829416490 |
| 88.55 | 0.04 | 96.22 | 0.00 | 89.53 | 0.14 | 91.89 | 0.00 | 93.33 | 0.00 | 90.10 | 0.00 | 98.11 | 0.00 | 60.63 | 0.14 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.1605579716 |
| 88.58 | 0.04 | 96.22 | 0.00 | 89.53 | 0.00 | 91.89 | 0.00 | 93.33 | 0.00 | 90.10 | 0.00 | 98.11 | 0.00 | 60.91 | 0.27 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_intg_err.126759913 |
| 88.62 | 0.04 | 96.22 | 0.00 | 89.53 | 0.00 | 91.89 | 0.00 | 93.33 | 0.00 | 90.10 | 0.00 | 98.11 | 0.00 | 61.18 | 0.27 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/17.rv_dm_autoincr_sba_tl_access.243665250 |
| 88.66 | 0.03 | 96.27 | 0.05 | 89.53 | 0.00 | 91.89 | 0.00 | 93.33 | 0.00 | 90.27 | 0.17 | 98.11 | 0.00 | 61.18 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.4226433155 |
| 88.69 | 0.03 | 96.32 | 0.05 | 89.53 | 0.00 | 91.89 | 0.00 | 93.33 | 0.00 | 90.44 | 0.17 | 98.11 | 0.00 | 61.18 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.1398442500 |
| 88.72 | 0.03 | 96.32 | 0.00 | 89.53 | 0.00 | 91.89 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 98.32 | 0.21 | 61.18 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2350693436 |
| 88.74 | 0.02 | 96.32 | 0.00 | 89.67 | 0.14 | 91.89 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 98.32 | 0.00 | 61.18 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3980758223 |
| 88.76 | 0.02 | 96.32 | 0.00 | 89.67 | 0.00 | 92.02 | 0.13 | 93.33 | 0.00 | 90.44 | 0.00 | 98.32 | 0.00 | 61.18 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3208932703 |
| 88.77 | 0.02 | 96.32 | 0.00 | 89.67 | 0.00 | 92.02 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 98.42 | 0.11 | 61.18 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.1824526967 |
| 88.79 | 0.02 | 96.32 | 0.00 | 89.67 | 0.00 | 92.02 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 98.53 | 0.11 | 61.18 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/2.rv_dm_sparse_lc_gate_fsm.3428904668 |
| 88.80 | 0.01 | 96.32 | 0.00 | 89.67 | 0.00 | 92.10 | 0.08 | 93.33 | 0.00 | 90.44 | 0.00 | 98.53 | 0.00 | 61.18 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1485441950 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2648784728 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3405368124 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.496858076 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.587057549 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2551378559 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1274969338 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.773656141 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2535478125 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1001583521 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.4052857698 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.2117041026 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1209915906 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3884850844 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.2036603005 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1931454614 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1034906620 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2382347485 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3648104625 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.3761453816 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.79578182 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.331655417 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1521862009 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1693013507 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2560843808 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3639665640 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1339806317 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3289290552 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1753549292 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.4289892775 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.4005801584 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.567741229 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.2224596303 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1242561675 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.1632447764 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2311787718 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2350267161 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1786860245 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.50987588 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.704327933 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_intg_err.4262377451 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1035366334 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_rw.2762164362 |
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| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.3315645180 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/19.rv_dm_bad_sba_tl_access.2825550147 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2357795562 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/19.rv_dm_sba_tl_access.1029585608 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.2519387540 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.997877193 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.3946535725 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.2687829803 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.937431252 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.3808581264 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.2347474575 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.1496709152 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all.399169429 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.3799744192 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/20.rv_dm_alert_test.203158283 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.3135937846 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/21.rv_dm_alert_test.2734557100 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/21.rv_dm_stress_all.2577216603 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/22.rv_dm_alert_test.3124412402 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.4287163336 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/23.rv_dm_alert_test.3775149732 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/23.rv_dm_stress_all.2077391962 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/24.rv_dm_alert_test.2961833256 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/24.rv_dm_stress_all.4054542902 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/25.rv_dm_alert_test.4113072900 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.2842578806 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/26.rv_dm_alert_test.3028563269 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/27.rv_dm_alert_test.3795240365 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.352600508 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/28.rv_dm_alert_test.1961535908 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/28.rv_dm_stress_all.2699055929 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/29.rv_dm_alert_test.4084216640 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.1676434242 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.1749935715 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.3875166013 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.2684376148 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.756697543 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.1033490940 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/3.rv_dm_hart_unavail.1156053553 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.483255255 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/3.rv_dm_sec_cm.308233839 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.1544643920 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.3721621539 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/30.rv_dm_alert_test.4211072080 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.1989321541 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/31.rv_dm_alert_test.120751859 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/31.rv_dm_stress_all.560849305 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/32.rv_dm_alert_test.3741409644 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/32.rv_dm_stress_all.3169044891 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/33.rv_dm_alert_test.2670729574 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.586254555 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/34.rv_dm_alert_test.519701585 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/34.rv_dm_stress_all.1864777315 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/35.rv_dm_alert_test.1579728299 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/35.rv_dm_stress_all.1875789951 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/36.rv_dm_alert_test.2547303832 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/36.rv_dm_stress_all.2036101813 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/37.rv_dm_alert_test.1031516529 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/37.rv_dm_stress_all.413284169 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/38.rv_dm_alert_test.1651286898 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/38.rv_dm_stress_all.3004319620 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/39.rv_dm_alert_test.1679153297 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/39.rv_dm_stress_all.1139815081 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/4.rv_dm_alert_test.2740199906 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/4.rv_dm_autoincr_sba_tl_access.3011913905 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/4.rv_dm_bad_sba_tl_access.466993913 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/4.rv_dm_buffered_enable.3440065922 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3736032886 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.501449990 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.3257460841 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/4.rv_dm_sba_tl_access.641343636 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/4.rv_dm_sec_cm.476832616 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.1143386921 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.385031103 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/40.rv_dm_alert_test.881204458 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/40.rv_dm_stress_all.1094890063 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/41.rv_dm_alert_test.628461359 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/41.rv_dm_stress_all.2168123718 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/42.rv_dm_alert_test.1164135789 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/42.rv_dm_stress_all.3100785605 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/43.rv_dm_alert_test.3293441870 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/43.rv_dm_stress_all.2007531059 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/44.rv_dm_alert_test.1087026974 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.3831054076 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/45.rv_dm_alert_test.1724759865 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/45.rv_dm_stress_all.1285013610 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/46.rv_dm_alert_test.3370045028 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.3604880537 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/47.rv_dm_alert_test.831819723 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/47.rv_dm_stress_all.1615545128 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/48.rv_dm_alert_test.364230192 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/48.rv_dm_stress_all.3522560815 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/49.rv_dm_alert_test.1317309908 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/49.rv_dm_stress_all.4256101214 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/5.rv_dm_alert_test.1727263063 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.644904637 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.3857882645 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/5.rv_dm_buffered_enable.1229730633 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.65340445 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/5.rv_dm_halt_resume_whereto.899214037 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/5.rv_dm_sba_tl_access.3310429164 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.1116314822 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/6.rv_dm_alert_test.3099695380 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/6.rv_dm_autoincr_sba_tl_access.928511547 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/6.rv_dm_bad_sba_tl_access.3962375084 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/6.rv_dm_buffered_enable.2410708665 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.3108286045 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/6.rv_dm_halt_resume_whereto.4042350144 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/6.rv_dm_sba_tl_access.1623148688 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all.132330847 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/7.rv_dm_alert_test.3939275016 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.1039523847 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.1900677487 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/7.rv_dm_buffered_enable.1836352550 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.843792416 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/7.rv_dm_sba_tl_access.2591946832 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all.3619438408 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.4218560304 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/8.rv_dm_alert_test.2404787895 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.775028328 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/8.rv_dm_bad_sba_tl_access.3873088136 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/8.rv_dm_buffered_enable.2758768132 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.805624046 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/8.rv_dm_sba_tl_access.1195394169 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.2108848232 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.2144700056 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.635972304 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.3289168412 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/9.rv_dm_buffered_enable.3799796600 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.2010681023 |
| /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.3890257020 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_smoke.2445092147 | Aug 27 07:01:53 AM UTC 24 | Aug 27 07:01:56 AM UTC 24 | 922294035 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.2357565840 | Aug 27 07:01:54 AM UTC 24 | Aug 27 07:01:56 AM UTC 24 | 200234154 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.1013573426 | Aug 27 07:01:54 AM UTC 24 | Aug 27 07:01:56 AM UTC 24 | 139546935 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_busy.1082304179 | Aug 27 07:01:54 AM UTC 24 | Aug 27 07:01:57 AM UTC 24 | 176068175 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_halted.1061595333 | Aug 27 07:01:55 AM UTC 24 | Aug 27 07:01:57 AM UTC 24 | 197296781 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_hart_unavail.140878139 | Aug 27 07:01:55 AM UTC 24 | Aug 27 07:01:57 AM UTC 24 | 128511528 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_resuming.579898720 | Aug 27 07:01:55 AM UTC 24 | Aug 27 07:01:58 AM UTC 24 | 241269996 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_dataaddr_rw_access.1862384399 | Aug 27 07:01:56 AM UTC 24 | Aug 27 07:01:58 AM UTC 24 | 230481950 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.3691935093 | Aug 27 07:01:54 AM UTC 24 | Aug 27 07:01:59 AM UTC 24 | 2551705539 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.542423282 | Aug 27 07:01:55 AM UTC 24 | Aug 27 07:01:59 AM UTC 24 | 610856457 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.1137493631 | Aug 27 07:01:57 AM UTC 24 | Aug 27 07:02:00 AM UTC 24 | 123722149 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_hard_reset.3099136794 | Aug 27 07:01:58 AM UTC 24 | Aug 27 07:02:00 AM UTC 24 | 130836270 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.3820083855 | Aug 27 07:01:58 AM UTC 24 | Aug 27 07:02:00 AM UTC 24 | 176409558 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.1398442500 | Aug 27 07:01:58 AM UTC 24 | Aug 27 07:02:00 AM UTC 24 | 189284102 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_idle_hint.1932671640 | Aug 27 07:01:58 AM UTC 24 | Aug 27 07:02:00 AM UTC 24 | 111960477 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.3643562403 | Aug 27 07:01:53 AM UTC 24 | Aug 27 07:02:00 AM UTC 24 | 8674656787 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.3937934731 | Aug 27 07:01:57 AM UTC 24 | Aug 27 07:02:00 AM UTC 24 | 774944666 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.1227799408 | Aug 27 07:01:59 AM UTC 24 | Aug 27 07:02:01 AM UTC 24 | 87198204 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_hartsel_warl.4156575512 | Aug 27 07:01:59 AM UTC 24 | Aug 27 07:02:01 AM UTC 24 | 114699397 ps | ||
| T86 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_debug_disabled.2163868139 | Aug 27 07:01:59 AM UTC 24 | Aug 27 07:02:01 AM UTC 24 | 130511759 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.4055166059 | Aug 27 07:01:59 AM UTC 24 | Aug 27 07:02:01 AM UTC 24 | 353769414 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.1824526967 | Aug 27 07:01:59 AM UTC 24 | Aug 27 07:02:01 AM UTC 24 | 112088975 ps | ||
| T99 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.2158594046 | Aug 27 07:01:59 AM UTC 24 | Aug 27 07:02:01 AM UTC 24 | 14676365 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_tl_access.3947691392 | Aug 27 07:01:53 AM UTC 24 | Aug 27 07:02:01 AM UTC 24 | 1778829648 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2850581544 | Aug 27 07:01:53 AM UTC 24 | Aug 27 07:02:01 AM UTC 24 | 5511838951 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.325383587 | Aug 27 07:01:59 AM UTC 24 | Aug 27 07:02:01 AM UTC 24 | 214634170 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1986467713 | Aug 27 07:01:58 AM UTC 24 | Aug 27 07:02:01 AM UTC 24 | 2168371343 ps | ||
| T51 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.2191791410 | Aug 27 07:02:00 AM UTC 24 | Aug 27 07:02:02 AM UTC 24 | 131455660 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.2829416490 | Aug 27 07:01:57 AM UTC 24 | Aug 27 07:02:03 AM UTC 24 | 2138603897 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.3818565123 | Aug 27 07:01:59 AM UTC 24 | Aug 27 07:02:03 AM UTC 24 | 747020104 ps | ||
| T100 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.3017944910 | Aug 27 07:02:00 AM UTC 24 | Aug 27 07:02:03 AM UTC 24 | 1062462592 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/3.rv_dm_hart_unavail.1156053553 | Aug 27 07:02:07 AM UTC 24 | Aug 27 07:02:09 AM UTC 24 | 54775676 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_busy.208639429 | Aug 27 07:02:01 AM UTC 24 | Aug 27 07:02:04 AM UTC 24 | 599679827 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_not_supported.55110229 | Aug 27 07:02:02 AM UTC 24 | Aug 27 07:02:04 AM UTC 24 | 188852506 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_dataaddr_rw_access.1939204067 | Aug 27 07:02:02 AM UTC 24 | Aug 27 07:02:04 AM UTC 24 | 134644727 ps | ||
| T174 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_halted.2885959942 | Aug 27 07:02:02 AM UTC 24 | Aug 27 07:02:04 AM UTC 24 | 146504113 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_halt_resume_whereto.1562536431 | Aug 27 07:02:02 AM UTC 24 | Aug 27 07:02:04 AM UTC 24 | 244197176 ps | ||
| T277 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_hart_unavail.1453811906 | Aug 27 07:02:02 AM UTC 24 | Aug 27 07:02:04 AM UTC 24 | 64194125 ps | ||
| T79 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_idle_hint.2200466026 | Aug 27 07:02:02 AM UTC 24 | Aug 27 07:02:04 AM UTC 24 | 156830376 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_resuming.2593220148 | Aug 27 07:02:02 AM UTC 24 | Aug 27 07:02:04 AM UTC 24 | 127822666 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.1605579716 | Aug 27 07:02:02 AM UTC 24 | Aug 27 07:02:04 AM UTC 24 | 612391276 ps | ||
| T78 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_hard_reset.516196212 | Aug 27 07:02:02 AM UTC 24 | Aug 27 07:02:05 AM UTC 24 | 335048260 ps | ||
| T193 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.3914660679 | Aug 27 07:02:02 AM UTC 24 | Aug 27 07:02:05 AM UTC 24 | 436073648 ps | ||
| T280 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1416264595 | Aug 27 07:02:02 AM UTC 24 | Aug 27 07:02:05 AM UTC 24 | 336585845 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.2549441049 | Aug 27 07:02:00 AM UTC 24 | Aug 27 07:02:05 AM UTC 24 | 3465160279 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.2405941330 | Aug 27 07:02:00 AM UTC 24 | Aug 27 07:02:05 AM UTC 24 | 479638583 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.3092103443 | Aug 27 07:02:02 AM UTC 24 | Aug 27 07:02:05 AM UTC 24 | 372181781 ps | ||
| T93 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_smoke.1834516355 | Aug 27 07:02:00 AM UTC 24 | Aug 27 07:02:05 AM UTC 24 | 705975705 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_abstractcmd_status.2081161134 | Aug 27 07:02:03 AM UTC 24 | Aug 27 07:02:05 AM UTC 24 | 197429131 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_ndmreset_req.2788432233 | Aug 27 07:02:02 AM UTC 24 | Aug 27 07:02:06 AM UTC 24 | 348948345 ps | ||
| T90 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_debug_disabled.2364676323 | Aug 27 07:02:03 AM UTC 24 | Aug 27 07:02:06 AM UTC 24 | 111404114 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_rom_read_access.2056587179 | Aug 27 07:02:03 AM UTC 24 | Aug 27 07:02:06 AM UTC 24 | 93027875 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_progbuf_read_write_execute.3424083386 | Aug 27 07:02:03 AM UTC 24 | Aug 27 07:02:06 AM UTC 24 | 207685685 ps | ||
| T94 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_debug_disabled.477023829 | Aug 27 07:02:02 AM UTC 24 | Aug 27 07:02:06 AM UTC 24 | 988564281 ps | ||
| T95 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_bad_sba_tl_access.741600894 | Aug 27 07:02:00 AM UTC 24 | Aug 27 07:02:06 AM UTC 24 | 1011828244 ps | ||
| T84 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_buffered_enable.316696086 | Aug 27 07:02:04 AM UTC 24 | Aug 27 07:02:06 AM UTC 24 | 210936661 ps | ||
| T52 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_alert_test.747044604 | Aug 27 07:02:05 AM UTC 24 | Aug 27 07:02:07 AM UTC 24 | 115834506 ps | ||
| T76 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.827128873 | Aug 27 07:02:04 AM UTC 24 | Aug 27 07:02:07 AM UTC 24 | 117956186 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.2683598715 | Aug 27 07:02:05 AM UTC 24 | Aug 27 07:02:07 AM UTC 24 | 253146246 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.997877193 | Aug 27 07:02:06 AM UTC 24 | Aug 27 07:02:09 AM UTC 24 | 2001007837 ps | ||
| T88 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_sec_cm.3750045979 | Aug 27 07:02:05 AM UTC 24 | Aug 27 07:02:08 AM UTC 24 | 830866503 ps | ||
| T83 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/2.rv_dm_sparse_lc_gate_fsm.3428904668 | Aug 27 07:02:06 AM UTC 24 | Aug 27 07:02:08 AM UTC 24 | 131156251 ps | ||
| T96 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.3808581264 | Aug 27 07:02:06 AM UTC 24 | Aug 27 07:02:08 AM UTC 24 | 73155267 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.885253560 | Aug 27 07:02:06 AM UTC 24 | Aug 27 07:02:08 AM UTC 24 | 164273204 ps | ||
| T97 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.2687829803 | Aug 27 07:02:05 AM UTC 24 | Aug 27 07:02:08 AM UTC 24 | 988017030 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.937431252 | Aug 27 07:02:06 AM UTC 24 | Aug 27 07:02:09 AM UTC 24 | 230858143 ps | ||
| T89 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.1496709152 | Aug 27 07:02:06 AM UTC 24 | Aug 27 07:02:09 AM UTC 24 | 1398786998 ps | ||
| T98 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.1676434242 | Aug 27 07:02:08 AM UTC 24 | Aug 27 07:02:10 AM UTC 24 | 57852836 ps | ||
| T73 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.2684376148 | Aug 27 07:02:07 AM UTC 24 | Aug 27 07:02:10 AM UTC 24 | 213380841 ps | ||
| T70 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.1033490940 | Aug 27 07:02:07 AM UTC 24 | Aug 27 07:02:10 AM UTC 24 | 756632524 ps | ||
| T85 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.1544643920 | Aug 27 07:02:07 AM UTC 24 | Aug 27 07:02:10 AM UTC 24 | 250176870 ps | ||
| T117 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.3946535725 | Aug 27 07:02:06 AM UTC 24 | Aug 27 07:02:11 AM UTC 24 | 627847206 ps | ||
| T281 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.3257460841 | Aug 27 07:02:09 AM UTC 24 | Aug 27 07:02:11 AM UTC 24 | 348593194 ps | ||
| T59 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.501449990 | Aug 27 07:02:09 AM UTC 24 | Aug 27 07:02:11 AM UTC 24 | 290774074 ps | ||
| T87 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.1324207543 | Aug 27 07:02:05 AM UTC 24 | Aug 27 07:02:11 AM UTC 24 | 2584815410 ps | ||
| T118 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.775974078 | Aug 27 07:02:06 AM UTC 24 | Aug 27 07:02:11 AM UTC 24 | 3507735597 ps | ||
| T91 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/3.rv_dm_sec_cm.308233839 | Aug 27 07:02:08 AM UTC 24 | Aug 27 07:02:12 AM UTC 24 | 570215818 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/4.rv_dm_alert_test.2740199906 | Aug 27 07:02:10 AM UTC 24 | Aug 27 07:02:12 AM UTC 24 | 101985090 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/4.rv_dm_autoincr_sba_tl_access.3011913905 | Aug 27 07:02:09 AM UTC 24 | Aug 27 07:02:12 AM UTC 24 | 3296427880 ps | ||
| T140 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/4.rv_dm_buffered_enable.3440065922 | Aug 27 07:02:10 AM UTC 24 | Aug 27 07:02:12 AM UTC 24 | 113321474 ps | ||
| T139 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.3875166013 | Aug 27 07:02:06 AM UTC 24 | Aug 27 07:02:12 AM UTC 24 | 6774104496 ps | ||
| T199 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/4.rv_dm_bad_sba_tl_access.466993913 | Aug 27 07:02:09 AM UTC 24 | Aug 27 07:02:13 AM UTC 24 | 2646861343 ps | ||
| T92 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/4.rv_dm_sec_cm.476832616 | Aug 27 07:02:10 AM UTC 24 | Aug 27 07:02:13 AM UTC 24 | 300267642 ps | ||
| T239 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/5.rv_dm_sba_tl_access.3310429164 | Aug 27 07:02:10 AM UTC 24 | Aug 27 07:02:13 AM UTC 24 | 1217698514 ps | ||
| T176 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/5.rv_dm_alert_test.1727263063 | Aug 27 07:02:12 AM UTC 24 | Aug 27 07:02:14 AM UTC 24 | 27169545 ps | ||
| T226 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/5.rv_dm_buffered_enable.1229730633 | Aug 27 07:02:11 AM UTC 24 | Aug 27 07:02:14 AM UTC 24 | 589598103 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.1749935715 | Aug 27 07:02:07 AM UTC 24 | Aug 27 07:02:14 AM UTC 24 | 2799814523 ps | ||
| T228 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/5.rv_dm_halt_resume_whereto.899214037 | Aug 27 07:02:10 AM UTC 24 | Aug 27 07:02:15 AM UTC 24 | 866521651 ps | ||
| T235 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.65340445 | Aug 27 07:02:10 AM UTC 24 | Aug 27 07:02:15 AM UTC 24 | 2457994043 ps | ||
| T177 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/6.rv_dm_alert_test.3099695380 | Aug 27 07:02:13 AM UTC 24 | Aug 27 07:02:15 AM UTC 24 | 43643128 ps | ||
| T282 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.483255255 | Aug 27 07:02:06 AM UTC 24 | Aug 27 07:02:15 AM UTC 24 | 2299422240 ps | ||
| T254 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3736032886 | Aug 27 07:02:09 AM UTC 24 | Aug 27 07:02:15 AM UTC 24 | 4038208674 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.1506988820 | Aug 27 07:02:11 AM UTC 24 | Aug 27 07:02:15 AM UTC 24 | 2195560251 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all.399169429 | Aug 27 07:02:06 AM UTC 24 | Aug 27 07:02:16 AM UTC 24 | 5438804209 ps | ||
| T202 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/6.rv_dm_bad_sba_tl_access.3962375084 | Aug 27 07:02:13 AM UTC 24 | Aug 27 07:02:16 AM UTC 24 | 1100708330 ps | ||
| T227 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.843792416 | Aug 27 07:02:14 AM UTC 24 | Aug 27 07:02:16 AM UTC 24 | 194166570 ps | ||
| T211 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.1143386921 | Aug 27 07:02:10 AM UTC 24 | Aug 27 07:02:17 AM UTC 24 | 2429075581 ps | ||
| T141 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/6.rv_dm_buffered_enable.2410708665 | Aug 27 07:02:13 AM UTC 24 | Aug 27 07:02:17 AM UTC 24 | 584061638 ps | ||
| T264 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/7.rv_dm_alert_test.3939275016 | Aug 27 07:02:16 AM UTC 24 | Aug 27 07:02:18 AM UTC 24 | 57402913 ps | ||
| T196 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/7.rv_dm_buffered_enable.1836352550 | Aug 27 07:02:14 AM UTC 24 | Aug 27 07:02:18 AM UTC 24 | 496303663 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/8.rv_dm_buffered_enable.2758768132 | Aug 27 07:02:16 AM UTC 24 | Aug 27 07:02:18 AM UTC 24 | 290796337 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.3979894657 | Aug 27 07:02:05 AM UTC 24 | Aug 27 07:02:18 AM UTC 24 | 1119963665 ps | ||
| T121 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.756697543 | Aug 27 07:02:06 AM UTC 24 | Aug 27 07:02:19 AM UTC 24 | 3900965959 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/6.rv_dm_halt_resume_whereto.4042350144 | Aug 27 07:02:13 AM UTC 24 | Aug 27 07:02:19 AM UTC 24 | 1219273540 ps | ||
| T122 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.3108286045 | Aug 27 07:02:12 AM UTC 24 | Aug 27 07:02:19 AM UTC 24 | 1858052542 ps | ||
| T123 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/8.rv_dm_alert_test.2404787895 | Aug 27 07:02:17 AM UTC 24 | Aug 27 07:02:19 AM UTC 24 | 144951717 ps | ||
| T124 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_tl_access.278909424 | Aug 27 07:02:00 AM UTC 24 | Aug 27 07:02:20 AM UTC 24 | 6855379231 ps | ||
| T125 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all.3619438408 | Aug 27 07:02:14 AM UTC 24 | Aug 27 07:02:20 AM UTC 24 | 1518840384 ps | ||
| T126 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.635972304 | Aug 27 07:02:19 AM UTC 24 | Aug 27 07:02:21 AM UTC 24 | 80745933 ps | ||
| T127 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.775028328 | Aug 27 07:02:16 AM UTC 24 | Aug 27 07:02:22 AM UTC 24 | 4592172974 ps | ||
| T128 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.2108848232 | Aug 27 07:02:17 AM UTC 24 | Aug 27 07:02:22 AM UTC 24 | 2316178545 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/9.rv_dm_buffered_enable.3799796600 | Aug 27 07:02:18 AM UTC 24 | Aug 27 07:02:22 AM UTC 24 | 782425760 ps | ||
| T278 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3208932703 | Aug 27 07:02:13 AM UTC 24 | Aug 27 07:02:22 AM UTC 24 | 13073684441 ps | ||
| T255 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.3289168412 | Aug 27 07:02:18 AM UTC 24 | Aug 27 07:02:22 AM UTC 24 | 2166897065 ps | ||
| T270 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.3890257020 | Aug 27 07:02:17 AM UTC 24 | Aug 27 07:02:22 AM UTC 24 | 1415875693 ps | ||
| T247 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/8.rv_dm_bad_sba_tl_access.3873088136 | Aug 27 07:02:16 AM UTC 24 | Aug 27 07:02:22 AM UTC 24 | 4923037528 ps | ||
| T243 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/10.rv_dm_alert_test.2621435976 | Aug 27 07:02:21 AM UTC 24 | Aug 27 07:02:23 AM UTC 24 | 41470707 ps | ||
| T279 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.2022419910 | Aug 27 07:02:20 AM UTC 24 | Aug 27 07:02:23 AM UTC 24 | 1820302524 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/10.rv_dm_stress_all.3948313824 | Aug 27 07:02:21 AM UTC 24 | Aug 27 07:02:23 AM UTC 24 | 1247986052 ps | ||
| T209 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/7.rv_dm_sba_tl_access.2591946832 | Aug 27 07:02:13 AM UTC 24 | Aug 27 07:02:23 AM UTC 24 | 10615721609 ps | ||
| T61 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all.132330847 | Aug 27 07:02:13 AM UTC 24 | Aug 27 07:02:24 AM UTC 24 | 2805030380 ps | ||
| T263 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/17.rv_dm_alert_test.3405681200 | Aug 27 07:02:33 AM UTC 24 | Aug 27 07:02:35 AM UTC 24 | 121637980 ps | ||
| T283 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.1900677487 | Aug 27 07:02:14 AM UTC 24 | Aug 27 07:02:24 AM UTC 24 | 4337516295 ps | ||
| T284 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/11.rv_dm_alert_test.1140186446 | Aug 27 07:02:23 AM UTC 24 | Aug 27 07:02:25 AM UTC 24 | 180253445 ps | ||
| T285 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.805624046 | Aug 27 07:02:16 AM UTC 24 | Aug 27 07:02:25 AM UTC 24 | 10101965214 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.241188201 | Aug 27 07:02:18 AM UTC 24 | Aug 27 07:02:26 AM UTC 24 | 2018230898 ps | ||
| T286 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/12.rv_dm_alert_test.3584346085 | Aug 27 07:02:24 AM UTC 24 | Aug 27 07:02:26 AM UTC 24 | 38740331 ps | ||
| T287 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/12.rv_dm_bad_sba_tl_access.3922286731 | Aug 27 07:02:23 AM UTC 24 | Aug 27 07:02:26 AM UTC 24 | 843988955 ps | ||
| T260 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/13.rv_dm_alert_test.4025093525 | Aug 27 07:02:25 AM UTC 24 | Aug 27 07:02:27 AM UTC 24 | 59793338 ps | ||
| T273 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/13.rv_dm_sba_tl_access.1774997647 | Aug 27 07:02:24 AM UTC 24 | Aug 27 07:02:27 AM UTC 24 | 1534113688 ps | ||
| T200 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/4.rv_dm_sba_tl_access.641343636 | Aug 27 07:02:09 AM UTC 24 | Aug 27 07:02:28 AM UTC 24 | 12908558402 ps | ||
| T244 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/11.rv_dm_autoincr_sba_tl_access.1500980101 | Aug 27 07:02:23 AM UTC 24 | Aug 27 07:02:28 AM UTC 24 | 1912391642 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.3721621539 | Aug 27 07:02:07 AM UTC 24 | Aug 27 07:02:28 AM UTC 24 | 6171434047 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.3656027746 | Aug 27 07:02:07 AM UTC 24 | Aug 27 07:02:29 AM UTC 24 | 4361576954 ps | ||
| T185 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/14.rv_dm_sba_tl_access.4216787918 | Aug 27 07:02:25 AM UTC 24 | Aug 27 07:02:29 AM UTC 24 | 2183266782 ps | ||
| T186 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/12.rv_dm_sba_tl_access.1381977561 | Aug 27 07:02:23 AM UTC 24 | Aug 27 07:02:29 AM UTC 24 | 3533499042 ps | ||
| T187 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.2347474575 | Aug 27 07:02:05 AM UTC 24 | Aug 27 07:02:29 AM UTC 24 | 8940503850 ps | ||
| T188 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/10.rv_dm_autoincr_sba_tl_access.1022665779 | Aug 27 07:02:21 AM UTC 24 | Aug 27 07:02:30 AM UTC 24 | 7947497981 ps | ||
| T189 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/14.rv_dm_alert_test.257328814 | Aug 27 07:02:28 AM UTC 24 | Aug 27 07:02:30 AM UTC 24 | 104455144 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/12.rv_dm_stress_all.828289840 | Aug 27 07:02:24 AM UTC 24 | Aug 27 07:02:31 AM UTC 24 | 3076112737 ps | ||
| T190 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/13.rv_dm_bad_sba_tl_access.839145756 | Aug 27 07:02:24 AM UTC 24 | Aug 27 07:02:31 AM UTC 24 | 1140944776 ps | ||
| T191 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.2010681023 | Aug 27 07:02:17 AM UTC 24 | Aug 27 07:02:32 AM UTC 24 | 2694787166 ps | ||
| T192 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/15.rv_dm_alert_test.3982228333 | Aug 27 07:02:30 AM UTC 24 | Aug 27 07:02:32 AM UTC 24 | 54077160 ps | ||
| T288 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.1776819965 | Aug 27 07:02:23 AM UTC 24 | Aug 27 07:02:32 AM UTC 24 | 4560569634 ps | ||
| T197 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.3857882645 | Aug 27 07:02:10 AM UTC 24 | Aug 27 07:02:32 AM UTC 24 | 13796889582 ps | ||
| T249 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/11.rv_dm_sba_tl_access.371708225 | Aug 27 07:02:21 AM UTC 24 | Aug 27 07:02:32 AM UTC 24 | 9033359989 ps | ||
| T250 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/15.rv_dm_bad_sba_tl_access.4109818444 | Aug 27 07:02:29 AM UTC 24 | Aug 27 07:02:32 AM UTC 24 | 1734042602 ps | ||
| T289 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/10.rv_dm_sba_tl_access.993176557 | Aug 27 07:02:20 AM UTC 24 | Aug 27 07:02:33 AM UTC 24 | 9046552685 ps | ||
| T290 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/16.rv_dm_alert_test.3101624571 | Aug 27 07:02:31 AM UTC 24 | Aug 27 07:02:33 AM UTC 24 | 61826612 ps | ||
| T72 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.4218560304 | Aug 27 07:02:16 AM UTC 24 | Aug 27 07:02:34 AM UTC 24 | 1194587368 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/14.rv_dm_stress_all.2039374341 | Aug 27 07:02:27 AM UTC 24 | Aug 27 07:02:34 AM UTC 24 | 5514279680 ps | ||
| T291 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/8.rv_dm_sba_tl_access.1195394169 | Aug 27 07:02:16 AM UTC 24 | Aug 27 07:02:34 AM UTC 24 | 10892929953 ps | ||
| T292 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/15.rv_dm_sba_tl_access.2714592479 | Aug 27 07:02:28 AM UTC 24 | Aug 27 07:02:34 AM UTC 24 | 1783987388 ps | ||
| T293 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.3660884980 | Aug 27 07:02:24 AM UTC 24 | Aug 27 07:02:35 AM UTC 24 | 2581405920 ps | ||
| T294 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.1039523847 | Aug 27 07:02:14 AM UTC 24 | Aug 27 07:02:35 AM UTC 24 | 22084209055 ps | ||
| T295 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/14.rv_dm_bad_sba_tl_access.392713521 | Aug 27 07:02:27 AM UTC 24 | Aug 27 07:02:35 AM UTC 24 | 2805641780 ps | ||
| T206 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/16.rv_dm_bad_sba_tl_access.321385009 | Aug 27 07:02:30 AM UTC 24 | Aug 27 07:02:35 AM UTC 24 | 1852886876 ps | ||
| T203 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/15.rv_dm_autoincr_sba_tl_access.973612838 | Aug 27 07:02:29 AM UTC 24 | Aug 27 07:02:35 AM UTC 24 | 4569820713 ps | ||
| T248 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/11.rv_dm_bad_sba_tl_access.1688931801 | Aug 27 07:02:23 AM UTC 24 | Aug 27 07:02:36 AM UTC 24 | 7605429066 ps | ||
| T296 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.3456806392 | Aug 27 07:02:26 AM UTC 24 | Aug 27 07:02:36 AM UTC 24 | 1987855721 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/13.rv_dm_stress_all.3492410264 | Aug 27 07:02:25 AM UTC 24 | Aug 27 07:02:36 AM UTC 24 | 2592531723 ps | ||
| T257 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/18.rv_dm_alert_test.161356103 | Aug 27 07:02:35 AM UTC 24 | Aug 27 07:02:37 AM UTC 24 | 57932828 ps | ||
| T234 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/16.rv_dm_stress_all.3174958010 | Aug 27 07:02:31 AM UTC 24 | Aug 27 07:02:37 AM UTC 24 | 4471490857 ps | ||
| T236 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/16.rv_dm_autoincr_sba_tl_access.2291706244 | Aug 27 07:02:31 AM UTC 24 | Aug 27 07:02:38 AM UTC 24 | 5561503168 ps | ||
| T204 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.978406326 | Aug 27 07:02:32 AM UTC 24 | Aug 27 07:02:38 AM UTC 24 | 2496702700 ps | ||
| T265 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/18.rv_dm_bad_sba_tl_access.3885721055 | Aug 27 07:02:34 AM UTC 24 | Aug 27 07:02:38 AM UTC 24 | 3070852917 ps | ||
| T262 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/10.rv_dm_bad_sba_tl_access.284407348 | Aug 27 07:02:20 AM UTC 24 | Aug 27 07:02:39 AM UTC 24 | 5836403893 ps | ||
| T238 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/20.rv_dm_alert_test.203158283 | Aug 27 07:02:37 AM UTC 24 | Aug 27 07:02:39 AM UTC 24 | 29983230 ps | ||
| T246 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/19.rv_dm_alert_test.2923693644 | Aug 27 07:02:37 AM UTC 24 | Aug 27 07:02:39 AM UTC 24 | 71529536 ps | ||
| T205 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/11.rv_dm_stress_all.4198129845 | Aug 27 07:02:23 AM UTC 24 | Aug 27 07:02:39 AM UTC 24 | 5747676514 ps | ||
| T297 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/16.rv_dm_sba_tl_access.897200083 | Aug 27 07:02:30 AM UTC 24 | Aug 27 07:02:39 AM UTC 24 | 14074261702 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/17.rv_dm_stress_all.865329554 | Aug 27 07:02:33 AM UTC 24 | Aug 27 07:02:39 AM UTC 24 | 6893670687 ps | ||
| T298 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/21.rv_dm_alert_test.2734557100 | Aug 27 07:02:37 AM UTC 24 | Aug 27 07:02:39 AM UTC 24 | 37862656 ps | ||
| T299 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/22.rv_dm_alert_test.3124412402 | Aug 27 07:02:37 AM UTC 24 | Aug 27 07:02:40 AM UTC 24 | 60233594 ps | ||
| T300 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.644904637 | Aug 27 07:02:10 AM UTC 24 | Aug 27 07:02:40 AM UTC 24 | 15785469479 ps | ||
| T275 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/23.rv_dm_alert_test.3775149732 | Aug 27 07:02:39 AM UTC 24 | Aug 27 07:02:40 AM UTC 24 | 123269863 ps | ||
| T301 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/18.rv_dm_sba_tl_access.3372608245 | Aug 27 07:02:33 AM UTC 24 | Aug 27 07:02:41 AM UTC 24 | 1879900383 ps | ||
| T302 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.1562011794 | Aug 27 07:02:23 AM UTC 24 | Aug 27 07:02:41 AM UTC 24 | 10934740827 ps | ||
| T229 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/24.rv_dm_alert_test.2961833256 | Aug 27 07:02:39 AM UTC 24 | Aug 27 07:02:41 AM UTC 24 | 165821212 ps | ||
| T303 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2357795562 | Aug 27 07:02:35 AM UTC 24 | Aug 27 07:02:41 AM UTC 24 | 1737227436 ps | ||
| T304 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/19.rv_dm_sba_tl_access.1029585608 | Aug 27 07:02:35 AM UTC 24 | Aug 27 07:02:41 AM UTC 24 | 1158345500 ps | ||
| T272 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.1698781770 | Aug 27 07:02:29 AM UTC 24 | Aug 27 07:02:42 AM UTC 24 | 5819965229 ps | ||
| T305 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/14.rv_dm_autoincr_sba_tl_access.2712711977 | Aug 27 07:02:27 AM UTC 24 | Aug 27 07:02:42 AM UTC 24 | 15140490195 ps | ||
| T306 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/26.rv_dm_alert_test.3028563269 | Aug 27 07:02:40 AM UTC 24 | Aug 27 07:02:42 AM UTC 24 | 51317432 ps | ||
| T307 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/28.rv_dm_alert_test.1961535908 | Aug 27 07:02:40 AM UTC 24 | Aug 27 07:02:42 AM UTC 24 | 40932981 ps | ||
| T274 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/27.rv_dm_alert_test.3795240365 | Aug 27 07:02:40 AM UTC 24 | Aug 27 07:02:42 AM UTC 24 | 76777858 ps | ||
| T308 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.3315645180 | Aug 27 07:02:35 AM UTC 24 | Aug 27 07:02:42 AM UTC 24 | 4197501139 ps | ||
| T245 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/19.rv_dm_bad_sba_tl_access.2825550147 | Aug 27 07:02:35 AM UTC 24 | Aug 27 07:02:42 AM UTC 24 | 5313170405 ps | ||
| T309 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/25.rv_dm_alert_test.4113072900 | Aug 27 07:02:40 AM UTC 24 | Aug 27 07:02:42 AM UTC 24 | 154934574 ps | ||
| T310 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.599151261 | Aug 27 07:02:30 AM UTC 24 | Aug 27 07:02:43 AM UTC 24 | 5902694477 ps | ||
| T311 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.262305500 | Aug 27 07:02:33 AM UTC 24 | Aug 27 07:02:43 AM UTC 24 | 4282514529 ps | ||
| T210 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/17.rv_dm_bad_sba_tl_access.2625982208 | Aug 27 07:02:33 AM UTC 24 | Aug 27 07:02:43 AM UTC 24 | 6309239000 ps | ||
| T242 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/30.rv_dm_alert_test.4211072080 | Aug 27 07:02:41 AM UTC 24 | Aug 27 07:02:43 AM UTC 24 | 54234982 ps | ||
| T253 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/29.rv_dm_alert_test.4084216640 | Aug 27 07:02:41 AM UTC 24 | Aug 27 07:02:43 AM UTC 24 | 35276132 ps | ||
| T312 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.3135937846 | Aug 27 07:02:37 AM UTC 24 | Aug 27 07:02:43 AM UTC 24 | 1110715970 ps | ||
| T232 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/21.rv_dm_stress_all.2577216603 | Aug 27 07:02:37 AM UTC 24 | Aug 27 07:02:43 AM UTC 24 | 2358629557 ps | ||
| T313 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/31.rv_dm_alert_test.120751859 | Aug 27 07:02:41 AM UTC 24 | Aug 27 07:02:43 AM UTC 24 | 32319536 ps | ||
| T237 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/32.rv_dm_alert_test.3741409644 | Aug 27 07:02:41 AM UTC 24 | Aug 27 07:02:43 AM UTC 24 | 54685955 ps | ||
| T314 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/17.rv_dm_sba_tl_access.2989616783 | Aug 27 07:02:31 AM UTC 24 | Aug 27 07:02:44 AM UTC 24 | 3738708667 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/26.rv_dm_stress_all.493249243 | Aug 27 07:02:40 AM UTC 24 | Aug 27 07:02:44 AM UTC 24 | 3262360787 ps | ||
| T315 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/24.rv_dm_stress_all.4054542902 | Aug 27 07:02:39 AM UTC 24 | Aug 27 07:02:44 AM UTC 24 | 1188396455 ps | ||
| T258 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/35.rv_dm_alert_test.1579728299 | Aug 27 07:02:43 AM UTC 24 | Aug 27 07:02:45 AM UTC 24 | 39385394 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/35.rv_dm_stress_all.1875789951 | Aug 27 07:02:43 AM UTC 24 | Aug 27 07:02:51 AM UTC 24 | 7488927089 ps | ||
| T208 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/15.rv_dm_stress_all.2004704864 | Aug 27 07:02:29 AM UTC 24 | Aug 27 07:02:45 AM UTC 24 | 4278315712 ps | ||
| T251 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/36.rv_dm_alert_test.2547303832 | Aug 27 07:02:43 AM UTC 24 | Aug 27 07:02:45 AM UTC 24 | 219581474 ps | ||
| T316 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/33.rv_dm_alert_test.2670729574 | Aug 27 07:02:43 AM UTC 24 | Aug 27 07:02:45 AM UTC 24 | 56245600 ps | ||
| T267 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/34.rv_dm_alert_test.519701585 | Aug 27 07:02:43 AM UTC 24 | Aug 27 07:02:45 AM UTC 24 | 42676117 ps | ||
| T201 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/31.rv_dm_stress_all.560849305 | Aug 27 07:02:41 AM UTC 24 | Aug 27 07:02:45 AM UTC 24 | 2207752906 ps | ||
| T198 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/28.rv_dm_stress_all.2699055929 | Aug 27 07:02:40 AM UTC 24 | Aug 27 07:02:45 AM UTC 24 | 1912789630 ps | ||
| T317 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/38.rv_dm_alert_test.1651286898 | Aug 27 07:02:44 AM UTC 24 | Aug 27 07:02:46 AM UTC 24 | 129182874 ps | ||
| T271 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/39.rv_dm_alert_test.1679153297 | Aug 27 07:02:44 AM UTC 24 | Aug 27 07:02:46 AM UTC 24 | 52588815 ps | ||
| T318 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/37.rv_dm_alert_test.1031516529 | Aug 27 07:02:44 AM UTC 24 | Aug 27 07:02:46 AM UTC 24 | 29014983 ps | ||
| T319 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/40.rv_dm_alert_test.881204458 | Aug 27 07:02:44 AM UTC 24 | Aug 27 07:02:46 AM UTC 24 | 73432000 ps | ||
| T320 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/41.rv_dm_alert_test.628461359 | Aug 27 07:02:44 AM UTC 24 | Aug 27 07:02:46 AM UTC 24 | 57320342 ps | ||
| T241 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/42.rv_dm_alert_test.1164135789 | Aug 27 07:02:44 AM UTC 24 | Aug 27 07:02:47 AM UTC 24 | 30784678 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/34.rv_dm_stress_all.1864777315 | Aug 27 07:02:43 AM UTC 24 | Aug 27 07:02:47 AM UTC 24 | 3628917622 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/18.rv_dm_stress_all.2947370733 | Aug 27 07:02:34 AM UTC 24 | Aug 27 07:02:47 AM UTC 24 | 4534504874 ps | ||
| T321 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.352600508 | Aug 27 07:02:40 AM UTC 24 | Aug 27 07:02:47 AM UTC 24 | 1615573124 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.2842578806 | Aug 27 07:02:39 AM UTC 24 | Aug 27 07:02:47 AM UTC 24 | 7968141437 ps | ||
| T322 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/23.rv_dm_stress_all.2077391962 | Aug 27 07:02:37 AM UTC 24 | Aug 27 07:02:48 AM UTC 24 | 3134860661 ps | ||
| T261 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/44.rv_dm_alert_test.1087026974 | Aug 27 07:02:46 AM UTC 24 | Aug 27 07:02:48 AM UTC 24 | 81803584 ps | ||
| T252 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/43.rv_dm_alert_test.3293441870 | Aug 27 07:02:46 AM UTC 24 | Aug 27 07:02:48 AM UTC 24 | 120608062 ps | ||
| T233 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/47.rv_dm_alert_test.831819723 | Aug 27 07:02:46 AM UTC 24 | Aug 27 07:02:48 AM UTC 24 | 53552521 ps | ||
| T323 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/46.rv_dm_alert_test.3370045028 | Aug 27 07:02:46 AM UTC 24 | Aug 27 07:02:48 AM UTC 24 | 150902803 ps | ||
| T324 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/45.rv_dm_alert_test.1724759865 | Aug 27 07:02:46 AM UTC 24 | Aug 27 07:02:48 AM UTC 24 | 62107523 ps | ||
| T259 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.3831054076 | Aug 27 07:02:46 AM UTC 24 | Aug 27 07:02:49 AM UTC 24 | 2555081167 ps | ||
| T212 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/17.rv_dm_autoincr_sba_tl_access.243665250 | Aug 27 07:02:33 AM UTC 24 | Aug 27 07:02:49 AM UTC 24 | 7499130518 ps | ||
| T266 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/37.rv_dm_stress_all.413284169 | Aug 27 07:02:43 AM UTC 24 | Aug 27 07:02:49 AM UTC 24 | 3481590553 ps | ||
| T240 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/49.rv_dm_alert_test.1317309908 | Aug 27 07:02:47 AM UTC 24 | Aug 27 07:02:49 AM UTC 24 | 33236901 ps | ||
| T256 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.3604880537 | Aug 27 07:02:46 AM UTC 24 | Aug 27 07:02:49 AM UTC 24 | 1275797948 ps | ||
| T269 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/41.rv_dm_stress_all.2168123718 | Aug 27 07:02:44 AM UTC 24 | Aug 27 07:02:49 AM UTC 24 | 3233364800 ps | ||
| T325 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/48.rv_dm_alert_test.364230192 | Aug 27 07:02:47 AM UTC 24 | Aug 27 07:02:49 AM UTC 24 | 116868790 ps | ||
| T326 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/38.rv_dm_stress_all.3004319620 | Aug 27 07:02:44 AM UTC 24 | Aug 27 07:02:50 AM UTC 24 | 2120852741 ps | ||
| T207 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/42.rv_dm_stress_all.3100785605 | Aug 27 07:02:44 AM UTC 24 | Aug 27 07:02:50 AM UTC 24 | 4379750204 ps | ||
| T327 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/40.rv_dm_stress_all.1094890063 | Aug 27 07:02:44 AM UTC 24 | Aug 27 07:02:50 AM UTC 24 | 775437672 ps | ||
| T276 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/6.rv_dm_sba_tl_access.1623148688 | Aug 27 07:02:12 AM UTC 24 | Aug 27 07:02:50 AM UTC 24 | 13277560780 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.1989321541 | Aug 27 07:02:41 AM UTC 24 | Aug 27 07:02:51 AM UTC 24 | 2511912332 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.2519387540 | Aug 27 07:02:37 AM UTC 24 | Aug 27 07:02:52 AM UTC 24 | 4035545123 ps | ||
| T230 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/39.rv_dm_stress_all.1139815081 | Aug 27 07:02:44 AM UTC 24 | Aug 27 07:02:52 AM UTC 24 | 3321448151 ps | ||
| T328 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/36.rv_dm_stress_all.2036101813 | Aug 27 07:02:43 AM UTC 24 | Aug 27 07:02:52 AM UTC 24 | 8890990743 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.3928692034 | Aug 27 07:02:00 AM UTC 24 | Aug 27 07:02:52 AM UTC 24 | 3943703901 ps | ||
| T329 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/49.rv_dm_stress_all.4256101214 | Aug 27 07:02:47 AM UTC 24 | Aug 27 07:02:54 AM UTC 24 | 4212168260 ps | ||
| T231 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/32.rv_dm_stress_all.3169044891 | Aug 27 07:02:41 AM UTC 24 | Aug 27 07:02:55 AM UTC 24 | 3703470660 ps | ||
| T213 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/45.rv_dm_stress_all.1285013610 | Aug 27 07:02:46 AM UTC 24 | Aug 27 07:02:57 AM UTC 24 | 3148637335 ps | ||
| T268 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/43.rv_dm_stress_all.2007531059 | Aug 27 07:02:46 AM UTC 24 | Aug 27 07:02:58 AM UTC 24 | 2917366282 ps | ||
| T330 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.586254555 | Aug 27 07:02:43 AM UTC 24 | Aug 27 07:03:00 AM UTC 24 | 4904640188 ps | ||
| T80 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all_with_rand_reset.693719702 | Aug 27 07:02:13 AM UTC 24 | Aug 27 07:03:01 AM UTC 24 | 12268744661 ps | ||
| T331 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/48.rv_dm_stress_all.3522560815 | Aug 27 07:02:47 AM UTC 24 | Aug 27 07:03:02 AM UTC 24 | 10855305081 ps | ||
| T332 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/47.rv_dm_stress_all.1615545128 | Aug 27 07:02:46 AM UTC 24 | Aug 27 07:03:02 AM UTC 24 | 5904991865 ps | ||
| T333 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/coverage/default/29.rv_dm_stress_all.2828708779 | Aug 27 07:02:40 AM UTC 24 | Aug 27 07:03:05 AM UTC 24 | 11012555868 ps |
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