| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 88.83 | 96.32 | 89.96 | 92.10 | 93.33 | 90.44 | 98.63 | 61.04 |
| T324 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/47.rv_dm_stress_all.3764465049 | Aug 28 10:21:22 PM UTC 24 | Aug 28 10:21:40 PM UTC 24 | 5637728113 ps | ||
| T325 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.3494961271 | Aug 28 10:21:10 PM UTC 24 | Aug 28 10:21:42 PM UTC 24 | 7964688775 ps | ||
| T116 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all_with_rand_reset.769626160 | Aug 28 10:20:43 PM UTC 24 | Aug 28 10:21:45 PM UTC 24 | 13518549965 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.1522795765 | Aug 28 10:20:42 PM UTC 24 | Aug 28 10:21:48 PM UTC 24 | 15487233958 ps | ||
| T326 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.2315043520 | Aug 28 10:21:20 PM UTC 24 | Aug 28 10:21:50 PM UTC 24 | 6917382794 ps | ||
| T82 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.296609496 | Aug 28 10:20:44 PM UTC 24 | Aug 28 10:21:56 PM UTC 24 | 8983551597 ps | ||
| T327 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.4245687602 | Aug 28 10:20:47 PM UTC 24 | Aug 28 10:22:03 PM UTC 24 | 26880111337 ps | ||
| T328 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/37.rv_dm_stress_all.856150941 | Aug 28 10:21:17 PM UTC 24 | Aug 28 10:22:05 PM UTC 24 | 11764457476 ps | ||
| T84 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.923598115 | Aug 28 10:20:42 PM UTC 24 | Aug 28 10:22:15 PM UTC 24 | 13351806069 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.29161233 | Aug 28 10:20:33 PM UTC 24 | Aug 28 10:22:32 PM UTC 24 | 64479767919 ps | ||
| T329 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_autoincr_sba_tl_access.166076874 | Aug 28 10:20:12 PM UTC 24 | Aug 28 10:23:50 PM UTC 24 | 63083674280 ps | ||
| T330 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/12.rv_dm_autoincr_sba_tl_access.828494674 | Aug 28 10:20:54 PM UTC 24 | Aug 28 10:23:54 PM UTC 24 | 57466761187 ps | ||
| T104 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3580461315 | Aug 28 10:55:10 PM UTC 24 | Aug 28 10:55:13 PM UTC 24 | 284225729 ps | ||
| T105 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1466624237 | Aug 28 10:55:10 PM UTC 24 | Aug 28 10:55:13 PM UTC 24 | 998196654 ps | ||
| T148 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.923535342 | Aug 28 10:55:10 PM UTC 24 | Aug 28 10:55:14 PM UTC 24 | 1155787145 ps | ||
| T106 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2547535305 | Aug 28 10:55:10 PM UTC 24 | Aug 28 10:55:14 PM UTC 24 | 5692658993 ps | ||
| T331 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3205392206 | Aug 28 10:55:10 PM UTC 24 | Aug 28 10:55:15 PM UTC 24 | 972808405 ps | ||
| T332 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2858433828 | Aug 28 10:55:13 PM UTC 24 | Aug 28 10:55:16 PM UTC 24 | 136193180 ps | ||
| T333 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.761708863 | Aug 28 10:55:14 PM UTC 24 | Aug 28 10:55:16 PM UTC 24 | 150916887 ps | ||
| T334 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.1384315637 | Aug 28 10:55:11 PM UTC 24 | Aug 28 10:55:17 PM UTC 24 | 134708976 ps | ||
| T335 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.94475724 | Aug 28 10:55:14 PM UTC 24 | Aug 28 10:55:17 PM UTC 24 | 377915318 ps | ||
| T134 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1591562039 | Aug 28 10:55:13 PM UTC 24 | Aug 28 10:55:19 PM UTC 24 | 825137597 ps | ||
| T117 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.213290930 | Aug 28 10:55:13 PM UTC 24 | Aug 28 10:55:19 PM UTC 24 | 79649729 ps | ||
| T336 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.4025013864 | Aug 28 10:55:14 PM UTC 24 | Aug 28 10:55:20 PM UTC 24 | 3176723158 ps | ||
| T337 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.2751044524 | Aug 28 10:55:11 PM UTC 24 | Aug 28 10:55:21 PM UTC 24 | 288191586 ps | ||
| T338 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2083823277 | Aug 28 10:55:14 PM UTC 24 | Aug 28 10:55:42 PM UTC 24 | 7825272880 ps | ||
| T339 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3912868973 | Aug 28 10:55:16 PM UTC 24 | Aug 28 10:55:21 PM UTC 24 | 112563012 ps | ||
| T340 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.4005904183 | Aug 28 10:55:13 PM UTC 24 | Aug 28 10:55:22 PM UTC 24 | 124320640 ps | ||
| T341 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1478561070 | Aug 28 10:55:14 PM UTC 24 | Aug 28 10:55:23 PM UTC 24 | 1534857449 ps | ||
| T342 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.967604881 | Aug 28 10:55:18 PM UTC 24 | Aug 28 10:55:23 PM UTC 24 | 661200755 ps | ||
| T179 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3019189601 | Aug 28 10:55:11 PM UTC 24 | Aug 28 10:55:23 PM UTC 24 | 2158813101 ps | ||
| T135 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2850089425 | Aug 28 10:55:16 PM UTC 24 | Aug 28 10:55:23 PM UTC 24 | 1507682241 ps | ||
| T136 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.2301885567 | Aug 28 10:55:13 PM UTC 24 | Aug 28 10:55:23 PM UTC 24 | 119222407 ps | ||
| T137 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1055359229 | Aug 28 10:55:13 PM UTC 24 | Aug 28 10:55:24 PM UTC 24 | 305298542 ps | ||
| T343 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3551474353 | Aug 28 10:55:17 PM UTC 24 | Aug 28 10:55:24 PM UTC 24 | 595632255 ps | ||
| T118 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2317734512 | Aug 28 10:55:17 PM UTC 24 | Aug 28 10:55:24 PM UTC 24 | 93588480 ps | ||
| T344 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2695045930 | Aug 28 10:55:11 PM UTC 24 | Aug 28 10:55:24 PM UTC 24 | 1781233422 ps | ||
| T345 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.2801661502 | Aug 28 10:55:16 PM UTC 24 | Aug 28 10:55:25 PM UTC 24 | 1201694287 ps | ||
| T138 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.1015885220 | Aug 28 10:55:17 PM UTC 24 | Aug 28 10:55:25 PM UTC 24 | 539948043 ps | ||
| T149 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1462161787 | Aug 28 10:55:19 PM UTC 24 | Aug 28 10:55:26 PM UTC 24 | 2805304687 ps | ||
| T346 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_errors.2278979107 | Aug 28 10:55:35 PM UTC 24 | Aug 28 10:55:43 PM UTC 24 | 596107015 ps | ||
| T347 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3782028471 | Aug 28 10:55:18 PM UTC 24 | Aug 28 10:55:26 PM UTC 24 | 1127565884 ps | ||
| T348 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_partial_access.645157161 | Aug 28 10:55:23 PM UTC 24 | Aug 28 10:55:26 PM UTC 24 | 48876148 ps | ||
| T349 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.4092811533 | Aug 28 10:55:18 PM UTC 24 | Aug 28 10:55:26 PM UTC 24 | 2957754675 ps | ||
| T350 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_walk.1000159552 | Aug 28 10:55:23 PM UTC 24 | Aug 28 10:55:26 PM UTC 24 | 137195403 ps | ||
| T139 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_rw.957409903 | Aug 28 10:55:23 PM UTC 24 | Aug 28 10:55:28 PM UTC 24 | 134261533 ps | ||
| T351 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1053030475 | Aug 28 10:55:24 PM UTC 24 | Aug 28 10:55:28 PM UTC 24 | 1229307668 ps | ||
| T140 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1757863732 | Aug 28 10:55:23 PM UTC 24 | Aug 28 10:55:28 PM UTC 24 | 134879917 ps | ||
| T115 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3589573114 | Aug 28 10:55:24 PM UTC 24 | Aug 28 10:55:29 PM UTC 24 | 117756461 ps | ||
| T352 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1368784997 | Aug 28 10:55:21 PM UTC 24 | Aug 28 10:55:29 PM UTC 24 | 2166601489 ps | ||
| T141 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4249900715 | Aug 28 10:55:17 PM UTC 24 | Aug 28 10:55:48 PM UTC 24 | 2833113110 ps | ||
| T142 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.4067373471 | Aug 28 10:55:24 PM UTC 24 | Aug 28 10:55:30 PM UTC 24 | 235010462 ps | ||
| T353 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.500818112 | Aug 28 10:55:16 PM UTC 24 | Aug 28 10:55:31 PM UTC 24 | 65534281 ps | ||
| T354 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.185281482 | Aug 28 10:55:26 PM UTC 24 | Aug 28 10:55:31 PM UTC 24 | 329319014 ps | ||
| T355 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2773586455 | Aug 28 10:55:29 PM UTC 24 | Aug 28 10:55:31 PM UTC 24 | 59831107 ps | ||
| T356 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_walk.1481111935 | Aug 28 10:55:29 PM UTC 24 | Aug 28 10:55:32 PM UTC 24 | 43649102 ps | ||
| T357 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_errors.1520503341 | Aug 28 10:55:22 PM UTC 24 | Aug 28 10:55:32 PM UTC 24 | 247417843 ps | ||
| T143 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.473404815 | Aug 28 10:55:29 PM UTC 24 | Aug 28 10:55:32 PM UTC 24 | 153115838 ps | ||
| T153 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.731982287 | Aug 28 10:55:16 PM UTC 24 | Aug 28 10:55:32 PM UTC 24 | 250353002 ps | ||
| T154 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_rw.2078826723 | Aug 28 10:55:30 PM UTC 24 | Aug 28 10:55:34 PM UTC 24 | 198285503 ps | ||
| T150 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.911159460 | Aug 28 10:55:26 PM UTC 24 | Aug 28 10:55:34 PM UTC 24 | 2078797576 ps | ||
| T358 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3797177564 | Aug 28 10:55:33 PM UTC 24 | Aug 28 10:55:35 PM UTC 24 | 222303448 ps | ||
| T359 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.4134647662 | Aug 28 10:55:33 PM UTC 24 | Aug 28 10:55:35 PM UTC 24 | 242943465 ps | ||
| T360 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.4109943585 | Aug 28 10:55:33 PM UTC 24 | Aug 28 10:55:36 PM UTC 24 | 493771832 ps | ||
| T155 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1823341804 | Aug 28 10:55:10 PM UTC 24 | Aug 28 10:55:48 PM UTC 24 | 7202300507 ps | ||
| T361 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_errors.1642760242 | Aug 28 10:55:27 PM UTC 24 | Aug 28 10:55:36 PM UTC 24 | 194737475 ps | ||
| T119 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3188281372 | Aug 28 10:55:32 PM UTC 24 | Aug 28 10:55:36 PM UTC 24 | 48358348 ps | ||
| T362 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3170785978 | Aug 28 10:55:33 PM UTC 24 | Aug 28 10:55:37 PM UTC 24 | 932870398 ps | ||
| T363 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.80757133 | Aug 28 10:55:26 PM UTC 24 | Aug 28 10:55:37 PM UTC 24 | 1092968437 ps | ||
| T182 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3334459534 | Aug 28 10:55:22 PM UTC 24 | Aug 28 10:55:37 PM UTC 24 | 3578623726 ps | ||
| T364 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_walk.1363546599 | Aug 28 10:55:36 PM UTC 24 | Aug 28 10:55:39 PM UTC 24 | 35822014 ps | ||
| T365 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2226604528 | Aug 28 10:55:37 PM UTC 24 | Aug 28 10:55:39 PM UTC 24 | 43142732 ps | ||
| T183 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3281092864 | Aug 28 10:55:16 PM UTC 24 | Aug 28 10:55:39 PM UTC 24 | 4863102141 ps | ||
| T180 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.2168811832 | Aug 28 10:55:11 PM UTC 24 | Aug 28 10:55:39 PM UTC 24 | 5080805294 ps | ||
| T151 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.718684004 | Aug 28 10:55:14 PM UTC 24 | Aug 28 10:55:40 PM UTC 24 | 21352082230 ps | ||
| T174 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2462073570 | Aug 28 10:55:37 PM UTC 24 | Aug 28 10:55:42 PM UTC 24 | 365356363 ps | ||
| T156 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_rw.179163713 | Aug 28 10:55:38 PM UTC 24 | Aug 28 10:55:42 PM UTC 24 | 181952742 ps | ||
| T366 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.915092209 | Aug 28 10:55:38 PM UTC 24 | Aug 28 10:55:42 PM UTC 24 | 56718141 ps | ||
| T157 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3703870698 | Aug 28 10:55:13 PM UTC 24 | Aug 28 10:55:42 PM UTC 24 | 1124699664 ps | ||
| T209 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3929879225 | Aug 28 10:55:27 PM UTC 24 | Aug 28 10:55:42 PM UTC 24 | 3520923006 ps | ||
| T163 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_rw.158424833 | Aug 28 10:55:41 PM UTC 24 | Aug 28 10:55:44 PM UTC 24 | 163467692 ps | ||
| T167 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.451854622 | Aug 28 10:55:32 PM UTC 24 | Aug 28 10:55:44 PM UTC 24 | 848960289 ps | ||
| T367 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.213021187 | Aug 28 10:55:39 PM UTC 24 | Aug 28 10:55:45 PM UTC 24 | 693689915 ps | ||
| T368 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.231982988 | Aug 28 10:55:33 PM UTC 24 | Aug 28 10:55:45 PM UTC 24 | 7854596706 ps | ||
| T369 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3672592004 | Aug 28 10:55:40 PM UTC 24 | Aug 28 10:55:46 PM UTC 24 | 5075430675 ps | ||
| T370 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1808467744 | Aug 28 10:55:43 PM UTC 24 | Aug 28 10:55:46 PM UTC 24 | 394016832 ps | ||
| T168 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.4127794900 | Aug 28 10:55:38 PM UTC 24 | Aug 28 10:55:46 PM UTC 24 | 286398136 ps | ||
| T371 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_errors.2988547302 | Aug 28 10:55:41 PM UTC 24 | Aug 28 10:55:47 PM UTC 24 | 232862435 ps | ||
| T372 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1222039197 | Aug 28 10:55:43 PM UTC 24 | Aug 28 10:55:47 PM UTC 24 | 127271081 ps | ||
| T373 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.368057439 | Aug 28 10:55:11 PM UTC 24 | Aug 28 10:55:48 PM UTC 24 | 81852743862 ps | ||
| T164 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_rw.141505920 | Aug 28 10:55:45 PM UTC 24 | Aug 28 10:55:49 PM UTC 24 | 88439544 ps | ||
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| T375 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1260080977 | Aug 28 10:55:46 PM UTC 24 | Aug 28 10:55:49 PM UTC 24 | 224285753 ps | ||
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| T207 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2266603936 | Aug 28 10:55:54 PM UTC 24 | Aug 28 10:56:18 PM UTC 24 | 4433354006 ps | ||
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| T377 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3844651375 | Aug 28 10:55:49 PM UTC 24 | Aug 28 10:55:51 PM UTC 24 | 307064401 ps | ||
| T378 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_errors.4210450195 | Aug 28 10:55:44 PM UTC 24 | Aug 28 10:55:51 PM UTC 24 | 146955302 ps | ||
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| T380 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_errors.1021160339 | Aug 28 10:55:47 PM UTC 24 | Aug 28 10:55:52 PM UTC 24 | 90367158 ps | ||
| T381 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.246005078 | Aug 28 10:55:49 PM UTC 24 | Aug 28 10:55:52 PM UTC 24 | 103676049 ps | ||
| T382 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1214080308 | Aug 28 10:55:21 PM UTC 24 | Aug 28 10:55:53 PM UTC 24 | 15086864170 ps | ||
| T383 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1302764934 | Aug 28 10:55:49 PM UTC 24 | Aug 28 10:55:53 PM UTC 24 | 5610994674 ps | ||
| T165 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_rw.681514136 | Aug 28 10:55:49 PM UTC 24 | Aug 28 10:55:53 PM UTC 24 | 217786569 ps | ||
| T384 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2354043675 | Aug 28 10:55:47 PM UTC 24 | Aug 28 10:55:54 PM UTC 24 | 4083271482 ps | ||
| T385 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3805943428 | Aug 28 10:55:17 PM UTC 24 | Aug 28 10:55:54 PM UTC 24 | 2539228011 ps | ||
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| T388 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_errors.3510097933 | Aug 28 10:55:51 PM UTC 24 | Aug 28 10:55:57 PM UTC 24 | 193714476 ps | ||
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| T389 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_rw.1446362908 | Aug 28 10:55:54 PM UTC 24 | Aug 28 10:55:57 PM UTC 24 | 47880089 ps | ||
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| T391 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3088064940 | Aug 28 10:55:52 PM UTC 24 | Aug 28 10:55:58 PM UTC 24 | 262809012 ps | ||
| T152 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2936433663 | Aug 28 10:55:33 PM UTC 24 | Aug 28 10:55:58 PM UTC 24 | 18117916556 ps | ||
| T392 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2098489141 | Aug 28 10:55:52 PM UTC 24 | Aug 28 10:56:00 PM UTC 24 | 1605159281 ps | ||
| T393 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1539028184 | Aug 28 10:55:55 PM UTC 24 | Aug 28 10:56:00 PM UTC 24 | 182049156 ps | ||
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| T395 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_errors.1730751394 | Aug 28 10:55:54 PM UTC 24 | Aug 28 10:56:01 PM UTC 24 | 527857286 ps | ||
| T158 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1539141963 | Aug 28 10:55:49 PM UTC 24 | Aug 28 10:56:01 PM UTC 24 | 2265512936 ps | ||
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| T397 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.426482049 | Aug 28 10:55:44 PM UTC 24 | Aug 28 10:56:03 PM UTC 24 | 10596281350 ps | ||
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| T159 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.3913404578 | Aug 28 10:55:58 PM UTC 24 | Aug 28 10:56:03 PM UTC 24 | 275116658 ps | ||
| T398 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.343271280 | Aug 28 10:55:58 PM UTC 24 | Aug 28 10:56:03 PM UTC 24 | 126667701 ps | ||
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| T401 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1897923701 | Aug 28 10:55:14 PM UTC 24 | Aug 28 10:56:05 PM UTC 24 | 105721015770 ps | ||
| T211 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_intg_err.247249851 | Aug 28 10:55:45 PM UTC 24 | Aug 28 10:56:05 PM UTC 24 | 1397921528 ps | ||
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| T402 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.1476122172 | Aug 28 10:55:57 PM UTC 24 | Aug 28 10:56:05 PM UTC 24 | 197606090 ps | ||
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| T404 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_rw.3127222205 | Aug 28 10:56:02 PM UTC 24 | Aug 28 10:56:07 PM UTC 24 | 128123486 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1976171243 | Aug 28 10:55:54 PM UTC 24 | Aug 28 10:56:07 PM UTC 24 | 572244679 ps | ||
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| T406 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2608772081 | Aug 28 10:55:52 PM UTC 24 | Aug 28 10:56:07 PM UTC 24 | 2361787102 ps | ||
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| T408 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_errors.2973406082 | Aug 28 10:56:01 PM UTC 24 | Aug 28 10:56:08 PM UTC 24 | 258266422 ps | ||
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| T161 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1739880324 | Aug 28 10:56:02 PM UTC 24 | Aug 28 10:56:08 PM UTC 24 | 181669516 ps | ||
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| T411 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_errors.389096299 | Aug 28 10:56:04 PM UTC 24 | Aug 28 10:56:09 PM UTC 24 | 472670928 ps | ||
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| T412 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_intg_err.605196085 | Aug 28 10:55:51 PM UTC 24 | Aug 28 10:56:10 PM UTC 24 | 2996077809 ps | ||
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| T212 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3041268628 | Aug 28 10:55:41 PM UTC 24 | Aug 28 10:56:11 PM UTC 24 | 2792485256 ps | ||
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| T416 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2151360420 | Aug 28 10:56:08 PM UTC 24 | Aug 28 10:56:12 PM UTC 24 | 190811332 ps | ||
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| T418 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.2566218797 | Aug 28 10:55:27 PM UTC 24 | Aug 28 10:56:13 PM UTC 24 | 5518505614 ps | ||
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| T420 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_rw.22945320 | Aug 28 10:56:11 PM UTC 24 | Aug 28 10:56:14 PM UTC 24 | 611495865 ps | ||
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| T422 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2310728075 | Aug 28 10:56:12 PM UTC 24 | Aug 28 10:56:14 PM UTC 24 | 121425630 ps | ||
| T423 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_errors.3859943816 | Aug 28 10:56:09 PM UTC 24 | Aug 28 10:56:15 PM UTC 24 | 431472674 ps | ||
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| T111 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.4293378380 | Aug 28 10:55:50 PM UTC 24 | Aug 28 10:56:16 PM UTC 24 | 2585587111 ps | ||
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| T162 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3739713158 | Aug 28 10:56:06 PM UTC 24 | Aug 28 10:56:17 PM UTC 24 | 813045825 ps | ||
| T426 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3325966055 | Aug 28 10:55:27 PM UTC 24 | Aug 28 10:56:17 PM UTC 24 | 12032507170 ps | ||
| T427 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1559577028 | Aug 28 10:56:11 PM UTC 24 | Aug 28 10:56:17 PM UTC 24 | 185969381 ps | ||
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| T429 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1853785445 | Aug 28 10:56:08 PM UTC 24 | Aug 28 10:56:17 PM UTC 24 | 460500034 ps | ||
| T430 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1665566433 | Aug 28 10:56:11 PM UTC 24 | Aug 28 10:56:18 PM UTC 24 | 245192725 ps | ||
| T431 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_errors.3707852390 | Aug 28 10:56:12 PM UTC 24 | Aug 28 10:56:18 PM UTC 24 | 134147811 ps | ||
| T432 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1966881120 | Aug 28 10:56:14 PM UTC 24 | Aug 28 10:56:18 PM UTC 24 | 73689311 ps | ||
| T433 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_errors.1955433404 | Aug 28 10:56:14 PM UTC 24 | Aug 28 10:56:18 PM UTC 24 | 1228227898 ps | ||
| T434 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2003595262 | Aug 28 10:56:17 PM UTC 24 | Aug 28 10:56:19 PM UTC 24 | 173659937 ps | ||
| T435 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_rw.4253288628 | Aug 28 10:56:16 PM UTC 24 | Aug 28 10:56:19 PM UTC 24 | 166841011 ps | ||
| T436 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.4038451257 | Aug 28 10:55:34 PM UTC 24 | Aug 28 10:56:19 PM UTC 24 | 40855437512 ps | ||
| T437 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.498786494 | Aug 28 10:56:14 PM UTC 24 | Aug 28 10:56:20 PM UTC 24 | 1090972147 ps | ||
| T438 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2390522387 | Aug 28 10:56:16 PM UTC 24 | Aug 28 10:56:21 PM UTC 24 | 841319810 ps | ||
| T439 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.2687802807 | Aug 28 10:56:09 PM UTC 24 | Aug 28 10:56:21 PM UTC 24 | 8189224836 ps | ||
| T440 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_rw.2589445742 | Aug 28 10:56:18 PM UTC 24 | Aug 28 10:56:21 PM UTC 24 | 177016529 ps | ||
| T441 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2561504665 | Aug 28 10:56:18 PM UTC 24 | Aug 28 10:56:22 PM UTC 24 | 4417667991 ps | ||
| T442 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.237433953 | Aug 28 10:56:19 PM UTC 24 | Aug 28 10:56:22 PM UTC 24 | 233253252 ps | ||
| T443 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.405422869 | Aug 28 10:56:00 PM UTC 24 | Aug 28 10:56:22 PM UTC 24 | 4944425424 ps | ||
| T444 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2999933132 | Aug 28 10:56:07 PM UTC 24 | Aug 28 10:56:22 PM UTC 24 | 2612642258 ps | ||
| T445 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.248953187 | Aug 28 10:55:57 PM UTC 24 | Aug 28 10:56:22 PM UTC 24 | 6420461676 ps | ||
| T113 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1483794298 | Aug 28 10:56:17 PM UTC 24 | Aug 28 10:56:23 PM UTC 24 | 125714177 ps | ||
| T446 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.573951578 | Aug 28 10:56:13 PM UTC 24 | Aug 28 10:56:23 PM UTC 24 | 830575395 ps | ||
| T447 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_rw.3982637990 | Aug 28 10:56:20 PM UTC 24 | Aug 28 10:56:23 PM UTC 24 | 273961114 ps | ||
| T448 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2498075628 | Aug 28 10:56:19 PM UTC 24 | Aug 28 10:56:23 PM UTC 24 | 61445357 ps | ||
| T449 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_errors.1884948552 | Aug 28 10:56:18 PM UTC 24 | Aug 28 10:56:23 PM UTC 24 | 226741505 ps | ||
| T450 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_errors.1074253191 | Aug 28 10:56:20 PM UTC 24 | Aug 28 10:56:24 PM UTC 24 | 298796860 ps | ||
| T451 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.118444856 | Aug 28 10:56:22 PM UTC 24 | Aug 28 10:56:24 PM UTC 24 | 198288645 ps | ||
| T215 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1020402908 | Aug 28 10:56:08 PM UTC 24 | Aug 28 10:56:24 PM UTC 24 | 1318502073 ps | ||
| T452 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1669279065 | Aug 28 10:56:14 PM UTC 24 | Aug 28 10:56:25 PM UTC 24 | 17362467292 ps | ||
| T453 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.314205252 | Aug 28 10:55:34 PM UTC 24 | Aug 28 10:56:25 PM UTC 24 | 23201455668 ps | ||
| T454 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2937571499 | Aug 28 10:56:21 PM UTC 24 | Aug 28 10:56:25 PM UTC 24 | 168777381 ps | ||
| T455 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1546100311 | Aug 28 10:56:20 PM UTC 24 | Aug 28 10:56:25 PM UTC 24 | 98180513 ps | ||
| T456 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1364391523 | Aug 28 10:56:09 PM UTC 24 | Aug 28 10:56:26 PM UTC 24 | 3193284073 ps | ||
| T457 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_rw.1222725760 | Aug 28 10:56:23 PM UTC 24 | Aug 28 10:56:26 PM UTC 24 | 775654880 ps | ||
| T214 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3512279382 | Aug 28 10:56:04 PM UTC 24 | Aug 28 10:56:27 PM UTC 24 | 1606140923 ps | ||
| T210 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1379197356 | Aug 28 10:56:12 PM UTC 24 | Aug 28 10:56:27 PM UTC 24 | 1351146228 ps | ||
| T458 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1808351369 | Aug 28 10:56:18 PM UTC 24 | Aug 28 10:56:28 PM UTC 24 | 170926014 ps | ||
| T459 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2634815952 | Aug 28 10:56:16 PM UTC 24 | Aug 28 10:56:28 PM UTC 24 | 2634377673 ps | ||
| T460 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2586987976 | Aug 28 10:56:23 PM UTC 24 | Aug 28 10:56:29 PM UTC 24 | 171686723 ps | ||
| T461 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3577397124 | Aug 28 10:56:23 PM UTC 24 | Aug 28 10:56:30 PM UTC 24 | 411024254 ps | ||
| T462 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.192204331 | Aug 28 10:56:09 PM UTC 24 | Aug 28 10:56:30 PM UTC 24 | 5306488279 ps | ||
| T463 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2037312250 | Aug 28 10:56:22 PM UTC 24 | Aug 28 10:56:30 PM UTC 24 | 1703950365 ps | ||
| T464 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.538700153 | Aug 28 10:55:11 PM UTC 24 | Aug 28 10:56:30 PM UTC 24 | 43016417081 ps | ||
| T206 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3502621762 | Aug 28 10:56:02 PM UTC 24 | Aug 28 10:56:31 PM UTC 24 | 2389123954 ps | ||
| T465 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_errors.495920237 | Aug 28 10:56:23 PM UTC 24 | Aug 28 10:56:32 PM UTC 24 | 442770830 ps | ||
| T466 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3176691521 | Aug 28 10:56:20 PM UTC 24 | Aug 28 10:56:32 PM UTC 24 | 1238829776 ps | ||
| T467 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2908439393 | Aug 28 10:56:18 PM UTC 24 | Aug 28 10:56:38 PM UTC 24 | 1372533141 ps | ||
| T108 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1909839395 | Aug 28 10:55:47 PM UTC 24 | Aug 28 10:56:39 PM UTC 24 | 8226592483 ps | ||
| T468 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1186062962 | Aug 28 10:55:38 PM UTC 24 | Aug 28 10:56:40 PM UTC 24 | 3020651989 ps | ||
| T469 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2989162674 | Aug 28 10:55:24 PM UTC 24 | Aug 28 10:56:41 PM UTC 24 | 23468653901 ps | ||
| T470 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2494541552 | Aug 28 10:56:01 PM UTC 24 | Aug 28 10:56:44 PM UTC 24 | 14527677658 ps | ||
| T471 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2145087311 | Aug 28 10:56:19 PM UTC 24 | Aug 28 10:56:45 PM UTC 24 | 5077261529 ps | ||
| T472 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.2036625497 | Aug 28 10:56:22 PM UTC 24 | Aug 28 10:56:48 PM UTC 24 | 8125508742 ps | ||
| T473 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.4033083284 | Aug 28 10:55:46 PM UTC 24 | Aug 28 10:56:51 PM UTC 24 | 15346615737 ps | ||
| T474 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_aliasing.472480613 | Aug 28 10:55:32 PM UTC 24 | Aug 28 10:56:52 PM UTC 24 | 8827710903 ps | ||
| T475 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2367274988 | Aug 28 10:56:07 PM UTC 24 | Aug 28 10:57:00 PM UTC 24 | 26210766184 ps | ||
| T476 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_aliasing.992061571 | Aug 28 10:55:24 PM UTC 24 | Aug 28 10:57:01 PM UTC 24 | 4521760524 ps | ||
| T120 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2494991659 | Aug 28 10:55:34 PM UTC 24 | Aug 28 10:57:03 PM UTC 24 | 8359565687 ps | ||
| T477 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2677379959 | Aug 28 10:56:23 PM UTC 24 | Aug 28 10:57:07 PM UTC 24 | 4254991550 ps | ||
| T114 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3718513161 | Aug 28 10:55:44 PM UTC 24 | Aug 28 10:57:14 PM UTC 24 | 4678199993 ps | ||
| T121 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2276334865 | Aug 28 10:55:40 PM UTC 24 | Aug 28 10:57:17 PM UTC 24 | 63056838332 ps | ||
| T478 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2444385703 | Aug 28 10:55:53 PM UTC 24 | Aug 28 10:57:28 PM UTC 24 | 3377710604 ps | ||
| T479 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.2072812448 | Aug 28 10:56:19 PM UTC 24 | Aug 28 10:57:32 PM UTC 24 | 63070692193 ps | ||
| T480 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.933743859 | Aug 28 10:55:50 PM UTC 24 | Aug 28 10:57:33 PM UTC 24 | 25114670094 ps | ||
| T481 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.4278957452 | Aug 28 10:55:40 PM UTC 24 | Aug 28 10:57:59 PM UTC 24 | 32851122871 ps | ||
| T482 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.2414704865 | Aug 28 10:56:18 PM UTC 24 | Aug 28 10:58:47 PM UTC 24 | 54887145629 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_tl_access.366170637 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1083765804 ps |
| CPU time | 1.88 seconds |
| Started | Aug 28 10:20:02 PM UTC 24 |
| Finished | Aug 28 10:20:05 PM UTC 24 |
| Peak memory | 215416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366170637 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.366170637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.2860537682 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 2744016872 ps |
| CPU time | 43.53 seconds |
| Started | Aug 28 10:20:11 PM UTC 24 |
| Finished | Aug 28 10:20:56 PM UTC 24 |
| Peak memory | 233316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2860537682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stres s_all_with_rand_reset.2860537682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.2572161934 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 218358251 ps |
| CPU time | 1.71 seconds |
| Started | Aug 28 10:20:32 PM UTC 24 |
| Finished | Aug 28 10:20:35 PM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572161934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_halt_resume_whereto.2572161934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/2.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.3871296165 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 4134042740 ps |
| CPU time | 6.85 seconds |
| Started | Aug 28 10:20:02 PM UTC 24 |
| Finished | Aug 28 10:20:10 PM UTC 24 |
| Peak memory | 216064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871296165 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.3871296165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.3190243538 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 2231530935 ps |
| CPU time | 39.5 seconds |
| Started | Aug 28 10:20:48 PM UTC 24 |
| Finished | Aug 28 10:21:29 PM UTC 24 |
| Peak memory | 233236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3190243538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stres s_all_with_rand_reset.3190243538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.3326933569 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 4975268008 ps |
| CPU time | 8.29 seconds |
| Started | Aug 28 10:20:07 PM UTC 24 |
| Finished | Aug 28 10:20:16 PM UTC 24 |
| Peak memory | 216140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326933569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.3326933569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_sba_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.802217245 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 344680891 ps |
| CPU time | 1.87 seconds |
| Started | Aug 28 10:20:11 PM UTC 24 |
| Finished | Aug 28 10:20:14 PM UTC 24 |
| Peak memory | 252296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802217245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_buffered_enable.802217245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.4049283954 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 4074754370 ps |
| CPU time | 3.73 seconds |
| Started | Aug 28 10:20:11 PM UTC 24 |
| Finished | Aug 28 10:20:16 PM UTC 24 |
| Peak memory | 216244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049283954 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.4049283954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3019189601 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 2158813101 ps |
| CPU time | 10.15 seconds |
| Started | Aug 28 10:55:11 PM UTC 24 |
| Finished | Aug 28 10:55:23 PM UTC 24 |
| Peak memory | 232524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019189601 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.3019189601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.3162867789 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 32038033 ps |
| CPU time | 1.09 seconds |
| Started | Aug 28 10:20:11 PM UTC 24 |
| Finished | Aug 28 10:20:13 PM UTC 24 |
| Peak memory | 215916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162867789 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.3162867789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/4.rv_dm_autoincr_sba_tl_access.526183422 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 5774096499 ps |
| CPU time | 10.63 seconds |
| Started | Aug 28 10:20:33 PM UTC 24 |
| Finished | Aug 28 10:20:45 PM UTC 24 |
| Peak memory | 226436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526183422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.526183422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/4.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_autoincr_sba_tl_access.166076874 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 63083674280 ps |
| CPU time | 214.33 seconds |
| Started | Aug 28 10:20:12 PM UTC 24 |
| Finished | Aug 28 10:23:50 PM UTC 24 |
| Peak memory | 226568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166076874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.166076874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.750441322 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 204183610 ps |
| CPU time | 1.31 seconds |
| Started | Aug 28 10:20:10 PM UTC 24 |
| Finished | Aug 28 10:20:12 PM UTC 24 |
| Peak memory | 215952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750441322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_dmi_failed_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.750441322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_dmi_failed_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.651076510 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 2720539643 ps |
| CPU time | 50.08 seconds |
| Started | Aug 28 10:55:21 PM UTC 24 |
| Finished | Aug 28 10:56:16 PM UTC 24 |
| Peak memory | 227920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=651076510 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.651076510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/2.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.1428481820 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 57570630 ps |
| CPU time | 1.03 seconds |
| Started | Aug 28 10:20:11 PM UTC 24 |
| Finished | Aug 28 10:20:13 PM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428481820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_scanmode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 0.rv_dm_scanmode.1428481820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_scanmode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/31.rv_dm_stress_all.2456630097 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1687739454 ps |
| CPU time | 4.51 seconds |
| Started | Aug 28 10:21:15 PM UTC 24 |
| Finished | Aug 28 10:21:20 PM UTC 24 |
| Peak memory | 215852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456630097 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.2456630097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/31.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all.289360199 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1855048591 ps |
| CPU time | 3.66 seconds |
| Started | Aug 28 10:20:43 PM UTC 24 |
| Finished | Aug 28 10:20:48 PM UTC 24 |
| Peak memory | 226184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289360199 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.289360199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/6.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.473404815 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 153115838 ps |
| CPU time | 1.83 seconds |
| Started | Aug 28 10:55:29 PM UTC 24 |
| Finished | Aug 28 10:55:32 PM UTC 24 |
| Peak memory | 225164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473404815 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.473404815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/3.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.3982556581 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 2529419489 ps |
| CPU time | 3.15 seconds |
| Started | Aug 28 10:20:32 PM UTC 24 |
| Finished | Aug 28 10:20:37 PM UTC 24 |
| Peak memory | 254836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982556581 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.3982556581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/2.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3718513161 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 4678199993 ps |
| CPU time | 88.22 seconds |
| Started | Aug 28 10:55:44 PM UTC 24 |
| Finished | Aug 28 10:57:14 PM UTC 24 |
| Peak memory | 227864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3718513161 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_re set.3718513161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/6.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.3815535449 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 398696291 ps |
| CPU time | 2.14 seconds |
| Started | Aug 28 10:20:18 PM UTC 24 |
| Finished | Aug 28 10:20:21 PM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815535449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.3815535449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_dmi_failed_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.3174937521 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 451547632 ps |
| CPU time | 1.55 seconds |
| Started | Aug 28 10:20:13 PM UTC 24 |
| Finished | Aug 28 10:20:15 PM UTC 24 |
| Peak memory | 213460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174937521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.3174937521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_cmderr_exception/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3041268628 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 2792485256 ps |
| CPU time | 28.54 seconds |
| Started | Aug 28 10:55:41 PM UTC 24 |
| Finished | Aug 28 10:56:11 PM UTC 24 |
| Peak memory | 225892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041268628 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.3041268628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/5.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/42.rv_dm_stress_all.3292130302 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 3884121027 ps |
| CPU time | 15.17 seconds |
| Started | Aug 28 10:21:19 PM UTC 24 |
| Finished | Aug 28 10:21:35 PM UTC 24 |
| Peak memory | 215916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292130302 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.3292130302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/42.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.4102050230 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 91138820 ps |
| CPU time | 1.16 seconds |
| Started | Aug 28 10:20:09 PM UTC 24 |
| Finished | Aug 28 10:20:12 PM UTC 24 |
| Peak memory | 225912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102050230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_rom_read_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.4102050230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_rom_read_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/41.rv_dm_stress_all.2627090581 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 3344596103 ps |
| CPU time | 9.64 seconds |
| Started | Aug 28 10:21:19 PM UTC 24 |
| Finished | Aug 28 10:21:30 PM UTC 24 |
| Peak memory | 226304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627090581 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.2627090581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/41.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/16.rv_dm_autoincr_sba_tl_access.171965507 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 2960452418 ps |
| CPU time | 6.37 seconds |
| Started | Aug 28 10:21:03 PM UTC 24 |
| Finished | Aug 28 10:21:10 PM UTC 24 |
| Peak memory | 216264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171965507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.171965507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/16.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.923598115 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 13351806069 ps |
| CPU time | 90.33 seconds |
| Started | Aug 28 10:20:42 PM UTC 24 |
| Finished | Aug 28 10:22:15 PM UTC 24 |
| Peak memory | 233264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=923598115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress _all_with_rand_reset.923598115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.2050765568 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 10971303978 ps |
| CPU time | 34.15 seconds |
| Started | Aug 28 10:20:43 PM UTC 24 |
| Finished | Aug 28 10:21:19 PM UTC 24 |
| Peak memory | 233192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050765568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.2050765568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/7.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/17.rv_dm_autoincr_sba_tl_access.1744385639 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 6261983985 ps |
| CPU time | 14.67 seconds |
| Started | Aug 28 10:21:04 PM UTC 24 |
| Finished | Aug 28 10:21:20 PM UTC 24 |
| Peak memory | 226568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744385639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.1744385639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/17.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/43.rv_dm_stress_all.3076282560 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 5562647971 ps |
| CPU time | 9.21 seconds |
| Started | Aug 28 10:21:19 PM UTC 24 |
| Finished | Aug 28 10:21:29 PM UTC 24 |
| Peak memory | 216112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076282560 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.3076282560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/43.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1621063502 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 1192636132 ps |
| CPU time | 11.79 seconds |
| Started | Aug 28 10:55:58 PM UTC 24 |
| Finished | Aug 28 10:56:11 PM UTC 24 |
| Peak memory | 225708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621063502 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.1621063502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/10.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/45.rv_dm_stress_all.7315209 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 7685634352 ps |
| CPU time | 14.93 seconds |
| Started | Aug 28 10:21:22 PM UTC 24 |
| Finished | Aug 28 10:21:38 PM UTC 24 |
| Peak memory | 216064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7315209 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.7315209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/45.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1466624237 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 998196654 ps |
| CPU time | 2.2 seconds |
| Started | Aug 28 10:55:10 PM UTC 24 |
| Finished | Aug 28 10:55:13 PM UTC 24 |
| Peak memory | 215168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466624237 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_aliasing.1466624237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.836499136 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 77213609 ps |
| CPU time | 1.28 seconds |
| Started | Aug 28 10:20:09 PM UTC 24 |
| Finished | Aug 28 10:20:12 PM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836499136 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_abstractcmd_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.836499136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_abstractcmd_status/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1591562039 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 825137597 ps |
| CPU time | 4.42 seconds |
| Started | Aug 28 10:55:13 PM UTC 24 |
| Finished | Aug 28 10:55:19 PM UTC 24 |
| Peak memory | 215452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591562039 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_csr_outstanding.1591562039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3703870698 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 1124699664 ps |
| CPU time | 26.89 seconds |
| Started | Aug 28 10:55:13 PM UTC 24 |
| Finished | Aug 28 10:55:42 PM UTC 24 |
| Peak memory | 215432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703870698 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_aliasing.3703870698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.3989187357 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 377099887 ps |
| CPU time | 2.51 seconds |
| Started | Aug 28 10:20:05 PM UTC 24 |
| Finished | Aug 28 10:20:08 PM UTC 24 |
| Peak memory | 215996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989187357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.3989187357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_cmderr_halt_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2494991659 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 8359565687 ps |
| CPU time | 86.52 seconds |
| Started | Aug 28 10:55:34 PM UTC 24 |
| Finished | Aug 28 10:57:03 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2494991659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_re set.2494991659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/4.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3281092864 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 4863102141 ps |
| CPU time | 18.94 seconds |
| Started | Aug 28 10:55:16 PM UTC 24 |
| Finished | Aug 28 10:55:39 PM UTC 24 |
| Peak memory | 227776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281092864 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.3281092864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3502621762 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 2389123954 ps |
| CPU time | 27.29 seconds |
| Started | Aug 28 10:56:02 PM UTC 24 |
| Finished | Aug 28 10:56:31 PM UTC 24 |
| Peak memory | 227824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502621762 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.3502621762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/11.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1379197356 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 1351146228 ps |
| CPU time | 14.1 seconds |
| Started | Aug 28 10:56:12 PM UTC 24 |
| Finished | Aug 28 10:56:27 PM UTC 24 |
| Peak memory | 225664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379197356 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.1379197356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/15.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.4199922672 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 3427325370 ps |
| CPU time | 6.98 seconds |
| Started | Aug 28 10:21:09 PM UTC 24 |
| Finished | Aug 28 10:21:17 PM UTC 24 |
| Peak memory | 216072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199922672 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.4199922672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/20.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.119784072 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 150090969 ps |
| CPU time | 1.3 seconds |
| Started | Aug 28 10:20:11 PM UTC 24 |
| Finished | Aug 28 10:20:13 PM UTC 24 |
| Peak memory | 225800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119784072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sparse_lc_gate_fsm.119784072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_sparse_lc_gate_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.3832758513 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 71197746 ps |
| CPU time | 1.16 seconds |
| Started | Aug 28 10:20:18 PM UTC 24 |
| Finished | Aug 28 10:20:20 PM UTC 24 |
| Peak memory | 225856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832758513 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sparse_lc_gate_fsm.3832758513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_sparse_lc_gate_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2444385703 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 3377710604 ps |
| CPU time | 93 seconds |
| Started | Aug 28 10:55:53 PM UTC 24 |
| Finished | Aug 28 10:57:28 PM UTC 24 |
| Peak memory | 229960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2444385703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_re set.2444385703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/9.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_alert_test.240987015 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 106407532 ps |
| CPU time | 0.73 seconds |
| Started | Aug 28 10:20:32 PM UTC 24 |
| Finished | Aug 28 10:20:34 PM UTC 24 |
| Peak memory | 215936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240987015 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.240987015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1823341804 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 7202300507 ps |
| CPU time | 36.69 seconds |
| Started | Aug 28 10:55:10 PM UTC 24 |
| Finished | Aug 28 10:55:48 PM UTC 24 |
| Peak memory | 215560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823341804 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_aliasing.1823341804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.422996980 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 12910017095 ps |
| CPU time | 36.63 seconds |
| Started | Aug 28 10:55:13 PM UTC 24 |
| Finished | Aug 28 10:55:52 PM UTC 24 |
| Peak memory | 225640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422996980 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.422996980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1055359229 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 305298542 ps |
| CPU time | 2.66 seconds |
| Started | Aug 28 10:55:13 PM UTC 24 |
| Finished | Aug 28 10:55:24 PM UTC 24 |
| Peak memory | 225764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055359229 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.1055359229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.213290930 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 79649729 ps |
| CPU time | 4.42 seconds |
| Started | Aug 28 10:55:13 PM UTC 24 |
| Finished | Aug 28 10:55:19 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=213290930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_ra nd_reset.213290930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.2301885567 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 119222407 ps |
| CPU time | 2.65 seconds |
| Started | Aug 28 10:55:13 PM UTC 24 |
| Finished | Aug 28 10:55:23 PM UTC 24 |
| Peak memory | 225720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301885567 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.2301885567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.538700153 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 43016417081 ps |
| CPU time | 74.36 seconds |
| Started | Aug 28 10:55:11 PM UTC 24 |
| Finished | Aug 28 10:56:30 PM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538700153 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_aliasing.538700153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.368057439 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 81852743862 ps |
| CPU time | 35.02 seconds |
| Started | Aug 28 10:55:11 PM UTC 24 |
| Finished | Aug 28 10:55:48 PM UTC 24 |
| Peak memory | 215288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368057439 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_bit_bash.368057439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.923535342 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 1155787145 ps |
| CPU time | 2.6 seconds |
| Started | Aug 28 10:55:10 PM UTC 24 |
| Finished | Aug 28 10:55:14 PM UTC 24 |
| Peak memory | 215304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923535342 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_hw_reset.923535342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2695045930 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 1781233422 ps |
| CPU time | 8.85 seconds |
| Started | Aug 28 10:55:11 PM UTC 24 |
| Finished | Aug 28 10:55:24 PM UTC 24 |
| Peak memory | 215220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695045930 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.2695045930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2547535305 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 5692658993 ps |
| CPU time | 3.34 seconds |
| Started | Aug 28 10:55:10 PM UTC 24 |
| Finished | Aug 28 10:55:14 PM UTC 24 |
| Peak memory | 215488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547535305 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_bit_bash.2547535305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3580461315 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 284225729 ps |
| CPU time | 1.7 seconds |
| Started | Aug 28 10:55:10 PM UTC 24 |
| Finished | Aug 28 10:55:13 PM UTC 24 |
| Peak memory | 214612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580461315 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_hw_reset.3580461315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3205392206 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 972808405 ps |
| CPU time | 3.85 seconds |
| Started | Aug 28 10:55:10 PM UTC 24 |
| Finished | Aug 28 10:55:15 PM UTC 24 |
| Peak memory | 215072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205392206 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.3205392206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.4005904183 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 124320640 ps |
| CPU time | 1.35 seconds |
| Started | Aug 28 10:55:13 PM UTC 24 |
| Finished | Aug 28 10:55:22 PM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005904183 -assert nopostproc +UVM _TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_partial_access.4005904183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.1384315637 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 134708976 ps |
| CPU time | 1.54 seconds |
| Started | Aug 28 10:55:11 PM UTC 24 |
| Finished | Aug 28 10:55:17 PM UTC 24 |
| Peak memory | 215140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384315637 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.1384315637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.2168811832 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 5080805294 ps |
| CPU time | 23.11 seconds |
| Started | Aug 28 10:55:11 PM UTC 24 |
| Finished | Aug 28 10:55:39 PM UTC 24 |
| Peak memory | 227912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2168811832 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_re set.2168811832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.2751044524 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 288191586 ps |
| CPU time | 5.04 seconds |
| Started | Aug 28 10:55:11 PM UTC 24 |
| Finished | Aug 28 10:55:21 PM UTC 24 |
| Peak memory | 225788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751044524 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.2751044524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4249900715 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 2833113110 ps |
| CPU time | 26.35 seconds |
| Started | Aug 28 10:55:17 PM UTC 24 |
| Finished | Aug 28 10:55:48 PM UTC 24 |
| Peak memory | 225712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249900715 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.4249900715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2850089425 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 1507682241 ps |
| CPU time | 2.82 seconds |
| Started | Aug 28 10:55:16 PM UTC 24 |
| Finished | Aug 28 10:55:23 PM UTC 24 |
| Peak memory | 225608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850089425 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2850089425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2317734512 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 93588480 ps |
| CPU time | 2.84 seconds |
| Started | Aug 28 10:55:17 PM UTC 24 |
| Finished | Aug 28 10:55:24 PM UTC 24 |
| Peak memory | 227912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2317734512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_r and_reset.2317734512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.731982287 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 250353002 ps |
| CPU time | 2.16 seconds |
| Started | Aug 28 10:55:16 PM UTC 24 |
| Finished | Aug 28 10:55:32 PM UTC 24 |
| Peak memory | 225724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731982287 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.731982287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1897923701 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 105721015770 ps |
| CPU time | 48.74 seconds |
| Started | Aug 28 10:55:14 PM UTC 24 |
| Finished | Aug 28 10:56:05 PM UTC 24 |
| Peak memory | 215288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897923701 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_aliasing.1897923701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.4025013864 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 3176723158 ps |
| CPU time | 4.71 seconds |
| Started | Aug 28 10:55:14 PM UTC 24 |
| Finished | Aug 28 10:55:20 PM UTC 24 |
| Peak memory | 215444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025013864 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_bit_bash.4025013864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.718684004 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 21352082230 ps |
| CPU time | 24.09 seconds |
| Started | Aug 28 10:55:14 PM UTC 24 |
| Finished | Aug 28 10:55:40 PM UTC 24 |
| Peak memory | 215424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718684004 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_hw_reset.718684004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1478561070 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 1534857449 ps |
| CPU time | 7.05 seconds |
| Started | Aug 28 10:55:14 PM UTC 24 |
| Finished | Aug 28 10:55:23 PM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478561070 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.1478561070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.94475724 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 377915318 ps |
| CPU time | 2.09 seconds |
| Started | Aug 28 10:55:14 PM UTC 24 |
| Finished | Aug 28 10:55:17 PM UTC 24 |
| Peak memory | 215072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94475724 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_aliasing.94475724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2083823277 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 7825272880 ps |
| CPU time | 27.07 seconds |
| Started | Aug 28 10:55:14 PM UTC 24 |
| Finished | Aug 28 10:55:42 PM UTC 24 |
| Peak memory | 215516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083823277 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_bit_bash.2083823277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2858433828 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 136193180 ps |
| CPU time | 0.87 seconds |
| Started | Aug 28 10:55:13 PM UTC 24 |
| Finished | Aug 28 10:55:16 PM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858433828 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_hw_reset.2858433828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.761708863 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 150916887 ps |
| CPU time | 1.19 seconds |
| Started | Aug 28 10:55:14 PM UTC 24 |
| Finished | Aug 28 10:55:16 PM UTC 24 |
| Peak memory | 215084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761708863 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.761708863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3912868973 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 112563012 ps |
| CPU time | 1.47 seconds |
| Started | Aug 28 10:55:16 PM UTC 24 |
| Finished | Aug 28 10:55:21 PM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912868973 -assert nopostproc +UVM _TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_partial_access.3912868973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.500818112 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 65534281 ps |
| CPU time | 0.94 seconds |
| Started | Aug 28 10:55:16 PM UTC 24 |
| Finished | Aug 28 10:55:31 PM UTC 24 |
| Peak memory | 215084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500818112 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.500818112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.1015885220 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 539948043 ps |
| CPU time | 4.2 seconds |
| Started | Aug 28 10:55:17 PM UTC 24 |
| Finished | Aug 28 10:55:25 PM UTC 24 |
| Peak memory | 215392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015885220 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_csr_outstanding.1015885220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2300241832 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 7181821344 ps |
| CPU time | 40.96 seconds |
| Started | Aug 28 10:55:14 PM UTC 24 |
| Finished | Aug 28 10:55:57 PM UTC 24 |
| Peak memory | 229884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2300241832 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_re set.2300241832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.2801661502 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 1201694287 ps |
| CPU time | 4.99 seconds |
| Started | Aug 28 10:55:16 PM UTC 24 |
| Finished | Aug 28 10:55:25 PM UTC 24 |
| Peak memory | 225820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801661502 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.2801661502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.343271280 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 126667701 ps |
| CPU time | 3.23 seconds |
| Started | Aug 28 10:55:58 PM UTC 24 |
| Finished | Aug 28 10:56:03 PM UTC 24 |
| Peak memory | 227760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=343271280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_r and_reset.343271280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/10.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.3913404578 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 275116658 ps |
| CPU time | 3.14 seconds |
| Started | Aug 28 10:55:58 PM UTC 24 |
| Finished | Aug 28 10:56:03 PM UTC 24 |
| Peak memory | 229676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913404578 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.3913404578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/10.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.248953187 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 6420461676 ps |
| CPU time | 23.82 seconds |
| Started | Aug 28 10:55:57 PM UTC 24 |
| Finished | Aug 28 10:56:22 PM UTC 24 |
| Peak memory | 215364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248953187 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_bit_bash.248953187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/10.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2657011098 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 3647361560 ps |
| CPU time | 4.99 seconds |
| Started | Aug 28 10:55:56 PM UTC 24 |
| Finished | Aug 28 10:56:02 PM UTC 24 |
| Peak memory | 215516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657011098 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.2657011098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/10.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1048939385 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 114050554 ps |
| CPU time | 1.48 seconds |
| Started | Aug 28 10:55:55 PM UTC 24 |
| Finished | Aug 28 10:55:57 PM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048939385 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.1048939385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/10.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2224337411 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 386288493 ps |
| CPU time | 5.44 seconds |
| Started | Aug 28 10:55:58 PM UTC 24 |
| Finished | Aug 28 10:56:05 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224337411 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_csr_outstanding.2224337411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/10.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.1476122172 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 197606090 ps |
| CPU time | 6.85 seconds |
| Started | Aug 28 10:55:57 PM UTC 24 |
| Finished | Aug 28 10:56:05 PM UTC 24 |
| Peak memory | 225916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476122172 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.1476122172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/10.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.98118105 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 189329845 ps |
| CPU time | 2.92 seconds |
| Started | Aug 28 10:56:03 PM UTC 24 |
| Finished | Aug 28 10:56:07 PM UTC 24 |
| Peak memory | 229900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=98118105 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_ra nd_reset.98118105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/11.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_rw.3127222205 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 128123486 ps |
| CPU time | 3.51 seconds |
| Started | Aug 28 10:56:02 PM UTC 24 |
| Finished | Aug 28 10:56:07 PM UTC 24 |
| Peak memory | 231716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127222205 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.3127222205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/11.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2494541552 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 14527677658 ps |
| CPU time | 41.86 seconds |
| Started | Aug 28 10:56:01 PM UTC 24 |
| Finished | Aug 28 10:56:44 PM UTC 24 |
| Peak memory | 215292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494541552 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_bit_bash.2494541552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/11.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.405422869 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 4944425424 ps |
| CPU time | 21.1 seconds |
| Started | Aug 28 10:56:00 PM UTC 24 |
| Finished | Aug 28 10:56:22 PM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405422869 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.405422869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/11.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.790174333 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 627245284 ps |
| CPU time | 2.67 seconds |
| Started | Aug 28 10:56:00 PM UTC 24 |
| Finished | Aug 28 10:56:03 PM UTC 24 |
| Peak memory | 215148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790174333 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.790174333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/11.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1739880324 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 181669516 ps |
| CPU time | 5.11 seconds |
| Started | Aug 28 10:56:02 PM UTC 24 |
| Finished | Aug 28 10:56:08 PM UTC 24 |
| Peak memory | 215560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739880324 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_csr_outstanding.1739880324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/11.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_errors.2973406082 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 258266422 ps |
| CPU time | 5.76 seconds |
| Started | Aug 28 10:56:01 PM UTC 24 |
| Finished | Aug 28 10:56:08 PM UTC 24 |
| Peak memory | 225792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973406082 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.2973406082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/11.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.256610185 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 168732785 ps |
| CPU time | 2.53 seconds |
| Started | Aug 28 10:56:06 PM UTC 24 |
| Finished | Aug 28 10:56:09 PM UTC 24 |
| Peak memory | 225500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=256610185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_r and_reset.256610185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/12.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_rw.1606304605 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 57592241 ps |
| CPU time | 2.24 seconds |
| Started | Aug 28 10:56:04 PM UTC 24 |
| Finished | Aug 28 10:56:08 PM UTC 24 |
| Peak memory | 229752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606304605 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.1606304605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/12.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2073537334 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 3723426620 ps |
| CPU time | 5.72 seconds |
| Started | Aug 28 10:56:04 PM UTC 24 |
| Finished | Aug 28 10:56:11 PM UTC 24 |
| Peak memory | 215320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073537334 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_bit_bash.2073537334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/12.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1894848238 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 2005297759 ps |
| CPU time | 4.87 seconds |
| Started | Aug 28 10:56:03 PM UTC 24 |
| Finished | Aug 28 10:56:09 PM UTC 24 |
| Peak memory | 215424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894848238 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.1894848238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/12.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3539718977 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 317980917 ps |
| CPU time | 2.75 seconds |
| Started | Aug 28 10:56:03 PM UTC 24 |
| Finished | Aug 28 10:56:07 PM UTC 24 |
| Peak memory | 215140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539718977 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.3539718977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/12.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3739713158 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 813045825 ps |
| CPU time | 10.23 seconds |
| Started | Aug 28 10:56:06 PM UTC 24 |
| Finished | Aug 28 10:56:17 PM UTC 24 |
| Peak memory | 215568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739713158 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same_csr_outstanding.3739713158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/12.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_errors.389096299 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 472670928 ps |
| CPU time | 3.82 seconds |
| Started | Aug 28 10:56:04 PM UTC 24 |
| Finished | Aug 28 10:56:09 PM UTC 24 |
| Peak memory | 225732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389096299 -assert nopostproc +UVM_TESTNAME=rv_dm_base _test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.389096299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/12.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3512279382 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 1606140923 ps |
| CPU time | 21.3 seconds |
| Started | Aug 28 10:56:04 PM UTC 24 |
| Finished | Aug 28 10:56:27 PM UTC 24 |
| Peak memory | 227640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512279382 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.3512279382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/12.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2151360420 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 190811332 ps |
| CPU time | 2.93 seconds |
| Started | Aug 28 10:56:08 PM UTC 24 |
| Finished | Aug 28 10:56:12 PM UTC 24 |
| Peak memory | 231892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2151360420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_ rand_reset.2151360420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/13.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_rw.26811152 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 232291313 ps |
| CPU time | 2.12 seconds |
| Started | Aug 28 10:56:08 PM UTC 24 |
| Finished | Aug 28 10:56:11 PM UTC 24 |
| Peak memory | 225580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26811152 -assert nopostproc +UVM_TESTNAME=rv_dm_ba se_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv _dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.26811152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/13.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2367274988 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 26210766184 ps |
| CPU time | 52.11 seconds |
| Started | Aug 28 10:56:07 PM UTC 24 |
| Finished | Aug 28 10:57:00 PM UTC 24 |
| Peak memory | 215360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367274988 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_bit_bash.2367274988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/13.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2999933132 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 2612642258 ps |
| CPU time | 14.65 seconds |
| Started | Aug 28 10:56:07 PM UTC 24 |
| Finished | Aug 28 10:56:22 PM UTC 24 |
| Peak memory | 215360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999933132 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.2999933132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/13.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3744039273 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 360728059 ps |
| CPU time | 1.36 seconds |
| Started | Aug 28 10:56:06 PM UTC 24 |
| Finished | Aug 28 10:56:08 PM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744039273 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.3744039273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/13.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1853785445 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 460500034 ps |
| CPU time | 8.09 seconds |
| Started | Aug 28 10:56:08 PM UTC 24 |
| Finished | Aug 28 10:56:17 PM UTC 24 |
| Peak memory | 215440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853785445 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_csr_outstanding.1853785445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/13.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_errors.2086537441 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 156519041 ps |
| CPU time | 3.84 seconds |
| Started | Aug 28 10:56:08 PM UTC 24 |
| Finished | Aug 28 10:56:13 PM UTC 24 |
| Peak memory | 225848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086537441 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.2086537441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/13.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1020402908 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 1318502073 ps |
| CPU time | 15.37 seconds |
| Started | Aug 28 10:56:08 PM UTC 24 |
| Finished | Aug 28 10:56:24 PM UTC 24 |
| Peak memory | 232356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020402908 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.1020402908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/13.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1559577028 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 185969381 ps |
| CPU time | 5.24 seconds |
| Started | Aug 28 10:56:11 PM UTC 24 |
| Finished | Aug 28 10:56:17 PM UTC 24 |
| Peak memory | 231980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1559577028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_ rand_reset.1559577028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/14.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_rw.22945320 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 611495865 ps |
| CPU time | 2.1 seconds |
| Started | Aug 28 10:56:11 PM UTC 24 |
| Finished | Aug 28 10:56:14 PM UTC 24 |
| Peak memory | 225620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22945320 -assert nopostproc +UVM_TESTNAME=rv_dm_ba se_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv _dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.22945320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/14.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.2687802807 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 8189224836 ps |
| CPU time | 10.97 seconds |
| Started | Aug 28 10:56:09 PM UTC 24 |
| Finished | Aug 28 10:56:21 PM UTC 24 |
| Peak memory | 215356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687802807 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_bit_bash.2687802807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/14.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.192204331 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 5306488279 ps |
| CPU time | 19.45 seconds |
| Started | Aug 28 10:56:09 PM UTC 24 |
| Finished | Aug 28 10:56:30 PM UTC 24 |
| Peak memory | 215420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192204331 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.192204331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/14.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.348199967 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 531670576 ps |
| CPU time | 1.86 seconds |
| Started | Aug 28 10:56:08 PM UTC 24 |
| Finished | Aug 28 10:56:11 PM UTC 24 |
| Peak memory | 215084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348199967 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.348199967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/14.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1665566433 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 245192725 ps |
| CPU time | 5.85 seconds |
| Started | Aug 28 10:56:11 PM UTC 24 |
| Finished | Aug 28 10:56:18 PM UTC 24 |
| Peak memory | 215424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665566433 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same_csr_outstanding.1665566433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/14.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_errors.3859943816 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 431472674 ps |
| CPU time | 4.26 seconds |
| Started | Aug 28 10:56:09 PM UTC 24 |
| Finished | Aug 28 10:56:15 PM UTC 24 |
| Peak memory | 225788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859943816 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.3859943816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/14.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1364391523 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 3193284073 ps |
| CPU time | 15.33 seconds |
| Started | Aug 28 10:56:09 PM UTC 24 |
| Finished | Aug 28 10:56:26 PM UTC 24 |
| Peak memory | 225800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364391523 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.1364391523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/14.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1966881120 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 73689311 ps |
| CPU time | 2.94 seconds |
| Started | Aug 28 10:56:14 PM UTC 24 |
| Finished | Aug 28 10:56:18 PM UTC 24 |
| Peak memory | 227888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1966881120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_ rand_reset.1966881120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/15.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_rw.552623926 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 210694853 ps |
| CPU time | 2 seconds |
| Started | Aug 28 10:56:12 PM UTC 24 |
| Finished | Aug 28 10:56:15 PM UTC 24 |
| Peak memory | 225228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552623926 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.552623926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/15.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2310728075 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 121425630 ps |
| CPU time | 1.34 seconds |
| Started | Aug 28 10:56:12 PM UTC 24 |
| Finished | Aug 28 10:56:14 PM UTC 24 |
| Peak memory | 215208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310728075 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_bit_bash.2310728075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/15.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2977502483 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 3572841593 ps |
| CPU time | 4.28 seconds |
| Started | Aug 28 10:56:12 PM UTC 24 |
| Finished | Aug 28 10:56:17 PM UTC 24 |
| Peak memory | 215380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977502483 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.2977502483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/15.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2222157914 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 199225891 ps |
| CPU time | 2.02 seconds |
| Started | Aug 28 10:56:11 PM UTC 24 |
| Finished | Aug 28 10:56:14 PM UTC 24 |
| Peak memory | 215208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222157914 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.2222157914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/15.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.573951578 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 830575395 ps |
| CPU time | 8.68 seconds |
| Started | Aug 28 10:56:13 PM UTC 24 |
| Finished | Aug 28 10:56:23 PM UTC 24 |
| Peak memory | 215428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573951578 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_csr_outstanding.573951578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/15.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_errors.3707852390 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 134147811 ps |
| CPU time | 4.76 seconds |
| Started | Aug 28 10:56:12 PM UTC 24 |
| Finished | Aug 28 10:56:18 PM UTC 24 |
| Peak memory | 225800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707852390 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.3707852390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/15.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1483794298 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 125714177 ps |
| CPU time | 4.84 seconds |
| Started | Aug 28 10:56:17 PM UTC 24 |
| Finished | Aug 28 10:56:23 PM UTC 24 |
| Peak memory | 232372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1483794298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_ rand_reset.1483794298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/16.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_rw.4253288628 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 166841011 ps |
| CPU time | 2.38 seconds |
| Started | Aug 28 10:56:16 PM UTC 24 |
| Finished | Aug 28 10:56:19 PM UTC 24 |
| Peak memory | 225596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253288628 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.4253288628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/16.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1669279065 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 17362467292 ps |
| CPU time | 9.53 seconds |
| Started | Aug 28 10:56:14 PM UTC 24 |
| Finished | Aug 28 10:56:25 PM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669279065 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_bit_bash.1669279065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/16.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.498786494 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 1090972147 ps |
| CPU time | 4.55 seconds |
| Started | Aug 28 10:56:14 PM UTC 24 |
| Finished | Aug 28 10:56:20 PM UTC 24 |
| Peak memory | 215388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498786494 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.498786494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/16.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2288127550 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 128810130 ps |
| CPU time | 1.43 seconds |
| Started | Aug 28 10:56:14 PM UTC 24 |
| Finished | Aug 28 10:56:17 PM UTC 24 |
| Peak memory | 215140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288127550 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.2288127550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/16.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2390522387 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 841319810 ps |
| CPU time | 4.59 seconds |
| Started | Aug 28 10:56:16 PM UTC 24 |
| Finished | Aug 28 10:56:21 PM UTC 24 |
| Peak memory | 215452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390522387 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_csr_outstanding.2390522387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/16.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_errors.1955433404 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 1228227898 ps |
| CPU time | 2.78 seconds |
| Started | Aug 28 10:56:14 PM UTC 24 |
| Finished | Aug 28 10:56:18 PM UTC 24 |
| Peak memory | 225860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955433404 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.1955433404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/16.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2634815952 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 2634377673 ps |
| CPU time | 11.36 seconds |
| Started | Aug 28 10:56:16 PM UTC 24 |
| Finished | Aug 28 10:56:28 PM UTC 24 |
| Peak memory | 232492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634815952 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.2634815952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/16.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2498075628 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 61445357 ps |
| CPU time | 2.84 seconds |
| Started | Aug 28 10:56:19 PM UTC 24 |
| Finished | Aug 28 10:56:23 PM UTC 24 |
| Peak memory | 225872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2498075628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_ rand_reset.2498075628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/17.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_rw.2589445742 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 177016529 ps |
| CPU time | 2.34 seconds |
| Started | Aug 28 10:56:18 PM UTC 24 |
| Finished | Aug 28 10:56:21 PM UTC 24 |
| Peak memory | 225656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589445742 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.2589445742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/17.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.2414704865 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 54887145629 ps |
| CPU time | 146.13 seconds |
| Started | Aug 28 10:56:18 PM UTC 24 |
| Finished | Aug 28 10:58:47 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414704865 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_bit_bash.2414704865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/17.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2561504665 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 4417667991 ps |
| CPU time | 2.77 seconds |
| Started | Aug 28 10:56:18 PM UTC 24 |
| Finished | Aug 28 10:56:22 PM UTC 24 |
| Peak memory | 215364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561504665 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.2561504665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/17.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2003595262 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 173659937 ps |
| CPU time | 1.16 seconds |
| Started | Aug 28 10:56:17 PM UTC 24 |
| Finished | Aug 28 10:56:19 PM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003595262 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.2003595262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/17.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1808351369 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 170926014 ps |
| CPU time | 8.3 seconds |
| Started | Aug 28 10:56:18 PM UTC 24 |
| Finished | Aug 28 10:56:28 PM UTC 24 |
| Peak memory | 215492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808351369 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same_csr_outstanding.1808351369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/17.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_errors.1884948552 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 226741505 ps |
| CPU time | 4.48 seconds |
| Started | Aug 28 10:56:18 PM UTC 24 |
| Finished | Aug 28 10:56:23 PM UTC 24 |
| Peak memory | 225856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884948552 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.1884948552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/17.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2908439393 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 1372533141 ps |
| CPU time | 18.45 seconds |
| Started | Aug 28 10:56:18 PM UTC 24 |
| Finished | Aug 28 10:56:38 PM UTC 24 |
| Peak memory | 225660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908439393 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.2908439393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/17.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2937571499 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 168777381 ps |
| CPU time | 3.61 seconds |
| Started | Aug 28 10:56:21 PM UTC 24 |
| Finished | Aug 28 10:56:25 PM UTC 24 |
| Peak memory | 231892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2937571499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_ rand_reset.2937571499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/18.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_rw.3982637990 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 273961114 ps |
| CPU time | 2.41 seconds |
| Started | Aug 28 10:56:20 PM UTC 24 |
| Finished | Aug 28 10:56:23 PM UTC 24 |
| Peak memory | 225596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982637990 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.3982637990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/18.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.2072812448 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 63070692193 ps |
| CPU time | 71.23 seconds |
| Started | Aug 28 10:56:19 PM UTC 24 |
| Finished | Aug 28 10:57:32 PM UTC 24 |
| Peak memory | 215420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072812448 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_bit_bash.2072812448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/18.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2145087311 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 5077261529 ps |
| CPU time | 24.28 seconds |
| Started | Aug 28 10:56:19 PM UTC 24 |
| Finished | Aug 28 10:56:45 PM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145087311 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.2145087311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/18.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.237433953 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 233253252 ps |
| CPU time | 1.41 seconds |
| Started | Aug 28 10:56:19 PM UTC 24 |
| Finished | Aug 28 10:56:22 PM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237433953 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.237433953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/18.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1546100311 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 98180513 ps |
| CPU time | 4.75 seconds |
| Started | Aug 28 10:56:20 PM UTC 24 |
| Finished | Aug 28 10:56:25 PM UTC 24 |
| Peak memory | 215496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546100311 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same_csr_outstanding.1546100311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/18.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_errors.1074253191 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 298796860 ps |
| CPU time | 3.31 seconds |
| Started | Aug 28 10:56:20 PM UTC 24 |
| Finished | Aug 28 10:56:24 PM UTC 24 |
| Peak memory | 227628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074253191 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.1074253191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/18.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3176691521 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 1238829776 ps |
| CPU time | 11.25 seconds |
| Started | Aug 28 10:56:20 PM UTC 24 |
| Finished | Aug 28 10:56:32 PM UTC 24 |
| Peak memory | 232408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176691521 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3176691521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/18.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2586987976 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 171686723 ps |
| CPU time | 4.57 seconds |
| Started | Aug 28 10:56:23 PM UTC 24 |
| Finished | Aug 28 10:56:29 PM UTC 24 |
| Peak memory | 229876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2586987976 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_ rand_reset.2586987976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/19.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_rw.1222725760 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 775654880 ps |
| CPU time | 2.24 seconds |
| Started | Aug 28 10:56:23 PM UTC 24 |
| Finished | Aug 28 10:56:26 PM UTC 24 |
| Peak memory | 229692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222725760 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.1222725760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/19.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.2036625497 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 8125508742 ps |
| CPU time | 25.12 seconds |
| Started | Aug 28 10:56:22 PM UTC 24 |
| Finished | Aug 28 10:56:48 PM UTC 24 |
| Peak memory | 215488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036625497 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_bit_bash.2036625497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/19.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2037312250 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 1703950365 ps |
| CPU time | 7.21 seconds |
| Started | Aug 28 10:56:22 PM UTC 24 |
| Finished | Aug 28 10:56:30 PM UTC 24 |
| Peak memory | 215328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037312250 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.2037312250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/19.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.118444856 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 198288645 ps |
| CPU time | 1.15 seconds |
| Started | Aug 28 10:56:22 PM UTC 24 |
| Finished | Aug 28 10:56:24 PM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118444856 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.118444856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/19.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3577397124 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 411024254 ps |
| CPU time | 5.33 seconds |
| Started | Aug 28 10:56:23 PM UTC 24 |
| Finished | Aug 28 10:56:30 PM UTC 24 |
| Peak memory | 215492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577397124 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_csr_outstanding.3577397124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/19.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_errors.495920237 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 442770830 ps |
| CPU time | 7.58 seconds |
| Started | Aug 28 10:56:23 PM UTC 24 |
| Finished | Aug 28 10:56:32 PM UTC 24 |
| Peak memory | 225752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495920237 -assert nopostproc +UVM_TESTNAME=rv_dm_base _test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.495920237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/19.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2677379959 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 4254991550 ps |
| CPU time | 42.86 seconds |
| Started | Aug 28 10:56:23 PM UTC 24 |
| Finished | Aug 28 10:57:07 PM UTC 24 |
| Peak memory | 231948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677379959 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.2677379959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/19.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3805943428 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 2539228011 ps |
| CPU time | 32.79 seconds |
| Started | Aug 28 10:55:17 PM UTC 24 |
| Finished | Aug 28 10:55:54 PM UTC 24 |
| Peak memory | 225692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805943428 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_aliasing.3805943428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/2.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2989162674 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 23468653901 ps |
| CPU time | 74.38 seconds |
| Started | Aug 28 10:55:24 PM UTC 24 |
| Finished | Aug 28 10:56:41 PM UTC 24 |
| Peak memory | 215464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989162674 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.2989162674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/2.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1757863732 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 134879917 ps |
| CPU time | 3.06 seconds |
| Started | Aug 28 10:55:23 PM UTC 24 |
| Finished | Aug 28 10:55:28 PM UTC 24 |
| Peak memory | 225612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757863732 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.1757863732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/2.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3589573114 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 117756461 ps |
| CPU time | 3.23 seconds |
| Started | Aug 28 10:55:24 PM UTC 24 |
| Finished | Aug 28 10:55:29 PM UTC 24 |
| Peak memory | 227744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3589573114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_r and_reset.3589573114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/2.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_rw.957409903 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 134261533 ps |
| CPU time | 2.46 seconds |
| Started | Aug 28 10:55:23 PM UTC 24 |
| Finished | Aug 28 10:55:28 PM UTC 24 |
| Peak memory | 225724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957409903 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.957409903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/2.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2348480654 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 14001753869 ps |
| CPU time | 41.23 seconds |
| Started | Aug 28 10:55:21 PM UTC 24 |
| Finished | Aug 28 10:56:07 PM UTC 24 |
| Peak memory | 215420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348480654 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_aliasing.2348480654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1214080308 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 15086864170 ps |
| CPU time | 27.46 seconds |
| Started | Aug 28 10:55:21 PM UTC 24 |
| Finished | Aug 28 10:55:53 PM UTC 24 |
| Peak memory | 215292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214080308 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_bit_bash.1214080308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1462161787 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 2805304687 ps |
| CPU time | 4.99 seconds |
| Started | Aug 28 10:55:19 PM UTC 24 |
| Finished | Aug 28 10:55:26 PM UTC 24 |
| Peak memory | 215520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462161787 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_hw_reset.1462161787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1368784997 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 2166601489 ps |
| CPU time | 7.8 seconds |
| Started | Aug 28 10:55:21 PM UTC 24 |
| Finished | Aug 28 10:55:29 PM UTC 24 |
| Peak memory | 215424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368784997 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1368784997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3782028471 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 1127565884 ps |
| CPU time | 5.14 seconds |
| Started | Aug 28 10:55:18 PM UTC 24 |
| Finished | Aug 28 10:55:26 PM UTC 24 |
| Peak memory | 215072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782028471 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_aliasing.3782028471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.4092811533 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 2957754675 ps |
| CPU time | 5.63 seconds |
| Started | Aug 28 10:55:18 PM UTC 24 |
| Finished | Aug 28 10:55:26 PM UTC 24 |
| Peak memory | 215364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092811533 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_bit_bash.4092811533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3551474353 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 595632255 ps |
| CPU time | 2.67 seconds |
| Started | Aug 28 10:55:17 PM UTC 24 |
| Finished | Aug 28 10:55:24 PM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551474353 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_hw_reset.3551474353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.967604881 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 661200755 ps |
| CPU time | 2.22 seconds |
| Started | Aug 28 10:55:18 PM UTC 24 |
| Finished | Aug 28 10:55:23 PM UTC 24 |
| Peak memory | 215076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967604881 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.967604881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_partial_access.645157161 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 48876148 ps |
| CPU time | 0.88 seconds |
| Started | Aug 28 10:55:23 PM UTC 24 |
| Finished | Aug 28 10:55:26 PM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645157161 -assert nopostproc +UVM_ TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_partial_access.645157161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/2.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_walk.1000159552 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 137195403 ps |
| CPU time | 1.19 seconds |
| Started | Aug 28 10:55:23 PM UTC 24 |
| Finished | Aug 28 10:55:26 PM UTC 24 |
| Peak memory | 215140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000159552 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.1000159552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/2.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.4067373471 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 235010462 ps |
| CPU time | 4.72 seconds |
| Started | Aug 28 10:55:24 PM UTC 24 |
| Finished | Aug 28 10:55:30 PM UTC 24 |
| Peak memory | 215304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067373471 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_csr_outstanding.4067373471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/2.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_errors.1520503341 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 247417843 ps |
| CPU time | 5.55 seconds |
| Started | Aug 28 10:55:22 PM UTC 24 |
| Finished | Aug 28 10:55:32 PM UTC 24 |
| Peak memory | 225724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520503341 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.1520503341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/2.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3334459534 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 3578623726 ps |
| CPU time | 11.16 seconds |
| Started | Aug 28 10:55:22 PM UTC 24 |
| Finished | Aug 28 10:55:37 PM UTC 24 |
| Peak memory | 225864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334459534 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.3334459534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/2.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_aliasing.992061571 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 4521760524 ps |
| CPU time | 94.01 seconds |
| Started | Aug 28 10:55:24 PM UTC 24 |
| Finished | Aug 28 10:57:01 PM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992061571 -asse rt nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_aliasing.992061571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/3.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.707587870 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 15207644854 ps |
| CPU time | 41.52 seconds |
| Started | Aug 28 10:55:30 PM UTC 24 |
| Finished | Aug 28 10:56:14 PM UTC 24 |
| Peak memory | 225704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707587870 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.707587870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/3.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3188281372 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 48358348 ps |
| CPU time | 3.79 seconds |
| Started | Aug 28 10:55:32 PM UTC 24 |
| Finished | Aug 28 10:55:36 PM UTC 24 |
| Peak memory | 229896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3188281372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_r and_reset.3188281372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/3.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_rw.2078826723 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 198285503 ps |
| CPU time | 2.33 seconds |
| Started | Aug 28 10:55:30 PM UTC 24 |
| Finished | Aug 28 10:55:34 PM UTC 24 |
| Peak memory | 229752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078826723 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.2078826723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/3.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.237980886 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 31133850029 ps |
| CPU time | 28.99 seconds |
| Started | Aug 28 10:55:27 PM UTC 24 |
| Finished | Aug 28 10:56:00 PM UTC 24 |
| Peak memory | 215352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237980886 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_aliasing.237980886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3325966055 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 12032507170 ps |
| CPU time | 45.54 seconds |
| Started | Aug 28 10:55:27 PM UTC 24 |
| Finished | Aug 28 10:56:17 PM UTC 24 |
| Peak memory | 215292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325966055 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_bit_bash.3325966055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.911159460 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 2078797576 ps |
| CPU time | 4.6 seconds |
| Started | Aug 28 10:55:26 PM UTC 24 |
| Finished | Aug 28 10:55:34 PM UTC 24 |
| Peak memory | 215320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911159460 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_hw_reset.911159460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.4014642260 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 11165975941 ps |
| CPU time | 16.92 seconds |
| Started | Aug 28 10:55:27 PM UTC 24 |
| Finished | Aug 28 10:55:48 PM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014642260 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.4014642260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.80757133 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 1092968437 ps |
| CPU time | 7.48 seconds |
| Started | Aug 28 10:55:26 PM UTC 24 |
| Finished | Aug 28 10:55:37 PM UTC 24 |
| Peak memory | 215148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80757133 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_aliasing.80757133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1711496879 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 18792713864 ps |
| CPU time | 33.4 seconds |
| Started | Aug 28 10:55:26 PM UTC 24 |
| Finished | Aug 28 10:56:03 PM UTC 24 |
| Peak memory | 215364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711496879 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_bit_bash.1711496879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1053030475 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 1229307668 ps |
| CPU time | 2.4 seconds |
| Started | Aug 28 10:55:24 PM UTC 24 |
| Finished | Aug 28 10:55:28 PM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053030475 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_hw_reset.1053030475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.185281482 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 329319014 ps |
| CPU time | 1.47 seconds |
| Started | Aug 28 10:55:26 PM UTC 24 |
| Finished | Aug 28 10:55:31 PM UTC 24 |
| Peak memory | 215084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185281482 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.185281482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2773586455 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 59831107 ps |
| CPU time | 1.17 seconds |
| Started | Aug 28 10:55:29 PM UTC 24 |
| Finished | Aug 28 10:55:31 PM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773586455 -assert nopostproc +UVM _TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_partial_access.2773586455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/3.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_walk.1481111935 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 43649102 ps |
| CPU time | 1.23 seconds |
| Started | Aug 28 10:55:29 PM UTC 24 |
| Finished | Aug 28 10:55:32 PM UTC 24 |
| Peak memory | 215140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481111935 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.1481111935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/3.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.451854622 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 848960289 ps |
| CPU time | 11.51 seconds |
| Started | Aug 28 10:55:32 PM UTC 24 |
| Finished | Aug 28 10:55:44 PM UTC 24 |
| Peak memory | 215432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451854622 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_csr_outstanding.451854622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/3.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.2566218797 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 5518505614 ps |
| CPU time | 41.79 seconds |
| Started | Aug 28 10:55:27 PM UTC 24 |
| Finished | Aug 28 10:56:13 PM UTC 24 |
| Peak memory | 232332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2566218797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_re set.2566218797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/3.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_errors.1642760242 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 194737475 ps |
| CPU time | 4.73 seconds |
| Started | Aug 28 10:55:27 PM UTC 24 |
| Finished | Aug 28 10:55:36 PM UTC 24 |
| Peak memory | 225856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642760242 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.1642760242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/3.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3929879225 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 3520923006 ps |
| CPU time | 11.05 seconds |
| Started | Aug 28 10:55:27 PM UTC 24 |
| Finished | Aug 28 10:55:42 PM UTC 24 |
| Peak memory | 225720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929879225 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.3929879225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/3.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_aliasing.472480613 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 8827710903 ps |
| CPU time | 78.47 seconds |
| Started | Aug 28 10:55:32 PM UTC 24 |
| Finished | Aug 28 10:56:52 PM UTC 24 |
| Peak memory | 215616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472480613 -asse rt nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_aliasing.472480613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/4.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1186062962 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 3020651989 ps |
| CPU time | 60.34 seconds |
| Started | Aug 28 10:55:38 PM UTC 24 |
| Finished | Aug 28 10:56:40 PM UTC 24 |
| Peak memory | 215408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186062962 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.1186062962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/4.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2462073570 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 365356363 ps |
| CPU time | 3.93 seconds |
| Started | Aug 28 10:55:37 PM UTC 24 |
| Finished | Aug 28 10:55:42 PM UTC 24 |
| Peak memory | 225700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462073570 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.2462073570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/4.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.915092209 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 56718141 ps |
| CPU time | 3.06 seconds |
| Started | Aug 28 10:55:38 PM UTC 24 |
| Finished | Aug 28 10:55:42 PM UTC 24 |
| Peak memory | 225816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=915092209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_ra nd_reset.915092209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/4.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_rw.179163713 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 181952742 ps |
| CPU time | 3.07 seconds |
| Started | Aug 28 10:55:38 PM UTC 24 |
| Finished | Aug 28 10:55:42 PM UTC 24 |
| Peak memory | 225620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179163713 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.179163713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/4.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.4038451257 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 40855437512 ps |
| CPU time | 43.31 seconds |
| Started | Aug 28 10:55:34 PM UTC 24 |
| Finished | Aug 28 10:56:19 PM UTC 24 |
| Peak memory | 215484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038451257 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_aliasing.4038451257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.314205252 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 23201455668 ps |
| CPU time | 49.78 seconds |
| Started | Aug 28 10:55:34 PM UTC 24 |
| Finished | Aug 28 10:56:25 PM UTC 24 |
| Peak memory | 215364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314205252 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_bit_bash.314205252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2936433663 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 18117916556 ps |
| CPU time | 24.17 seconds |
| Started | Aug 28 10:55:33 PM UTC 24 |
| Finished | Aug 28 10:55:58 PM UTC 24 |
| Peak memory | 215428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936433663 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_hw_reset.2936433663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3170785978 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 932870398 ps |
| CPU time | 3.07 seconds |
| Started | Aug 28 10:55:33 PM UTC 24 |
| Finished | Aug 28 10:55:37 PM UTC 24 |
| Peak memory | 215260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170785978 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.3170785978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.4109943585 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 493771832 ps |
| CPU time | 1.71 seconds |
| Started | Aug 28 10:55:33 PM UTC 24 |
| Finished | Aug 28 10:55:36 PM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109943585 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_aliasing.4109943585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.231982988 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 7854596706 ps |
| CPU time | 11.11 seconds |
| Started | Aug 28 10:55:33 PM UTC 24 |
| Finished | Aug 28 10:55:45 PM UTC 24 |
| Peak memory | 215420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231982988 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_bit_bash.231982988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.4134647662 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 242943465 ps |
| CPU time | 1.3 seconds |
| Started | Aug 28 10:55:33 PM UTC 24 |
| Finished | Aug 28 10:55:35 PM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134647662 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_hw_reset.4134647662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3797177564 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 222303448 ps |
| CPU time | 1.31 seconds |
| Started | Aug 28 10:55:33 PM UTC 24 |
| Finished | Aug 28 10:55:35 PM UTC 24 |
| Peak memory | 215200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797177564 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.3797177564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2226604528 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 43142732 ps |
| CPU time | 1.15 seconds |
| Started | Aug 28 10:55:37 PM UTC 24 |
| Finished | Aug 28 10:55:39 PM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226604528 -assert nopostproc +UVM _TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_partial_access.2226604528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/4.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_walk.1363546599 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 35822014 ps |
| CPU time | 1.09 seconds |
| Started | Aug 28 10:55:36 PM UTC 24 |
| Finished | Aug 28 10:55:39 PM UTC 24 |
| Peak memory | 215140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363546599 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.1363546599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/4.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.4127794900 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 286398136 ps |
| CPU time | 7.51 seconds |
| Started | Aug 28 10:55:38 PM UTC 24 |
| Finished | Aug 28 10:55:46 PM UTC 24 |
| Peak memory | 215496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127794900 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_csr_outstanding.4127794900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/4.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_errors.2278979107 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 596107015 ps |
| CPU time | 6.25 seconds |
| Started | Aug 28 10:55:35 PM UTC 24 |
| Finished | Aug 28 10:55:43 PM UTC 24 |
| Peak memory | 225924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278979107 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2278979107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/4.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1672908328 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 2852623496 ps |
| CPU time | 13.28 seconds |
| Started | Aug 28 10:55:36 PM UTC 24 |
| Finished | Aug 28 10:55:51 PM UTC 24 |
| Peak memory | 225664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672908328 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.1672908328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/4.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1222039197 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 127271081 ps |
| CPU time | 3 seconds |
| Started | Aug 28 10:55:43 PM UTC 24 |
| Finished | Aug 28 10:55:47 PM UTC 24 |
| Peak memory | 227796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1222039197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_r and_reset.1222039197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/5.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_rw.158424833 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 163467692 ps |
| CPU time | 1.77 seconds |
| Started | Aug 28 10:55:41 PM UTC 24 |
| Finished | Aug 28 10:55:44 PM UTC 24 |
| Peak memory | 229160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158424833 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.158424833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/5.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.4278957452 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 32851122871 ps |
| CPU time | 136.27 seconds |
| Started | Aug 28 10:55:40 PM UTC 24 |
| Finished | Aug 28 10:57:59 PM UTC 24 |
| Peak memory | 215396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278957452 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_bit_bash.4278957452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/5.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3672592004 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 5075430675 ps |
| CPU time | 4.65 seconds |
| Started | Aug 28 10:55:40 PM UTC 24 |
| Finished | Aug 28 10:55:46 PM UTC 24 |
| Peak memory | 215452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672592004 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.3672592004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/5.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.213021187 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 693689915 ps |
| CPU time | 4.36 seconds |
| Started | Aug 28 10:55:39 PM UTC 24 |
| Finished | Aug 28 10:55:45 PM UTC 24 |
| Peak memory | 215148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213021187 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.213021187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/5.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2568585073 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 1189260950 ps |
| CPU time | 6.05 seconds |
| Started | Aug 28 10:55:42 PM UTC 24 |
| Finished | Aug 28 10:55:50 PM UTC 24 |
| Peak memory | 215492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568585073 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_csr_outstanding.2568585073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/5.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2276334865 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 63056838332 ps |
| CPU time | 94.5 seconds |
| Started | Aug 28 10:55:40 PM UTC 24 |
| Finished | Aug 28 10:57:17 PM UTC 24 |
| Peak memory | 225860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2276334865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_re set.2276334865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/5.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_errors.2988547302 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 232862435 ps |
| CPU time | 4.37 seconds |
| Started | Aug 28 10:55:41 PM UTC 24 |
| Finished | Aug 28 10:55:47 PM UTC 24 |
| Peak memory | 225820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988547302 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.2988547302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/5.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2164577608 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 221955502 ps |
| CPU time | 2.68 seconds |
| Started | Aug 28 10:55:46 PM UTC 24 |
| Finished | Aug 28 10:55:50 PM UTC 24 |
| Peak memory | 227288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2164577608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_r and_reset.2164577608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/6.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_rw.141505920 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 88439544 ps |
| CPU time | 2.57 seconds |
| Started | Aug 28 10:55:45 PM UTC 24 |
| Finished | Aug 28 10:55:49 PM UTC 24 |
| Peak memory | 225640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141505920 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.141505920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/6.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.426482049 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 10596281350 ps |
| CPU time | 17.29 seconds |
| Started | Aug 28 10:55:44 PM UTC 24 |
| Finished | Aug 28 10:56:03 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426482049 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_bit_bash.426482049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/6.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1227855777 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 2230181736 ps |
| CPU time | 9.63 seconds |
| Started | Aug 28 10:55:44 PM UTC 24 |
| Finished | Aug 28 10:55:55 PM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227855777 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.1227855777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/6.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1808467744 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 394016832 ps |
| CPU time | 2.23 seconds |
| Started | Aug 28 10:55:43 PM UTC 24 |
| Finished | Aug 28 10:55:46 PM UTC 24 |
| Peak memory | 215068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808467744 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.1808467744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/6.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1091179228 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 253156386 ps |
| CPU time | 4.28 seconds |
| Started | Aug 28 10:55:45 PM UTC 24 |
| Finished | Aug 28 10:55:51 PM UTC 24 |
| Peak memory | 215500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091179228 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_csr_outstanding.1091179228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/6.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_errors.4210450195 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 146955302 ps |
| CPU time | 6.43 seconds |
| Started | Aug 28 10:55:44 PM UTC 24 |
| Finished | Aug 28 10:55:51 PM UTC 24 |
| Peak memory | 225708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210450195 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.4210450195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/6.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_intg_err.247249851 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 1397921528 ps |
| CPU time | 18.34 seconds |
| Started | Aug 28 10:55:45 PM UTC 24 |
| Finished | Aug 28 10:56:05 PM UTC 24 |
| Peak memory | 225672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247249851 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.247249851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/6.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.246005078 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 103676049 ps |
| CPU time | 2.82 seconds |
| Started | Aug 28 10:55:49 PM UTC 24 |
| Finished | Aug 28 10:55:52 PM UTC 24 |
| Peak memory | 225964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=246005078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_ra nd_reset.246005078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/7.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_rw.681514136 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 217786569 ps |
| CPU time | 3.4 seconds |
| Started | Aug 28 10:55:49 PM UTC 24 |
| Finished | Aug 28 10:55:53 PM UTC 24 |
| Peak memory | 225580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681514136 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.681514136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/7.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2354043675 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 4083271482 ps |
| CPU time | 5.98 seconds |
| Started | Aug 28 10:55:47 PM UTC 24 |
| Finished | Aug 28 10:55:54 PM UTC 24 |
| Peak memory | 215364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354043675 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_bit_bash.2354043675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/7.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.4033083284 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 15346615737 ps |
| CPU time | 63.43 seconds |
| Started | Aug 28 10:55:46 PM UTC 24 |
| Finished | Aug 28 10:56:51 PM UTC 24 |
| Peak memory | 215484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033083284 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.4033083284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/7.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1260080977 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 224285753 ps |
| CPU time | 1.97 seconds |
| Started | Aug 28 10:55:46 PM UTC 24 |
| Finished | Aug 28 10:55:49 PM UTC 24 |
| Peak memory | 214812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260080977 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1260080977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/7.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1539141963 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 2265512936 ps |
| CPU time | 11.08 seconds |
| Started | Aug 28 10:55:49 PM UTC 24 |
| Finished | Aug 28 10:56:01 PM UTC 24 |
| Peak memory | 215304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539141963 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_csr_outstanding.1539141963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/7.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1909839395 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 8226592483 ps |
| CPU time | 49.74 seconds |
| Started | Aug 28 10:55:47 PM UTC 24 |
| Finished | Aug 28 10:56:39 PM UTC 24 |
| Peak memory | 229896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1909839395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_re set.1909839395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/7.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_errors.1021160339 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 90367158 ps |
| CPU time | 3.23 seconds |
| Started | Aug 28 10:55:47 PM UTC 24 |
| Finished | Aug 28 10:55:52 PM UTC 24 |
| Peak memory | 225884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021160339 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.1021160339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/7.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_intg_err.404219197 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 1515724367 ps |
| CPU time | 16.58 seconds |
| Started | Aug 28 10:55:48 PM UTC 24 |
| Finished | Aug 28 10:56:06 PM UTC 24 |
| Peak memory | 227652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404219197 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.404219197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/7.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3088064940 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 262809012 ps |
| CPU time | 4.71 seconds |
| Started | Aug 28 10:55:52 PM UTC 24 |
| Finished | Aug 28 10:55:58 PM UTC 24 |
| Peak memory | 229712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3088064940 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_r and_reset.3088064940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/8.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_rw.2794633622 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 351233052 ps |
| CPU time | 3.54 seconds |
| Started | Aug 28 10:55:51 PM UTC 24 |
| Finished | Aug 28 10:55:56 PM UTC 24 |
| Peak memory | 225720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794633622 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.2794633622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/8.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.933743859 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 25114670094 ps |
| CPU time | 101.56 seconds |
| Started | Aug 28 10:55:50 PM UTC 24 |
| Finished | Aug 28 10:57:33 PM UTC 24 |
| Peak memory | 215556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933743859 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_bit_bash.933743859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/8.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1302764934 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 5610994674 ps |
| CPU time | 2.9 seconds |
| Started | Aug 28 10:55:49 PM UTC 24 |
| Finished | Aug 28 10:55:53 PM UTC 24 |
| Peak memory | 215356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302764934 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.1302764934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/8.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3844651375 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 307064401 ps |
| CPU time | 1.45 seconds |
| Started | Aug 28 10:55:49 PM UTC 24 |
| Finished | Aug 28 10:55:51 PM UTC 24 |
| Peak memory | 215200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844651375 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.3844651375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/8.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.494871460 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 1276973763 ps |
| CPU time | 9.24 seconds |
| Started | Aug 28 10:55:52 PM UTC 24 |
| Finished | Aug 28 10:56:03 PM UTC 24 |
| Peak memory | 215496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494871460 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_csr_outstanding.494871460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/8.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.4293378380 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 2585587111 ps |
| CPU time | 24.46 seconds |
| Started | Aug 28 10:55:50 PM UTC 24 |
| Finished | Aug 28 10:56:16 PM UTC 24 |
| Peak memory | 227912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=4293378380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_re set.4293378380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/8.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_errors.3510097933 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 193714476 ps |
| CPU time | 4.68 seconds |
| Started | Aug 28 10:55:51 PM UTC 24 |
| Finished | Aug 28 10:55:57 PM UTC 24 |
| Peak memory | 225764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510097933 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.3510097933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/8.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_intg_err.605196085 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 2996077809 ps |
| CPU time | 17.59 seconds |
| Started | Aug 28 10:55:51 PM UTC 24 |
| Finished | Aug 28 10:56:10 PM UTC 24 |
| Peak memory | 225832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605196085 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.605196085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/8.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1539028184 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 182049156 ps |
| CPU time | 4.12 seconds |
| Started | Aug 28 10:55:55 PM UTC 24 |
| Finished | Aug 28 10:56:00 PM UTC 24 |
| Peak memory | 232176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1539028184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_r and_reset.1539028184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/9.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_rw.1446362908 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 47880089 ps |
| CPU time | 2.19 seconds |
| Started | Aug 28 10:55:54 PM UTC 24 |
| Finished | Aug 28 10:55:57 PM UTC 24 |
| Peak memory | 229752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446362908 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.1446362908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/9.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2608772081 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 2361787102 ps |
| CPU time | 13.08 seconds |
| Started | Aug 28 10:55:52 PM UTC 24 |
| Finished | Aug 28 10:56:07 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608772081 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_bit_bash.2608772081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/9.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2098489141 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 1605159281 ps |
| CPU time | 6.19 seconds |
| Started | Aug 28 10:55:52 PM UTC 24 |
| Finished | Aug 28 10:56:00 PM UTC 24 |
| Peak memory | 215228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098489141 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.2098489141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/9.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1756139027 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 341378842 ps |
| CPU time | 2.44 seconds |
| Started | Aug 28 10:55:52 PM UTC 24 |
| Finished | Aug 28 10:55:56 PM UTC 24 |
| Peak memory | 214960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756139027 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.1756139027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/9.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1976171243 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 572244679 ps |
| CPU time | 11.71 seconds |
| Started | Aug 28 10:55:54 PM UTC 24 |
| Finished | Aug 28 10:56:07 PM UTC 24 |
| Peak memory | 215556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976171243 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_csr_outstanding.1976171243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/9.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_errors.1730751394 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 527857286 ps |
| CPU time | 5.95 seconds |
| Started | Aug 28 10:55:54 PM UTC 24 |
| Finished | Aug 28 10:56:01 PM UTC 24 |
| Peak memory | 225796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730751394 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.1730751394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/9.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2266603936 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 4433354006 ps |
| CPU time | 22.46 seconds |
| Started | Aug 28 10:55:54 PM UTC 24 |
| Finished | Aug 28 10:56:18 PM UTC 24 |
| Peak memory | 225640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266603936 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.2266603936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/9.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.4259569604 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 1906494420 ps |
| CPU time | 7.72 seconds |
| Started | Aug 28 10:20:02 PM UTC 24 |
| Finished | Aug 28 10:20:11 PM UTC 24 |
| Peak memory | 216188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259569604 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.4259569604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.2028381578 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 4804223424 ps |
| CPU time | 15.08 seconds |
| Started | Aug 28 10:20:02 PM UTC 24 |
| Finished | Aug 28 10:20:19 PM UTC 24 |
| Peak memory | 226632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028381578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.2028381578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_busy.1627943201 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 395345971 ps |
| CPU time | 2.31 seconds |
| Started | Aug 28 10:20:02 PM UTC 24 |
| Finished | Aug 28 10:20:06 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627943201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.1627943201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_cmderr_busy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.189070212 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 788409098 ps |
| CPU time | 5.32 seconds |
| Started | Aug 28 10:20:02 PM UTC 24 |
| Finished | Aug 28 10:20:09 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189070212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_cmderr_exception_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.189070212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_cmderr_exception/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.190837853 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 124986604 ps |
| CPU time | 1.09 seconds |
| Started | Aug 28 10:20:02 PM UTC 24 |
| Finished | Aug 28 10:20:05 PM UTC 24 |
| Peak memory | 215356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190837853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.190837853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_cmderr_not_supported/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_dataaddr_rw_access.3819486566 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 120262039 ps |
| CPU time | 1.33 seconds |
| Started | Aug 28 10:20:06 PM UTC 24 |
| Finished | Aug 28 10:20:08 PM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819486566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.3819486566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_dataaddr_rw_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_debug_disabled.140699563 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 41407634 ps |
| CPU time | 1.11 seconds |
| Started | Aug 28 10:20:09 PM UTC 24 |
| Finished | Aug 28 10:20:12 PM UTC 24 |
| Peak memory | 236048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140699563 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.140699563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2164684918 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 6645293786 ps |
| CPU time | 27.37 seconds |
| Started | Aug 28 10:20:02 PM UTC 24 |
| Finished | Aug 28 10:20:31 PM UTC 24 |
| Peak memory | 216264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164684918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_tl_access.2164684918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.1616106764 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 521106625 ps |
| CPU time | 1.2 seconds |
| Started | Aug 28 10:20:06 PM UTC 24 |
| Finished | Aug 28 10:20:08 PM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616106764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.1616106764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_hart_unavail.394948620 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 203641840 ps |
| CPU time | 1.34 seconds |
| Started | Aug 28 10:20:04 PM UTC 24 |
| Finished | Aug 28 10:20:06 PM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394948620 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.394948620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_hartsel_warl.700822474 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 67293740 ps |
| CPU time | 1.28 seconds |
| Started | Aug 28 10:20:11 PM UTC 24 |
| Finished | Aug 28 10:20:13 PM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700822474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_hartsel_warl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.700822474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_hartsel_warl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.4090102021 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 185727918 ps |
| CPU time | 2.08 seconds |
| Started | Aug 28 10:20:09 PM UTC 24 |
| Finished | Aug 28 10:20:12 PM UTC 24 |
| Peak memory | 216004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090102021 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.4090102021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1493171088 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 692948490 ps |
| CPU time | 1.81 seconds |
| Started | Aug 28 10:20:07 PM UTC 24 |
| Finished | Aug 28 10:20:10 PM UTC 24 |
| Peak memory | 213464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493171088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.1493171088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_dm_inactive/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2288428435 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 310985406 ps |
| CPU time | 1.48 seconds |
| Started | Aug 28 10:20:09 PM UTC 24 |
| Finished | Aug 28 10:20:12 PM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288428435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.2288428435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_hard_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_idle_hint.2384174513 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 248181894 ps |
| CPU time | 1.51 seconds |
| Started | Aug 28 10:20:07 PM UTC 24 |
| Finished | Aug 28 10:20:09 PM UTC 24 |
| Peak memory | 213336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384174513 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.2384174513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_idle_hint/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_halted.3266614427 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 115562365 ps |
| CPU time | 1.08 seconds |
| Started | Aug 28 10:20:04 PM UTC 24 |
| Finished | Aug 28 10:20:06 PM UTC 24 |
| Peak memory | 213464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266614427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.3266614427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_halted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_resuming.177082664 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 662528050 ps |
| CPU time | 2.05 seconds |
| Started | Aug 28 10:20:04 PM UTC 24 |
| Finished | Aug 28 10:20:07 PM UTC 24 |
| Peak memory | 215940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177082664 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.177082664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_resuming/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.2222244945 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 801036133 ps |
| CPU time | 1.9 seconds |
| Started | Aug 28 10:20:07 PM UTC 24 |
| Finished | Aug 28 10:20:10 PM UTC 24 |
| Peak memory | 225860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222244945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.2222244945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_ndmreset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.1775067635 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 467635950 ps |
| CPU time | 4.32 seconds |
| Started | Aug 28 10:20:09 PM UTC 24 |
| Finished | Aug 28 10:20:15 PM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775067635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_progbuf_read_write_execute_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_d m-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.1775067635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_progbuf_read_write_execute/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.2593698828 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 2354556955 ps |
| CPU time | 8.06 seconds |
| Started | Aug 28 10:20:11 PM UTC 24 |
| Finished | Aug 28 10:20:20 PM UTC 24 |
| Peak memory | 254876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593698828 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.2593698828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_smoke.2176387114 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 2200226501 ps |
| CPU time | 11.51 seconds |
| Started | Aug 28 10:20:02 PM UTC 24 |
| Finished | Aug 28 10:20:15 PM UTC 24 |
| Peak memory | 216000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176387114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.2176387114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/0.rv_dm_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_abstractcmd_status.1582578646 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 515181655 ps |
| CPU time | 1.79 seconds |
| Started | Aug 28 10:20:16 PM UTC 24 |
| Finished | Aug 28 10:20:19 PM UTC 24 |
| Peak memory | 213336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582578646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_abstractcmd_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.1582578646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_abstractcmd_status/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_bad_sba_tl_access.4080556619 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 7880977505 ps |
| CPU time | 22.81 seconds |
| Started | Aug 28 10:20:12 PM UTC 24 |
| Finished | Aug 28 10:20:36 PM UTC 24 |
| Peak memory | 216328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080556619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.4080556619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_buffered_enable.2670906447 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 88929514 ps |
| CPU time | 1.49 seconds |
| Started | Aug 28 10:20:18 PM UTC 24 |
| Finished | Aug 28 10:20:20 PM UTC 24 |
| Peak memory | 257304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670906447 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_buffered_enable.2670906447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_busy.2038418212 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 309644849 ps |
| CPU time | 1.88 seconds |
| Started | Aug 28 10:20:13 PM UTC 24 |
| Finished | Aug 28 10:20:15 PM UTC 24 |
| Peak memory | 213340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038418212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.2038418212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_cmderr_busy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.256882959 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 3079200661 ps |
| CPU time | 3.07 seconds |
| Started | Aug 28 10:20:14 PM UTC 24 |
| Finished | Aug 28 10:20:18 PM UTC 24 |
| Peak memory | 215876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256882959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_cmderr_halt_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.256882959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_cmderr_halt_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_not_supported.4205857379 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 791266292 ps |
| CPU time | 3.1 seconds |
| Started | Aug 28 10:20:13 PM UTC 24 |
| Finished | Aug 28 10:20:17 PM UTC 24 |
| Peak memory | 215936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205857379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.4205857379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_cmderr_not_supported/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_dataaddr_rw_access.4228386351 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 97628453 ps |
| CPU time | 1.48 seconds |
| Started | Aug 28 10:20:14 PM UTC 24 |
| Finished | Aug 28 10:20:16 PM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228386351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.4228386351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_dataaddr_rw_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_debug_disabled.1205603166 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 64129048 ps |
| CPU time | 1.3 seconds |
| Started | Aug 28 10:20:18 PM UTC 24 |
| Finished | Aug 28 10:20:20 PM UTC 24 |
| Peak memory | 236056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205603166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.1205603166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.3569435634 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 6894256450 ps |
| CPU time | 24.03 seconds |
| Started | Aug 28 10:20:12 PM UTC 24 |
| Finished | Aug 28 10:20:38 PM UTC 24 |
| Peak memory | 226548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569435634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_tl_access.3569435634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_halt_resume_whereto.1637628786 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 833585658 ps |
| CPU time | 2.35 seconds |
| Started | Aug 28 10:20:14 PM UTC 24 |
| Finished | Aug 28 10:20:17 PM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637628786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.1637628786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_hart_unavail.81853827 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 54759784 ps |
| CPU time | 1.34 seconds |
| Started | Aug 28 10:20:14 PM UTC 24 |
| Finished | Aug 28 10:20:16 PM UTC 24 |
| Peak memory | 213400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81853827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv _dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.81853827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.4211365942 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 135125045 ps |
| CPU time | 1.23 seconds |
| Started | Aug 28 10:20:15 PM UTC 24 |
| Finished | Aug 28 10:20:18 PM UTC 24 |
| Peak memory | 213460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211365942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.4211365942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1672054646 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 2281916318 ps |
| CPU time | 3.2 seconds |
| Started | Aug 28 10:20:15 PM UTC 24 |
| Finished | Aug 28 10:20:19 PM UTC 24 |
| Peak memory | 215936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672054646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.1672054646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_dm_inactive/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3880187866 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 629178974 ps |
| CPU time | 4.4 seconds |
| Started | Aug 28 10:20:16 PM UTC 24 |
| Finished | Aug 28 10:20:22 PM UTC 24 |
| Peak memory | 215936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880187866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.3880187866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_hard_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_idle_hint.2960802988 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 683104044 ps |
| CPU time | 1.37 seconds |
| Started | Aug 28 10:20:15 PM UTC 24 |
| Finished | Aug 28 10:20:18 PM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960802988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.2960802988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_idle_hint/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_halted.3013365982 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 81712426 ps |
| CPU time | 1.16 seconds |
| Started | Aug 28 10:20:13 PM UTC 24 |
| Finished | Aug 28 10:20:15 PM UTC 24 |
| Peak memory | 213464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013365982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.3013365982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_mem_tl_access_halted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_resuming.3136275091 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 664190135 ps |
| CPU time | 1.8 seconds |
| Started | Aug 28 10:20:14 PM UTC 24 |
| Finished | Aug 28 10:20:17 PM UTC 24 |
| Peak memory | 215940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136275091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.3136275091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_mem_tl_access_resuming/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_ndmreset_req.1737629502 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 700023711 ps |
| CPU time | 1.99 seconds |
| Started | Aug 28 10:20:15 PM UTC 24 |
| Finished | Aug 28 10:20:18 PM UTC 24 |
| Peak memory | 225788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737629502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.1737629502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_ndmreset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_progbuf_read_write_execute.12525660 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 355682963 ps |
| CPU time | 1.91 seconds |
| Started | Aug 28 10:20:17 PM UTC 24 |
| Finished | Aug 28 10:20:19 PM UTC 24 |
| Peak memory | 215944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12525660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv _dm_progbuf_read_write_execute_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.12525660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_progbuf_read_write_execute/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_rom_read_access.2468060430 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 34142324 ps |
| CPU time | 1 seconds |
| Started | Aug 28 10:20:17 PM UTC 24 |
| Finished | Aug 28 10:20:19 PM UTC 24 |
| Peak memory | 225920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468060430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_rom_read_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.2468060430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_rom_read_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_debug_disabled.3574367234 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 2638604015 ps |
| CPU time | 13.3 seconds |
| Started | Aug 28 10:20:15 PM UTC 24 |
| Finished | Aug 28 10:20:30 PM UTC 24 |
| Peak memory | 216012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574367234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.3574367234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_sba_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_tl_access.31800561 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 2754932587 ps |
| CPU time | 9.17 seconds |
| Started | Aug 28 10:20:12 PM UTC 24 |
| Finished | Aug 28 10:20:23 PM UTC 24 |
| Peak memory | 216272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31800561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv _dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.31800561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_sec_cm.2669266925 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 556199456 ps |
| CPU time | 1.61 seconds |
| Started | Aug 28 10:20:18 PM UTC 24 |
| Finished | Aug 28 10:20:21 PM UTC 24 |
| Peak memory | 252384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669266925 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.2669266925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_smoke.4006589238 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 609566233 ps |
| CPU time | 2.04 seconds |
| Started | Aug 28 10:20:11 PM UTC 24 |
| Finished | Aug 28 10:20:14 PM UTC 24 |
| Peak memory | 215968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006589238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.4006589238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.148075217 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 2080029368 ps |
| CPU time | 7.19 seconds |
| Started | Aug 28 10:20:18 PM UTC 24 |
| Finished | Aug 28 10:20:26 PM UTC 24 |
| Peak memory | 215944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148075217 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.148075217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.2462372688 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 43252948694 ps |
| CPU time | 61.3 seconds |
| Started | Aug 28 10:20:18 PM UTC 24 |
| Finished | Aug 28 10:21:21 PM UTC 24 |
| Peak memory | 233196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2462372688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stres s_all_with_rand_reset.2462372688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/10.rv_dm_alert_test.2108271722 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 42687242 ps |
| CPU time | 1.13 seconds |
| Started | Aug 28 10:20:50 PM UTC 24 |
| Finished | Aug 28 10:20:52 PM UTC 24 |
| Peak memory | 215880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108271722 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.2108271722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/10.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/10.rv_dm_autoincr_sba_tl_access.3100650536 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 6535097051 ps |
| CPU time | 17.62 seconds |
| Started | Aug 28 10:20:50 PM UTC 24 |
| Finished | Aug 28 10:21:08 PM UTC 24 |
| Peak memory | 226492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100650536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.3100650536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/10.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/10.rv_dm_bad_sba_tl_access.1973452508 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 4544383117 ps |
| CPU time | 19.78 seconds |
| Started | Aug 28 10:20:50 PM UTC 24 |
| Finished | Aug 28 10:21:10 PM UTC 24 |
| Peak memory | 216260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973452508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.1973452508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/10.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.646369625 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 3778994239 ps |
| CPU time | 18.21 seconds |
| Started | Aug 28 10:20:49 PM UTC 24 |
| Finished | Aug 28 10:21:09 PM UTC 24 |
| Peak memory | 216200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646369625 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_tl_access.646369625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/10.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/10.rv_dm_sba_tl_access.1045207155 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 833204218 ps |
| CPU time | 2.82 seconds |
| Started | Aug 28 10:20:49 PM UTC 24 |
| Finished | Aug 28 10:20:53 PM UTC 24 |
| Peak memory | 216144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045207155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.1045207155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/10.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/10.rv_dm_stress_all.3794837148 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 2299605320 ps |
| CPU time | 10.96 seconds |
| Started | Aug 28 10:20:50 PM UTC 24 |
| Finished | Aug 28 10:21:02 PM UTC 24 |
| Peak memory | 216008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794837148 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.3794837148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/10.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/11.rv_dm_alert_test.2182998196 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 112775036 ps |
| CPU time | 1.32 seconds |
| Started | Aug 28 10:20:53 PM UTC 24 |
| Finished | Aug 28 10:20:55 PM UTC 24 |
| Peak memory | 215880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182998196 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.2182998196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/11.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/11.rv_dm_autoincr_sba_tl_access.441216383 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 4276424357 ps |
| CPU time | 15.03 seconds |
| Started | Aug 28 10:20:52 PM UTC 24 |
| Finished | Aug 28 10:21:08 PM UTC 24 |
| Peak memory | 216196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441216383 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.441216383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/11.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/11.rv_dm_bad_sba_tl_access.3992875270 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 1149913046 ps |
| CPU time | 1.95 seconds |
| Started | Aug 28 10:20:52 PM UTC 24 |
| Finished | Aug 28 10:20:55 PM UTC 24 |
| Peak memory | 215484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992875270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.3992875270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/11.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.3789840566 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 16735552153 ps |
| CPU time | 20.71 seconds |
| Started | Aug 28 10:20:51 PM UTC 24 |
| Finished | Aug 28 10:21:13 PM UTC 24 |
| Peak memory | 226632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789840566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_tl_access.3789840566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/11.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/11.rv_dm_sba_tl_access.884162544 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 2897630207 ps |
| CPU time | 9.05 seconds |
| Started | Aug 28 10:20:51 PM UTC 24 |
| Finished | Aug 28 10:21:01 PM UTC 24 |
| Peak memory | 216324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884162544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.884162544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/11.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/11.rv_dm_stress_all.3253978807 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 2588528152 ps |
| CPU time | 7.36 seconds |
| Started | Aug 28 10:20:52 PM UTC 24 |
| Finished | Aug 28 10:21:00 PM UTC 24 |
| Peak memory | 226248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253978807 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.3253978807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/11.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/12.rv_dm_alert_test.746041186 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 106646022 ps |
| CPU time | 1.25 seconds |
| Started | Aug 28 10:20:56 PM UTC 24 |
| Finished | Aug 28 10:20:58 PM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746041186 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.746041186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/12.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/12.rv_dm_autoincr_sba_tl_access.828494674 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 57466761187 ps |
| CPU time | 177 seconds |
| Started | Aug 28 10:20:54 PM UTC 24 |
| Finished | Aug 28 10:23:54 PM UTC 24 |
| Peak memory | 226432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828494674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.828494674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/12.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/12.rv_dm_bad_sba_tl_access.1427090897 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 1848229168 ps |
| CPU time | 5.38 seconds |
| Started | Aug 28 10:20:54 PM UTC 24 |
| Finished | Aug 28 10:21:01 PM UTC 24 |
| Peak memory | 216188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427090897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.1427090897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/12.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.4019565813 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 2380880256 ps |
| CPU time | 4.18 seconds |
| Started | Aug 28 10:20:53 PM UTC 24 |
| Finished | Aug 28 10:20:58 PM UTC 24 |
| Peak memory | 216252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019565813 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_tl_access.4019565813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/12.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/12.rv_dm_sba_tl_access.3344916438 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 1358277192 ps |
| CPU time | 5.24 seconds |
| Started | Aug 28 10:20:53 PM UTC 24 |
| Finished | Aug 28 10:20:59 PM UTC 24 |
| Peak memory | 216204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344916438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.3344916438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/12.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/12.rv_dm_stress_all.279556791 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1630462812 ps |
| CPU time | 5.39 seconds |
| Started | Aug 28 10:20:55 PM UTC 24 |
| Finished | Aug 28 10:21:02 PM UTC 24 |
| Peak memory | 216008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279556791 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.279556791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/12.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/13.rv_dm_alert_test.1317031919 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 132910820 ps |
| CPU time | 1.09 seconds |
| Started | Aug 28 10:20:58 PM UTC 24 |
| Finished | Aug 28 10:21:00 PM UTC 24 |
| Peak memory | 215880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317031919 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.1317031919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/13.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/13.rv_dm_autoincr_sba_tl_access.2909760809 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 1175609061 ps |
| CPU time | 6.96 seconds |
| Started | Aug 28 10:20:57 PM UTC 24 |
| Finished | Aug 28 10:21:05 PM UTC 24 |
| Peak memory | 216188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909760809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.2909760809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/13.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/13.rv_dm_bad_sba_tl_access.770094918 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 1746806132 ps |
| CPU time | 6.28 seconds |
| Started | Aug 28 10:20:57 PM UTC 24 |
| Finished | Aug 28 10:21:04 PM UTC 24 |
| Peak memory | 226424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770094918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.770094918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/13.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.3229192319 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 2596951146 ps |
| CPU time | 7.35 seconds |
| Started | Aug 28 10:20:57 PM UTC 24 |
| Finished | Aug 28 10:21:05 PM UTC 24 |
| Peak memory | 216512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229192319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_tl_access.3229192319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/13.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/13.rv_dm_sba_tl_access.3957363606 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 10696871648 ps |
| CPU time | 41.35 seconds |
| Started | Aug 28 10:20:56 PM UTC 24 |
| Finished | Aug 28 10:21:38 PM UTC 24 |
| Peak memory | 226496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957363606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.3957363606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/13.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/13.rv_dm_stress_all.2747259082 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 4165841847 ps |
| CPU time | 5.21 seconds |
| Started | Aug 28 10:20:57 PM UTC 24 |
| Finished | Aug 28 10:21:03 PM UTC 24 |
| Peak memory | 226304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747259082 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.2747259082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/13.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/14.rv_dm_alert_test.3882346263 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 52390568 ps |
| CPU time | 1.24 seconds |
| Started | Aug 28 10:21:02 PM UTC 24 |
| Finished | Aug 28 10:21:05 PM UTC 24 |
| Peak memory | 215880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882346263 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.3882346263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/14.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/14.rv_dm_autoincr_sba_tl_access.3669041938 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 1965789016 ps |
| CPU time | 12.77 seconds |
| Started | Aug 28 10:21:02 PM UTC 24 |
| Finished | Aug 28 10:21:16 PM UTC 24 |
| Peak memory | 216176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669041938 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.3669041938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/14.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/14.rv_dm_bad_sba_tl_access.3833859321 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 10280542121 ps |
| CPU time | 22.12 seconds |
| Started | Aug 28 10:21:02 PM UTC 24 |
| Finished | Aug 28 10:21:26 PM UTC 24 |
| Peak memory | 226628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833859321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.3833859321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/14.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.3018927376 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 1896391571 ps |
| CPU time | 9.28 seconds |
| Started | Aug 28 10:20:58 PM UTC 24 |
| Finished | Aug 28 10:21:08 PM UTC 24 |
| Peak memory | 216136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018927376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_tl_access.3018927376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/14.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/14.rv_dm_sba_tl_access.97071906 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 1507342892 ps |
| CPU time | 2.51 seconds |
| Started | Aug 28 10:20:58 PM UTC 24 |
| Finished | Aug 28 10:21:01 PM UTC 24 |
| Peak memory | 216272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97071906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv _dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.97071906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/14.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/14.rv_dm_stress_all.2472023808 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 2707622555 ps |
| CPU time | 13.34 seconds |
| Started | Aug 28 10:21:02 PM UTC 24 |
| Finished | Aug 28 10:21:17 PM UTC 24 |
| Peak memory | 216068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472023808 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.2472023808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/14.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/15.rv_dm_alert_test.586890780 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 42031012 ps |
| CPU time | 0.99 seconds |
| Started | Aug 28 10:21:03 PM UTC 24 |
| Finished | Aug 28 10:21:05 PM UTC 24 |
| Peak memory | 215940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586890780 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.586890780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/15.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/15.rv_dm_autoincr_sba_tl_access.3104308971 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 12671756575 ps |
| CPU time | 14.28 seconds |
| Started | Aug 28 10:21:03 PM UTC 24 |
| Finished | Aug 28 10:21:18 PM UTC 24 |
| Peak memory | 233240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104308971 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.3104308971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/15.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/15.rv_dm_bad_sba_tl_access.4283349972 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 792684732 ps |
| CPU time | 2.19 seconds |
| Started | Aug 28 10:21:02 PM UTC 24 |
| Finished | Aug 28 10:21:06 PM UTC 24 |
| Peak memory | 216260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283349972 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.4283349972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/15.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.3823680267 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 9304112635 ps |
| CPU time | 29.46 seconds |
| Started | Aug 28 10:21:02 PM UTC 24 |
| Finished | Aug 28 10:21:33 PM UTC 24 |
| Peak memory | 226428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823680267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_tl_access.3823680267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/15.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/15.rv_dm_sba_tl_access.652141305 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 5079229214 ps |
| CPU time | 5.51 seconds |
| Started | Aug 28 10:21:02 PM UTC 24 |
| Finished | Aug 28 10:21:09 PM UTC 24 |
| Peak memory | 216324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652141305 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.652141305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/15.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/15.rv_dm_stress_all.4265468543 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 1591872906 ps |
| CPU time | 3.7 seconds |
| Started | Aug 28 10:21:03 PM UTC 24 |
| Finished | Aug 28 10:21:07 PM UTC 24 |
| Peak memory | 216000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265468543 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.4265468543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/15.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/16.rv_dm_alert_test.343929763 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 155706036 ps |
| CPU time | 1.42 seconds |
| Started | Aug 28 10:21:04 PM UTC 24 |
| Finished | Aug 28 10:21:07 PM UTC 24 |
| Peak memory | 215760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343929763 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.343929763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/16.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/16.rv_dm_bad_sba_tl_access.2779596886 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 1513593359 ps |
| CPU time | 5.81 seconds |
| Started | Aug 28 10:21:03 PM UTC 24 |
| Finished | Aug 28 10:21:10 PM UTC 24 |
| Peak memory | 216208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779596886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.2779596886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/16.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.1529340550 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 2670536758 ps |
| CPU time | 15.81 seconds |
| Started | Aug 28 10:21:03 PM UTC 24 |
| Finished | Aug 28 10:21:20 PM UTC 24 |
| Peak memory | 216308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529340550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_tl_access.1529340550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/16.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/16.rv_dm_sba_tl_access.721606804 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 6914925638 ps |
| CPU time | 10.32 seconds |
| Started | Aug 28 10:21:03 PM UTC 24 |
| Finished | Aug 28 10:21:14 PM UTC 24 |
| Peak memory | 216196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721606804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.721606804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/16.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/16.rv_dm_stress_all.1754210592 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 1721037835 ps |
| CPU time | 3.67 seconds |
| Started | Aug 28 10:21:03 PM UTC 24 |
| Finished | Aug 28 10:21:08 PM UTC 24 |
| Peak memory | 216084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754210592 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.1754210592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/16.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/17.rv_dm_alert_test.1611174973 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 119008183 ps |
| CPU time | 1.31 seconds |
| Started | Aug 28 10:21:05 PM UTC 24 |
| Finished | Aug 28 10:21:08 PM UTC 24 |
| Peak memory | 215880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611174973 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.1611174973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/17.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/17.rv_dm_bad_sba_tl_access.2867122759 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 9003630147 ps |
| CPU time | 24.23 seconds |
| Started | Aug 28 10:21:04 PM UTC 24 |
| Finished | Aug 28 10:21:30 PM UTC 24 |
| Peak memory | 226436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867122759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.2867122759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/17.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.2890357524 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 14942990373 ps |
| CPU time | 21.25 seconds |
| Started | Aug 28 10:21:04 PM UTC 24 |
| Finished | Aug 28 10:21:27 PM UTC 24 |
| Peak memory | 226344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890357524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_tl_access.2890357524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/17.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/17.rv_dm_sba_tl_access.335526287 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 9956268989 ps |
| CPU time | 16.44 seconds |
| Started | Aug 28 10:21:04 PM UTC 24 |
| Finished | Aug 28 10:21:22 PM UTC 24 |
| Peak memory | 216280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335526287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.335526287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/17.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/17.rv_dm_stress_all.490985663 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 1918526929 ps |
| CPU time | 7.8 seconds |
| Started | Aug 28 10:21:05 PM UTC 24 |
| Finished | Aug 28 10:21:14 PM UTC 24 |
| Peak memory | 226152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490985663 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.490985663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/17.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/18.rv_dm_alert_test.3995646471 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 32604522 ps |
| CPU time | 1.1 seconds |
| Started | Aug 28 10:21:07 PM UTC 24 |
| Finished | Aug 28 10:21:09 PM UTC 24 |
| Peak memory | 215880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995646471 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.3995646471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/18.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/18.rv_dm_autoincr_sba_tl_access.2526403089 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 2252651558 ps |
| CPU time | 10.32 seconds |
| Started | Aug 28 10:21:07 PM UTC 24 |
| Finished | Aug 28 10:21:18 PM UTC 24 |
| Peak memory | 226556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526403089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.2526403089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/18.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/18.rv_dm_bad_sba_tl_access.1239421279 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 3648402830 ps |
| CPU time | 4.75 seconds |
| Started | Aug 28 10:21:07 PM UTC 24 |
| Finished | Aug 28 10:21:12 PM UTC 24 |
| Peak memory | 216316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239421279 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.1239421279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/18.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.1486940574 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 6895354897 ps |
| CPU time | 7.72 seconds |
| Started | Aug 28 10:21:06 PM UTC 24 |
| Finished | Aug 28 10:21:14 PM UTC 24 |
| Peak memory | 216384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486940574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_tl_access.1486940574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/18.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/18.rv_dm_sba_tl_access.1526099542 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 5145452384 ps |
| CPU time | 12.83 seconds |
| Started | Aug 28 10:21:05 PM UTC 24 |
| Finished | Aug 28 10:21:19 PM UTC 24 |
| Peak memory | 226316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526099542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.1526099542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/18.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/18.rv_dm_stress_all.2352117141 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 1871263516 ps |
| CPU time | 4.03 seconds |
| Started | Aug 28 10:21:07 PM UTC 24 |
| Finished | Aug 28 10:21:12 PM UTC 24 |
| Peak memory | 226316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352117141 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.2352117141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/18.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/19.rv_dm_alert_test.1849724834 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 59650079 ps |
| CPU time | 1.04 seconds |
| Started | Aug 28 10:21:09 PM UTC 24 |
| Finished | Aug 28 10:21:11 PM UTC 24 |
| Peak memory | 215880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849724834 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.1849724834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/19.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.1819113776 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 4286504577 ps |
| CPU time | 3.2 seconds |
| Started | Aug 28 10:21:08 PM UTC 24 |
| Finished | Aug 28 10:21:12 PM UTC 24 |
| Peak memory | 226544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819113776 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.1819113776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/19.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/19.rv_dm_bad_sba_tl_access.2982262594 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 1649879426 ps |
| CPU time | 8.59 seconds |
| Started | Aug 28 10:21:08 PM UTC 24 |
| Finished | Aug 28 10:21:18 PM UTC 24 |
| Peak memory | 226512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982262594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.2982262594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/19.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2758172895 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 3116559597 ps |
| CPU time | 4.41 seconds |
| Started | Aug 28 10:21:08 PM UTC 24 |
| Finished | Aug 28 10:21:13 PM UTC 24 |
| Peak memory | 216320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758172895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_tl_access.2758172895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/19.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/19.rv_dm_sba_tl_access.2762096076 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 1329624068 ps |
| CPU time | 8.3 seconds |
| Started | Aug 28 10:21:08 PM UTC 24 |
| Finished | Aug 28 10:21:17 PM UTC 24 |
| Peak memory | 216320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762096076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.2762096076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/19.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.2586208798 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 4609688438 ps |
| CPU time | 9.7 seconds |
| Started | Aug 28 10:21:08 PM UTC 24 |
| Finished | Aug 28 10:21:19 PM UTC 24 |
| Peak memory | 216068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586208798 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.2586208798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/19.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.3851707381 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 204285683 ps |
| CPU time | 0.69 seconds |
| Started | Aug 28 10:20:33 PM UTC 24 |
| Finished | Aug 28 10:20:34 PM UTC 24 |
| Peak memory | 215940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851707381 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.3851707381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/2.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.1665478385 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 6363661721 ps |
| CPU time | 11.83 seconds |
| Started | Aug 28 10:20:32 PM UTC 24 |
| Finished | Aug 28 10:20:45 PM UTC 24 |
| Peak memory | 226512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665478385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.1665478385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/2.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.3070632382 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 3962107224 ps |
| CPU time | 2.89 seconds |
| Started | Aug 28 10:20:32 PM UTC 24 |
| Finished | Aug 28 10:20:36 PM UTC 24 |
| Peak memory | 226136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070632382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.3070632382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/2.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.1653410699 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 122371349 ps |
| CPU time | 1.14 seconds |
| Started | Aug 28 10:20:32 PM UTC 24 |
| Finished | Aug 28 10:20:35 PM UTC 24 |
| Peak memory | 244744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653410699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_buffered_enable.1653410699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/2.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.2238058738 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 4133412300 ps |
| CPU time | 9.74 seconds |
| Started | Aug 28 10:20:32 PM UTC 24 |
| Finished | Aug 28 10:20:43 PM UTC 24 |
| Peak memory | 226196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238058738 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_tl_access.2238058738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/2.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.3684929813 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 76415800 ps |
| CPU time | 0.92 seconds |
| Started | Aug 28 10:20:32 PM UTC 24 |
| Finished | Aug 28 10:20:34 PM UTC 24 |
| Peak memory | 213460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684929813 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.3684929813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/2.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.4094789621 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 2661173101 ps |
| CPU time | 6.82 seconds |
| Started | Aug 28 10:20:32 PM UTC 24 |
| Finished | Aug 28 10:20:40 PM UTC 24 |
| Peak memory | 226500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094789621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.4094789621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/2.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/2.rv_dm_sparse_lc_gate_fsm.2234715487 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 287308629 ps |
| CPU time | 1.85 seconds |
| Started | Aug 28 10:20:32 PM UTC 24 |
| Finished | Aug 28 10:20:35 PM UTC 24 |
| Peak memory | 225856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234715487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sparse_lc_gate_fsm.2234715487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/2.rv_dm_sparse_lc_gate_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all.3831462074 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 7749393196 ps |
| CPU time | 24.66 seconds |
| Started | Aug 28 10:20:32 PM UTC 24 |
| Finished | Aug 28 10:20:58 PM UTC 24 |
| Peak memory | 216004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831462074 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.3831462074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/2.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/20.rv_dm_alert_test.2157413933 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 64384934 ps |
| CPU time | 1.29 seconds |
| Started | Aug 28 10:21:09 PM UTC 24 |
| Finished | Aug 28 10:21:12 PM UTC 24 |
| Peak memory | 215880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157413933 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.2157413933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/20.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/21.rv_dm_alert_test.1476021949 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 144281423 ps |
| CPU time | 1.19 seconds |
| Started | Aug 28 10:21:09 PM UTC 24 |
| Finished | Aug 28 10:21:12 PM UTC 24 |
| Peak memory | 215880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476021949 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.1476021949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/21.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/21.rv_dm_stress_all.3481873229 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 1078526583 ps |
| CPU time | 3.86 seconds |
| Started | Aug 28 10:21:09 PM UTC 24 |
| Finished | Aug 28 10:21:14 PM UTC 24 |
| Peak memory | 216004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481873229 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.3481873229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/21.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/22.rv_dm_alert_test.3206067697 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 103234167 ps |
| CPU time | 1.33 seconds |
| Started | Aug 28 10:21:10 PM UTC 24 |
| Finished | Aug 28 10:21:12 PM UTC 24 |
| Peak memory | 215880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206067697 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.3206067697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/22.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.3494961271 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 7964688775 ps |
| CPU time | 31.23 seconds |
| Started | Aug 28 10:21:10 PM UTC 24 |
| Finished | Aug 28 10:21:42 PM UTC 24 |
| Peak memory | 226432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494961271 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.3494961271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/22.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/23.rv_dm_alert_test.2166754383 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 56026213 ps |
| CPU time | 0.88 seconds |
| Started | Aug 28 10:21:11 PM UTC 24 |
| Finished | Aug 28 10:21:13 PM UTC 24 |
| Peak memory | 215724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166754383 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.2166754383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/23.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/23.rv_dm_stress_all.3385617068 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 2196235774 ps |
| CPU time | 6.15 seconds |
| Started | Aug 28 10:21:11 PM UTC 24 |
| Finished | Aug 28 10:21:18 PM UTC 24 |
| Peak memory | 216004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385617068 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.3385617068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/23.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/24.rv_dm_alert_test.2095000766 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 80707022 ps |
| CPU time | 1.31 seconds |
| Started | Aug 28 10:21:12 PM UTC 24 |
| Finished | Aug 28 10:21:14 PM UTC 24 |
| Peak memory | 215880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095000766 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.2095000766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/24.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/24.rv_dm_stress_all.1533386263 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 2830040813 ps |
| CPU time | 4.17 seconds |
| Started | Aug 28 10:21:11 PM UTC 24 |
| Finished | Aug 28 10:21:16 PM UTC 24 |
| Peak memory | 216188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533386263 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.1533386263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/24.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/25.rv_dm_alert_test.3042681416 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 44995317 ps |
| CPU time | 1.27 seconds |
| Started | Aug 28 10:21:13 PM UTC 24 |
| Finished | Aug 28 10:21:15 PM UTC 24 |
| Peak memory | 215880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042681416 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.3042681416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/25.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.393211925 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4459116668 ps |
| CPU time | 9.07 seconds |
| Started | Aug 28 10:21:12 PM UTC 24 |
| Finished | Aug 28 10:21:22 PM UTC 24 |
| Peak memory | 216200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393211925 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.393211925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/25.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/26.rv_dm_alert_test.1134346487 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 51800273 ps |
| CPU time | 1.08 seconds |
| Started | Aug 28 10:21:13 PM UTC 24 |
| Finished | Aug 28 10:21:15 PM UTC 24 |
| Peak memory | 215880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134346487 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.1134346487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/26.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/26.rv_dm_stress_all.1222950805 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 5013460702 ps |
| CPU time | 11.97 seconds |
| Started | Aug 28 10:21:13 PM UTC 24 |
| Finished | Aug 28 10:21:26 PM UTC 24 |
| Peak memory | 216128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222950805 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.1222950805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/26.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/27.rv_dm_alert_test.1575053248 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 56391289 ps |
| CPU time | 1.32 seconds |
| Started | Aug 28 10:21:13 PM UTC 24 |
| Finished | Aug 28 10:21:16 PM UTC 24 |
| Peak memory | 215880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575053248 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.1575053248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/27.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.715403701 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 2559584551 ps |
| CPU time | 4.52 seconds |
| Started | Aug 28 10:21:13 PM UTC 24 |
| Finished | Aug 28 10:21:19 PM UTC 24 |
| Peak memory | 216268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715403701 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.715403701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/27.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/28.rv_dm_alert_test.971476609 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 59712661 ps |
| CPU time | 1.23 seconds |
| Started | Aug 28 10:21:13 PM UTC 24 |
| Finished | Aug 28 10:21:16 PM UTC 24 |
| Peak memory | 215940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971476609 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.971476609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/28.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/28.rv_dm_stress_all.2682506224 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 6006431156 ps |
| CPU time | 21.02 seconds |
| Started | Aug 28 10:21:13 PM UTC 24 |
| Finished | Aug 28 10:21:36 PM UTC 24 |
| Peak memory | 216144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682506224 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.2682506224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/28.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/29.rv_dm_alert_test.2275353156 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 54755616 ps |
| CPU time | 1.23 seconds |
| Started | Aug 28 10:21:13 PM UTC 24 |
| Finished | Aug 28 10:21:16 PM UTC 24 |
| Peak memory | 215880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275353156 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.2275353156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/29.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/29.rv_dm_stress_all.1609868825 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 1220245729 ps |
| CPU time | 2.55 seconds |
| Started | Aug 28 10:21:13 PM UTC 24 |
| Finished | Aug 28 10:21:17 PM UTC 24 |
| Peak memory | 226312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609868825 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.1609868825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/29.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.3984308923 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 47612924 ps |
| CPU time | 0.93 seconds |
| Started | Aug 28 10:20:33 PM UTC 24 |
| Finished | Aug 28 10:20:35 PM UTC 24 |
| Peak memory | 215940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984308923 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.3984308923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/3.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.40715674 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 9716609591 ps |
| CPU time | 32 seconds |
| Started | Aug 28 10:20:33 PM UTC 24 |
| Finished | Aug 28 10:21:06 PM UTC 24 |
| Peak memory | 226628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40715674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv _dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.40715674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/3.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.1828286436 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 4723653820 ps |
| CPU time | 7.74 seconds |
| Started | Aug 28 10:20:33 PM UTC 24 |
| Finished | Aug 28 10:20:42 PM UTC 24 |
| Peak memory | 226492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828286436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.1828286436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/3.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.1003049059 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 452948958 ps |
| CPU time | 2.08 seconds |
| Started | Aug 28 10:20:33 PM UTC 24 |
| Finished | Aug 28 10:20:36 PM UTC 24 |
| Peak memory | 250196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003049059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_buffered_enable.1003049059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/3.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1700057599 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 12154664792 ps |
| CPU time | 28.6 seconds |
| Started | Aug 28 10:20:33 PM UTC 24 |
| Finished | Aug 28 10:21:03 PM UTC 24 |
| Peak memory | 226532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700057599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_tl_access.1700057599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/3.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.1031702914 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 456858333 ps |
| CPU time | 1.95 seconds |
| Started | Aug 28 10:20:33 PM UTC 24 |
| Finished | Aug 28 10:20:36 PM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031702914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_halt_resume_whereto.1031702914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/3.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/3.rv_dm_hart_unavail.4191061712 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 139172414 ps |
| CPU time | 0.79 seconds |
| Started | Aug 28 10:20:33 PM UTC 24 |
| Finished | Aug 28 10:20:35 PM UTC 24 |
| Peak memory | 213460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191061712 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.4191061712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/3.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.418431251 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 1135175839 ps |
| CPU time | 4.46 seconds |
| Started | Aug 28 10:20:33 PM UTC 24 |
| Finished | Aug 28 10:20:38 PM UTC 24 |
| Peak memory | 216136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418431251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.418431251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/3.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/3.rv_dm_sec_cm.3610925223 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 684915463 ps |
| CPU time | 2.86 seconds |
| Started | Aug 28 10:20:33 PM UTC 24 |
| Finished | Aug 28 10:20:37 PM UTC 24 |
| Peak memory | 256872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610925223 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.3610925223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/3.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.284847773 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 89814753 ps |
| CPU time | 0.94 seconds |
| Started | Aug 28 10:20:33 PM UTC 24 |
| Finished | Aug 28 10:20:35 PM UTC 24 |
| Peak memory | 225856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284847773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sparse_lc_gate_fsm.284847773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/3.rv_dm_sparse_lc_gate_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.1746276247 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 2197680596 ps |
| CPU time | 5.73 seconds |
| Started | Aug 28 10:20:33 PM UTC 24 |
| Finished | Aug 28 10:20:40 PM UTC 24 |
| Peak memory | 226392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746276247 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.1746276247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/3.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.29161233 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 64479767919 ps |
| CPU time | 116.84 seconds |
| Started | Aug 28 10:20:33 PM UTC 24 |
| Finished | Aug 28 10:22:32 PM UTC 24 |
| Peak memory | 243432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=29161233 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_ all_with_rand_reset.29161233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/30.rv_dm_alert_test.1587444424 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 99658252 ps |
| CPU time | 1.05 seconds |
| Started | Aug 28 10:21:15 PM UTC 24 |
| Finished | Aug 28 10:21:17 PM UTC 24 |
| Peak memory | 215880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587444424 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.1587444424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/30.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.2180880929 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 2544717430 ps |
| CPU time | 2.46 seconds |
| Started | Aug 28 10:21:15 PM UTC 24 |
| Finished | Aug 28 10:21:18 PM UTC 24 |
| Peak memory | 226304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180880929 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.2180880929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/30.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/31.rv_dm_alert_test.3829189614 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 115718260 ps |
| CPU time | 1.07 seconds |
| Started | Aug 28 10:21:15 PM UTC 24 |
| Finished | Aug 28 10:21:17 PM UTC 24 |
| Peak memory | 215880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829189614 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.3829189614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/31.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/32.rv_dm_alert_test.2001527615 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 38299174 ps |
| CPU time | 1.18 seconds |
| Started | Aug 28 10:21:15 PM UTC 24 |
| Finished | Aug 28 10:21:17 PM UTC 24 |
| Peak memory | 215880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001527615 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.2001527615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/32.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/32.rv_dm_stress_all.1869121777 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 10082531854 ps |
| CPU time | 19.59 seconds |
| Started | Aug 28 10:21:15 PM UTC 24 |
| Finished | Aug 28 10:21:36 PM UTC 24 |
| Peak memory | 216072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869121777 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.1869121777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/32.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/33.rv_dm_alert_test.1541109290 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 34928264 ps |
| CPU time | 0.94 seconds |
| Started | Aug 28 10:21:16 PM UTC 24 |
| Finished | Aug 28 10:21:18 PM UTC 24 |
| Peak memory | 215700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541109290 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.1541109290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/33.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.2315651878 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 10655482876 ps |
| CPU time | 8.22 seconds |
| Started | Aug 28 10:21:15 PM UTC 24 |
| Finished | Aug 28 10:21:24 PM UTC 24 |
| Peak memory | 216136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315651878 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.2315651878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/33.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/34.rv_dm_alert_test.2987559451 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 81718577 ps |
| CPU time | 1.62 seconds |
| Started | Aug 28 10:21:16 PM UTC 24 |
| Finished | Aug 28 10:21:19 PM UTC 24 |
| Peak memory | 215880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987559451 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.2987559451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/34.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/34.rv_dm_stress_all.2614970034 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 1929972429 ps |
| CPU time | 6.94 seconds |
| Started | Aug 28 10:21:16 PM UTC 24 |
| Finished | Aug 28 10:21:24 PM UTC 24 |
| Peak memory | 226380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614970034 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.2614970034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/34.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/35.rv_dm_alert_test.3724204138 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 77575835 ps |
| CPU time | 0.98 seconds |
| Started | Aug 28 10:21:16 PM UTC 24 |
| Finished | Aug 28 10:21:18 PM UTC 24 |
| Peak memory | 215880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724204138 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.3724204138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/35.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/35.rv_dm_stress_all.1351712552 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 4103419715 ps |
| CPU time | 11.77 seconds |
| Started | Aug 28 10:21:16 PM UTC 24 |
| Finished | Aug 28 10:21:29 PM UTC 24 |
| Peak memory | 226308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351712552 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.1351712552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/35.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/36.rv_dm_alert_test.455565080 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 61985959 ps |
| CPU time | 1.04 seconds |
| Started | Aug 28 10:21:17 PM UTC 24 |
| Finished | Aug 28 10:21:19 PM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455565080 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.455565080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/36.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/36.rv_dm_stress_all.3777268560 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 2757846023 ps |
| CPU time | 4.22 seconds |
| Started | Aug 28 10:21:17 PM UTC 24 |
| Finished | Aug 28 10:21:23 PM UTC 24 |
| Peak memory | 216200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777268560 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.3777268560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/36.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/37.rv_dm_alert_test.2119037256 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 115776674 ps |
| CPU time | 1.4 seconds |
| Started | Aug 28 10:21:17 PM UTC 24 |
| Finished | Aug 28 10:21:20 PM UTC 24 |
| Peak memory | 215880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119037256 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.2119037256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/37.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/37.rv_dm_stress_all.856150941 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 11764457476 ps |
| CPU time | 46.55 seconds |
| Started | Aug 28 10:21:17 PM UTC 24 |
| Finished | Aug 28 10:22:05 PM UTC 24 |
| Peak memory | 226316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856150941 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.856150941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/37.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/38.rv_dm_alert_test.3489026051 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 33460752 ps |
| CPU time | 1.17 seconds |
| Started | Aug 28 10:21:18 PM UTC 24 |
| Finished | Aug 28 10:21:20 PM UTC 24 |
| Peak memory | 215880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489026051 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.3489026051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/38.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/38.rv_dm_stress_all.3382148214 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 2605461438 ps |
| CPU time | 15.15 seconds |
| Started | Aug 28 10:21:18 PM UTC 24 |
| Finished | Aug 28 10:21:34 PM UTC 24 |
| Peak memory | 226384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382148214 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.3382148214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/38.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/39.rv_dm_alert_test.3779965381 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 71263342 ps |
| CPU time | 1.04 seconds |
| Started | Aug 28 10:21:19 PM UTC 24 |
| Finished | Aug 28 10:21:21 PM UTC 24 |
| Peak memory | 215880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779965381 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.3779965381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/39.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/39.rv_dm_stress_all.35353037 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 4624869661 ps |
| CPU time | 8.74 seconds |
| Started | Aug 28 10:21:19 PM UTC 24 |
| Finished | Aug 28 10:21:29 PM UTC 24 |
| Peak memory | 216084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35353037 -assert nopostproc +UVM_TESTNAME=rv_ dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.35353037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/39.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/4.rv_dm_alert_test.1907227391 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 162576846 ps |
| CPU time | 0.97 seconds |
| Started | Aug 28 10:20:42 PM UTC 24 |
| Finished | Aug 28 10:20:44 PM UTC 24 |
| Peak memory | 215936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907227391 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.1907227391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/4.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/4.rv_dm_bad_sba_tl_access.4123613067 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 7132156544 ps |
| CPU time | 21.35 seconds |
| Started | Aug 28 10:20:33 PM UTC 24 |
| Finished | Aug 28 10:20:56 PM UTC 24 |
| Peak memory | 226500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123613067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.4123613067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/4.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/4.rv_dm_buffered_enable.2484512612 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 273527521 ps |
| CPU time | 2.03 seconds |
| Started | Aug 28 10:20:42 PM UTC 24 |
| Finished | Aug 28 10:20:45 PM UTC 24 |
| Peak memory | 246208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484512612 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_buffered_enable.2484512612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/4.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.2341936273 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 14531313917 ps |
| CPU time | 51.88 seconds |
| Started | Aug 28 10:20:33 PM UTC 24 |
| Finished | Aug 28 10:21:27 PM UTC 24 |
| Peak memory | 226548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341936273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_tl_access.2341936273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/4.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.289948216 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 914259433 ps |
| CPU time | 3.09 seconds |
| Started | Aug 28 10:20:33 PM UTC 24 |
| Finished | Aug 28 10:20:38 PM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289948216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_halt_resume_whereto.289948216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/4.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.1217825606 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 196444927 ps |
| CPU time | 1.33 seconds |
| Started | Aug 28 10:20:33 PM UTC 24 |
| Finished | Aug 28 10:20:36 PM UTC 24 |
| Peak memory | 213460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217825606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.1217825606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/4.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/4.rv_dm_sba_tl_access.314399184 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 7732819021 ps |
| CPU time | 14.46 seconds |
| Started | Aug 28 10:20:33 PM UTC 24 |
| Finished | Aug 28 10:20:49 PM UTC 24 |
| Peak memory | 216276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314399184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.314399184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/4.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/4.rv_dm_sec_cm.1055239294 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 553311135 ps |
| CPU time | 1.98 seconds |
| Started | Aug 28 10:20:42 PM UTC 24 |
| Finished | Aug 28 10:20:45 PM UTC 24 |
| Peak memory | 255600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055239294 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.1055239294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/4.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.4120173128 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 3383329746 ps |
| CPU time | 18.26 seconds |
| Started | Aug 28 10:20:42 PM UTC 24 |
| Finished | Aug 28 10:21:02 PM UTC 24 |
| Peak memory | 226260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120173128 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.4120173128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/4.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.1522795765 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 15487233958 ps |
| CPU time | 64.11 seconds |
| Started | Aug 28 10:20:42 PM UTC 24 |
| Finished | Aug 28 10:21:48 PM UTC 24 |
| Peak memory | 233320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1522795765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stres s_all_with_rand_reset.1522795765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/40.rv_dm_alert_test.1547187391 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 59245558 ps |
| CPU time | 1.13 seconds |
| Started | Aug 28 10:21:19 PM UTC 24 |
| Finished | Aug 28 10:21:21 PM UTC 24 |
| Peak memory | 215700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547187391 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.1547187391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/40.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/40.rv_dm_stress_all.2250545421 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 2594249420 ps |
| CPU time | 4.6 seconds |
| Started | Aug 28 10:21:19 PM UTC 24 |
| Finished | Aug 28 10:21:24 PM UTC 24 |
| Peak memory | 216132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250545421 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.2250545421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/40.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/41.rv_dm_alert_test.3538573777 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 62243013 ps |
| CPU time | 0.99 seconds |
| Started | Aug 28 10:21:19 PM UTC 24 |
| Finished | Aug 28 10:21:21 PM UTC 24 |
| Peak memory | 215880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538573777 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.3538573777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/41.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/42.rv_dm_alert_test.1449349058 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 91945631 ps |
| CPU time | 1.05 seconds |
| Started | Aug 28 10:21:19 PM UTC 24 |
| Finished | Aug 28 10:21:21 PM UTC 24 |
| Peak memory | 215880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449349058 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.1449349058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/42.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/43.rv_dm_alert_test.1908323160 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 36990299 ps |
| CPU time | 1.04 seconds |
| Started | Aug 28 10:21:19 PM UTC 24 |
| Finished | Aug 28 10:21:21 PM UTC 24 |
| Peak memory | 215880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908323160 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.1908323160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/43.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/44.rv_dm_alert_test.914928714 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 46483112 ps |
| CPU time | 1.15 seconds |
| Started | Aug 28 10:21:21 PM UTC 24 |
| Finished | Aug 28 10:21:24 PM UTC 24 |
| Peak memory | 215940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914928714 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.914928714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/44.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.2315043520 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 6917382794 ps |
| CPU time | 28.21 seconds |
| Started | Aug 28 10:21:20 PM UTC 24 |
| Finished | Aug 28 10:21:50 PM UTC 24 |
| Peak memory | 216200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315043520 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.2315043520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/44.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/45.rv_dm_alert_test.4279571772 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 49606396 ps |
| CPU time | 1.11 seconds |
| Started | Aug 28 10:21:22 PM UTC 24 |
| Finished | Aug 28 10:21:24 PM UTC 24 |
| Peak memory | 215880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279571772 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.4279571772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/45.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/46.rv_dm_alert_test.2562865085 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 36400987 ps |
| CPU time | 0.95 seconds |
| Started | Aug 28 10:21:22 PM UTC 24 |
| Finished | Aug 28 10:21:24 PM UTC 24 |
| Peak memory | 215880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562865085 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.2562865085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/46.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.3104424229 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 3827449360 ps |
| CPU time | 12.95 seconds |
| Started | Aug 28 10:21:22 PM UTC 24 |
| Finished | Aug 28 10:21:36 PM UTC 24 |
| Peak memory | 226312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104424229 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.3104424229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/46.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/47.rv_dm_alert_test.1398693815 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 95479845 ps |
| CPU time | 1.08 seconds |
| Started | Aug 28 10:21:22 PM UTC 24 |
| Finished | Aug 28 10:21:24 PM UTC 24 |
| Peak memory | 215880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398693815 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.1398693815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/47.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/47.rv_dm_stress_all.3764465049 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 5637728113 ps |
| CPU time | 16.92 seconds |
| Started | Aug 28 10:21:22 PM UTC 24 |
| Finished | Aug 28 10:21:40 PM UTC 24 |
| Peak memory | 216124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764465049 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.3764465049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/47.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/48.rv_dm_alert_test.104457445 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 98580191 ps |
| CPU time | 1.06 seconds |
| Started | Aug 28 10:21:22 PM UTC 24 |
| Finished | Aug 28 10:21:24 PM UTC 24 |
| Peak memory | 215940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104457445 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.104457445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/48.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/48.rv_dm_stress_all.1074083586 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 4570197386 ps |
| CPU time | 14.48 seconds |
| Started | Aug 28 10:21:22 PM UTC 24 |
| Finished | Aug 28 10:21:37 PM UTC 24 |
| Peak memory | 216136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074083586 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.1074083586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/48.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/49.rv_dm_alert_test.3570433850 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 47402736 ps |
| CPU time | 1.07 seconds |
| Started | Aug 28 10:21:23 PM UTC 24 |
| Finished | Aug 28 10:21:25 PM UTC 24 |
| Peak memory | 215880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570433850 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.3570433850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/49.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/49.rv_dm_stress_all.446757108 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 4802443263 ps |
| CPU time | 5.52 seconds |
| Started | Aug 28 10:21:23 PM UTC 24 |
| Finished | Aug 28 10:21:30 PM UTC 24 |
| Peak memory | 216144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446757108 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.446757108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/49.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/5.rv_dm_alert_test.2182623495 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 81659489 ps |
| CPU time | 0.91 seconds |
| Started | Aug 28 10:20:42 PM UTC 24 |
| Finished | Aug 28 10:20:45 PM UTC 24 |
| Peak memory | 215940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182623495 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.2182623495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/5.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.1024661821 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 2857283449 ps |
| CPU time | 10.06 seconds |
| Started | Aug 28 10:20:42 PM UTC 24 |
| Finished | Aug 28 10:20:54 PM UTC 24 |
| Peak memory | 226556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024661821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.1024661821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/5.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.3818436948 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 3833928786 ps |
| CPU time | 17.68 seconds |
| Started | Aug 28 10:20:42 PM UTC 24 |
| Finished | Aug 28 10:21:02 PM UTC 24 |
| Peak memory | 226696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818436948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.3818436948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/5.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/5.rv_dm_buffered_enable.3999748458 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 219149042 ps |
| CPU time | 1.73 seconds |
| Started | Aug 28 10:20:42 PM UTC 24 |
| Finished | Aug 28 10:20:46 PM UTC 24 |
| Peak memory | 258632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999748458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_buffered_enable.3999748458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/5.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.788014502 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 3732577729 ps |
| CPU time | 13.8 seconds |
| Started | Aug 28 10:20:42 PM UTC 24 |
| Finished | Aug 28 10:20:57 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788014502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl_access.788014502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/5.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/5.rv_dm_halt_resume_whereto.778252864 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 302943767 ps |
| CPU time | 1.24 seconds |
| Started | Aug 28 10:20:42 PM UTC 24 |
| Finished | Aug 28 10:20:45 PM UTC 24 |
| Peak memory | 213340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778252864 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_halt_resume_whereto.778252864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/5.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/5.rv_dm_sba_tl_access.2032012587 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 10073271215 ps |
| CPU time | 7.18 seconds |
| Started | Aug 28 10:20:42 PM UTC 24 |
| Finished | Aug 28 10:20:51 PM UTC 24 |
| Peak memory | 226576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032012587 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.2032012587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/5.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.782853048 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 734618801 ps |
| CPU time | 4.36 seconds |
| Started | Aug 28 10:20:42 PM UTC 24 |
| Finished | Aug 28 10:20:48 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782853048 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.782853048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/5.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/6.rv_dm_alert_test.2010498524 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 40148801 ps |
| CPU time | 1.03 seconds |
| Started | Aug 28 10:20:43 PM UTC 24 |
| Finished | Aug 28 10:20:45 PM UTC 24 |
| Peak memory | 215940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010498524 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.2010498524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/6.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/6.rv_dm_autoincr_sba_tl_access.2087189698 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 11809899298 ps |
| CPU time | 47.64 seconds |
| Started | Aug 28 10:20:43 PM UTC 24 |
| Finished | Aug 28 10:21:32 PM UTC 24 |
| Peak memory | 228604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087189698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.2087189698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/6.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/6.rv_dm_bad_sba_tl_access.1435507255 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 4507609897 ps |
| CPU time | 8.33 seconds |
| Started | Aug 28 10:20:43 PM UTC 24 |
| Finished | Aug 28 10:20:52 PM UTC 24 |
| Peak memory | 226496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435507255 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.1435507255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/6.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/6.rv_dm_buffered_enable.789772210 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 328409751 ps |
| CPU time | 1.03 seconds |
| Started | Aug 28 10:20:43 PM UTC 24 |
| Finished | Aug 28 10:20:45 PM UTC 24 |
| Peak memory | 251696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789772210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_buffered_enable.789772210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/6.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.2759606584 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 1265460372 ps |
| CPU time | 8.22 seconds |
| Started | Aug 28 10:20:42 PM UTC 24 |
| Finished | Aug 28 10:20:52 PM UTC 24 |
| Peak memory | 216256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759606584 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_tl_access.2759606584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/6.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/6.rv_dm_halt_resume_whereto.2942039962 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 412379534 ps |
| CPU time | 1.14 seconds |
| Started | Aug 28 10:20:43 PM UTC 24 |
| Finished | Aug 28 10:20:45 PM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942039962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_halt_resume_whereto.2942039962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/6.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/6.rv_dm_sba_tl_access.1769802573 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 2824130829 ps |
| CPU time | 14.46 seconds |
| Started | Aug 28 10:20:42 PM UTC 24 |
| Finished | Aug 28 10:20:59 PM UTC 24 |
| Peak memory | 216120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769802573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.1769802573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/6.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all_with_rand_reset.769626160 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 13518549965 ps |
| CPU time | 60.31 seconds |
| Started | Aug 28 10:20:43 PM UTC 24 |
| Finished | Aug 28 10:21:45 PM UTC 24 |
| Peak memory | 233328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=769626160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress _all_with_rand_reset.769626160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/7.rv_dm_alert_test.4127206139 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 194385777 ps |
| CPU time | 1.1 seconds |
| Started | Aug 28 10:20:45 PM UTC 24 |
| Finished | Aug 28 10:20:48 PM UTC 24 |
| Peak memory | 215940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127206139 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.4127206139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/7.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.436488374 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 6650855958 ps |
| CPU time | 18.75 seconds |
| Started | Aug 28 10:20:43 PM UTC 24 |
| Finished | Aug 28 10:21:03 PM UTC 24 |
| Peak memory | 226688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436488374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.436488374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/7.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/7.rv_dm_buffered_enable.3629300373 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 205736841 ps |
| CPU time | 1.16 seconds |
| Started | Aug 28 10:20:43 PM UTC 24 |
| Finished | Aug 28 10:20:46 PM UTC 24 |
| Peak memory | 257180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629300373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_buffered_enable.3629300373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/7.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.1733106273 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 1145453435 ps |
| CPU time | 2.71 seconds |
| Started | Aug 28 10:20:43 PM UTC 24 |
| Finished | Aug 28 10:20:47 PM UTC 24 |
| Peak memory | 216244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733106273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_tl_access.1733106273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/7.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.1857833441 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 241275567 ps |
| CPU time | 0.87 seconds |
| Started | Aug 28 10:20:43 PM UTC 24 |
| Finished | Aug 28 10:20:45 PM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857833441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_halt_resume_whereto.1857833441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/7.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/7.rv_dm_sba_tl_access.1883788629 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 6005287949 ps |
| CPU time | 23.61 seconds |
| Started | Aug 28 10:20:43 PM UTC 24 |
| Finished | Aug 28 10:21:08 PM UTC 24 |
| Peak memory | 216328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883788629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.1883788629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/7.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all.4052622240 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 1220188721 ps |
| CPU time | 2.81 seconds |
| Started | Aug 28 10:20:44 PM UTC 24 |
| Finished | Aug 28 10:20:48 PM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052622240 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.4052622240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/7.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.296609496 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 8983551597 ps |
| CPU time | 70.03 seconds |
| Started | Aug 28 10:20:44 PM UTC 24 |
| Finished | Aug 28 10:21:56 PM UTC 24 |
| Peak memory | 243480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=296609496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress _all_with_rand_reset.296609496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/8.rv_dm_alert_test.459362486 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 142796587 ps |
| CPU time | 0.93 seconds |
| Started | Aug 28 10:20:47 PM UTC 24 |
| Finished | Aug 28 10:20:49 PM UTC 24 |
| Peak memory | 215936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459362486 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.459362486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/8.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.4245687602 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 26880111337 ps |
| CPU time | 74.48 seconds |
| Started | Aug 28 10:20:47 PM UTC 24 |
| Finished | Aug 28 10:22:03 PM UTC 24 |
| Peak memory | 226436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245687602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.4245687602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/8.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/8.rv_dm_bad_sba_tl_access.111956270 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 2092601726 ps |
| CPU time | 9.05 seconds |
| Started | Aug 28 10:20:47 PM UTC 24 |
| Finished | Aug 28 10:20:57 PM UTC 24 |
| Peak memory | 226448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111956270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.111956270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/8.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/8.rv_dm_buffered_enable.3063523036 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 483834371 ps |
| CPU time | 2.5 seconds |
| Started | Aug 28 10:20:47 PM UTC 24 |
| Finished | Aug 28 10:20:50 PM UTC 24 |
| Peak memory | 252672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063523036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_buffered_enable.3063523036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/8.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.38619622 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 11922321070 ps |
| CPU time | 19.44 seconds |
| Started | Aug 28 10:20:45 PM UTC 24 |
| Finished | Aug 28 10:21:06 PM UTC 24 |
| Peak memory | 226436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38619622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl_access.38619622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/8.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/8.rv_dm_sba_tl_access.2129437905 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 1594644873 ps |
| CPU time | 4.12 seconds |
| Started | Aug 28 10:20:45 PM UTC 24 |
| Finished | Aug 28 10:20:51 PM UTC 24 |
| Peak memory | 216260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129437905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.2129437905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/8.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.4048423541 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 1781683151 ps |
| CPU time | 7.53 seconds |
| Started | Aug 28 10:20:47 PM UTC 24 |
| Finished | Aug 28 10:20:55 PM UTC 24 |
| Peak memory | 226248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048423541 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.4048423541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/8.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.782946975 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 3028654624 ps |
| CPU time | 49.92 seconds |
| Started | Aug 28 10:20:47 PM UTC 24 |
| Finished | Aug 28 10:21:38 PM UTC 24 |
| Peak memory | 233328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=782946975 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress _all_with_rand_reset.782946975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.455483746 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 125759936 ps |
| CPU time | 1.77 seconds |
| Started | Aug 28 10:20:48 PM UTC 24 |
| Finished | Aug 28 10:20:51 PM UTC 24 |
| Peak memory | 215936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455483746 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.455483746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/9.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/9.rv_dm_autoincr_sba_tl_access.1003807071 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 28528762975 ps |
| CPU time | 9.5 seconds |
| Started | Aug 28 10:20:47 PM UTC 24 |
| Finished | Aug 28 10:20:58 PM UTC 24 |
| Peak memory | 226696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003807071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.1003807071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/9.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.3396010824 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 3113736583 ps |
| CPU time | 5.27 seconds |
| Started | Aug 28 10:20:47 PM UTC 24 |
| Finished | Aug 28 10:20:53 PM UTC 24 |
| Peak memory | 226500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396010824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.3396010824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/9.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/9.rv_dm_buffered_enable.2957889094 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 286971809 ps |
| CPU time | 1.52 seconds |
| Started | Aug 28 10:20:47 PM UTC 24 |
| Finished | Aug 28 10:20:50 PM UTC 24 |
| Peak memory | 256220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957889094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_buffered_enable.2957889094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/9.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.3940498407 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 7620191704 ps |
| CPU time | 25.14 seconds |
| Started | Aug 28 10:20:47 PM UTC 24 |
| Finished | Aug 28 10:21:13 PM UTC 24 |
| Peak memory | 226492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940498407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_tl_access.3940498407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/9.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.3420658165 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 2626579797 ps |
| CPU time | 10.8 seconds |
| Started | Aug 28 10:20:47 PM UTC 24 |
| Finished | Aug 28 10:20:59 PM UTC 24 |
| Peak memory | 216328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420658165 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.3420658165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/9.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.3515151691 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 4383795887 ps |
| CPU time | 17.52 seconds |
| Started | Aug 28 10:20:48 PM UTC 24 |
| Finished | Aug 28 10:21:07 PM UTC 24 |
| Peak memory | 226312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515151691 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.3515151691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/9.rv_dm_stress_all/latest |
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