Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.83 96.32 89.96 92.10 93.33 90.44 98.63 61.04


Total tests in report: 482
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
54.71 54.71 83.98 83.98 51.20 51.20 45.00 45.00 44.00 44.00 63.31 63.31 93.17 93.17 2.33 2.33 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_tl_access.366170637
65.22 10.51 86.10 2.12 62.94 11.74 50.46 5.46 53.33 9.33 71.16 7.85 94.43 1.26 38.13 35.80 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.2860537682
72.80 7.58 89.92 3.83 72.70 9.76 71.09 20.63 60.00 6.67 79.01 7.85 95.58 1.16 41.29 3.16 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.2572161934
76.35 3.55 90.83 0.91 75.53 2.83 74.20 3.11 74.67 14.67 81.23 2.22 96.00 0.42 41.98 0.69 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.3871296165
78.60 2.25 91.08 0.25 75.67 0.14 74.54 0.34 80.00 5.33 81.57 0.34 96.00 0.00 51.30 9.33 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.3190243538
80.50 1.91 92.09 1.01 77.37 1.70 80.63 6.09 82.67 2.67 83.45 1.88 96.00 0.00 51.30 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.3326933569
81.64 1.13 92.29 0.20 77.93 0.57 83.11 2.48 86.67 4.00 83.79 0.34 96.21 0.21 51.44 0.14 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.802217245
82.50 0.86 93.55 1.26 79.92 1.98 83.70 0.59 86.67 0.00 85.49 1.71 96.42 0.21 51.71 0.27 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.4049283954
83.28 0.79 93.65 0.10 81.47 1.56 84.03 0.34 86.67 0.00 86.01 0.51 96.42 0.00 54.73 3.02 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3019189601
84.05 0.76 94.11 0.45 83.17 1.70 86.30 2.27 86.67 0.00 86.52 0.51 96.42 0.00 55.14 0.41 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.3162867789
84.66 0.61 94.41 0.30 84.44 1.27 87.18 0.88 86.67 0.00 87.37 0.85 96.42 0.00 56.10 0.96 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/4.rv_dm_autoincr_sba_tl_access.526183422
85.13 0.47 94.41 0.00 84.44 0.00 90.46 3.28 86.67 0.00 87.37 0.00 96.42 0.00 56.10 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_autoincr_sba_tl_access.166076874
85.53 0.40 94.61 0.20 84.87 0.42 90.84 0.38 88.00 1.33 87.71 0.34 96.42 0.00 56.24 0.14 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.750441322
85.91 0.38 94.61 0.00 84.87 0.00 90.84 0.00 90.67 2.67 87.71 0.00 96.42 0.00 56.24 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.651076510
86.23 0.32 94.61 0.00 87.13 2.26 90.84 0.00 90.67 0.00 87.71 0.00 96.42 0.00 56.24 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.1428481820
86.54 0.31 95.21 0.60 87.98 0.85 90.92 0.08 90.67 0.00 88.23 0.51 96.42 0.00 56.38 0.14 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/31.rv_dm_stress_all.2456630097
86.77 0.22 95.72 0.50 88.26 0.28 90.92 0.00 90.67 0.00 88.74 0.51 96.42 0.00 56.65 0.27 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all.289360199
86.98 0.21 95.72 0.00 88.26 0.00 90.92 0.00 90.67 0.00 88.74 0.00 97.90 1.47 56.65 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.473404815
87.18 0.20 95.72 0.00 88.68 0.42 91.51 0.59 90.67 0.00 88.74 0.00 98.00 0.11 56.93 0.27 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.3982556581
87.37 0.19 95.72 0.00 88.68 0.00 91.51 0.00 92.00 1.33 88.74 0.00 98.00 0.00 56.93 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3718513161
87.56 0.19 95.72 0.00 88.68 0.00 91.51 0.00 93.33 1.33 88.74 0.00 98.00 0.00 56.93 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.3815535449
87.73 0.17 95.97 0.25 88.83 0.14 91.68 0.17 93.33 0.00 89.25 0.51 98.00 0.00 57.06 0.14 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.3174937521
87.87 0.14 95.97 0.00 88.83 0.00 91.68 0.00 93.33 0.00 89.25 0.00 98.00 0.00 58.02 0.96 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3041268628
87.98 0.11 96.02 0.05 88.97 0.14 91.68 0.00 93.33 0.00 89.42 0.17 98.00 0.00 58.44 0.41 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/42.rv_dm_stress_all.3292130302
88.08 0.10 96.07 0.05 89.11 0.14 91.68 0.00 93.33 0.00 89.76 0.34 98.00 0.00 58.57 0.14 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.4102050230
88.16 0.09 96.22 0.15 89.25 0.14 91.68 0.00 93.33 0.00 89.93 0.17 98.00 0.00 58.71 0.14 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/41.rv_dm_stress_all.2627090581
88.24 0.08 96.22 0.00 89.25 0.00 91.68 0.00 93.33 0.00 89.93 0.00 98.00 0.00 59.26 0.55 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/16.rv_dm_autoincr_sba_tl_access.171965507
88.30 0.06 96.22 0.00 89.39 0.14 91.68 0.00 93.33 0.00 90.10 0.17 98.00 0.00 59.40 0.14 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.923598115
88.36 0.06 96.22 0.00 89.39 0.00 91.68 0.00 93.33 0.00 90.10 0.00 98.00 0.00 59.81 0.41 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.2050765568
88.41 0.05 96.22 0.00 89.39 0.00 91.89 0.21 93.33 0.00 90.10 0.00 98.00 0.00 59.95 0.14 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/17.rv_dm_autoincr_sba_tl_access.1744385639
88.45 0.04 96.22 0.00 89.67 0.28 91.89 0.00 93.33 0.00 90.10 0.00 98.00 0.00 59.95 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/43.rv_dm_stress_all.3076282560
88.49 0.04 96.22 0.00 89.67 0.00 91.89 0.00 93.33 0.00 90.10 0.00 98.00 0.00 60.22 0.27 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1621063502
88.53 0.04 96.22 0.00 89.67 0.00 91.89 0.00 93.33 0.00 90.10 0.00 98.00 0.00 60.49 0.27 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/45.rv_dm_stress_all.7315209
88.56 0.03 96.27 0.05 89.67 0.00 91.89 0.00 93.33 0.00 90.27 0.17 98.00 0.00 60.49 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1466624237
88.59 0.03 96.32 0.05 89.67 0.00 91.89 0.00 93.33 0.00 90.44 0.17 98.00 0.00 60.49 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.836499136
88.62 0.03 96.32 0.00 89.67 0.00 91.89 0.00 93.33 0.00 90.44 0.00 98.21 0.21 60.49 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1591562039
88.65 0.03 96.32 0.00 89.67 0.00 91.89 0.00 93.33 0.00 90.44 0.00 98.42 0.21 60.49 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3703870698
88.68 0.03 96.32 0.00 89.82 0.14 91.93 0.04 93.33 0.00 90.44 0.00 98.42 0.00 60.49 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.3989187357
88.70 0.02 96.32 0.00 89.96 0.14 91.93 0.00 93.33 0.00 90.44 0.00 98.42 0.00 60.49 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2494991659
88.72 0.02 96.32 0.00 89.96 0.00 91.93 0.00 93.33 0.00 90.44 0.00 98.42 0.00 60.63 0.14 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3281092864
88.74 0.02 96.32 0.00 89.96 0.00 91.93 0.00 93.33 0.00 90.44 0.00 98.42 0.00 60.77 0.14 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3502621762
88.76 0.02 96.32 0.00 89.96 0.00 91.93 0.00 93.33 0.00 90.44 0.00 98.42 0.00 60.91 0.14 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1379197356
88.78 0.02 96.32 0.00 89.96 0.00 91.93 0.00 93.33 0.00 90.44 0.00 98.42 0.00 61.04 0.14 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.4199922672
88.79 0.02 96.32 0.00 89.96 0.00 91.93 0.00 93.33 0.00 90.44 0.00 98.53 0.11 61.04 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.119784072
88.81 0.02 96.32 0.00 89.96 0.00 91.93 0.00 93.33 0.00 90.44 0.00 98.63 0.11 61.04 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.3832758513
88.82 0.01 96.32 0.00 89.96 0.00 92.02 0.08 93.33 0.00 90.44 0.00 98.63 0.00 61.04 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2444385703
88.83 0.01 96.32 0.00 89.96 0.00 92.10 0.08 93.33 0.00 90.44 0.00 98.63 0.00 61.04 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_alert_test.240987015

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1823341804
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.422996980
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1055359229
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.213290930
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.2301885567
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.538700153
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.368057439
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.923535342
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2695045930
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2547535305
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3580461315
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3205392206
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.4005904183
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.1384315637
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.2168811832
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.2751044524
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4249900715
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2850089425
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2317734512
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.731982287
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1897923701
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.4025013864
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.718684004
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1478561070
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.94475724
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2083823277
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2858433828
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.761708863
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3912868973
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.500818112
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.1015885220
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2300241832
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.2801661502
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.343271280
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.3913404578
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.248953187
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2657011098
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1048939385
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2224337411
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.1476122172
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.98118105
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_rw.3127222205
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2494541552
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.405422869
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.790174333
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1739880324
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_errors.2973406082
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.256610185
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_rw.1606304605
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2073537334
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/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.3515151691



Total test records in report: 482
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.190837853 Aug 28 10:20:02 PM UTC 24 Aug 28 10:20:05 PM UTC 24 124986604 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_tl_access.366170637 Aug 28 10:20:02 PM UTC 24 Aug 28 10:20:05 PM UTC 24 1083765804 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_busy.1627943201 Aug 28 10:20:02 PM UTC 24 Aug 28 10:20:06 PM UTC 24 395345971 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_halted.3266614427 Aug 28 10:20:04 PM UTC 24 Aug 28 10:20:06 PM UTC 24 115562365 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_hart_unavail.394948620 Aug 28 10:20:04 PM UTC 24 Aug 28 10:20:06 PM UTC 24 203641840 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_resuming.177082664 Aug 28 10:20:04 PM UTC 24 Aug 28 10:20:07 PM UTC 24 662528050 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_dataaddr_rw_access.3819486566 Aug 28 10:20:06 PM UTC 24 Aug 28 10:20:08 PM UTC 24 120262039 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.1616106764 Aug 28 10:20:06 PM UTC 24 Aug 28 10:20:08 PM UTC 24 521106625 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.3989187357 Aug 28 10:20:05 PM UTC 24 Aug 28 10:20:08 PM UTC 24 377099887 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.2572161934 Aug 28 10:20:32 PM UTC 24 Aug 28 10:20:35 PM UTC 24 218358251 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.189070212 Aug 28 10:20:02 PM UTC 24 Aug 28 10:20:09 PM UTC 24 788409098 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_idle_hint.2384174513 Aug 28 10:20:07 PM UTC 24 Aug 28 10:20:09 PM UTC 24 248181894 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1493171088 Aug 28 10:20:07 PM UTC 24 Aug 28 10:20:10 PM UTC 24 692948490 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.2222244945 Aug 28 10:20:07 PM UTC 24 Aug 28 10:20:10 PM UTC 24 801036133 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.3871296165 Aug 28 10:20:02 PM UTC 24 Aug 28 10:20:10 PM UTC 24 4134042740 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.4259569604 Aug 28 10:20:02 PM UTC 24 Aug 28 10:20:11 PM UTC 24 1906494420 ps
T91 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_debug_disabled.140699563 Aug 28 10:20:09 PM UTC 24 Aug 28 10:20:12 PM UTC 24 41407634 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.4102050230 Aug 28 10:20:09 PM UTC 24 Aug 28 10:20:12 PM UTC 24 91138820 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.836499136 Aug 28 10:20:09 PM UTC 24 Aug 28 10:20:12 PM UTC 24 77213609 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2288428435 Aug 28 10:20:09 PM UTC 24 Aug 28 10:20:12 PM UTC 24 310985406 ps
T78 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.750441322 Aug 28 10:20:10 PM UTC 24 Aug 28 10:20:12 PM UTC 24 204183610 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.4090102021 Aug 28 10:20:09 PM UTC 24 Aug 28 10:20:12 PM UTC 24 185727918 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.1428481820 Aug 28 10:20:11 PM UTC 24 Aug 28 10:20:13 PM UTC 24 57570630 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_hartsel_warl.700822474 Aug 28 10:20:11 PM UTC 24 Aug 28 10:20:13 PM UTC 24 67293740 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.119784072 Aug 28 10:20:11 PM UTC 24 Aug 28 10:20:13 PM UTC 24 150090969 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.3162867789 Aug 28 10:20:11 PM UTC 24 Aug 28 10:20:13 PM UTC 24 32038033 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.802217245 Aug 28 10:20:11 PM UTC 24 Aug 28 10:20:14 PM UTC 24 344680891 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_smoke.4006589238 Aug 28 10:20:11 PM UTC 24 Aug 28 10:20:14 PM UTC 24 609566233 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_smoke.2176387114 Aug 28 10:20:02 PM UTC 24 Aug 28 10:20:15 PM UTC 24 2200226501 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.1775067635 Aug 28 10:20:09 PM UTC 24 Aug 28 10:20:15 PM UTC 24 467635950 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_halted.3013365982 Aug 28 10:20:13 PM UTC 24 Aug 28 10:20:15 PM UTC 24 81712426 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.3174937521 Aug 28 10:20:13 PM UTC 24 Aug 28 10:20:15 PM UTC 24 451547632 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_busy.2038418212 Aug 28 10:20:13 PM UTC 24 Aug 28 10:20:15 PM UTC 24 309644849 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.4049283954 Aug 28 10:20:11 PM UTC 24 Aug 28 10:20:16 PM UTC 24 4074754370 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_hart_unavail.81853827 Aug 28 10:20:14 PM UTC 24 Aug 28 10:20:16 PM UTC 24 54759784 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.3326933569 Aug 28 10:20:07 PM UTC 24 Aug 28 10:20:16 PM UTC 24 4975268008 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_dataaddr_rw_access.4228386351 Aug 28 10:20:14 PM UTC 24 Aug 28 10:20:16 PM UTC 24 97628453 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_not_supported.4205857379 Aug 28 10:20:13 PM UTC 24 Aug 28 10:20:17 PM UTC 24 791266292 ps
T133 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_resuming.3136275091 Aug 28 10:20:14 PM UTC 24 Aug 28 10:20:17 PM UTC 24 664190135 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_halt_resume_whereto.1637628786 Aug 28 10:20:14 PM UTC 24 Aug 28 10:20:17 PM UTC 24 833585658 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.4211365942 Aug 28 10:20:15 PM UTC 24 Aug 28 10:20:18 PM UTC 24 135125045 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_idle_hint.2960802988 Aug 28 10:20:15 PM UTC 24 Aug 28 10:20:18 PM UTC 24 683104044 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.256882959 Aug 28 10:20:14 PM UTC 24 Aug 28 10:20:18 PM UTC 24 3079200661 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_ndmreset_req.1737629502 Aug 28 10:20:15 PM UTC 24 Aug 28 10:20:18 PM UTC 24 700023711 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.2028381578 Aug 28 10:20:02 PM UTC 24 Aug 28 10:20:19 PM UTC 24 4804223424 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_rom_read_access.2468060430 Aug 28 10:20:17 PM UTC 24 Aug 28 10:20:19 PM UTC 24 34142324 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_abstractcmd_status.1582578646 Aug 28 10:20:16 PM UTC 24 Aug 28 10:20:19 PM UTC 24 515181655 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_progbuf_read_write_execute.12525660 Aug 28 10:20:17 PM UTC 24 Aug 28 10:20:19 PM UTC 24 355682963 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1672054646 Aug 28 10:20:15 PM UTC 24 Aug 28 10:20:19 PM UTC 24 2281916318 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_debug_disabled.1205603166 Aug 28 10:20:18 PM UTC 24 Aug 28 10:20:20 PM UTC 24 64129048 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.3832758513 Aug 28 10:20:18 PM UTC 24 Aug 28 10:20:20 PM UTC 24 71197746 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_buffered_enable.2670906447 Aug 28 10:20:18 PM UTC 24 Aug 28 10:20:20 PM UTC 24 88929514 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.2593698828 Aug 28 10:20:11 PM UTC 24 Aug 28 10:20:20 PM UTC 24 2354556955 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_sec_cm.2669266925 Aug 28 10:20:18 PM UTC 24 Aug 28 10:20:21 PM UTC 24 556199456 ps
T79 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.3815535449 Aug 28 10:20:18 PM UTC 24 Aug 28 10:20:21 PM UTC 24 398696291 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3880187866 Aug 28 10:20:16 PM UTC 24 Aug 28 10:20:22 PM UTC 24 629178974 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_tl_access.31800561 Aug 28 10:20:12 PM UTC 24 Aug 28 10:20:23 PM UTC 24 2754932587 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.148075217 Aug 28 10:20:18 PM UTC 24 Aug 28 10:20:26 PM UTC 24 2080029368 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_debug_disabled.3574367234 Aug 28 10:20:15 PM UTC 24 Aug 28 10:20:30 PM UTC 24 2638604015 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2164684918 Aug 28 10:20:02 PM UTC 24 Aug 28 10:20:31 PM UTC 24 6645293786 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.1746276247 Aug 28 10:20:33 PM UTC 24 Aug 28 10:20:40 PM UTC 24 2197680596 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_alert_test.240987015 Aug 28 10:20:32 PM UTC 24 Aug 28 10:20:34 PM UTC 24 106407532 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.3684929813 Aug 28 10:20:32 PM UTC 24 Aug 28 10:20:34 PM UTC 24 76415800 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.3851707381 Aug 28 10:20:33 PM UTC 24 Aug 28 10:20:34 PM UTC 24 204285683 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/3.rv_dm_hart_unavail.4191061712 Aug 28 10:20:33 PM UTC 24 Aug 28 10:20:35 PM UTC 24 139172414 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.1653410699 Aug 28 10:20:32 PM UTC 24 Aug 28 10:20:35 PM UTC 24 122371349 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.284847773 Aug 28 10:20:33 PM UTC 24 Aug 28 10:20:35 PM UTC 24 89814753 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.3984308923 Aug 28 10:20:33 PM UTC 24 Aug 28 10:20:35 PM UTC 24 47612924 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/2.rv_dm_sparse_lc_gate_fsm.2234715487 Aug 28 10:20:32 PM UTC 24 Aug 28 10:20:35 PM UTC 24 287308629 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.1217825606 Aug 28 10:20:33 PM UTC 24 Aug 28 10:20:36 PM UTC 24 196444927 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.1031702914 Aug 28 10:20:33 PM UTC 24 Aug 28 10:20:36 PM UTC 24 456858333 ps
T123 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.1003049059 Aug 28 10:20:33 PM UTC 24 Aug 28 10:20:36 PM UTC 24 452948958 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.3070632382 Aug 28 10:20:32 PM UTC 24 Aug 28 10:20:36 PM UTC 24 3962107224 ps
T124 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_bad_sba_tl_access.4080556619 Aug 28 10:20:12 PM UTC 24 Aug 28 10:20:36 PM UTC 24 7880977505 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.3982556581 Aug 28 10:20:32 PM UTC 24 Aug 28 10:20:37 PM UTC 24 2529419489 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/3.rv_dm_sec_cm.3610925223 Aug 28 10:20:33 PM UTC 24 Aug 28 10:20:37 PM UTC 24 684915463 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.289948216 Aug 28 10:20:33 PM UTC 24 Aug 28 10:20:38 PM UTC 24 914259433 ps
T144 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.3569435634 Aug 28 10:20:12 PM UTC 24 Aug 28 10:20:38 PM UTC 24 6894256450 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.418431251 Aug 28 10:20:33 PM UTC 24 Aug 28 10:20:38 PM UTC 24 1135175839 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.4094789621 Aug 28 10:20:32 PM UTC 24 Aug 28 10:20:40 PM UTC 24 2661173101 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.1828286436 Aug 28 10:20:33 PM UTC 24 Aug 28 10:20:42 PM UTC 24 4723653820 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.2238058738 Aug 28 10:20:32 PM UTC 24 Aug 28 10:20:43 PM UTC 24 4133412300 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/4.rv_dm_alert_test.1907227391 Aug 28 10:20:42 PM UTC 24 Aug 28 10:20:44 PM UTC 24 162576846 ps
T176 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/5.rv_dm_alert_test.2182623495 Aug 28 10:20:42 PM UTC 24 Aug 28 10:20:45 PM UTC 24 81659489 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/5.rv_dm_halt_resume_whereto.778252864 Aug 28 10:20:42 PM UTC 24 Aug 28 10:20:45 PM UTC 24 302943767 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/4.rv_dm_autoincr_sba_tl_access.526183422 Aug 28 10:20:33 PM UTC 24 Aug 28 10:20:45 PM UTC 24 5774096499 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/6.rv_dm_halt_resume_whereto.2942039962 Aug 28 10:20:43 PM UTC 24 Aug 28 10:20:45 PM UTC 24 412379534 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/6.rv_dm_buffered_enable.789772210 Aug 28 10:20:43 PM UTC 24 Aug 28 10:20:45 PM UTC 24 328409751 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/6.rv_dm_alert_test.2010498524 Aug 28 10:20:43 PM UTC 24 Aug 28 10:20:45 PM UTC 24 40148801 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.1665478385 Aug 28 10:20:32 PM UTC 24 Aug 28 10:20:45 PM UTC 24 6363661721 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/4.rv_dm_buffered_enable.2484512612 Aug 28 10:20:42 PM UTC 24 Aug 28 10:20:45 PM UTC 24 273527521 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.1857833441 Aug 28 10:20:43 PM UTC 24 Aug 28 10:20:45 PM UTC 24 241275567 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/4.rv_dm_sec_cm.1055239294 Aug 28 10:20:42 PM UTC 24 Aug 28 10:20:45 PM UTC 24 553311135 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/7.rv_dm_buffered_enable.3629300373 Aug 28 10:20:43 PM UTC 24 Aug 28 10:20:46 PM UTC 24 205736841 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/5.rv_dm_buffered_enable.3999748458 Aug 28 10:20:42 PM UTC 24 Aug 28 10:20:46 PM UTC 24 219149042 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.646369625 Aug 28 10:20:49 PM UTC 24 Aug 28 10:21:09 PM UTC 24 3778994239 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.1733106273 Aug 28 10:20:43 PM UTC 24 Aug 28 10:20:47 PM UTC 24 1145453435 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/7.rv_dm_alert_test.4127206139 Aug 28 10:20:45 PM UTC 24 Aug 28 10:20:48 PM UTC 24 194385777 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all.289360199 Aug 28 10:20:43 PM UTC 24 Aug 28 10:20:48 PM UTC 24 1855048591 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all.4052622240 Aug 28 10:20:44 PM UTC 24 Aug 28 10:20:48 PM UTC 24 1220188721 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.782853048 Aug 28 10:20:42 PM UTC 24 Aug 28 10:20:48 PM UTC 24 734618801 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/18.rv_dm_alert_test.3995646471 Aug 28 10:21:07 PM UTC 24 Aug 28 10:21:09 PM UTC 24 32604522 ps
T232 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/8.rv_dm_alert_test.459362486 Aug 28 10:20:47 PM UTC 24 Aug 28 10:20:49 PM UTC 24 142796587 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/4.rv_dm_sba_tl_access.314399184 Aug 28 10:20:33 PM UTC 24 Aug 28 10:20:49 PM UTC 24 7732819021 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/9.rv_dm_buffered_enable.2957889094 Aug 28 10:20:47 PM UTC 24 Aug 28 10:20:50 PM UTC 24 286971809 ps
T77 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/8.rv_dm_buffered_enable.3063523036 Aug 28 10:20:47 PM UTC 24 Aug 28 10:20:50 PM UTC 24 483834371 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/8.rv_dm_sba_tl_access.2129437905 Aug 28 10:20:45 PM UTC 24 Aug 28 10:20:51 PM UTC 24 1594644873 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/5.rv_dm_sba_tl_access.2032012587 Aug 28 10:20:42 PM UTC 24 Aug 28 10:20:51 PM UTC 24 10073271215 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.455483746 Aug 28 10:20:48 PM UTC 24 Aug 28 10:20:51 PM UTC 24 125759936 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/10.rv_dm_alert_test.2108271722 Aug 28 10:20:50 PM UTC 24 Aug 28 10:20:52 PM UTC 24 42687242 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.2759606584 Aug 28 10:20:42 PM UTC 24 Aug 28 10:20:52 PM UTC 24 1265460372 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/6.rv_dm_bad_sba_tl_access.1435507255 Aug 28 10:20:43 PM UTC 24 Aug 28 10:20:52 PM UTC 24 4507609897 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/10.rv_dm_sba_tl_access.1045207155 Aug 28 10:20:49 PM UTC 24 Aug 28 10:20:53 PM UTC 24 833204218 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.3396010824 Aug 28 10:20:47 PM UTC 24 Aug 28 10:20:53 PM UTC 24 3113736583 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.1024661821 Aug 28 10:20:42 PM UTC 24 Aug 28 10:20:54 PM UTC 24 2857283449 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/11.rv_dm_bad_sba_tl_access.3992875270 Aug 28 10:20:52 PM UTC 24 Aug 28 10:20:55 PM UTC 24 1149913046 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.4048423541 Aug 28 10:20:47 PM UTC 24 Aug 28 10:20:55 PM UTC 24 1781683151 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/11.rv_dm_alert_test.2182998196 Aug 28 10:20:53 PM UTC 24 Aug 28 10:20:55 PM UTC 24 112775036 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/4.rv_dm_bad_sba_tl_access.4123613067 Aug 28 10:20:33 PM UTC 24 Aug 28 10:20:56 PM UTC 24 7132156544 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.2860537682 Aug 28 10:20:11 PM UTC 24 Aug 28 10:20:56 PM UTC 24 2744016872 ps
T125 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/8.rv_dm_bad_sba_tl_access.111956270 Aug 28 10:20:47 PM UTC 24 Aug 28 10:20:57 PM UTC 24 2092601726 ps
T126 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.788014502 Aug 28 10:20:42 PM UTC 24 Aug 28 10:20:57 PM UTC 24 3732577729 ps
T127 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/9.rv_dm_autoincr_sba_tl_access.1003807071 Aug 28 10:20:47 PM UTC 24 Aug 28 10:20:58 PM UTC 24 28528762975 ps
T128 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/12.rv_dm_alert_test.746041186 Aug 28 10:20:56 PM UTC 24 Aug 28 10:20:58 PM UTC 24 106646022 ps
T129 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.4019565813 Aug 28 10:20:53 PM UTC 24 Aug 28 10:20:58 PM UTC 24 2380880256 ps
T130 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/6.rv_dm_sba_tl_access.1769802573 Aug 28 10:20:42 PM UTC 24 Aug 28 10:20:59 PM UTC 24 2824130829 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all.3831462074 Aug 28 10:20:32 PM UTC 24 Aug 28 10:20:58 PM UTC 24 7749393196 ps
T131 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.3420658165 Aug 28 10:20:47 PM UTC 24 Aug 28 10:20:59 PM UTC 24 2626579797 ps
T132 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/12.rv_dm_sba_tl_access.3344916438 Aug 28 10:20:53 PM UTC 24 Aug 28 10:20:59 PM UTC 24 1358277192 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/13.rv_dm_alert_test.1317031919 Aug 28 10:20:58 PM UTC 24 Aug 28 10:21:00 PM UTC 24 132910820 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/11.rv_dm_stress_all.3253978807 Aug 28 10:20:52 PM UTC 24 Aug 28 10:21:00 PM UTC 24 2588528152 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/12.rv_dm_bad_sba_tl_access.1427090897 Aug 28 10:20:54 PM UTC 24 Aug 28 10:21:01 PM UTC 24 1848229168 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/11.rv_dm_sba_tl_access.884162544 Aug 28 10:20:51 PM UTC 24 Aug 28 10:21:01 PM UTC 24 2897630207 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/14.rv_dm_sba_tl_access.97071906 Aug 28 10:20:58 PM UTC 24 Aug 28 10:21:01 PM UTC 24 1507342892 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/10.rv_dm_stress_all.3794837148 Aug 28 10:20:50 PM UTC 24 Aug 28 10:21:02 PM UTC 24 2299605320 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.3818436948 Aug 28 10:20:42 PM UTC 24 Aug 28 10:21:02 PM UTC 24 3833928786 ps
T228 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.4120173128 Aug 28 10:20:42 PM UTC 24 Aug 28 10:21:02 PM UTC 24 3383329746 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/12.rv_dm_stress_all.279556791 Aug 28 10:20:55 PM UTC 24 Aug 28 10:21:02 PM UTC 24 1630462812 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1700057599 Aug 28 10:20:33 PM UTC 24 Aug 28 10:21:03 PM UTC 24 12154664792 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/13.rv_dm_stress_all.2747259082 Aug 28 10:20:57 PM UTC 24 Aug 28 10:21:03 PM UTC 24 4165841847 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.436488374 Aug 28 10:20:43 PM UTC 24 Aug 28 10:21:03 PM UTC 24 6650855958 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/13.rv_dm_bad_sba_tl_access.770094918 Aug 28 10:20:57 PM UTC 24 Aug 28 10:21:04 PM UTC 24 1746806132 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/14.rv_dm_alert_test.3882346263 Aug 28 10:21:02 PM UTC 24 Aug 28 10:21:05 PM UTC 24 52390568 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/15.rv_dm_alert_test.586890780 Aug 28 10:21:03 PM UTC 24 Aug 28 10:21:05 PM UTC 24 42031012 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/13.rv_dm_autoincr_sba_tl_access.2909760809 Aug 28 10:20:57 PM UTC 24 Aug 28 10:21:05 PM UTC 24 1175609061 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.3229192319 Aug 28 10:20:57 PM UTC 24 Aug 28 10:21:05 PM UTC 24 2596951146 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/15.rv_dm_bad_sba_tl_access.4283349972 Aug 28 10:21:02 PM UTC 24 Aug 28 10:21:06 PM UTC 24 792684732 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.38619622 Aug 28 10:20:45 PM UTC 24 Aug 28 10:21:06 PM UTC 24 11922321070 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.40715674 Aug 28 10:20:33 PM UTC 24 Aug 28 10:21:06 PM UTC 24 9716609591 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/16.rv_dm_alert_test.343929763 Aug 28 10:21:04 PM UTC 24 Aug 28 10:21:07 PM UTC 24 155706036 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.3515151691 Aug 28 10:20:48 PM UTC 24 Aug 28 10:21:07 PM UTC 24 4383795887 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/15.rv_dm_stress_all.4265468543 Aug 28 10:21:03 PM UTC 24 Aug 28 10:21:07 PM UTC 24 1591872906 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/16.rv_dm_stress_all.1754210592 Aug 28 10:21:03 PM UTC 24 Aug 28 10:21:08 PM UTC 24 1721037835 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/17.rv_dm_alert_test.1611174973 Aug 28 10:21:05 PM UTC 24 Aug 28 10:21:08 PM UTC 24 119008183 ps
T227 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/11.rv_dm_autoincr_sba_tl_access.441216383 Aug 28 10:20:52 PM UTC 24 Aug 28 10:21:08 PM UTC 24 4276424357 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/7.rv_dm_sba_tl_access.1883788629 Aug 28 10:20:43 PM UTC 24 Aug 28 10:21:08 PM UTC 24 6005287949 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.3018927376 Aug 28 10:20:58 PM UTC 24 Aug 28 10:21:08 PM UTC 24 1896391571 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/10.rv_dm_autoincr_sba_tl_access.3100650536 Aug 28 10:20:50 PM UTC 24 Aug 28 10:21:08 PM UTC 24 6535097051 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/15.rv_dm_sba_tl_access.652141305 Aug 28 10:21:02 PM UTC 24 Aug 28 10:21:09 PM UTC 24 5079229214 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/16.rv_dm_bad_sba_tl_access.2779596886 Aug 28 10:21:03 PM UTC 24 Aug 28 10:21:10 PM UTC 24 1513593359 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/16.rv_dm_autoincr_sba_tl_access.171965507 Aug 28 10:21:03 PM UTC 24 Aug 28 10:21:10 PM UTC 24 2960452418 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/10.rv_dm_bad_sba_tl_access.1973452508 Aug 28 10:20:50 PM UTC 24 Aug 28 10:21:10 PM UTC 24 4544383117 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/19.rv_dm_alert_test.1849724834 Aug 28 10:21:09 PM UTC 24 Aug 28 10:21:11 PM UTC 24 59650079 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/20.rv_dm_alert_test.2157413933 Aug 28 10:21:09 PM UTC 24 Aug 28 10:21:12 PM UTC 24 64384934 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/21.rv_dm_alert_test.1476021949 Aug 28 10:21:09 PM UTC 24 Aug 28 10:21:12 PM UTC 24 144281423 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/18.rv_dm_stress_all.2352117141 Aug 28 10:21:07 PM UTC 24 Aug 28 10:21:12 PM UTC 24 1871263516 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/22.rv_dm_alert_test.3206067697 Aug 28 10:21:10 PM UTC 24 Aug 28 10:21:12 PM UTC 24 103234167 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.1819113776 Aug 28 10:21:08 PM UTC 24 Aug 28 10:21:12 PM UTC 24 4286504577 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/18.rv_dm_bad_sba_tl_access.1239421279 Aug 28 10:21:07 PM UTC 24 Aug 28 10:21:12 PM UTC 24 3648402830 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.3789840566 Aug 28 10:20:51 PM UTC 24 Aug 28 10:21:13 PM UTC 24 16735552153 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/23.rv_dm_alert_test.2166754383 Aug 28 10:21:11 PM UTC 24 Aug 28 10:21:13 PM UTC 24 56026213 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.3940498407 Aug 28 10:20:47 PM UTC 24 Aug 28 10:21:13 PM UTC 24 7620191704 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2758172895 Aug 28 10:21:08 PM UTC 24 Aug 28 10:21:13 PM UTC 24 3116559597 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/24.rv_dm_alert_test.2095000766 Aug 28 10:21:12 PM UTC 24 Aug 28 10:21:14 PM UTC 24 80707022 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/16.rv_dm_sba_tl_access.721606804 Aug 28 10:21:03 PM UTC 24 Aug 28 10:21:14 PM UTC 24 6914925638 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.1486940574 Aug 28 10:21:06 PM UTC 24 Aug 28 10:21:14 PM UTC 24 6895354897 ps
T225 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/17.rv_dm_stress_all.490985663 Aug 28 10:21:05 PM UTC 24 Aug 28 10:21:14 PM UTC 24 1918526929 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/21.rv_dm_stress_all.3481873229 Aug 28 10:21:09 PM UTC 24 Aug 28 10:21:14 PM UTC 24 1078526583 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/25.rv_dm_alert_test.3042681416 Aug 28 10:21:13 PM UTC 24 Aug 28 10:21:15 PM UTC 24 44995317 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/26.rv_dm_alert_test.1134346487 Aug 28 10:21:13 PM UTC 24 Aug 28 10:21:15 PM UTC 24 51800273 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/28.rv_dm_alert_test.971476609 Aug 28 10:21:13 PM UTC 24 Aug 28 10:21:16 PM UTC 24 59712661 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/27.rv_dm_alert_test.1575053248 Aug 28 10:21:13 PM UTC 24 Aug 28 10:21:16 PM UTC 24 56391289 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/29.rv_dm_alert_test.2275353156 Aug 28 10:21:13 PM UTC 24 Aug 28 10:21:16 PM UTC 24 54755616 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/14.rv_dm_autoincr_sba_tl_access.3669041938 Aug 28 10:21:02 PM UTC 24 Aug 28 10:21:16 PM UTC 24 1965789016 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/24.rv_dm_stress_all.1533386263 Aug 28 10:21:11 PM UTC 24 Aug 28 10:21:16 PM UTC 24 2830040813 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/30.rv_dm_alert_test.1587444424 Aug 28 10:21:15 PM UTC 24 Aug 28 10:21:17 PM UTC 24 99658252 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/14.rv_dm_stress_all.2472023808 Aug 28 10:21:02 PM UTC 24 Aug 28 10:21:17 PM UTC 24 2707622555 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/31.rv_dm_alert_test.3829189614 Aug 28 10:21:15 PM UTC 24 Aug 28 10:21:17 PM UTC 24 115718260 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/32.rv_dm_alert_test.2001527615 Aug 28 10:21:15 PM UTC 24 Aug 28 10:21:17 PM UTC 24 38299174 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/29.rv_dm_stress_all.1609868825 Aug 28 10:21:13 PM UTC 24 Aug 28 10:21:17 PM UTC 24 1220245729 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.4199922672 Aug 28 10:21:09 PM UTC 24 Aug 28 10:21:17 PM UTC 24 3427325370 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/19.rv_dm_sba_tl_access.2762096076 Aug 28 10:21:08 PM UTC 24 Aug 28 10:21:17 PM UTC 24 1329624068 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/19.rv_dm_bad_sba_tl_access.2982262594 Aug 28 10:21:08 PM UTC 24 Aug 28 10:21:18 PM UTC 24 1649879426 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/15.rv_dm_autoincr_sba_tl_access.3104308971 Aug 28 10:21:03 PM UTC 24 Aug 28 10:21:18 PM UTC 24 12671756575 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/49.rv_dm_stress_all.446757108 Aug 28 10:21:23 PM UTC 24 Aug 28 10:21:30 PM UTC 24 4802443263 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/33.rv_dm_alert_test.1541109290 Aug 28 10:21:16 PM UTC 24 Aug 28 10:21:18 PM UTC 24 34928264 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/23.rv_dm_stress_all.3385617068 Aug 28 10:21:11 PM UTC 24 Aug 28 10:21:18 PM UTC 24 2196235774 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/18.rv_dm_autoincr_sba_tl_access.2526403089 Aug 28 10:21:07 PM UTC 24 Aug 28 10:21:18 PM UTC 24 2252651558 ps
T80 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.2180880929 Aug 28 10:21:15 PM UTC 24 Aug 28 10:21:18 PM UTC 24 2544717430 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/35.rv_dm_alert_test.3724204138 Aug 28 10:21:16 PM UTC 24 Aug 28 10:21:18 PM UTC 24 77575835 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/34.rv_dm_alert_test.2987559451 Aug 28 10:21:16 PM UTC 24 Aug 28 10:21:19 PM UTC 24 81718577 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.2050765568 Aug 28 10:20:43 PM UTC 24 Aug 28 10:21:19 PM UTC 24 10971303978 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.2586208798 Aug 28 10:21:08 PM UTC 24 Aug 28 10:21:19 PM UTC 24 4609688438 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.715403701 Aug 28 10:21:13 PM UTC 24 Aug 28 10:21:19 PM UTC 24 2559584551 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/18.rv_dm_sba_tl_access.1526099542 Aug 28 10:21:05 PM UTC 24 Aug 28 10:21:19 PM UTC 24 5145452384 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/36.rv_dm_alert_test.455565080 Aug 28 10:21:17 PM UTC 24 Aug 28 10:21:19 PM UTC 24 61985959 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/38.rv_dm_alert_test.3489026051 Aug 28 10:21:18 PM UTC 24 Aug 28 10:21:20 PM UTC 24 33460752 ps
T307 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.1529340550 Aug 28 10:21:03 PM UTC 24 Aug 28 10:21:20 PM UTC 24 2670536758 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/37.rv_dm_alert_test.2119037256 Aug 28 10:21:17 PM UTC 24 Aug 28 10:21:20 PM UTC 24 115776674 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/17.rv_dm_autoincr_sba_tl_access.1744385639 Aug 28 10:21:04 PM UTC 24 Aug 28 10:21:20 PM UTC 24 6261983985 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/31.rv_dm_stress_all.2456630097 Aug 28 10:21:15 PM UTC 24 Aug 28 10:21:20 PM UTC 24 1687739454 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/39.rv_dm_alert_test.3779965381 Aug 28 10:21:19 PM UTC 24 Aug 28 10:21:21 PM UTC 24 71263342 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.2462372688 Aug 28 10:20:18 PM UTC 24 Aug 28 10:21:21 PM UTC 24 43252948694 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/40.rv_dm_alert_test.1547187391 Aug 28 10:21:19 PM UTC 24 Aug 28 10:21:21 PM UTC 24 59245558 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/41.rv_dm_alert_test.3538573777 Aug 28 10:21:19 PM UTC 24 Aug 28 10:21:21 PM UTC 24 62243013 ps
T309 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/42.rv_dm_alert_test.1449349058 Aug 28 10:21:19 PM UTC 24 Aug 28 10:21:21 PM UTC 24 91945631 ps
T310 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/43.rv_dm_alert_test.1908323160 Aug 28 10:21:19 PM UTC 24 Aug 28 10:21:21 PM UTC 24 36990299 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/17.rv_dm_sba_tl_access.335526287 Aug 28 10:21:04 PM UTC 24 Aug 28 10:21:22 PM UTC 24 9956268989 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.393211925 Aug 28 10:21:12 PM UTC 24 Aug 28 10:21:22 PM UTC 24 4459116668 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/36.rv_dm_stress_all.3777268560 Aug 28 10:21:17 PM UTC 24 Aug 28 10:21:23 PM UTC 24 2757846023 ps
T311 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/44.rv_dm_alert_test.914928714 Aug 28 10:21:21 PM UTC 24 Aug 28 10:21:24 PM UTC 24 46483112 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/46.rv_dm_alert_test.2562865085 Aug 28 10:21:22 PM UTC 24 Aug 28 10:21:24 PM UTC 24 36400987 ps
T312 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/45.rv_dm_alert_test.4279571772 Aug 28 10:21:22 PM UTC 24 Aug 28 10:21:24 PM UTC 24 49606396 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/47.rv_dm_alert_test.1398693815 Aug 28 10:21:22 PM UTC 24 Aug 28 10:21:24 PM UTC 24 95479845 ps
T314 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/48.rv_dm_alert_test.104457445 Aug 28 10:21:22 PM UTC 24 Aug 28 10:21:24 PM UTC 24 98580191 ps
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T222 /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.2315651878 Aug 28 10:21:15 PM UTC 24 Aug 28 10:21:24 PM UTC 24 10655482876 ps
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