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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.10 96.32 89.53 92.10 93.33 90.44 98.63 56.31


Total test records in report: 483
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T324 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/49.rv_dm_stress_all.1863458202 Sep 01 09:43:44 AM UTC 24 Sep 01 09:43:49 AM UTC 24 2219963602 ps
T325 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/45.rv_dm_stress_all.3010061248 Sep 01 09:43:43 AM UTC 24 Sep 01 09:43:52 AM UTC 24 3826721828 ps
T326 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/43.rv_dm_stress_all.3624501930 Sep 01 09:43:40 AM UTC 24 Sep 01 09:43:52 AM UTC 24 4191678193 ps
T327 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.103544776 Sep 01 09:43:43 AM UTC 24 Sep 01 09:43:59 AM UTC 24 3783278314 ps
T328 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/48.rv_dm_stress_all.2553730617 Sep 01 09:43:44 AM UTC 24 Sep 01 09:44:00 AM UTC 24 7185191657 ps
T329 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/16.rv_dm_autoincr_sba_tl_access.4155412970 Sep 01 09:43:03 AM UTC 24 Sep 01 09:44:04 AM UTC 24 16899447139 ps
T112 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.3533858676 Sep 01 09:41:50 AM UTC 24 Sep 01 09:44:12 AM UTC 24 9255922923 ps
T330 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.1699000995 Sep 01 09:43:41 AM UTC 24 Sep 01 09:44:15 AM UTC 24 8026444357 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all_with_rand_reset.419497605 Sep 01 09:42:10 AM UTC 24 Sep 01 09:44:17 AM UTC 24 4023517476 ps
T331 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.1149133879 Sep 01 09:42:22 AM UTC 24 Sep 01 09:44:36 AM UTC 24 40143757460 ps
T332 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/14.rv_dm_autoincr_sba_tl_access.668463283 Sep 01 09:42:51 AM UTC 24 Sep 01 09:44:45 AM UTC 24 23434179152 ps
T333 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.3894952985 Sep 01 09:43:16 AM UTC 24 Sep 01 09:46:05 AM UTC 24 24162587347 ps
T334 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/11.rv_dm_autoincr_sba_tl_access.1734956336 Sep 01 09:42:39 AM UTC 24 Sep 01 09:51:36 AM UTC 24 128256923612 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.4259395637 Sep 01 09:02:31 AM UTC 24 Sep 01 09:02:35 AM UTC 24 490994521 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.917186096 Sep 01 09:02:32 AM UTC 24 Sep 01 09:02:35 AM UTC 24 270515546 ps
T133 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2387132008 Sep 01 09:02:32 AM UTC 24 Sep 01 09:02:36 AM UTC 24 1905139179 ps
T335 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.220594176 Sep 01 09:02:33 AM UTC 24 Sep 01 09:02:36 AM UTC 24 145968927 ps
T336 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2412608107 Sep 01 09:02:36 AM UTC 24 Sep 01 09:02:38 AM UTC 24 30216357 ps
T337 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.1723717464 Sep 01 09:02:35 AM UTC 24 Sep 01 09:02:38 AM UTC 24 82119871 ps
T338 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3710066521 Sep 01 09:02:32 AM UTC 24 Sep 01 09:02:38 AM UTC 24 2301336209 ps
T119 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.66836134 Sep 01 09:02:37 AM UTC 24 Sep 01 09:02:39 AM UTC 24 243374854 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1029803924 Sep 01 09:02:32 AM UTC 24 Sep 01 09:02:40 AM UTC 24 1354681035 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.63469713 Sep 01 09:02:36 AM UTC 24 Sep 01 09:02:40 AM UTC 24 478640413 ps
T339 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3640978723 Sep 01 09:02:38 AM UTC 24 Sep 01 09:02:41 AM UTC 24 572190984 ps
T340 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3808195341 Sep 01 09:02:38 AM UTC 24 Sep 01 09:02:41 AM UTC 24 222798235 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.152406551 Sep 01 09:02:37 AM UTC 24 Sep 01 09:02:41 AM UTC 24 80753128 ps
T341 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1553245947 Sep 01 09:02:39 AM UTC 24 Sep 01 09:02:41 AM UTC 24 34900774 ps
T342 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2791317085 Sep 01 09:02:38 AM UTC 24 Sep 01 09:02:42 AM UTC 24 331845581 ps
T343 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.4156738551 Sep 01 09:02:41 AM UTC 24 Sep 01 09:02:43 AM UTC 24 47560655 ps
T344 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1804574485 Sep 01 09:02:32 AM UTC 24 Sep 01 09:02:43 AM UTC 24 2316342467 ps
T345 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.26649566 Sep 01 09:02:41 AM UTC 24 Sep 01 09:02:43 AM UTC 24 131116369 ps
T121 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.513338114 Sep 01 09:02:41 AM UTC 24 Sep 01 09:02:44 AM UTC 24 97957876 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.504233467 Sep 01 09:02:38 AM UTC 24 Sep 01 09:02:45 AM UTC 24 3086818512 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.639465968 Sep 01 09:02:42 AM UTC 24 Sep 01 09:02:45 AM UTC 24 161119076 ps
T123 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2984537468 Sep 01 09:02:37 AM UTC 24 Sep 01 09:02:45 AM UTC 24 1624891605 ps
T346 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2594859642 Sep 01 09:02:43 AM UTC 24 Sep 01 09:02:45 AM UTC 24 273406393 ps
T347 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2110893258 Sep 01 09:02:43 AM UTC 24 Sep 01 09:02:46 AM UTC 24 352816456 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1236747645 Sep 01 09:02:42 AM UTC 24 Sep 01 09:02:46 AM UTC 24 80538692 ps
T348 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.907507625 Sep 01 09:02:41 AM UTC 24 Sep 01 09:02:48 AM UTC 24 121350496 ps
T349 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_walk.3731718446 Sep 01 09:02:47 AM UTC 24 Sep 01 09:02:49 AM UTC 24 37391223 ps
T350 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3612035946 Sep 01 09:02:47 AM UTC 24 Sep 01 09:02:49 AM UTC 24 58606027 ps
T351 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3846885102 Sep 01 09:02:45 AM UTC 24 Sep 01 09:02:51 AM UTC 24 859866745 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.4226669976 Sep 01 09:02:34 AM UTC 24 Sep 01 09:02:51 AM UTC 24 1641173121 ps
T352 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1975581545 Sep 01 09:02:45 AM UTC 24 Sep 01 09:02:51 AM UTC 24 1110879955 ps
T353 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.772284820 Sep 01 09:02:39 AM UTC 24 Sep 01 09:02:52 AM UTC 24 3906799607 ps
T354 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_errors.19919240 Sep 01 09:02:47 AM UTC 24 Sep 01 09:02:52 AM UTC 24 212412040 ps
T124 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1979950010 Sep 01 09:02:49 AM UTC 24 Sep 01 09:02:52 AM UTC 24 221188906 ps
T125 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2090291898 Sep 01 09:02:42 AM UTC 24 Sep 01 09:02:53 AM UTC 24 757919535 ps
T126 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_rw.3175864478 Sep 01 09:02:50 AM UTC 24 Sep 01 09:02:53 AM UTC 24 101919678 ps
T355 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3115156024 Sep 01 09:02:52 AM UTC 24 Sep 01 09:02:54 AM UTC 24 475029691 ps
T356 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3257881339 Sep 01 09:02:52 AM UTC 24 Sep 01 09:02:54 AM UTC 24 120491000 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1439488912 Sep 01 09:02:51 AM UTC 24 Sep 01 09:02:55 AM UTC 24 180695955 ps
T357 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.4179932882 Sep 01 09:02:53 AM UTC 24 Sep 01 09:02:55 AM UTC 24 607392426 ps
T358 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_walk.140102290 Sep 01 09:02:55 AM UTC 24 Sep 01 09:02:57 AM UTC 24 68337598 ps
T359 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3671439708 Sep 01 09:02:55 AM UTC 24 Sep 01 09:02:57 AM UTC 24 76536260 ps
T360 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3852049812 Sep 01 09:02:38 AM UTC 24 Sep 01 09:02:58 AM UTC 24 3497678172 ps
T361 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3007860148 Sep 01 09:02:44 AM UTC 24 Sep 01 09:02:58 AM UTC 24 6306013646 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3927117847 Sep 01 09:02:45 AM UTC 24 Sep 01 09:02:58 AM UTC 24 11001452504 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1263372133 Sep 01 09:02:53 AM UTC 24 Sep 01 09:03:00 AM UTC 24 2626385178 ps
T362 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3430183459 Sep 01 09:02:52 AM UTC 24 Sep 01 09:03:00 AM UTC 24 6201900170 ps
T127 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3917862640 Sep 01 09:02:56 AM UTC 24 Sep 01 09:03:01 AM UTC 24 345276643 ps
T363 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3525426649 Sep 01 09:02:40 AM UTC 24 Sep 01 09:03:01 AM UTC 24 19683575321 ps
T364 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2836876306 Sep 01 09:02:59 AM UTC 24 Sep 01 09:03:02 AM UTC 24 367685243 ps
T128 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2530685168 Sep 01 09:02:50 AM UTC 24 Sep 01 09:03:02 AM UTC 24 925419457 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_rw.1337362931 Sep 01 09:02:58 AM UTC 24 Sep 01 09:03:02 AM UTC 24 270019395 ps
T365 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_errors.619852885 Sep 01 09:02:54 AM UTC 24 Sep 01 09:03:02 AM UTC 24 291154485 ps
T366 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2082125268 Sep 01 09:03:00 AM UTC 24 Sep 01 09:03:02 AM UTC 24 189133937 ps
T367 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.458554087 Sep 01 09:02:59 AM UTC 24 Sep 01 09:03:03 AM UTC 24 57988897 ps
T368 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1443175616 Sep 01 09:03:01 AM UTC 24 Sep 01 09:03:04 AM UTC 24 1143896843 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.4017570224 Sep 01 09:02:41 AM UTC 24 Sep 01 09:03:05 AM UTC 24 5213804383 ps
T369 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_walk.496623599 Sep 01 09:03:04 AM UTC 24 Sep 01 09:03:06 AM UTC 24 36960832 ps
T370 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_partial_access.973771264 Sep 01 09:03:04 AM UTC 24 Sep 01 09:03:06 AM UTC 24 114737819 ps
T371 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2561080311 Sep 01 09:02:53 AM UTC 24 Sep 01 09:03:07 AM UTC 24 3672659116 ps
T372 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1185040028 Sep 01 09:02:54 AM UTC 24 Sep 01 09:03:07 AM UTC 24 21593440412 ps
T139 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_rw.841024292 Sep 01 09:03:05 AM UTC 24 Sep 01 09:03:08 AM UTC 24 41320353 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_errors.2508485428 Sep 01 09:03:02 AM UTC 24 Sep 01 09:03:08 AM UTC 24 1147875413 ps
T140 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2263365933 Sep 01 09:03:04 AM UTC 24 Sep 01 09:03:08 AM UTC 24 226297579 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3872573581 Sep 01 09:03:04 AM UTC 24 Sep 01 09:03:16 AM UTC 24 3494571696 ps
T373 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.172972326 Sep 01 09:03:01 AM UTC 24 Sep 01 09:03:09 AM UTC 24 5955018222 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2489274277 Sep 01 09:02:59 AM UTC 24 Sep 01 09:03:10 AM UTC 24 1714958345 ps
T374 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3090785299 Sep 01 09:03:07 AM UTC 24 Sep 01 09:03:10 AM UTC 24 207592817 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2052959430 Sep 01 09:03:07 AM UTC 24 Sep 01 09:03:11 AM UTC 24 100396147 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2876318280 Sep 01 09:03:06 AM UTC 24 Sep 01 09:03:12 AM UTC 24 184130732 ps
T375 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_errors.761069943 Sep 01 09:03:08 AM UTC 24 Sep 01 09:03:12 AM UTC 24 129236159 ps
T376 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3567097752 Sep 01 09:02:46 AM UTC 24 Sep 01 09:03:12 AM UTC 24 7025210517 ps
T377 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1025442546 Sep 01 09:03:10 AM UTC 24 Sep 01 09:03:13 AM UTC 24 801869147 ps
T378 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.872404299 Sep 01 09:03:10 AM UTC 24 Sep 01 09:03:13 AM UTC 24 53297552 ps
T379 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.690439417 Sep 01 09:02:53 AM UTC 24 Sep 01 09:03:13 AM UTC 24 11830821344 ps
T142 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_rw.1819701950 Sep 01 09:03:10 AM UTC 24 Sep 01 09:03:14 AM UTC 24 463229494 ps
T380 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_errors.2896655813 Sep 01 09:03:11 AM UTC 24 Sep 01 09:03:14 AM UTC 24 67011028 ps
T143 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3972140383 Sep 01 09:02:37 AM UTC 24 Sep 01 09:03:15 AM UTC 24 4216271519 ps
T381 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1654379636 Sep 01 09:03:00 AM UTC 24 Sep 01 09:03:16 AM UTC 24 16889477279 ps
T144 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3964415141 Sep 01 09:02:37 AM UTC 24 Sep 01 09:03:16 AM UTC 24 39691889448 ps
T382 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2107061836 Sep 01 09:03:13 AM UTC 24 Sep 01 09:03:16 AM UTC 24 77700361 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_rw.1420759347 Sep 01 09:03:12 AM UTC 24 Sep 01 09:03:16 AM UTC 24 83175727 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1327877551 Sep 01 09:03:10 AM UTC 24 Sep 01 09:03:17 AM UTC 24 1128353358 ps
T383 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3423661815 Sep 01 09:03:14 AM UTC 24 Sep 01 09:03:17 AM UTC 24 160865907 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3925549278 Sep 01 09:02:47 AM UTC 24 Sep 01 09:03:19 AM UTC 24 7584336743 ps
T384 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.575056841 Sep 01 09:03:02 AM UTC 24 Sep 01 09:03:19 AM UTC 24 22452092587 ps
T385 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3175556056 Sep 01 09:03:17 AM UTC 24 Sep 01 09:03:20 AM UTC 24 171986237 ps
T386 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_rw.565211272 Sep 01 09:03:17 AM UTC 24 Sep 01 09:03:20 AM UTC 24 124703699 ps
T387 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3505752372 Sep 01 09:03:17 AM UTC 24 Sep 01 09:03:21 AM UTC 24 212591680 ps
T388 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_errors.756136796 Sep 01 09:03:16 AM UTC 24 Sep 01 09:03:21 AM UTC 24 499714759 ps
T389 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1725294070 Sep 01 09:03:10 AM UTC 24 Sep 01 09:03:21 AM UTC 24 10849130911 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3852737518 Sep 01 09:03:01 AM UTC 24 Sep 01 09:03:22 AM UTC 24 5931928756 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.213859218 Sep 01 09:03:13 AM UTC 24 Sep 01 09:03:22 AM UTC 24 330908056 ps
T390 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_rw.3117787189 Sep 01 09:03:19 AM UTC 24 Sep 01 09:03:22 AM UTC 24 66244647 ps
T391 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.292964680 Sep 01 09:03:14 AM UTC 24 Sep 01 09:03:23 AM UTC 24 6124710816 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3724883889 Sep 01 09:02:55 AM UTC 24 Sep 01 09:03:23 AM UTC 24 1845939196 ps
T392 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1505131573 Sep 01 09:03:17 AM UTC 24 Sep 01 09:03:24 AM UTC 24 1848372593 ps
T393 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_errors.3779612146 Sep 01 09:03:18 AM UTC 24 Sep 01 09:03:24 AM UTC 24 599012250 ps
T394 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.3161974241 Sep 01 09:03:18 AM UTC 24 Sep 01 09:03:24 AM UTC 24 3268586739 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.318178707 Sep 01 09:03:17 AM UTC 24 Sep 01 09:03:24 AM UTC 24 375682611 ps
T210 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3230499661 Sep 01 09:03:12 AM UTC 24 Sep 01 09:03:24 AM UTC 24 679693085 ps
T395 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.661435544 Sep 01 09:03:07 AM UTC 24 Sep 01 09:03:25 AM UTC 24 14289135433 ps
T396 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.6585403 Sep 01 09:03:22 AM UTC 24 Sep 01 09:03:25 AM UTC 24 490756848 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2910512866 Sep 01 09:02:52 AM UTC 24 Sep 01 09:03:26 AM UTC 24 2372982523 ps
T397 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.4139533653 Sep 01 09:02:32 AM UTC 24 Sep 01 09:03:26 AM UTC 24 32389837499 ps
T398 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.792647908 Sep 01 09:03:21 AM UTC 24 Sep 01 09:03:26 AM UTC 24 98114469 ps
T399 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2038500222 Sep 01 09:02:50 AM UTC 24 Sep 01 09:03:26 AM UTC 24 781654932 ps
T400 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_errors.2903391464 Sep 01 09:03:23 AM UTC 24 Sep 01 09:03:26 AM UTC 24 164597320 ps
T401 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1890028646 Sep 01 09:03:24 AM UTC 24 Sep 01 09:03:27 AM UTC 24 197004258 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3405083959 Sep 01 09:03:10 AM UTC 24 Sep 01 09:03:27 AM UTC 24 2146595429 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_rw.2932807745 Sep 01 09:03:23 AM UTC 24 Sep 01 09:03:27 AM UTC 24 142074165 ps
T402 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1319361729 Sep 01 09:03:24 AM UTC 24 Sep 01 09:03:28 AM UTC 24 2637294079 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.1801942160 Sep 01 09:03:26 AM UTC 24 Sep 01 09:03:28 AM UTC 24 59078889 ps
T403 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.582499414 Sep 01 09:03:24 AM UTC 24 Sep 01 09:03:29 AM UTC 24 87636182 ps
T404 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2913766543 Sep 01 09:03:27 AM UTC 24 Sep 01 09:03:30 AM UTC 24 226785072 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.848306612 Sep 01 09:03:20 AM UTC 24 Sep 01 09:03:30 AM UTC 24 1103806093 ps
T405 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_rw.4217960869 Sep 01 09:03:27 AM UTC 24 Sep 01 09:03:30 AM UTC 24 596190985 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_intg_err.4175929622 Sep 01 09:03:16 AM UTC 24 Sep 01 09:03:30 AM UTC 24 1629875526 ps
T406 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3327273499 Sep 01 09:03:28 AM UTC 24 Sep 01 09:03:31 AM UTC 24 126660988 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2897813271 Sep 01 09:03:26 AM UTC 24 Sep 01 09:03:31 AM UTC 24 272100158 ps
T407 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.959362462 Sep 01 09:03:27 AM UTC 24 Sep 01 09:03:31 AM UTC 24 2535873148 ps
T408 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.916353292 Sep 01 09:02:40 AM UTC 24 Sep 01 09:03:31 AM UTC 24 4498342390 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.4204370690 Sep 01 09:03:26 AM UTC 24 Sep 01 09:03:32 AM UTC 24 176008056 ps
T409 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_errors.1022459703 Sep 01 09:03:27 AM UTC 24 Sep 01 09:03:32 AM UTC 24 316109105 ps
T410 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1090880475 Sep 01 09:03:22 AM UTC 24 Sep 01 09:03:32 AM UTC 24 1630950662 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3755088203 Sep 01 09:03:19 AM UTC 24 Sep 01 09:03:33 AM UTC 24 1325540507 ps
T411 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2383822350 Sep 01 09:03:31 AM UTC 24 Sep 01 09:03:33 AM UTC 24 167276264 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.671385670 Sep 01 09:03:24 AM UTC 24 Sep 01 09:03:33 AM UTC 24 732476585 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3699002890 Sep 01 09:03:28 AM UTC 24 Sep 01 09:03:33 AM UTC 24 201930463 ps
T412 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.4194294585 Sep 01 09:03:22 AM UTC 24 Sep 01 09:03:33 AM UTC 24 8946501740 ps
T413 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_rw.654931082 Sep 01 09:03:30 AM UTC 24 Sep 01 09:03:34 AM UTC 24 102945394 ps
T414 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.1446952265 Sep 01 09:03:25 AM UTC 24 Sep 01 09:03:34 AM UTC 24 291839103 ps
T415 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3491746640 Sep 01 09:03:31 AM UTC 24 Sep 01 09:03:34 AM UTC 24 52050948 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2509728373 Sep 01 09:03:28 AM UTC 24 Sep 01 09:03:35 AM UTC 24 244645426 ps
T416 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_errors.207355507 Sep 01 09:03:29 AM UTC 24 Sep 01 09:03:35 AM UTC 24 136567497 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3038102097 Sep 01 09:03:22 AM UTC 24 Sep 01 09:03:37 AM UTC 24 3206788649 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_rw.2187937267 Sep 01 09:03:32 AM UTC 24 Sep 01 09:03:37 AM UTC 24 189133984 ps
T417 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.4048699505 Sep 01 09:03:33 AM UTC 24 Sep 01 09:03:37 AM UTC 24 486435323 ps
T418 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1308293270 Sep 01 09:03:33 AM UTC 24 Sep 01 09:03:37 AM UTC 24 352170798 ps
T419 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.304744802 Sep 01 09:03:06 AM UTC 24 Sep 01 09:03:38 AM UTC 24 2892567275 ps
T420 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_errors.259283939 Sep 01 09:03:32 AM UTC 24 Sep 01 09:03:38 AM UTC 24 251578416 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_aliasing.920662998 Sep 01 09:02:59 AM UTC 24 Sep 01 09:03:39 AM UTC 24 3502778780 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1589787688 Sep 01 09:03:27 AM UTC 24 Sep 01 09:03:39 AM UTC 24 2347275914 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_rw.855385900 Sep 01 09:03:35 AM UTC 24 Sep 01 09:03:39 AM UTC 24 151205806 ps
T421 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.924527169 Sep 01 09:03:36 AM UTC 24 Sep 01 09:03:39 AM UTC 24 131675925 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2817260480 Sep 01 09:03:32 AM UTC 24 Sep 01 09:03:40 AM UTC 24 543785521 ps
T422 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_rw.3260980464 Sep 01 09:03:38 AM UTC 24 Sep 01 09:03:43 AM UTC 24 254749860 ps
T423 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1547371042 Sep 01 09:03:28 AM UTC 24 Sep 01 09:03:40 AM UTC 24 6015245942 ps
T424 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2685168540 Sep 01 09:03:25 AM UTC 24 Sep 01 09:03:40 AM UTC 24 5726589979 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2193902703 Sep 01 09:03:23 AM UTC 24 Sep 01 09:03:40 AM UTC 24 2450605112 ps
T425 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.220660179 Sep 01 09:03:31 AM UTC 24 Sep 01 09:03:41 AM UTC 24 1649611856 ps
T426 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_errors.1955195347 Sep 01 09:03:34 AM UTC 24 Sep 01 09:03:41 AM UTC 24 312716929 ps
T427 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3609208823 Sep 01 09:03:02 AM UTC 24 Sep 01 09:03:41 AM UTC 24 1744600932 ps
T428 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3518956004 Sep 01 09:03:38 AM UTC 24 Sep 01 09:03:41 AM UTC 24 404598427 ps
T429 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.3529584097 Sep 01 09:03:32 AM UTC 24 Sep 01 09:03:43 AM UTC 24 3755728131 ps
T430 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1454826153 Sep 01 09:03:33 AM UTC 24 Sep 01 09:03:41 AM UTC 24 2813838181 ps
T431 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3889128129 Sep 01 09:03:36 AM UTC 24 Sep 01 09:03:42 AM UTC 24 2387663398 ps
T432 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1430454889 Sep 01 09:03:38 AM UTC 24 Sep 01 09:03:42 AM UTC 24 115815138 ps
T433 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3442121096 Sep 01 09:03:35 AM UTC 24 Sep 01 09:03:42 AM UTC 24 147564701 ps
T434 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_errors.1667681682 Sep 01 09:03:37 AM UTC 24 Sep 01 09:03:43 AM UTC 24 293333028 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.1468862986 Sep 01 09:02:46 AM UTC 24 Sep 01 09:03:44 AM UTC 24 13613881970 ps
T435 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.516669971 Sep 01 09:03:41 AM UTC 24 Sep 01 09:03:44 AM UTC 24 203454038 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_rw.332078403 Sep 01 09:03:40 AM UTC 24 Sep 01 09:03:44 AM UTC 24 415775943 ps
T436 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.541415751 Sep 01 09:03:41 AM UTC 24 Sep 01 09:03:44 AM UTC 24 122360191 ps
T437 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3281344942 Sep 01 09:03:35 AM UTC 24 Sep 01 09:03:45 AM UTC 24 1888373702 ps
T438 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.187666693 Sep 01 09:03:42 AM UTC 24 Sep 01 09:03:45 AM UTC 24 269702550 ps
T439 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_rw.1806280595 Sep 01 09:03:42 AM UTC 24 Sep 01 09:03:46 AM UTC 24 410902953 ps
T440 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3937066420 Sep 01 09:03:40 AM UTC 24 Sep 01 09:03:46 AM UTC 24 392337739 ps
T441 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.4048556078 Sep 01 09:02:30 AM UTC 24 Sep 01 09:03:46 AM UTC 24 2395260766 ps
T442 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.676469621 Sep 01 09:03:42 AM UTC 24 Sep 01 09:03:46 AM UTC 24 361675027 ps
T443 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_errors.603923599 Sep 01 09:03:40 AM UTC 24 Sep 01 09:03:47 AM UTC 24 603977620 ps
T444 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.48848275 Sep 01 09:03:32 AM UTC 24 Sep 01 09:03:47 AM UTC 24 7648682722 ps
T445 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.892357326 Sep 01 09:03:45 AM UTC 24 Sep 01 09:03:47 AM UTC 24 189752858 ps
T446 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_errors.1297833264 Sep 01 09:03:44 AM UTC 24 Sep 01 09:03:48 AM UTC 24 301985118 ps
T447 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.569678425 Sep 01 09:03:38 AM UTC 24 Sep 01 09:03:48 AM UTC 24 2552678629 ps
T448 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_rw.1575171360 Sep 01 09:03:44 AM UTC 24 Sep 01 09:03:48 AM UTC 24 182992603 ps
T449 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.4060989364 Sep 01 09:02:33 AM UTC 24 Sep 01 09:03:49 AM UTC 24 7256986454 ps
T450 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2553377462 Sep 01 09:03:41 AM UTC 24 Sep 01 09:03:49 AM UTC 24 1346198045 ps
T451 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.536199144 Sep 01 09:03:38 AM UTC 24 Sep 01 09:03:49 AM UTC 24 484628721 ps
T452 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_rw.1604044105 Sep 01 09:03:46 AM UTC 24 Sep 01 09:03:49 AM UTC 24 138236810 ps
T453 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.381310369 Sep 01 09:03:45 AM UTC 24 Sep 01 09:03:50 AM UTC 24 1650566837 ps
T454 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_errors.1351748040 Sep 01 09:03:41 AM UTC 24 Sep 01 09:03:50 AM UTC 24 593233464 ps
T110 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.608072462 Sep 01 09:03:45 AM UTC 24 Sep 01 09:03:50 AM UTC 24 182946120 ps
T455 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_errors.4228247306 Sep 01 09:03:45 AM UTC 24 Sep 01 09:03:50 AM UTC 24 264899893 ps
T456 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.800586169 Sep 01 09:03:43 AM UTC 24 Sep 01 09:03:50 AM UTC 24 3989796233 ps
T457 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1749872530 Sep 01 09:03:44 AM UTC 24 Sep 01 09:03:51 AM UTC 24 243008962 ps
T458 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1450017849 Sep 01 09:03:27 AM UTC 24 Sep 01 09:03:51 AM UTC 24 14121910515 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1464847053 Sep 01 09:03:35 AM UTC 24 Sep 01 09:03:51 AM UTC 24 6495598410 ps
T459 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1876993982 Sep 01 09:02:42 AM UTC 24 Sep 01 09:03:53 AM UTC 24 13230311769 ps
T460 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2700481078 Sep 01 09:03:42 AM UTC 24 Sep 01 09:03:54 AM UTC 24 2378769559 ps
T461 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3658713609 Sep 01 09:03:47 AM UTC 24 Sep 01 09:03:54 AM UTC 24 356152824 ps
T462 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.332256592 Sep 01 09:03:40 AM UTC 24 Sep 01 09:03:55 AM UTC 24 1698401893 ps
T214 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3797470019 Sep 01 09:03:29 AM UTC 24 Sep 01 09:03:56 AM UTC 24 4032390467 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1445765340 Sep 01 09:03:25 AM UTC 24 Sep 01 09:03:58 AM UTC 24 5845395169 ps
T463 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3458496595 Sep 01 09:03:44 AM UTC 24 Sep 01 09:03:58 AM UTC 24 1535063831 ps
T464 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.4147885944 Sep 01 09:03:46 AM UTC 24 Sep 01 09:03:59 AM UTC 24 1184856966 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_intg_err.967970706 Sep 01 09:03:32 AM UTC 24 Sep 01 09:04:00 AM UTC 24 3710869688 ps
T465 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1536005785 Sep 01 09:03:38 AM UTC 24 Sep 01 09:04:00 AM UTC 24 7961802287 ps
T466 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1786318517 Sep 01 09:03:07 AM UTC 24 Sep 01 09:04:02 AM UTC 24 14087824172 ps
T467 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.4207448235 Sep 01 09:03:29 AM UTC 24 Sep 01 09:04:05 AM UTC 24 33686683246 ps
T468 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.1433266416 Sep 01 09:02:54 AM UTC 24 Sep 01 09:04:07 AM UTC 24 4528174865 ps
T469 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.211726368 Sep 01 09:03:08 AM UTC 24 Sep 01 09:04:07 AM UTC 24 5308355855 ps
T470 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3236741197 Sep 01 09:03:42 AM UTC 24 Sep 01 09:04:10 AM UTC 24 3416713236 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.2821794687 Sep 01 09:03:15 AM UTC 24 Sep 01 09:04:10 AM UTC 24 2691632218 ps
T471 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1736970405 Sep 01 09:03:41 AM UTC 24 Sep 01 09:04:10 AM UTC 24 12811681609 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_aliasing.936926998 Sep 01 09:02:42 AM UTC 24 Sep 01 09:04:12 AM UTC 24 7931516024 ps
T472 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.78256763 Sep 01 09:03:33 AM UTC 24 Sep 01 09:04:17 AM UTC 24 10219827610 ps
T473 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.4026054816 Sep 01 09:03:11 AM UTC 24 Sep 01 09:04:19 AM UTC 24 27252016543 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_intg_err.531400581 Sep 01 09:03:46 AM UTC 24 Sep 01 09:04:22 AM UTC 24 3403243286 ps
T474 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1530735153 Sep 01 09:02:59 AM UTC 24 Sep 01 09:04:25 AM UTC 24 55933047357 ps
T475 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1732752260 Sep 01 09:03:44 AM UTC 24 Sep 01 09:04:38 AM UTC 24 65404846753 ps
T476 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2340959687 Sep 01 09:03:40 AM UTC 24 Sep 01 09:04:38 AM UTC 24 27204848560 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.2406817629 Sep 01 09:03:11 AM UTC 24 Sep 01 09:04:38 AM UTC 24 13286976557 ps
T477 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1321715130 Sep 01 09:03:18 AM UTC 24 Sep 01 09:04:45 AM UTC 24 5930677311 ps
T478 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.290664488 Sep 01 09:03:45 AM UTC 24 Sep 01 09:05:31 AM UTC 24 79571914734 ps
T479 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.832407188 Sep 01 09:03:15 AM UTC 24 Sep 01 09:06:21 AM UTC 24 57182162453 ps
T480 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.980219267 Sep 01 09:03:36 AM UTC 24 Sep 01 09:07:10 AM UTC 24 78043055091 ps
T481 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3712239939 Sep 01 09:02:32 AM UTC 24 Sep 01 09:07:11 AM UTC 24 184306474844 ps
T482 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.4193480186 Sep 01 09:03:02 AM UTC 24 Sep 01 09:07:24 AM UTC 24 67085273271 ps
T483 /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2237346325 Sep 01 09:02:46 AM UTC 24 Sep 01 09:11:33 AM UTC 24 140694150043 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.1862400464
Short name T20
Test name
Test status
Simulation time 3162454658 ps
CPU time 18.89 seconds
Started Sep 01 09:40:34 AM UTC 24
Finished Sep 01 09:40:54 AM UTC 24
Peak memory 216380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862400464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.1862400464
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.3150757175
Short name T17
Test name
Test status
Simulation time 11796039026 ps
CPU time 50.38 seconds
Started Sep 01 09:41:33 AM UTC 24
Finished Sep 01 09:42:25 AM UTC 24
Peak memory 233280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=3150757175 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stres
s_all_with_rand_reset.3150757175
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.2424476423
Short name T42
Test name
Test status
Simulation time 1264795587 ps
CPU time 4.12 seconds
Started Sep 01 09:40:53 AM UTC 24
Finished Sep 01 09:40:59 AM UTC 24
Peak memory 215804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424476423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.2424476423
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_halt_resume_whereto/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.3511310439
Short name T68
Test name
Test status
Simulation time 845075969 ps
CPU time 7.01 seconds
Started Sep 01 09:41:03 AM UTC 24
Finished Sep 01 09:41:11 AM UTC 24
Peak memory 254744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511310439 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3511310439
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.3597426441
Short name T3
Test name
Test status
Simulation time 4387383877 ps
CPU time 18.54 seconds
Started Sep 01 09:40:18 AM UTC 24
Finished Sep 01 09:40:38 AM UTC 24
Peak memory 216208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597426441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.3597426441
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.2105927308
Short name T62
Test name
Test status
Simulation time 4119691700 ps
CPU time 45.64 seconds
Started Sep 01 09:41:39 AM UTC 24
Finished Sep 01 09:42:26 AM UTC 24
Peak memory 233256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=2105927308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stres
s_all_with_rand_reset.2105927308
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.4226669976
Short name T179
Test name
Test status
Simulation time 1641173121 ps
CPU time 15.24 seconds
Started Sep 01 09:02:34 AM UTC 24
Finished Sep 01 09:02:51 AM UTC 24
Peak memory 225792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226669976 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.4226669976
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/4.rv_dm_autoincr_sba_tl_access.3960091193
Short name T241
Test name
Test status
Simulation time 81961569939 ps
CPU time 48.29 seconds
Started Sep 01 09:41:43 AM UTC 24
Finished Sep 01 09:42:33 AM UTC 24
Peak memory 226564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960091193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.3960091193
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.1468862986
Short name T73
Test name
Test status
Simulation time 13613881970 ps
CPU time 56.42 seconds
Started Sep 01 09:02:46 AM UTC 24
Finished Sep 01 09:03:44 AM UTC 24
Peak memory 229892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=1468862986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_re
set.1468862986
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.2641334596
Short name T30
Test name
Test status
Simulation time 1711687925 ps
CPU time 7.3 seconds
Started Sep 01 09:41:02 AM UTC 24
Finished Sep 01 09:41:10 AM UTC 24
Peak memory 226304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641334596 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.2641334596
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.129915846
Short name T76
Test name
Test status
Simulation time 556217615 ps
CPU time 2.65 seconds
Started Sep 01 09:41:01 AM UTC 24
Finished Sep 01 09:41:04 AM UTC 24
Peak memory 258744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129915846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_buffered_enable.129915846
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.2264903617
Short name T34
Test name
Test status
Simulation time 14719990528 ps
CPU time 92.72 seconds
Started Sep 01 09:41:03 AM UTC 24
Finished Sep 01 09:42:38 AM UTC 24
Peak memory 243488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=2264903617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stres
s_all_with_rand_reset.2264903617
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.1577411245
Short name T49
Test name
Test status
Simulation time 2047438501 ps
CPU time 4.82 seconds
Started Sep 01 09:41:25 AM UTC 24
Finished Sep 01 09:41:31 AM UTC 24
Peak memory 216072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577411245 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.1577411245
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1321715130
Short name T477
Test name
Test status
Simulation time 5930677311 ps
CPU time 85.4 seconds
Started Sep 01 09:03:18 AM UTC 24
Finished Sep 01 09:04:45 AM UTC 24
Peak memory 229820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=1321715130 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_re
set.1321715130
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.2466982293
Short name T97
Test name
Test status
Simulation time 26617570 ps
CPU time 1.05 seconds
Started Sep 01 09:41:02 AM UTC 24
Finished Sep 01 09:41:04 AM UTC 24
Peak memory 213456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466982293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_scanmode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_scanmode.2466982293
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_scanmode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.3557229363
Short name T25
Test name
Test status
Simulation time 445907512 ps
CPU time 2.08 seconds
Started Sep 01 09:40:59 AM UTC 24
Finished Sep 01 09:41:03 AM UTC 24
Peak memory 215816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557229363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.3557229363
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_dmi_failed_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.128799145
Short name T26
Test name
Test status
Simulation time 3359427813 ps
CPU time 11.37 seconds
Started Sep 01 09:41:48 AM UTC 24
Finished Sep 01 09:42:00 AM UTC 24
Peak memory 216080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128799145 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.128799145
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/4.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.608072462
Short name T110
Test name
Test status
Simulation time 182946120 ps
CPU time 4.59 seconds
Started Sep 01 09:03:45 AM UTC 24
Finished Sep 01 09:03:50 AM UTC 24
Peak memory 231984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=608072462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_r
and_reset.608072462
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3038102097
Short name T104
Test name
Test status
Simulation time 3206788649 ps
CPU time 13.62 seconds
Started Sep 01 09:03:22 AM UTC 24
Finished Sep 01 09:03:37 AM UTC 24
Peak memory 227904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3038102097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_re
set.3038102097
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/41.rv_dm_stress_all.3157166903
Short name T10
Test name
Test status
Simulation time 8237828769 ps
CPU time 5.88 seconds
Started Sep 01 09:43:38 AM UTC 24
Finished Sep 01 09:43:45 AM UTC 24
Peak memory 216208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157166903 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.3157166903
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/41.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.2227659900
Short name T58
Test name
Test status
Simulation time 124657379 ps
CPU time 1.74 seconds
Started Sep 01 09:40:58 AM UTC 24
Finished Sep 01 09:41:01 AM UTC 24
Peak memory 225792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227659900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_rom_read_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.2227659900
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_rom_read_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_autoincr_sba_tl_access.4269044922
Short name T23
Test name
Test status
Simulation time 5046812017 ps
CPU time 12.22 seconds
Started Sep 01 09:41:07 AM UTC 24
Finished Sep 01 09:41:20 AM UTC 24
Peak memory 226580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269044922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.4269044922
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.63469713
Short name T120
Test name
Test status
Simulation time 478640413 ps
CPU time 3.57 seconds
Started Sep 01 09:02:36 AM UTC 24
Finished Sep 01 09:02:40 AM UTC 24
Peak memory 225668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63469713 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.63469713
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.2650811848
Short name T13
Test name
Test status
Simulation time 577181061 ps
CPU time 1.59 seconds
Started Sep 01 09:40:49 AM UTC 24
Finished Sep 01 09:40:52 AM UTC 24
Peak memory 215940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650811848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.2650811848
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_cmderr_exception/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3872573581
Short name T181
Test name
Test status
Simulation time 3494571696 ps
CPU time 11.05 seconds
Started Sep 01 09:03:04 AM UTC 24
Finished Sep 01 09:03:16 AM UTC 24
Peak memory 225860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872573581 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.3872573581
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/4.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/4.rv_dm_alert_test.387772627
Short name T234
Test name
Test status
Simulation time 160694443 ps
CPU time 1.21 seconds
Started Sep 01 09:41:53 AM UTC 24
Finished Sep 01 09:41:55 AM UTC 24
Peak memory 215996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387772627 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.387772627
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/4.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.799337842
Short name T9
Test name
Test status
Simulation time 9400276493 ps
CPU time 38.75 seconds
Started Sep 01 09:42:16 AM UTC 24
Finished Sep 01 09:42:57 AM UTC 24
Peak memory 233276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=799337842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress
_all_with_rand_reset.799337842
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/18.rv_dm_autoincr_sba_tl_access.970220988
Short name T296
Test name
Test status
Simulation time 16669999054 ps
CPU time 18.99 seconds
Started Sep 01 09:43:15 AM UTC 24
Finished Sep 01 09:43:35 AM UTC 24
Peak memory 226560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970220988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.970220988
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_rw.332078403
Short name T156
Test name
Test status
Simulation time 415775943 ps
CPU time 3 seconds
Started Sep 01 09:03:40 AM UTC 24
Finished Sep 01 09:03:44 AM UTC 24
Peak memory 225732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332078403 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/r
v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.332078403
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/16.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.4017570224
Short name T180
Test name
Test status
Simulation time 5213804383 ps
CPU time 22.61 seconds
Started Sep 01 09:02:41 AM UTC 24
Finished Sep 01 09:03:05 AM UTC 24
Peak memory 232444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017570224 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.4017570224
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2897813271
Short name T149
Test name
Test status
Simulation time 272100158 ps
CPU time 4.43 seconds
Started Sep 01 09:03:26 AM UTC 24
Finished Sep 01 09:03:31 AM UTC 24
Peak memory 215364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897813271 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_csr_outstanding.2897813271
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/10.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.322246498
Short name T41
Test name
Test status
Simulation time 2625660754 ps
CPU time 6.76 seconds
Started Sep 01 09:40:54 AM UTC 24
Finished Sep 01 09:41:01 AM UTC 24
Peak memory 216064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322246498 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_sba_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.322246498
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_sba_debug_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_intg_err.967970706
Short name T215
Test name
Test status
Simulation time 3710869688 ps
CPU time 25.96 seconds
Started Sep 01 09:03:32 AM UTC 24
Finished Sep 01 09:04:00 AM UTC 24
Peak memory 225740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967970706 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.967970706
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/13.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/29.rv_dm_stress_all.1485552586
Short name T194
Test name
Test status
Simulation time 2425859448 ps
CPU time 13.14 seconds
Started Sep 01 09:43:27 AM UTC 24
Finished Sep 01 09:43:42 AM UTC 24
Peak memory 216192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485552586 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.1485552586
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/29.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/39.rv_dm_stress_all.2861260800
Short name T200
Test name
Test status
Simulation time 7048020109 ps
CPU time 9.88 seconds
Started Sep 01 09:43:37 AM UTC 24
Finished Sep 01 09:43:48 AM UTC 24
Peak memory 216132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861260800 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.2861260800
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/39.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1029803924
Short name T100
Test name
Test status
Simulation time 1354681035 ps
CPU time 7.1 seconds
Started Sep 01 09:02:32 AM UTC 24
Finished Sep 01 09:02:40 AM UTC 24
Peak memory 214996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029803924 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_aliasing.1029803924
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.12914952
Short name T55
Test name
Test status
Simulation time 158242164 ps
CPU time 1.51 seconds
Started Sep 01 09:40:58 AM UTC 24
Finished Sep 01 09:41:00 AM UTC 24
Peak memory 213404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12914952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv
_dm_abstractcmd_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.12914952
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_abstractcmd_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2387132008
Short name T133
Test name
Test status
Simulation time 1905139179 ps
CPU time 3.34 seconds
Started Sep 01 09:02:32 AM UTC 24
Finished Sep 01 09:02:36 AM UTC 24
Peak memory 215432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387132008 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_hw_reset.2387132008
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.2874118407
Short name T4
Test name
Test status
Simulation time 775088000 ps
CPU time 1.58 seconds
Started Sep 01 09:40:49 AM UTC 24
Finished Sep 01 09:40:53 AM UTC 24
Peak memory 213456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874118407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.2874118407
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_cmderr_halt_resume/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1464847053
Short name T217
Test name
Test status
Simulation time 6495598410 ps
CPU time 15.51 seconds
Started Sep 01 09:03:35 AM UTC 24
Finished Sep 01 09:03:51 AM UTC 24
Peak memory 232376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464847053 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.1464847053
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/14.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.3981531193
Short name T67
Test name
Test status
Simulation time 58012287 ps
CPU time 1.24 seconds
Started Sep 01 09:41:02 AM UTC 24
Finished Sep 01 09:41:04 AM UTC 24
Peak memory 225856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981531193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sparse_lc_gate_fsm.3981531193
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_sparse_lc_gate_fsm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/2.rv_dm_sparse_lc_gate_fsm.3027503736
Short name T77
Test name
Test status
Simulation time 75852772 ps
CPU time 0.85 seconds
Started Sep 01 09:41:33 AM UTC 24
Finished Sep 01 09:41:35 AM UTC 24
Peak memory 225856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027503736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sparse_lc_gate_fsm.3027503736
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/2.rv_dm_sparse_lc_gate_fsm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3964415141
Short name T144
Test name
Test status
Simulation time 39691889448 ps
CPU time 37.82 seconds
Started Sep 01 09:02:37 AM UTC 24
Finished Sep 01 09:03:16 AM UTC 24
Peak memory 225700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964415141 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.3964415141
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.4048556078
Short name T441
Test name
Test status
Simulation time 2395260766 ps
CPU time 74.96 seconds
Started Sep 01 09:02:30 AM UTC 24
Finished Sep 01 09:03:46 AM UTC 24
Peak memory 229796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048556078 -ass
ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_aliasing.4048556078
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.152406551
Short name T106
Test name
Test status
Simulation time 80753128 ps
CPU time 3.21 seconds
Started Sep 01 09:02:37 AM UTC 24
Finished Sep 01 09:02:41 AM UTC 24
Peak memory 225804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=152406551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_ra
nd_reset.152406551
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.66836134
Short name T119
Test name
Test status
Simulation time 243374854 ps
CPU time 1.71 seconds
Started Sep 01 09:02:37 AM UTC 24
Finished Sep 01 09:02:39 AM UTC 24
Peak memory 229160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66836134 -assert nopostproc +UVM_TESTNAME=rv_dm_ba
se_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv
_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.66836134
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3712239939
Short name T481
Test name
Test status
Simulation time 184306474844 ps
CPU time 275.12 seconds
Started Sep 01 09:02:32 AM UTC 24
Finished Sep 01 09:07:11 AM UTC 24
Peak memory 215348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712239939 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_aliasing.3712239939
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.4139533653
Short name T397
Test name
Test status
Simulation time 32389837499 ps
CPU time 52.48 seconds
Started Sep 01 09:02:32 AM UTC 24
Finished Sep 01 09:03:26 AM UTC 24
Peak memory 215360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139533653 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_bit_bash.4139533653
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3710066521
Short name T338
Test name
Test status
Simulation time 2301336209 ps
CPU time 5.18 seconds
Started Sep 01 09:02:32 AM UTC 24
Finished Sep 01 09:02:38 AM UTC 24
Peak memory 215360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710066521 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.3710066521
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1804574485
Short name T344
Test name
Test status
Simulation time 2316342467 ps
CPU time 10.24 seconds
Started Sep 01 09:02:32 AM UTC 24
Finished Sep 01 09:02:43 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804574485 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_bit_bash.1804574485
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.4259395637
Short name T98
Test name
Test status
Simulation time 490994521 ps
CPU time 3.39 seconds
Started Sep 01 09:02:31 AM UTC 24
Finished Sep 01 09:02:35 AM UTC 24
Peak memory 215208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259395637 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_hw_reset.4259395637
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.917186096
Short name T99
Test name
Test status
Simulation time 270515546 ps
CPU time 2.24 seconds
Started Sep 01 09:02:32 AM UTC 24
Finished Sep 01 09:02:35 AM UTC 24
Peak memory 215152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917186096 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.917186096
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2412608107
Short name T336
Test name
Test status
Simulation time 30216357 ps
CPU time 0.96 seconds
Started Sep 01 09:02:36 AM UTC 24
Finished Sep 01 09:02:38 AM UTC 24
Peak memory 215140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412608107 -assert nopostproc +UVM
_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_partial_access.2412608107
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.1723717464
Short name T337
Test name
Test status
Simulation time 82119871 ps
CPU time 1.16 seconds
Started Sep 01 09:02:35 AM UTC 24
Finished Sep 01 09:02:38 AM UTC 24
Peak memory 215080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723717464 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.1723717464
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2984537468
Short name T123
Test name
Test status
Simulation time 1624891605 ps
CPU time 7.53 seconds
Started Sep 01 09:02:37 AM UTC 24
Finished Sep 01 09:02:45 AM UTC 24
Peak memory 215416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984537468 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_csr_outstanding.2984537468
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.4060989364
Short name T449
Test name
Test status
Simulation time 7256986454 ps
CPU time 73.43 seconds
Started Sep 01 09:02:33 AM UTC 24
Finished Sep 01 09:03:49 AM UTC 24
Peak memory 225812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=4060989364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_re
set.4060989364
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.220594176
Short name T335
Test name
Test status
Simulation time 145968927 ps
CPU time 2.01 seconds
Started Sep 01 09:02:33 AM UTC 24
Finished Sep 01 09:02:36 AM UTC 24
Peak memory 225200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220594176 -assert nopostproc +UVM_TESTNAME=rv_dm_base
_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_d
m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.220594176
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3972140383
Short name T143
Test name
Test status
Simulation time 4216271519 ps
CPU time 36.47 seconds
Started Sep 01 09:02:37 AM UTC 24
Finished Sep 01 09:03:15 AM UTC 24
Peak memory 215428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972140383 -ass
ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_aliasing.3972140383
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1876993982
Short name T459
Test name
Test status
Simulation time 13230311769 ps
CPU time 69.45 seconds
Started Sep 01 09:02:42 AM UTC 24
Finished Sep 01 09:03:53 AM UTC 24
Peak memory 215524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876993982 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.1876993982
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.513338114
Short name T121
Test name
Test status
Simulation time 97957876 ps
CPU time 2.51 seconds
Started Sep 01 09:02:41 AM UTC 24
Finished Sep 01 09:02:44 AM UTC 24
Peak memory 225564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513338114 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.513338114
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1236747645
Short name T166
Test name
Test status
Simulation time 80538692 ps
CPU time 2.72 seconds
Started Sep 01 09:02:42 AM UTC 24
Finished Sep 01 09:02:46 AM UTC 24
Peak memory 225812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=1236747645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_r
and_reset.1236747645
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.639465968
Short name T122
Test name
Test status
Simulation time 161119076 ps
CPU time 2.3 seconds
Started Sep 01 09:02:42 AM UTC 24
Finished Sep 01 09:02:45 AM UTC 24
Peak memory 225860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639465968 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/r
v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.639465968
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3525426649
Short name T363
Test name
Test status
Simulation time 19683575321 ps
CPU time 20.72 seconds
Started Sep 01 09:02:40 AM UTC 24
Finished Sep 01 09:03:01 AM UTC 24
Peak memory 215364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525426649 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_aliasing.3525426649
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1553245947
Short name T341
Test name
Test status
Simulation time 34900774 ps
CPU time 0.98 seconds
Started Sep 01 09:02:39 AM UTC 24
Finished Sep 01 09:02:41 AM UTC 24
Peak memory 215140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553245947 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_bit_bash.1553245947
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.504233467
Short name T134
Test name
Test status
Simulation time 3086818512 ps
CPU time 5.86 seconds
Started Sep 01 09:02:38 AM UTC 24
Finished Sep 01 09:02:45 AM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504233467 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_hw_reset.504233467
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.772284820
Short name T353
Test name
Test status
Simulation time 3906799607 ps
CPU time 11.06 seconds
Started Sep 01 09:02:39 AM UTC 24
Finished Sep 01 09:02:52 AM UTC 24
Peak memory 215520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772284820 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.772284820
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2791317085
Short name T342
Test name
Test status
Simulation time 331845581 ps
CPU time 2.53 seconds
Started Sep 01 09:02:38 AM UTC 24
Finished Sep 01 09:02:42 AM UTC 24
Peak memory 215152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791317085 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_aliasing.2791317085
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3852049812
Short name T360
Test name
Test status
Simulation time 3497678172 ps
CPU time 18.39 seconds
Started Sep 01 09:02:38 AM UTC 24
Finished Sep 01 09:02:58 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852049812 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_bit_bash.3852049812
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3808195341
Short name T340
Test name
Test status
Simulation time 222798235 ps
CPU time 1.89 seconds
Started Sep 01 09:02:38 AM UTC 24
Finished Sep 01 09:02:41 AM UTC 24
Peak memory 215144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808195341 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_hw_reset.3808195341
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3640978723
Short name T339
Test name
Test status
Simulation time 572190984 ps
CPU time 1.43 seconds
Started Sep 01 09:02:38 AM UTC 24
Finished Sep 01 09:02:41 AM UTC 24
Peak memory 215080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640978723 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.3640978723
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.4156738551
Short name T343
Test name
Test status
Simulation time 47560655 ps
CPU time 1.22 seconds
Started Sep 01 09:02:41 AM UTC 24
Finished Sep 01 09:02:43 AM UTC 24
Peak memory 215064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156738551 -assert nopostproc +UVM
_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_partial_access.4156738551
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.26649566
Short name T345
Test name
Test status
Simulation time 131116369 ps
CPU time 1.38 seconds
Started Sep 01 09:02:41 AM UTC 24
Finished Sep 01 09:02:43 AM UTC 24
Peak memory 215140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26649566 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.26649566
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2090291898
Short name T125
Test name
Test status
Simulation time 757919535 ps
CPU time 10.02 seconds
Started Sep 01 09:02:42 AM UTC 24
Finished Sep 01 09:02:53 AM UTC 24
Peak memory 215436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090291898 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_csr_outstanding.2090291898
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.916353292
Short name T408
Test name
Test status
Simulation time 4498342390 ps
CPU time 50.24 seconds
Started Sep 01 09:02:40 AM UTC 24
Finished Sep 01 09:03:31 AM UTC 24
Peak memory 230048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=916353292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.916353292
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.907507625
Short name T348
Test name
Test status
Simulation time 121350496 ps
CPU time 6.01 seconds
Started Sep 01 09:02:41 AM UTC 24
Finished Sep 01 09:02:48 AM UTC 24
Peak memory 225716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907507625 -assert nopostproc +UVM_TESTNAME=rv_dm_base
_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_d
m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.907507625
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.4204370690
Short name T109
Test name
Test status
Simulation time 176008056 ps
CPU time 5.37 seconds
Started Sep 01 09:03:26 AM UTC 24
Finished Sep 01 09:03:32 AM UTC 24
Peak memory 229772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=4204370690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_
rand_reset.4204370690
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.1801942160
Short name T155
Test name
Test status
Simulation time 59078889 ps
CPU time 1.73 seconds
Started Sep 01 09:03:26 AM UTC 24
Finished Sep 01 09:03:28 AM UTC 24
Peak memory 225116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801942160 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.1801942160
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/10.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2685168540
Short name T424
Test name
Test status
Simulation time 5726589979 ps
CPU time 13.75 seconds
Started Sep 01 09:03:25 AM UTC 24
Finished Sep 01 09:03:40 AM UTC 24
Peak memory 215588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685168540 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_bit_bash.2685168540
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1319361729
Short name T402
Test name
Test status
Simulation time 2637294079 ps
CPU time 2.79 seconds
Started Sep 01 09:03:24 AM UTC 24
Finished Sep 01 09:03:28 AM UTC 24
Peak memory 215288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319361729 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.1319361729
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1890028646
Short name T401
Test name
Test status
Simulation time 197004258 ps
CPU time 1.32 seconds
Started Sep 01 09:03:24 AM UTC 24
Finished Sep 01 09:03:27 AM UTC 24
Peak memory 215076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890028646 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.1890028646
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.1446952265
Short name T414
Test name
Test status
Simulation time 291839103 ps
CPU time 7.69 seconds
Started Sep 01 09:03:25 AM UTC 24
Finished Sep 01 09:03:34 AM UTC 24
Peak memory 225720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446952265 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.1446952265
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/10.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1445765340
Short name T212
Test name
Test status
Simulation time 5845395169 ps
CPU time 31.29 seconds
Started Sep 01 09:03:25 AM UTC 24
Finished Sep 01 09:03:58 AM UTC 24
Peak memory 232524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445765340 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.1445765340
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/10.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3699002890
Short name T102
Test name
Test status
Simulation time 201930463 ps
CPU time 3.84 seconds
Started Sep 01 09:03:28 AM UTC 24
Finished Sep 01 09:03:33 AM UTC 24
Peak memory 227756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=3699002890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_
rand_reset.3699002890
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_rw.4217960869
Short name T405
Test name
Test status
Simulation time 596190985 ps
CPU time 2.31 seconds
Started Sep 01 09:03:27 AM UTC 24
Finished Sep 01 09:03:30 AM UTC 24
Peak memory 229696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217960869 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.4217960869
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/11.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.959362462
Short name T407
Test name
Test status
Simulation time 2535873148 ps
CPU time 3.23 seconds
Started Sep 01 09:03:27 AM UTC 24
Finished Sep 01 09:03:31 AM UTC 24
Peak memory 215364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959362462 -assert nopostpro
c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_bit_bash.959362462
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1450017849
Short name T458
Test name
Test status
Simulation time 14121910515 ps
CPU time 23.48 seconds
Started Sep 01 09:03:27 AM UTC 24
Finished Sep 01 09:03:51 AM UTC 24
Peak memory 215356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450017849 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.1450017849
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2913766543
Short name T404
Test name
Test status
Simulation time 226785072 ps
CPU time 2.19 seconds
Started Sep 01 09:03:27 AM UTC 24
Finished Sep 01 09:03:30 AM UTC 24
Peak memory 215136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913766543 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.2913766543
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2509728373
Short name T151
Test name
Test status
Simulation time 244645426 ps
CPU time 5.35 seconds
Started Sep 01 09:03:28 AM UTC 24
Finished Sep 01 09:03:35 AM UTC 24
Peak memory 215524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509728373 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_csr_outstanding.2509728373
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/11.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_errors.1022459703
Short name T409
Test name
Test status
Simulation time 316109105 ps
CPU time 4.28 seconds
Started Sep 01 09:03:27 AM UTC 24
Finished Sep 01 09:03:32 AM UTC 24
Peak memory 225720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022459703 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.1022459703
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/11.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1589787688
Short name T211
Test name
Test status
Simulation time 2347275914 ps
CPU time 10.66 seconds
Started Sep 01 09:03:27 AM UTC 24
Finished Sep 01 09:03:39 AM UTC 24
Peak memory 225860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589787688 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.1589787688
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/11.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3491746640
Short name T415
Test name
Test status
Simulation time 52050948 ps
CPU time 2.62 seconds
Started Sep 01 09:03:31 AM UTC 24
Finished Sep 01 09:03:34 AM UTC 24
Peak memory 227892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=3491746640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_
rand_reset.3491746640
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_rw.654931082
Short name T413
Test name
Test status
Simulation time 102945394 ps
CPU time 2.58 seconds
Started Sep 01 09:03:30 AM UTC 24
Finished Sep 01 09:03:34 AM UTC 24
Peak memory 225728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654931082 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/r
v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.654931082
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/12.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.4207448235
Short name T467
Test name
Test status
Simulation time 33686683246 ps
CPU time 33.42 seconds
Started Sep 01 09:03:29 AM UTC 24
Finished Sep 01 09:04:05 AM UTC 24
Peak memory 215360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207448235 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_bit_bash.4207448235
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1547371042
Short name T423
Test name
Test status
Simulation time 6015245942 ps
CPU time 10.85 seconds
Started Sep 01 09:03:28 AM UTC 24
Finished Sep 01 09:03:40 AM UTC 24
Peak memory 215420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547371042 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.1547371042
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3327273499
Short name T406
Test name
Test status
Simulation time 126660988 ps
CPU time 1.6 seconds
Started Sep 01 09:03:28 AM UTC 24
Finished Sep 01 09:03:31 AM UTC 24
Peak memory 215076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327273499 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.3327273499
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.220660179
Short name T425
Test name
Test status
Simulation time 1649611856 ps
CPU time 9.39 seconds
Started Sep 01 09:03:31 AM UTC 24
Finished Sep 01 09:03:41 AM UTC 24
Peak memory 215556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220660179 -assert nopostproc +UV
M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same_csr_outstanding.220660179
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/12.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_errors.207355507
Short name T416
Test name
Test status
Simulation time 136567497 ps
CPU time 4.4 seconds
Started Sep 01 09:03:29 AM UTC 24
Finished Sep 01 09:03:35 AM UTC 24
Peak memory 225888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207355507 -assert nopostproc +UVM_TESTNAME=rv_dm_base
_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_d
m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.207355507
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/12.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3797470019
Short name T214
Test name
Test status
Simulation time 4032390467 ps
CPU time 25.03 seconds
Started Sep 01 09:03:29 AM UTC 24
Finished Sep 01 09:03:56 AM UTC 24
Peak memory 227820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797470019 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.3797470019
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/12.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1308293270
Short name T418
Test name
Test status
Simulation time 352170798 ps
CPU time 2.63 seconds
Started Sep 01 09:03:33 AM UTC 24
Finished Sep 01 09:03:37 AM UTC 24
Peak memory 229816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=1308293270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_
rand_reset.1308293270
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_rw.2187937267
Short name T159
Test name
Test status
Simulation time 189133984 ps
CPU time 3.2 seconds
Started Sep 01 09:03:32 AM UTC 24
Finished Sep 01 09:03:37 AM UTC 24
Peak memory 225588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187937267 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.2187937267
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/13.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.3529584097
Short name T429
Test name
Test status
Simulation time 3755728131 ps
CPU time 9.52 seconds
Started Sep 01 09:03:32 AM UTC 24
Finished Sep 01 09:03:43 AM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529584097 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_bit_bash.3529584097
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.48848275
Short name T444
Test name
Test status
Simulation time 7648682722 ps
CPU time 13.8 seconds
Started Sep 01 09:03:32 AM UTC 24
Finished Sep 01 09:03:47 AM UTC 24
Peak memory 215576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48848275 -assert nopostproc +UVM_TESTNAME=rv_dm_ba
se_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.48848275
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2383822350
Short name T411
Test name
Test status
Simulation time 167276264 ps
CPU time 1.14 seconds
Started Sep 01 09:03:31 AM UTC 24
Finished Sep 01 09:03:33 AM UTC 24
Peak memory 215076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383822350 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.2383822350
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2817260480
Short name T152
Test name
Test status
Simulation time 543785521 ps
CPU time 6.1 seconds
Started Sep 01 09:03:32 AM UTC 24
Finished Sep 01 09:03:40 AM UTC 24
Peak memory 215620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817260480 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_csr_outstanding.2817260480
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/13.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_errors.259283939
Short name T420
Test name
Test status
Simulation time 251578416 ps
CPU time 4.77 seconds
Started Sep 01 09:03:32 AM UTC 24
Finished Sep 01 09:03:38 AM UTC 24
Peak memory 225792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259283939 -assert nopostproc +UVM_TESTNAME=rv_dm_base
_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_d
m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.259283939
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/13.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3442121096
Short name T433
Test name
Test status
Simulation time 147564701 ps
CPU time 5.91 seconds
Started Sep 01 09:03:35 AM UTC 24
Finished Sep 01 09:03:42 AM UTC 24
Peak memory 229864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=3442121096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_
rand_reset.3442121096
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_rw.855385900
Short name T158
Test name
Test status
Simulation time 151205806 ps
CPU time 2.86 seconds
Started Sep 01 09:03:35 AM UTC 24
Finished Sep 01 09:03:39 AM UTC 24
Peak memory 225672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855385900 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/r
v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.855385900
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/14.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.78256763
Short name T472
Test name
Test status
Simulation time 10219827610 ps
CPU time 42.31 seconds
Started Sep 01 09:03:33 AM UTC 24
Finished Sep 01 09:04:17 AM UTC 24
Peak memory 215356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78256763 -assert nopostproc
+UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_bit_bash.78256763
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1454826153
Short name T430
Test name
Test status
Simulation time 2813838181 ps
CPU time 6.69 seconds
Started Sep 01 09:03:33 AM UTC 24
Finished Sep 01 09:03:41 AM UTC 24
Peak memory 215416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454826153 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.1454826153
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.4048699505
Short name T417
Test name
Test status
Simulation time 486435323 ps
CPU time 2.58 seconds
Started Sep 01 09:03:33 AM UTC 24
Finished Sep 01 09:03:37 AM UTC 24
Peak memory 215136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048699505 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.4048699505
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3281344942
Short name T437
Test name
Test status
Simulation time 1888373702 ps
CPU time 8.54 seconds
Started Sep 01 09:03:35 AM UTC 24
Finished Sep 01 09:03:45 AM UTC 24
Peak memory 215452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281344942 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same_csr_outstanding.3281344942
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/14.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_errors.1955195347
Short name T426
Test name
Test status
Simulation time 312716929 ps
CPU time 5.15 seconds
Started Sep 01 09:03:34 AM UTC 24
Finished Sep 01 09:03:41 AM UTC 24
Peak memory 225764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955195347 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.1955195347
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/14.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1430454889
Short name T432
Test name
Test status
Simulation time 115815138 ps
CPU time 2.54 seconds
Started Sep 01 09:03:38 AM UTC 24
Finished Sep 01 09:03:42 AM UTC 24
Peak memory 225756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=1430454889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_
rand_reset.1430454889
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_rw.3260980464
Short name T422
Test name
Test status
Simulation time 254749860 ps
CPU time 3.73 seconds
Started Sep 01 09:03:38 AM UTC 24
Finished Sep 01 09:03:43 AM UTC 24
Peak memory 229696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260980464 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.3260980464
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/15.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.980219267
Short name T480
Test name
Test status
Simulation time 78043055091 ps
CPU time 210.09 seconds
Started Sep 01 09:03:36 AM UTC 24
Finished Sep 01 09:07:10 AM UTC 24
Peak memory 215380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980219267 -assert nopostpro
c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_bit_bash.980219267
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3889128129
Short name T431
Test name
Test status
Simulation time 2387663398 ps
CPU time 4.58 seconds
Started Sep 01 09:03:36 AM UTC 24
Finished Sep 01 09:03:42 AM UTC 24
Peak memory 215288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889128129 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.3889128129
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.924527169
Short name T421
Test name
Test status
Simulation time 131675925 ps
CPU time 1.67 seconds
Started Sep 01 09:03:36 AM UTC 24
Finished Sep 01 09:03:39 AM UTC 24
Peak memory 215084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924527169 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.924527169
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.536199144
Short name T451
Test name
Test status
Simulation time 484628721 ps
CPU time 9.26 seconds
Started Sep 01 09:03:38 AM UTC 24
Finished Sep 01 09:03:49 AM UTC 24
Peak memory 215620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536199144 -assert nopostproc +UV
M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_csr_outstanding.536199144
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/15.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_errors.1667681682
Short name T434
Test name
Test status
Simulation time 293333028 ps
CPU time 5.24 seconds
Started Sep 01 09:03:37 AM UTC 24
Finished Sep 01 09:03:43 AM UTC 24
Peak memory 225764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667681682 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.1667681682
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/15.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1536005785
Short name T465
Test name
Test status
Simulation time 7961802287 ps
CPU time 20.91 seconds
Started Sep 01 09:03:38 AM UTC 24
Finished Sep 01 09:04:00 AM UTC 24
Peak memory 232468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536005785 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.1536005785
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/15.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.541415751
Short name T436
Test name
Test status
Simulation time 122360191 ps
CPU time 2.3 seconds
Started Sep 01 09:03:41 AM UTC 24
Finished Sep 01 09:03:44 AM UTC 24
Peak memory 225804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=541415751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_r
and_reset.541415751
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2340959687
Short name T476
Test name
Test status
Simulation time 27204848560 ps
CPU time 56.57 seconds
Started Sep 01 09:03:40 AM UTC 24
Finished Sep 01 09:04:38 AM UTC 24
Peak memory 215372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340959687 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_bit_bash.2340959687
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.569678425
Short name T447
Test name
Test status
Simulation time 2552678629 ps
CPU time 8.37 seconds
Started Sep 01 09:03:38 AM UTC 24
Finished Sep 01 09:03:48 AM UTC 24
Peak memory 215432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569678425 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.569678425
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3518956004
Short name T428
Test name
Test status
Simulation time 404598427 ps
CPU time 1.82 seconds
Started Sep 01 09:03:38 AM UTC 24
Finished Sep 01 09:03:41 AM UTC 24
Peak memory 215076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518956004 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.3518956004
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3937066420
Short name T440
Test name
Test status
Simulation time 392337739 ps
CPU time 5.21 seconds
Started Sep 01 09:03:40 AM UTC 24
Finished Sep 01 09:03:46 AM UTC 24
Peak memory 215596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937066420 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_csr_outstanding.3937066420
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/16.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_errors.603923599
Short name T443
Test name
Test status
Simulation time 603977620 ps
CPU time 5.97 seconds
Started Sep 01 09:03:40 AM UTC 24
Finished Sep 01 09:03:47 AM UTC 24
Peak memory 225760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603923599 -assert nopostproc +UVM_TESTNAME=rv_dm_base
_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_d
m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.603923599
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/16.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.332256592
Short name T462
Test name
Test status
Simulation time 1698401893 ps
CPU time 13.7 seconds
Started Sep 01 09:03:40 AM UTC 24
Finished Sep 01 09:03:55 AM UTC 24
Peak memory 225664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332256592 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.332256592
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/16.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.676469621
Short name T442
Test name
Test status
Simulation time 361675027 ps
CPU time 3.07 seconds
Started Sep 01 09:03:42 AM UTC 24
Finished Sep 01 09:03:46 AM UTC 24
Peak memory 232040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=676469621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_r
and_reset.676469621
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_rw.1806280595
Short name T439
Test name
Test status
Simulation time 410902953 ps
CPU time 2.59 seconds
Started Sep 01 09:03:42 AM UTC 24
Finished Sep 01 09:03:46 AM UTC 24
Peak memory 231808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806280595 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.1806280595
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/17.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1736970405
Short name T471
Test name
Test status
Simulation time 12811681609 ps
CPU time 27.64 seconds
Started Sep 01 09:03:41 AM UTC 24
Finished Sep 01 09:04:10 AM UTC 24
Peak memory 215324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736970405 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_bit_bash.1736970405
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2553377462
Short name T450
Test name
Test status
Simulation time 1346198045 ps
CPU time 6.59 seconds
Started Sep 01 09:03:41 AM UTC 24
Finished Sep 01 09:03:49 AM UTC 24
Peak memory 215356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553377462 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.2553377462
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.516669971
Short name T435
Test name
Test status
Simulation time 203454038 ps
CPU time 1.8 seconds
Started Sep 01 09:03:41 AM UTC 24
Finished Sep 01 09:03:44 AM UTC 24
Peak memory 215084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516669971 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.516669971
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2700481078
Short name T460
Test name
Test status
Simulation time 2378769559 ps
CPU time 10.31 seconds
Started Sep 01 09:03:42 AM UTC 24
Finished Sep 01 09:03:54 AM UTC 24
Peak memory 215628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700481078 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same_csr_outstanding.2700481078
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/17.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_errors.1351748040
Short name T454
Test name
Test status
Simulation time 593233464 ps
CPU time 7.75 seconds
Started Sep 01 09:03:41 AM UTC 24
Finished Sep 01 09:03:50 AM UTC 24
Peak memory 225724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351748040 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.1351748040
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/17.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3236741197
Short name T470
Test name
Test status
Simulation time 3416713236 ps
CPU time 26.24 seconds
Started Sep 01 09:03:42 AM UTC 24
Finished Sep 01 09:04:10 AM UTC 24
Peak memory 231940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236741197 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.3236741197
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/17.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_rw.1575171360
Short name T448
Test name
Test status
Simulation time 182992603 ps
CPU time 3.12 seconds
Started Sep 01 09:03:44 AM UTC 24
Finished Sep 01 09:03:48 AM UTC 24
Peak memory 225756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575171360 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.1575171360
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/18.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1732752260
Short name T475
Test name
Test status
Simulation time 65404846753 ps
CPU time 52.6 seconds
Started Sep 01 09:03:44 AM UTC 24
Finished Sep 01 09:04:38 AM UTC 24
Peak memory 215524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732752260 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_bit_bash.1732752260
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.800586169
Short name T456
Test name
Test status
Simulation time 3989796233 ps
CPU time 5.68 seconds
Started Sep 01 09:03:43 AM UTC 24
Finished Sep 01 09:03:50 AM UTC 24
Peak memory 215496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800586169 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.800586169
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.187666693
Short name T438
Test name
Test status
Simulation time 269702550 ps
CPU time 1.29 seconds
Started Sep 01 09:03:42 AM UTC 24
Finished Sep 01 09:03:45 AM UTC 24
Peak memory 215084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187666693 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.187666693
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1749872530
Short name T457
Test name
Test status
Simulation time 243008962 ps
CPU time 5.86 seconds
Started Sep 01 09:03:44 AM UTC 24
Finished Sep 01 09:03:51 AM UTC 24
Peak memory 215420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749872530 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same_csr_outstanding.1749872530
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/18.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_errors.1297833264
Short name T446
Test name
Test status
Simulation time 301985118 ps
CPU time 3.01 seconds
Started Sep 01 09:03:44 AM UTC 24
Finished Sep 01 09:03:48 AM UTC 24
Peak memory 225880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297833264 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.1297833264
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/18.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3458496595
Short name T463
Test name
Test status
Simulation time 1535063831 ps
CPU time 13.25 seconds
Started Sep 01 09:03:44 AM UTC 24
Finished Sep 01 09:03:58 AM UTC 24
Peak memory 225600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458496595 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3458496595
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/18.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3658713609
Short name T461
Test name
Test status
Simulation time 356152824 ps
CPU time 5.9 seconds
Started Sep 01 09:03:47 AM UTC 24
Finished Sep 01 09:03:54 AM UTC 24
Peak memory 229840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=3658713609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_
rand_reset.3658713609
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_rw.1604044105
Short name T452
Test name
Test status
Simulation time 138236810 ps
CPU time 1.64 seconds
Started Sep 01 09:03:46 AM UTC 24
Finished Sep 01 09:03:49 AM UTC 24
Peak memory 225252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604044105 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.1604044105
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/19.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.290664488
Short name T478
Test name
Test status
Simulation time 79571914734 ps
CPU time 104.39 seconds
Started Sep 01 09:03:45 AM UTC 24
Finished Sep 01 09:05:31 AM UTC 24
Peak memory 215452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290664488 -assert nopostpro
c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_bit_bash.290664488
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.381310369
Short name T453
Test name
Test status
Simulation time 1650566837 ps
CPU time 4.16 seconds
Started Sep 01 09:03:45 AM UTC 24
Finished Sep 01 09:03:50 AM UTC 24
Peak memory 215368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381310369 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.381310369
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.892357326
Short name T445
Test name
Test status
Simulation time 189752858 ps
CPU time 1.06 seconds
Started Sep 01 09:03:45 AM UTC 24
Finished Sep 01 09:03:47 AM UTC 24
Peak memory 215084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892357326 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.892357326
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.4147885944
Short name T464
Test name
Test status
Simulation time 1184856966 ps
CPU time 11.15 seconds
Started Sep 01 09:03:46 AM UTC 24
Finished Sep 01 09:03:59 AM UTC 24
Peak memory 215336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147885944 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_csr_outstanding.4147885944
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/19.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_errors.4228247306
Short name T455
Test name
Test status
Simulation time 264899893 ps
CPU time 4.28 seconds
Started Sep 01 09:03:45 AM UTC 24
Finished Sep 01 09:03:50 AM UTC 24
Peak memory 225912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228247306 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.4228247306
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/19.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_intg_err.531400581
Short name T218
Test name
Test status
Simulation time 3403243286 ps
CPU time 34.49 seconds
Started Sep 01 09:03:46 AM UTC 24
Finished Sep 01 09:04:22 AM UTC 24
Peak memory 232492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531400581 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.531400581
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/19.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_aliasing.936926998
Short name T157
Test name
Test status
Simulation time 7931516024 ps
CPU time 87.92 seconds
Started Sep 01 09:02:42 AM UTC 24
Finished Sep 01 09:04:12 AM UTC 24
Peak memory 225892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936926998 -asse
rt nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_aliasing.936926998
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/2.rv_dm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2038500222
Short name T399
Test name
Test status
Simulation time 781654932 ps
CPU time 34.43 seconds
Started Sep 01 09:02:50 AM UTC 24
Finished Sep 01 09:03:26 AM UTC 24
Peak memory 215268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038500222 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.2038500222
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/2.rv_dm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1979950010
Short name T124
Test name
Test status
Simulation time 221188906 ps
CPU time 2.35 seconds
Started Sep 01 09:02:49 AM UTC 24
Finished Sep 01 09:02:52 AM UTC 24
Peak memory 225532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979950010 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.1979950010
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/2.rv_dm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1439488912
Short name T107
Test name
Test status
Simulation time 180695955 ps
CPU time 2.38 seconds
Started Sep 01 09:02:51 AM UTC 24
Finished Sep 01 09:02:55 AM UTC 24
Peak memory 227924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=1439488912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_r
and_reset.1439488912
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_rw.3175864478
Short name T126
Test name
Test status
Simulation time 101919678 ps
CPU time 2.33 seconds
Started Sep 01 09:02:50 AM UTC 24
Finished Sep 01 09:02:53 AM UTC 24
Peak memory 225588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175864478 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.3175864478
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/2.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2237346325
Short name T483
Test name
Test status
Simulation time 140694150043 ps
CPU time 521.12 seconds
Started Sep 01 09:02:46 AM UTC 24
Finished Sep 01 09:11:33 AM UTC 24
Peak memory 218052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237346325 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_aliasing.2237346325
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3567097752
Short name T376
Test name
Test status
Simulation time 7025210517 ps
CPU time 25.6 seconds
Started Sep 01 09:02:46 AM UTC 24
Finished Sep 01 09:03:12 AM UTC 24
Peak memory 215516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567097752 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_bit_bash.3567097752
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3927117847
Short name T135
Test name
Test status
Simulation time 11001452504 ps
CPU time 12.61 seconds
Started Sep 01 09:02:45 AM UTC 24
Finished Sep 01 09:02:58 AM UTC 24
Peak memory 215432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927117847 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_hw_reset.3927117847
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1975581545
Short name T352
Test name
Test status
Simulation time 1110879955 ps
CPU time 5.44 seconds
Started Sep 01 09:02:45 AM UTC 24
Finished Sep 01 09:02:51 AM UTC 24
Peak memory 215296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975581545 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1975581545
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3846885102
Short name T351
Test name
Test status
Simulation time 859866745 ps
CPU time 5.06 seconds
Started Sep 01 09:02:45 AM UTC 24
Finished Sep 01 09:02:51 AM UTC 24
Peak memory 215148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846885102 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_aliasing.3846885102
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3007860148
Short name T361
Test name
Test status
Simulation time 6306013646 ps
CPU time 12.22 seconds
Started Sep 01 09:02:44 AM UTC 24
Finished Sep 01 09:02:58 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007860148 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_bit_bash.3007860148
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2110893258
Short name T347
Test name
Test status
Simulation time 352816456 ps
CPU time 1.47 seconds
Started Sep 01 09:02:43 AM UTC 24
Finished Sep 01 09:02:46 AM UTC 24
Peak memory 215084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110893258 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_hw_reset.2110893258
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2594859642
Short name T346
Test name
Test status
Simulation time 273406393 ps
CPU time 1.27 seconds
Started Sep 01 09:02:43 AM UTC 24
Finished Sep 01 09:02:45 AM UTC 24
Peak memory 215140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594859642 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.2594859642
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3612035946
Short name T350
Test name
Test status
Simulation time 58606027 ps
CPU time 1.1 seconds
Started Sep 01 09:02:47 AM UTC 24
Finished Sep 01 09:02:49 AM UTC 24
Peak memory 215140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612035946 -assert nopostproc +UVM
_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_partial_access.3612035946
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/2.rv_dm_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_walk.3731718446
Short name T349
Test name
Test status
Simulation time 37391223 ps
CPU time 1.06 seconds
Started Sep 01 09:02:47 AM UTC 24
Finished Sep 01 09:02:49 AM UTC 24
Peak memory 215080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731718446 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.3731718446
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/2.rv_dm_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2530685168
Short name T128
Test name
Test status
Simulation time 925419457 ps
CPU time 10.23 seconds
Started Sep 01 09:02:50 AM UTC 24
Finished Sep 01 09:03:02 AM UTC 24
Peak memory 215436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530685168 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_csr_outstanding.2530685168
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/2.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_errors.19919240
Short name T354
Test name
Test status
Simulation time 212412040 ps
CPU time 4.39 seconds
Started Sep 01 09:02:47 AM UTC 24
Finished Sep 01 09:02:52 AM UTC 24
Peak memory 225796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19919240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_
test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.19919240
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/2.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3925549278
Short name T209
Test name
Test status
Simulation time 7584336743 ps
CPU time 30.35 seconds
Started Sep 01 09:02:47 AM UTC 24
Finished Sep 01 09:03:19 AM UTC 24
Peak memory 232412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925549278 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.3925549278
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/2.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2910512866
Short name T154
Test name
Test status
Simulation time 2372982523 ps
CPU time 33.12 seconds
Started Sep 01 09:02:52 AM UTC 24
Finished Sep 01 09:03:26 AM UTC 24
Peak memory 215520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910512866 -ass
ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_aliasing.2910512866
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/3.rv_dm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1530735153
Short name T474
Test name
Test status
Simulation time 55933047357 ps
CPU time 84.2 seconds
Started Sep 01 09:02:59 AM UTC 24
Finished Sep 01 09:04:25 AM UTC 24
Peak memory 225628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530735153 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.1530735153
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/3.rv_dm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3917862640
Short name T127
Test name
Test status
Simulation time 345276643 ps
CPU time 4.04 seconds
Started Sep 01 09:02:56 AM UTC 24
Finished Sep 01 09:03:01 AM UTC 24
Peak memory 225624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917862640 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.3917862640
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/3.rv_dm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.458554087
Short name T367
Test name
Test status
Simulation time 57988897 ps
CPU time 2.82 seconds
Started Sep 01 09:02:59 AM UTC 24
Finished Sep 01 09:03:03 AM UTC 24
Peak memory 227908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=458554087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_ra
nd_reset.458554087
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_rw.1337362931
Short name T138
Test name
Test status
Simulation time 270019395 ps
CPU time 3.5 seconds
Started Sep 01 09:02:58 AM UTC 24
Finished Sep 01 09:03:02 AM UTC 24
Peak memory 225640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337362931 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.1337362931
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/3.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1185040028
Short name T372
Test name
Test status
Simulation time 21593440412 ps
CPU time 11.93 seconds
Started Sep 01 09:02:54 AM UTC 24
Finished Sep 01 09:03:07 AM UTC 24
Peak memory 215312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185040028 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_aliasing.1185040028
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.690439417
Short name T379
Test name
Test status
Simulation time 11830821344 ps
CPU time 19.2 seconds
Started Sep 01 09:02:53 AM UTC 24
Finished Sep 01 09:03:13 AM UTC 24
Peak memory 215360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690439417 -assert nopostpro
c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_bit_bash.690439417
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1263372133
Short name T136
Test name
Test status
Simulation time 2626385178 ps
CPU time 6.07 seconds
Started Sep 01 09:02:53 AM UTC 24
Finished Sep 01 09:03:00 AM UTC 24
Peak memory 215496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263372133 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_hw_reset.1263372133
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2561080311
Short name T371
Test name
Test status
Simulation time 3672659116 ps
CPU time 12.68 seconds
Started Sep 01 09:02:53 AM UTC 24
Finished Sep 01 09:03:07 AM UTC 24
Peak memory 215352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561080311 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.2561080311
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.4179932882
Short name T357
Test name
Test status
Simulation time 607392426 ps
CPU time 1.42 seconds
Started Sep 01 09:02:53 AM UTC 24
Finished Sep 01 09:02:55 AM UTC 24
Peak memory 215084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179932882 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_aliasing.4179932882
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3430183459
Short name T362
Test name
Test status
Simulation time 6201900170 ps
CPU time 7.6 seconds
Started Sep 01 09:02:52 AM UTC 24
Finished Sep 01 09:03:00 AM UTC 24
Peak memory 215428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430183459 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_bit_bash.3430183459
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3115156024
Short name T355
Test name
Test status
Simulation time 475029691 ps
CPU time 1.27 seconds
Started Sep 01 09:02:52 AM UTC 24
Finished Sep 01 09:02:54 AM UTC 24
Peak memory 215144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115156024 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_hw_reset.3115156024
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3257881339
Short name T356
Test name
Test status
Simulation time 120491000 ps
CPU time 1.62 seconds
Started Sep 01 09:02:52 AM UTC 24
Finished Sep 01 09:02:54 AM UTC 24
Peak memory 215080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257881339 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.3257881339
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3671439708
Short name T359
Test name
Test status
Simulation time 76536260 ps
CPU time 1.06 seconds
Started Sep 01 09:02:55 AM UTC 24
Finished Sep 01 09:02:57 AM UTC 24
Peak memory 215140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671439708 -assert nopostproc +UVM
_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_partial_access.3671439708
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/3.rv_dm_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_walk.140102290
Short name T358
Test name
Test status
Simulation time 68337598 ps
CPU time 1.05 seconds
Started Sep 01 09:02:55 AM UTC 24
Finished Sep 01 09:02:57 AM UTC 24
Peak memory 215080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140102290 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.140102290
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/3.rv_dm_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2489274277
Short name T141
Test name
Test status
Simulation time 1714958345 ps
CPU time 9.89 seconds
Started Sep 01 09:02:59 AM UTC 24
Finished Sep 01 09:03:10 AM UTC 24
Peak memory 215488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489274277 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_csr_outstanding.2489274277
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/3.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.1433266416
Short name T468
Test name
Test status
Simulation time 4528174865 ps
CPU time 70.9 seconds
Started Sep 01 09:02:54 AM UTC 24
Finished Sep 01 09:04:07 AM UTC 24
Peak memory 227844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=1433266416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_re
set.1433266416
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_errors.619852885
Short name T365
Test name
Test status
Simulation time 291154485 ps
CPU time 7.13 seconds
Started Sep 01 09:02:54 AM UTC 24
Finished Sep 01 09:03:02 AM UTC 24
Peak memory 225732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619852885 -assert nopostproc +UVM_TESTNAME=rv_dm_base
_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_d
m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.619852885
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/3.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3724883889
Short name T216
Test name
Test status
Simulation time 1845939196 ps
CPU time 26.6 seconds
Started Sep 01 09:02:55 AM UTC 24
Finished Sep 01 09:03:23 AM UTC 24
Peak memory 227704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724883889 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.3724883889
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/3.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_aliasing.920662998
Short name T160
Test name
Test status
Simulation time 3502778780 ps
CPU time 38.48 seconds
Started Sep 01 09:02:59 AM UTC 24
Finished Sep 01 09:03:39 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920662998 -asse
rt nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_aliasing.920662998
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/4.rv_dm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.304744802
Short name T419
Test name
Test status
Simulation time 2892567275 ps
CPU time 30.33 seconds
Started Sep 01 09:03:06 AM UTC 24
Finished Sep 01 09:03:38 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304744802 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.304744802
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/4.rv_dm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2263365933
Short name T140
Test name
Test status
Simulation time 226297579 ps
CPU time 3.62 seconds
Started Sep 01 09:03:04 AM UTC 24
Finished Sep 01 09:03:08 AM UTC 24
Peak memory 225668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263365933 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.2263365933
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/4.rv_dm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2052959430
Short name T168
Test name
Test status
Simulation time 100396147 ps
CPU time 2.4 seconds
Started Sep 01 09:03:07 AM UTC 24
Finished Sep 01 09:03:11 AM UTC 24
Peak memory 225804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=2052959430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_r
and_reset.2052959430
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_rw.841024292
Short name T139
Test name
Test status
Simulation time 41320353 ps
CPU time 1.97 seconds
Started Sep 01 09:03:05 AM UTC 24
Finished Sep 01 09:03:08 AM UTC 24
Peak memory 229196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841024292 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/r
v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.841024292
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/4.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.4193480186
Short name T482
Test name
Test status
Simulation time 67085273271 ps
CPU time 257.84 seconds
Started Sep 01 09:03:02 AM UTC 24
Finished Sep 01 09:07:24 AM UTC 24
Peak memory 214852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193480186 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_aliasing.4193480186
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.575056841
Short name T384
Test name
Test status
Simulation time 22452092587 ps
CPU time 15.61 seconds
Started Sep 01 09:03:02 AM UTC 24
Finished Sep 01 09:03:19 AM UTC 24
Peak memory 215360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575056841 -assert nopostpro
c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_bit_bash.575056841
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3852737518
Short name T137
Test name
Test status
Simulation time 5931928756 ps
CPU time 19.34 seconds
Started Sep 01 09:03:01 AM UTC 24
Finished Sep 01 09:03:22 AM UTC 24
Peak memory 215432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852737518 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_hw_reset.3852737518
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.172972326
Short name T373
Test name
Test status
Simulation time 5955018222 ps
CPU time 6.55 seconds
Started Sep 01 09:03:01 AM UTC 24
Finished Sep 01 09:03:09 AM UTC 24
Peak memory 215428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172972326 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.172972326
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1443175616
Short name T368
Test name
Test status
Simulation time 1143896843 ps
CPU time 1.9 seconds
Started Sep 01 09:03:01 AM UTC 24
Finished Sep 01 09:03:04 AM UTC 24
Peak memory 215084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443175616 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_aliasing.1443175616
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1654379636
Short name T381
Test name
Test status
Simulation time 16889477279 ps
CPU time 14.45 seconds
Started Sep 01 09:03:00 AM UTC 24
Finished Sep 01 09:03:16 AM UTC 24
Peak memory 215584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654379636 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_bit_bash.1654379636
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2836876306
Short name T364
Test name
Test status
Simulation time 367685243 ps
CPU time 1.75 seconds
Started Sep 01 09:02:59 AM UTC 24
Finished Sep 01 09:03:02 AM UTC 24
Peak memory 215084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836876306 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_hw_reset.2836876306
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2082125268
Short name T366
Test name
Test status
Simulation time 189133937 ps
CPU time 1.36 seconds
Started Sep 01 09:03:00 AM UTC 24
Finished Sep 01 09:03:02 AM UTC 24
Peak memory 215140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082125268 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.2082125268
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_partial_access.973771264
Short name T370
Test name
Test status
Simulation time 114737819 ps
CPU time 1.34 seconds
Started Sep 01 09:03:04 AM UTC 24
Finished Sep 01 09:03:06 AM UTC 24
Peak memory 215144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973771264 -assert nopostproc +UVM_
TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_partial_access.973771264
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/4.rv_dm_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_walk.496623599
Short name T369
Test name
Test status
Simulation time 36960832 ps
CPU time 1.06 seconds
Started Sep 01 09:03:04 AM UTC 24
Finished Sep 01 09:03:06 AM UTC 24
Peak memory 215080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496623599 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.496623599
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/4.rv_dm_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2876318280
Short name T161
Test name
Test status
Simulation time 184130732 ps
CPU time 4.72 seconds
Started Sep 01 09:03:06 AM UTC 24
Finished Sep 01 09:03:12 AM UTC 24
Peak memory 215464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876318280 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_csr_outstanding.2876318280
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/4.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3609208823
Short name T427
Test name
Test status
Simulation time 1744600932 ps
CPU time 37.47 seconds
Started Sep 01 09:03:02 AM UTC 24
Finished Sep 01 09:03:41 AM UTC 24
Peak memory 227304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3609208823 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_re
set.3609208823
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_errors.2508485428
Short name T167
Test name
Test status
Simulation time 1147875413 ps
CPU time 4.7 seconds
Started Sep 01 09:03:02 AM UTC 24
Finished Sep 01 09:03:08 AM UTC 24
Peak memory 225824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508485428 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2508485428
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/4.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.872404299
Short name T378
Test name
Test status
Simulation time 53297552 ps
CPU time 2.54 seconds
Started Sep 01 09:03:10 AM UTC 24
Finished Sep 01 09:03:13 AM UTC 24
Peak memory 225752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=872404299 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_ra
nd_reset.872404299
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_rw.1819701950
Short name T142
Test name
Test status
Simulation time 463229494 ps
CPU time 3.44 seconds
Started Sep 01 09:03:10 AM UTC 24
Finished Sep 01 09:03:14 AM UTC 24
Peak memory 231804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819701950 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.1819701950
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/5.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.661435544
Short name T395
Test name
Test status
Simulation time 14289135433 ps
CPU time 16.37 seconds
Started Sep 01 09:03:07 AM UTC 24
Finished Sep 01 09:03:25 AM UTC 24
Peak memory 215452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661435544 -assert nopostpro
c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_bit_bash.661435544
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1786318517
Short name T466
Test name
Test status
Simulation time 14087824172 ps
CPU time 53.45 seconds
Started Sep 01 09:03:07 AM UTC 24
Finished Sep 01 09:04:02 AM UTC 24
Peak memory 215360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786318517 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.1786318517
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3090785299
Short name T374
Test name
Test status
Simulation time 207592817 ps
CPU time 2 seconds
Started Sep 01 09:03:07 AM UTC 24
Finished Sep 01 09:03:10 AM UTC 24
Peak memory 215140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090785299 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.3090785299
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1327877551
Short name T162
Test name
Test status
Simulation time 1128353358 ps
CPU time 5.9 seconds
Started Sep 01 09:03:10 AM UTC 24
Finished Sep 01 09:03:17 AM UTC 24
Peak memory 215520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327877551 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_csr_outstanding.1327877551
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/5.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.211726368
Short name T469
Test name
Test status
Simulation time 5308355855 ps
CPU time 56.86 seconds
Started Sep 01 09:03:08 AM UTC 24
Finished Sep 01 09:04:07 AM UTC 24
Peak memory 227844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=211726368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.211726368
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_errors.761069943
Short name T375
Test name
Test status
Simulation time 129236159 ps
CPU time 2.94 seconds
Started Sep 01 09:03:08 AM UTC 24
Finished Sep 01 09:03:12 AM UTC 24
Peak memory 225768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761069943 -assert nopostproc +UVM_TESTNAME=rv_dm_base
_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_d
m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.761069943
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/5.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3405083959
Short name T219
Test name
Test status
Simulation time 2146595429 ps
CPU time 16.17 seconds
Started Sep 01 09:03:10 AM UTC 24
Finished Sep 01 09:03:27 AM UTC 24
Peak memory 225724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405083959 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.3405083959
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/5.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2107061836
Short name T382
Test name
Test status
Simulation time 77700361 ps
CPU time 1.92 seconds
Started Sep 01 09:03:13 AM UTC 24
Finished Sep 01 09:03:16 AM UTC 24
Peak memory 227132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=2107061836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_r
and_reset.2107061836
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_rw.1420759347
Short name T153
Test name
Test status
Simulation time 83175727 ps
CPU time 3.03 seconds
Started Sep 01 09:03:12 AM UTC 24
Finished Sep 01 09:03:16 AM UTC 24
Peak memory 225524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420759347 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.1420759347
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/6.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.4026054816
Short name T473
Test name
Test status
Simulation time 27252016543 ps
CPU time 66.96 seconds
Started Sep 01 09:03:11 AM UTC 24
Finished Sep 01 09:04:19 AM UTC 24
Peak memory 215360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026054816 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_bit_bash.4026054816
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1725294070
Short name T389
Test name
Test status
Simulation time 10849130911 ps
CPU time 10.24 seconds
Started Sep 01 09:03:10 AM UTC 24
Finished Sep 01 09:03:21 AM UTC 24
Peak memory 215364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725294070 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.1725294070
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1025442546
Short name T377
Test name
Test status
Simulation time 801869147 ps
CPU time 2.24 seconds
Started Sep 01 09:03:10 AM UTC 24
Finished Sep 01 09:03:13 AM UTC 24
Peak memory 215148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025442546 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.1025442546
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.213859218
Short name T145
Test name
Test status
Simulation time 330908056 ps
CPU time 7.65 seconds
Started Sep 01 09:03:13 AM UTC 24
Finished Sep 01 09:03:22 AM UTC 24
Peak memory 215364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213859218 -assert nopostproc +UV
M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_csr_outstanding.213859218
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/6.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.2406817629
Short name T101
Test name
Test status
Simulation time 13286976557 ps
CPU time 85.52 seconds
Started Sep 01 09:03:11 AM UTC 24
Finished Sep 01 09:04:38 AM UTC 24
Peak memory 230120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2406817629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_re
set.2406817629
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_errors.2896655813
Short name T380
Test name
Test status
Simulation time 67011028 ps
CPU time 2.46 seconds
Started Sep 01 09:03:11 AM UTC 24
Finished Sep 01 09:03:14 AM UTC 24
Peak memory 225888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896655813 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.2896655813
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/6.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3230499661
Short name T210
Test name
Test status
Simulation time 679693085 ps
CPU time 11.03 seconds
Started Sep 01 09:03:12 AM UTC 24
Finished Sep 01 09:03:24 AM UTC 24
Peak memory 225732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230499661 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.3230499661
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/6.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3505752372
Short name T387
Test name
Test status
Simulation time 212591680 ps
CPU time 2.58 seconds
Started Sep 01 09:03:17 AM UTC 24
Finished Sep 01 09:03:21 AM UTC 24
Peak memory 225760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=3505752372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_r
and_reset.3505752372
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_rw.565211272
Short name T386
Test name
Test status
Simulation time 124703699 ps
CPU time 2.29 seconds
Started Sep 01 09:03:17 AM UTC 24
Finished Sep 01 09:03:20 AM UTC 24
Peak memory 225696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565211272 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/r
v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.565211272
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/7.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.832407188
Short name T479
Test name
Test status
Simulation time 57182162453 ps
CPU time 183.65 seconds
Started Sep 01 09:03:15 AM UTC 24
Finished Sep 01 09:06:21 AM UTC 24
Peak memory 215288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832407188 -assert nopostpro
c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_bit_bash.832407188
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.292964680
Short name T391
Test name
Test status
Simulation time 6124710816 ps
CPU time 7.55 seconds
Started Sep 01 09:03:14 AM UTC 24
Finished Sep 01 09:03:23 AM UTC 24
Peak memory 215364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292964680 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.292964680
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3423661815
Short name T383
Test name
Test status
Simulation time 160865907 ps
CPU time 1.2 seconds
Started Sep 01 09:03:14 AM UTC 24
Finished Sep 01 09:03:17 AM UTC 24
Peak memory 215140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423661815 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.3423661815
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.318178707
Short name T146
Test name
Test status
Simulation time 375682611 ps
CPU time 6.39 seconds
Started Sep 01 09:03:17 AM UTC 24
Finished Sep 01 09:03:24 AM UTC 24
Peak memory 215520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318178707 -assert nopostproc +UV
M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_csr_outstanding.318178707
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/7.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.2821794687
Short name T103
Test name
Test status
Simulation time 2691632218 ps
CPU time 53.78 seconds
Started Sep 01 09:03:15 AM UTC 24
Finished Sep 01 09:04:10 AM UTC 24
Peak memory 227852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2821794687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_re
set.2821794687
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_errors.756136796
Short name T388
Test name
Test status
Simulation time 499714759 ps
CPU time 4.14 seconds
Started Sep 01 09:03:16 AM UTC 24
Finished Sep 01 09:03:21 AM UTC 24
Peak memory 225768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756136796 -assert nopostproc +UVM_TESTNAME=rv_dm_base
_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_d
m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.756136796
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/7.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_intg_err.4175929622
Short name T213
Test name
Test status
Simulation time 1629875526 ps
CPU time 13.55 seconds
Started Sep 01 09:03:16 AM UTC 24
Finished Sep 01 09:03:30 AM UTC 24
Peak memory 227748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175929622 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.4175929622
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/7.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.792647908
Short name T398
Test name
Test status
Simulation time 98114469 ps
CPU time 4.51 seconds
Started Sep 01 09:03:21 AM UTC 24
Finished Sep 01 09:03:26 AM UTC 24
Peak memory 231988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=792647908 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_ra
nd_reset.792647908
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_rw.3117787189
Short name T390
Test name
Test status
Simulation time 66244647 ps
CPU time 1.9 seconds
Started Sep 01 09:03:19 AM UTC 24
Finished Sep 01 09:03:22 AM UTC 24
Peak memory 229256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117787189 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.3117787189
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/8.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.3161974241
Short name T394
Test name
Test status
Simulation time 3268586739 ps
CPU time 4.94 seconds
Started Sep 01 09:03:18 AM UTC 24
Finished Sep 01 09:03:24 AM UTC 24
Peak memory 215360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161974241 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_bit_bash.3161974241
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1505131573
Short name T392
Test name
Test status
Simulation time 1848372593 ps
CPU time 5.46 seconds
Started Sep 01 09:03:17 AM UTC 24
Finished Sep 01 09:03:24 AM UTC 24
Peak memory 215488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505131573 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.1505131573
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3175556056
Short name T385
Test name
Test status
Simulation time 171986237 ps
CPU time 1.99 seconds
Started Sep 01 09:03:17 AM UTC 24
Finished Sep 01 09:03:20 AM UTC 24
Peak memory 215080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175556056 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.3175556056
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.848306612
Short name T148
Test name
Test status
Simulation time 1103806093 ps
CPU time 8.65 seconds
Started Sep 01 09:03:20 AM UTC 24
Finished Sep 01 09:03:30 AM UTC 24
Peak memory 215560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848306612 -assert nopostproc +UV
M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_csr_outstanding.848306612
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/8.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_errors.3779612146
Short name T393
Test name
Test status
Simulation time 599012250 ps
CPU time 4.72 seconds
Started Sep 01 09:03:18 AM UTC 24
Finished Sep 01 09:03:24 AM UTC 24
Peak memory 225720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779612146 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.3779612146
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/8.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3755088203
Short name T220
Test name
Test status
Simulation time 1325540507 ps
CPU time 12.28 seconds
Started Sep 01 09:03:19 AM UTC 24
Finished Sep 01 09:03:33 AM UTC 24
Peak memory 232288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755088203 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.3755088203
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/8.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.582499414
Short name T403
Test name
Test status
Simulation time 87636182 ps
CPU time 3.76 seconds
Started Sep 01 09:03:24 AM UTC 24
Finished Sep 01 09:03:29 AM UTC 24
Peak memory 231952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=582499414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_ra
nd_reset.582499414
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_rw.2932807745
Short name T147
Test name
Test status
Simulation time 142074165 ps
CPU time 2.99 seconds
Started Sep 01 09:03:23 AM UTC 24
Finished Sep 01 09:03:27 AM UTC 24
Peak memory 225660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932807745 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.2932807745
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/9.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.4194294585
Short name T412
Test name
Test status
Simulation time 8946501740 ps
CPU time 10.48 seconds
Started Sep 01 09:03:22 AM UTC 24
Finished Sep 01 09:03:33 AM UTC 24
Peak memory 215360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194294585 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_bit_bash.4194294585
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1090880475
Short name T410
Test name
Test status
Simulation time 1630950662 ps
CPU time 9.68 seconds
Started Sep 01 09:03:22 AM UTC 24
Finished Sep 01 09:03:32 AM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090880475 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.1090880475
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.6585403
Short name T396
Test name
Test status
Simulation time 490756848 ps
CPU time 2.49 seconds
Started Sep 01 09:03:22 AM UTC 24
Finished Sep 01 09:03:25 AM UTC 24
Peak memory 215144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6585403 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.6585403
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.671385670
Short name T150
Test name
Test status
Simulation time 732476585 ps
CPU time 7.86 seconds
Started Sep 01 09:03:24 AM UTC 24
Finished Sep 01 09:03:33 AM UTC 24
Peak memory 215428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671385670 -assert nopostproc +UV
M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_csr_outstanding.671385670
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/9.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_errors.2903391464
Short name T400
Test name
Test status
Simulation time 164597320 ps
CPU time 2.55 seconds
Started Sep 01 09:03:23 AM UTC 24
Finished Sep 01 09:03:26 AM UTC 24
Peak memory 225992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903391464 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.2903391464
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/9.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2193902703
Short name T221
Test name
Test status
Simulation time 2450605112 ps
CPU time 16.28 seconds
Started Sep 01 09:03:23 AM UTC 24
Finished Sep 01 09:03:40 AM UTC 24
Peak memory 225948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193902703 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.2193902703
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/9.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.1152601510
Short name T64
Test name
Test status
Simulation time 80891688 ps
CPU time 1.31 seconds
Started Sep 01 09:41:03 AM UTC 24
Finished Sep 01 09:41:05 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152601510 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.1152601510
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.2459839249
Short name T22
Test name
Test status
Simulation time 22881100169 ps
CPU time 18.74 seconds
Started Sep 01 09:40:39 AM UTC 24
Finished Sep 01 09:40:58 AM UTC 24
Peak memory 226632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459839249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.2459839249
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_busy.2973793281
Short name T11
Test name
Test status
Simulation time 317070993 ps
CPU time 1.82 seconds
Started Sep 01 09:40:39 AM UTC 24
Finished Sep 01 09:40:41 AM UTC 24
Peak memory 213340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973793281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.2973793281
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_cmderr_busy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.7071917
Short name T12
Test name
Test status
Simulation time 188656566 ps
CPU time 1.77 seconds
Started Sep 01 09:40:40 AM UTC 24
Finished Sep 01 09:40:43 AM UTC 24
Peak memory 213340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7071917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_
dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.7071917
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_cmderr_not_supported/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_dataaddr_rw_access.2532241496
Short name T5
Test name
Test status
Simulation time 269098016 ps
CPU time 2.6 seconds
Started Sep 01 09:40:53 AM UTC 24
Finished Sep 01 09:40:57 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532241496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.2532241496
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_dataaddr_rw_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_debug_disabled.4037896481
Short name T83
Test name
Test status
Simulation time 63436114 ps
CPU time 0.99 seconds
Started Sep 01 09:40:59 AM UTC 24
Finished Sep 01 09:41:01 AM UTC 24
Peak memory 236048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037896481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.4037896481
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_debug_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.3255268854
Short name T21
Test name
Test status
Simulation time 8465441810 ps
CPU time 25.71 seconds
Started Sep 01 09:40:30 AM UTC 24
Finished Sep 01 09:40:58 AM UTC 24
Peak memory 226556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255268854 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_tl_access.3255268854
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_hart_unavail.1678384809
Short name T45
Test name
Test status
Simulation time 112709558 ps
CPU time 1.78 seconds
Started Sep 01 09:40:49 AM UTC 24
Finished Sep 01 09:40:53 AM UTC 24
Peak memory 213452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678384809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.1678384809
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_hart_unavail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_hartsel_warl.3733086547
Short name T29
Test name
Test status
Simulation time 101896275 ps
CPU time 1.13 seconds
Started Sep 01 09:40:59 AM UTC 24
Finished Sep 01 09:41:02 AM UTC 24
Peak memory 213452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733086547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.3733086547
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_hartsel_warl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.3819260167
Short name T6
Test name
Test status
Simulation time 374748114 ps
CPU time 1.4 seconds
Started Sep 01 09:40:56 AM UTC 24
Finished Sep 01 09:40:58 AM UTC 24
Peak memory 213460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819260167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.3819260167
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.4173940690
Short name T16
Test name
Test status
Simulation time 2064764210 ps
CPU time 9.54 seconds
Started Sep 01 09:40:56 AM UTC 24
Finished Sep 01 09:41:06 AM UTC 24
Peak memory 215748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173940690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.4173940690
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_hard_reset.3693972893
Short name T7
Test name
Test status
Simulation time 106165160 ps
CPU time 1.34 seconds
Started Sep 01 09:40:57 AM UTC 24
Finished Sep 01 09:40:59 AM UTC 24
Peak memory 213452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693972893 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.3693972893
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_idle_hint.12447547
Short name T37
Test name
Test status
Simulation time 209448016 ps
CPU time 2.24 seconds
Started Sep 01 09:40:56 AM UTC 24
Finished Sep 01 09:40:59 AM UTC 24
Peak memory 215812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12447547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv
_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.12447547
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_halted.2400623284
Short name T44
Test name
Test status
Simulation time 428275889 ps
CPU time 3.3 seconds
Started Sep 01 09:40:49 AM UTC 24
Finished Sep 01 09:40:54 AM UTC 24
Peak memory 215748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400623284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.2400623284
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_halted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_resuming.361896485
Short name T14
Test name
Test status
Simulation time 366149208 ps
CPU time 1.73 seconds
Started Sep 01 09:40:49 AM UTC 24
Finished Sep 01 09:40:53 AM UTC 24
Peak memory 213384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361896485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.361896485
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.3250515367
Short name T15
Test name
Test status
Simulation time 408503065 ps
CPU time 1.78 seconds
Started Sep 01 09:40:54 AM UTC 24
Finished Sep 01 09:40:56 AM UTC 24
Peak memory 225852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250515367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.3250515367
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_ndmreset_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.700179903
Short name T43
Test name
Test status
Simulation time 251861214 ps
CPU time 1.12 seconds
Started Sep 01 09:40:59 AM UTC 24
Finished Sep 01 09:41:01 AM UTC 24
Peak memory 215944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700179903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_progbuf_read_write_execute_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.700179903
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_tl_access.1747759196
Short name T2
Test name
Test status
Simulation time 3620788309 ps
CPU time 8.3 seconds
Started Sep 01 09:40:20 AM UTC 24
Finished Sep 01 09:40:30 AM UTC 24
Peak memory 226628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747759196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.1747759196
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_smoke.3882210142
Short name T1
Test name
Test status
Simulation time 2461392661 ps
CPU time 10.11 seconds
Started Sep 01 09:40:06 AM UTC 24
Finished Sep 01 09:40:17 AM UTC 24
Peak memory 215936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882210142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.3882210142
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/0.rv_dm_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_abstractcmd_status.3688138614
Short name T56
Test name
Test status
Simulation time 92964974 ps
CPU time 1.15 seconds
Started Sep 01 09:41:19 AM UTC 24
Finished Sep 01 09:41:21 AM UTC 24
Peak memory 213456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688138614 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_abstractcmd_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.3688138614
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_abstractcmd_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_alert_test.4041819713
Short name T65
Test name
Test status
Simulation time 129255755 ps
CPU time 1.08 seconds
Started Sep 01 09:41:25 AM UTC 24
Finished Sep 01 09:41:27 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041819713 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.4041819713
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_bad_sba_tl_access.889475364
Short name T87
Test name
Test status
Simulation time 1914386431 ps
CPU time 6.85 seconds
Started Sep 01 09:41:06 AM UTC 24
Finished Sep 01 09:41:14 AM UTC 24
Peak memory 216132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889475364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.889475364
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_buffered_enable.2974771358
Short name T80
Test name
Test status
Simulation time 250459860 ps
CPU time 2.93 seconds
Started Sep 01 09:41:25 AM UTC 24
Finished Sep 01 09:41:29 AM UTC 24
Peak memory 256308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974771358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_buffered_enable.2974771358
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_busy.2135209209
Short name T32
Test name
Test status
Simulation time 1088774727 ps
CPU time 4.94 seconds
Started Sep 01 09:41:09 AM UTC 24
Finished Sep 01 09:41:16 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135209209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.2135209209
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_cmderr_busy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.494547874
Short name T31
Test name
Test status
Simulation time 367242524 ps
CPU time 2.96 seconds
Started Sep 01 09:41:11 AM UTC 24
Finished Sep 01 09:41:15 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494547874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_cmderr_exception_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.494547874
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_cmderr_exception/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.117134864
Short name T63
Test name
Test status
Simulation time 455263758 ps
CPU time 1.44 seconds
Started Sep 01 09:41:14 AM UTC 24
Finished Sep 01 09:41:16 AM UTC 24
Peak memory 213456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117134864 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_cmderr_halt_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.117134864
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_cmderr_halt_resume/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_not_supported.1612279148
Short name T46
Test name
Test status
Simulation time 144100642 ps
CPU time 1.57 seconds
Started Sep 01 09:41:10 AM UTC 24
Finished Sep 01 09:41:12 AM UTC 24
Peak memory 213460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612279148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.1612279148
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_cmderr_not_supported/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_dataaddr_rw_access.2531605710
Short name T92
Test name
Test status
Simulation time 451415883 ps
CPU time 1.3 seconds
Started Sep 01 09:41:15 AM UTC 24
Finished Sep 01 09:41:17 AM UTC 24
Peak memory 213396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531605710 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.2531605710
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_dataaddr_rw_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_debug_disabled.4266265760
Short name T79
Test name
Test status
Simulation time 280035619 ps
CPU time 1.45 seconds
Started Sep 01 09:41:25 AM UTC 24
Finished Sep 01 09:41:27 AM UTC 24
Peak memory 236048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266265760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.4266265760
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_debug_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.46205840
Short name T86
Test name
Test status
Simulation time 1596303815 ps
CPU time 2.88 seconds
Started Sep 01 09:41:05 AM UTC 24
Finished Sep 01 09:41:10 AM UTC 24
Peak memory 216124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46205840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_tl_access.46205840
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.661557859
Short name T70
Test name
Test status
Simulation time 146386238 ps
CPU time 1.79 seconds
Started Sep 01 09:41:25 AM UTC 24
Finished Sep 01 09:41:28 AM UTC 24
Peak memory 215940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661557859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_dmi_failed_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.661557859
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_dmi_failed_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_halt_resume_whereto.2324081234
Short name T48
Test name
Test status
Simulation time 177946070 ps
CPU time 1.91 seconds
Started Sep 01 09:41:15 AM UTC 24
Finished Sep 01 09:41:18 AM UTC 24
Peak memory 213452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324081234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.2324081234
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_halt_resume_whereto/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_hart_unavail.3896248305
Short name T90
Test name
Test status
Simulation time 122847653 ps
CPU time 1.03 seconds
Started Sep 01 09:41:13 AM UTC 24
Finished Sep 01 09:41:15 AM UTC 24
Peak memory 213452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896248305 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.3896248305
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_hart_unavail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.2057497533
Short name T230
Test name
Test status
Simulation time 702451237 ps
CPU time 3.42 seconds
Started Sep 01 09:41:17 AM UTC 24
Finished Sep 01 09:41:22 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057497533 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.2057497533
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.2064109031
Short name T231
Test name
Test status
Simulation time 1938438668 ps
CPU time 6.93 seconds
Started Sep 01 09:41:17 AM UTC 24
Finished Sep 01 09:41:25 AM UTC 24
Peak memory 215940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064109031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.2064109031
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_hard_reset.4255775514
Short name T71
Test name
Test status
Simulation time 174381606 ps
CPU time 1.22 seconds
Started Sep 01 09:41:19 AM UTC 24
Finished Sep 01 09:41:21 AM UTC 24
Peak memory 213452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255775514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.4255775514
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_idle_hint.710076417
Short name T72
Test name
Test status
Simulation time 268365988 ps
CPU time 2.82 seconds
Started Sep 01 09:41:16 AM UTC 24
Finished Sep 01 09:41:20 AM UTC 24
Peak memory 215792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710076417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.710076417
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_halted.3045726375
Short name T229
Test name
Test status
Simulation time 569564682 ps
CPU time 4.38 seconds
Started Sep 01 09:41:13 AM UTC 24
Finished Sep 01 09:41:18 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045726375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.3045726375
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_mem_tl_access_halted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_resuming.1848307183
Short name T91
Test name
Test status
Simulation time 654776703 ps
CPU time 1.54 seconds
Started Sep 01 09:41:13 AM UTC 24
Finished Sep 01 09:41:15 AM UTC 24
Peak memory 213464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848307183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.1848307183
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_ndmreset_req.2621974844
Short name T40
Test name
Test status
Simulation time 708797168 ps
CPU time 5.62 seconds
Started Sep 01 09:41:16 AM UTC 24
Finished Sep 01 09:41:23 AM UTC 24
Peak memory 226024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621974844 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.2621974844
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_ndmreset_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_progbuf_read_write_execute.481730644
Short name T53
Test name
Test status
Simulation time 203148699 ps
CPU time 1.47 seconds
Started Sep 01 09:41:25 AM UTC 24
Finished Sep 01 09:41:27 AM UTC 24
Peak memory 215944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481730644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_progbuf_read_write_execute_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.481730644
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_rom_read_access.3629075214
Short name T59
Test name
Test status
Simulation time 194848382 ps
CPU time 1.18 seconds
Started Sep 01 09:41:19 AM UTC 24
Finished Sep 01 09:41:21 AM UTC 24
Peak memory 225792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629075214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_rom_read_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.3629075214
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_rom_read_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_debug_disabled.793427186
Short name T178
Test name
Test status
Simulation time 2450347529 ps
CPU time 3.32 seconds
Started Sep 01 09:41:16 AM UTC 24
Finished Sep 01 09:41:20 AM UTC 24
Peak memory 216148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793427186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_sba_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.793427186
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_sba_debug_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_tl_access.2935618263
Short name T129
Test name
Test status
Simulation time 5584430583 ps
CPU time 23.83 seconds
Started Sep 01 09:41:04 AM UTC 24
Finished Sep 01 09:41:30 AM UTC 24
Peak memory 216400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935618263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.2935618263
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_sec_cm.4178708379
Short name T81
Test name
Test status
Simulation time 744030436 ps
CPU time 2.72 seconds
Started Sep 01 09:41:25 AM UTC 24
Finished Sep 01 09:41:29 AM UTC 24
Peak memory 254812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178708379 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.4178708379
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_smoke.1562237400
Short name T75
Test name
Test status
Simulation time 3138628086 ps
CPU time 9.28 seconds
Started Sep 01 09:41:03 AM UTC 24
Finished Sep 01 09:41:14 AM UTC 24
Peak memory 216080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562237400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.1562237400
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.3668914778
Short name T69
Test name
Test status
Simulation time 138995759 ps
CPU time 1.28 seconds
Started Sep 01 09:41:25 AM UTC 24
Finished Sep 01 09:41:27 AM UTC 24
Peak memory 225856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668914778 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sparse_lc_gate_fsm.3668914778
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_sparse_lc_gate_fsm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.967185522
Short name T54
Test name
Test status
Simulation time 684201156 ps
CPU time 29.36 seconds
Started Sep 01 09:41:25 AM UTC 24
Finished Sep 01 09:41:56 AM UTC 24
Peak memory 228560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=967185522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress
_all_with_rand_reset.967185522
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/10.rv_dm_alert_test.1390696088
Short name T245
Test name
Test status
Simulation time 61808984 ps
CPU time 0.99 seconds
Started Sep 01 09:42:36 AM UTC 24
Finished Sep 01 09:42:38 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390696088 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.1390696088
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/10.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/10.rv_dm_autoincr_sba_tl_access.3964956202
Short name T246
Test name
Test status
Simulation time 957632488 ps
CPU time 2.19 seconds
Started Sep 01 09:42:35 AM UTC 24
Finished Sep 01 09:42:38 AM UTC 24
Peak memory 216252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964956202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.3964956202
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/10.rv_dm_bad_sba_tl_access.1434892151
Short name T255
Test name
Test status
Simulation time 11735643099 ps
CPU time 18.4 seconds
Started Sep 01 09:42:34 AM UTC 24
Finished Sep 01 09:42:54 AM UTC 24
Peak memory 226632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434892151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.1434892151
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/10.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.1880005597
Short name T205
Test name
Test status
Simulation time 3036203181 ps
CPU time 7.05 seconds
Started Sep 01 09:42:34 AM UTC 24
Finished Sep 01 09:42:42 AM UTC 24
Peak memory 226624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880005597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_tl_access.1880005597
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/10.rv_dm_sba_tl_access.451564160
Short name T247
Test name
Test status
Simulation time 3302315890 ps
CPU time 6.12 seconds
Started Sep 01 09:42:33 AM UTC 24
Finished Sep 01 09:42:40 AM UTC 24
Peak memory 216328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451564160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.451564160
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/10.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/10.rv_dm_stress_all.4022280012
Short name T33
Test name
Test status
Simulation time 2774606519 ps
CPU time 1.86 seconds
Started Sep 01 09:42:36 AM UTC 24
Finished Sep 01 09:42:39 AM UTC 24
Peak memory 215996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022280012 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.4022280012
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/10.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/11.rv_dm_alert_test.2459320583
Short name T249
Test name
Test status
Simulation time 77151862 ps
CPU time 1.08 seconds
Started Sep 01 09:42:39 AM UTC 24
Finished Sep 01 09:42:41 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459320583 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.2459320583
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/11.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/11.rv_dm_autoincr_sba_tl_access.1734956336
Short name T334
Test name
Test status
Simulation time 128256923612 ps
CPU time 530.2 seconds
Started Sep 01 09:42:39 AM UTC 24
Finished Sep 01 09:51:36 AM UTC 24
Peak memory 232708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734956336 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.1734956336
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/11.rv_dm_bad_sba_tl_access.4038574749
Short name T171
Test name
Test status
Simulation time 3228686152 ps
CPU time 19.2 seconds
Started Sep 01 09:42:39 AM UTC 24
Finished Sep 01 09:42:59 AM UTC 24
Peak memory 216260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038574749 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.4038574749
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/11.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.2367190809
Short name T187
Test name
Test status
Simulation time 3530959951 ps
CPU time 5.35 seconds
Started Sep 01 09:42:39 AM UTC 24
Finished Sep 01 09:42:45 AM UTC 24
Peak memory 216244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367190809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_tl_access.2367190809
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/11.rv_dm_sba_tl_access.546702777
Short name T206
Test name
Test status
Simulation time 1873029459 ps
CPU time 6.25 seconds
Started Sep 01 09:42:36 AM UTC 24
Finished Sep 01 09:42:44 AM UTC 24
Peak memory 216252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546702777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.546702777
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/11.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/11.rv_dm_stress_all.2406371403
Short name T197
Test name
Test status
Simulation time 6115456317 ps
CPU time 13.44 seconds
Started Sep 01 09:42:39 AM UTC 24
Finished Sep 01 09:42:53 AM UTC 24
Peak memory 216204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406371403 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.2406371403
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/11.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/12.rv_dm_alert_test.1969415250
Short name T250
Test name
Test status
Simulation time 71873709 ps
CPU time 1.37 seconds
Started Sep 01 09:42:43 AM UTC 24
Finished Sep 01 09:42:45 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969415250 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.1969415250
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/12.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/12.rv_dm_autoincr_sba_tl_access.3972770387
Short name T261
Test name
Test status
Simulation time 6154949785 ps
CPU time 27.27 seconds
Started Sep 01 09:42:41 AM UTC 24
Finished Sep 01 09:43:10 AM UTC 24
Peak memory 226556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972770387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.3972770387
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/12.rv_dm_bad_sba_tl_access.315147020
Short name T191
Test name
Test status
Simulation time 4171315933 ps
CPU time 4.95 seconds
Started Sep 01 09:42:41 AM UTC 24
Finished Sep 01 09:42:47 AM UTC 24
Peak memory 216328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315147020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.315147020
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/12.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.625111
Short name T251
Test name
Test status
Simulation time 2457678810 ps
CPU time 5.41 seconds
Started Sep 01 09:42:40 AM UTC 24
Finished Sep 01 09:42:46 AM UTC 24
Peak memory 216460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UV
M_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_tl_access.625111
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/12.rv_dm_sba_tl_access.2639892040
Short name T252
Test name
Test status
Simulation time 1179356110 ps
CPU time 6.64 seconds
Started Sep 01 09:42:40 AM UTC 24
Finished Sep 01 09:42:48 AM UTC 24
Peak memory 216196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639892040 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.2639892040
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/12.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/12.rv_dm_stress_all.1613041405
Short name T18
Test name
Test status
Simulation time 1368470275 ps
CPU time 3.62 seconds
Started Sep 01 09:42:41 AM UTC 24
Finished Sep 01 09:42:46 AM UTC 24
Peak memory 226388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613041405 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.1613041405
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/12.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/13.rv_dm_alert_test.1405317563
Short name T224
Test name
Test status
Simulation time 118073441 ps
CPU time 1.58 seconds
Started Sep 01 09:42:48 AM UTC 24
Finished Sep 01 09:42:51 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405317563 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.1405317563
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/13.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/13.rv_dm_autoincr_sba_tl_access.3639718258
Short name T256
Test name
Test status
Simulation time 4442801913 ps
CPU time 8.03 seconds
Started Sep 01 09:42:46 AM UTC 24
Finished Sep 01 09:42:55 AM UTC 24
Peak memory 226560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639718258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.3639718258
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/13.rv_dm_bad_sba_tl_access.1377621427
Short name T192
Test name
Test status
Simulation time 2154214620 ps
CPU time 5.88 seconds
Started Sep 01 09:42:46 AM UTC 24
Finished Sep 01 09:42:52 AM UTC 24
Peak memory 216328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377621427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.1377621427
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/13.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.2543824793
Short name T257
Test name
Test status
Simulation time 5569263071 ps
CPU time 20.5 seconds
Started Sep 01 09:42:44 AM UTC 24
Finished Sep 01 09:43:06 AM UTC 24
Peak memory 216308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543824793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_tl_access.2543824793
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/13.rv_dm_sba_tl_access.186996616
Short name T254
Test name
Test status
Simulation time 3354967571 ps
CPU time 8.22 seconds
Started Sep 01 09:42:44 AM UTC 24
Finished Sep 01 09:42:54 AM UTC 24
Peak memory 216432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186996616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.186996616
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/13.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/13.rv_dm_stress_all.606807576
Short name T262
Test name
Test status
Simulation time 4444145149 ps
CPU time 22.12 seconds
Started Sep 01 09:42:47 AM UTC 24
Finished Sep 01 09:43:10 AM UTC 24
Peak memory 216076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606807576 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.606807576
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/13.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/14.rv_dm_alert_test.3531754984
Short name T169
Test name
Test status
Simulation time 31590111 ps
CPU time 1.18 seconds
Started Sep 01 09:42:55 AM UTC 24
Finished Sep 01 09:42:57 AM UTC 24
Peak memory 215824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531754984 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.3531754984
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/14.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/14.rv_dm_autoincr_sba_tl_access.668463283
Short name T332
Test name
Test status
Simulation time 23434179152 ps
CPU time 109.98 seconds
Started Sep 01 09:42:51 AM UTC 24
Finished Sep 01 09:44:45 AM UTC 24
Peak memory 226548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668463283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.668463283
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/14.rv_dm_bad_sba_tl_access.3327958978
Short name T202
Test name
Test status
Simulation time 10141331643 ps
CPU time 21.13 seconds
Started Sep 01 09:42:49 AM UTC 24
Finished Sep 01 09:43:12 AM UTC 24
Peak memory 226432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327958978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.3327958978
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/14.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.4062351028
Short name T259
Test name
Test status
Simulation time 5333842268 ps
CPU time 17.97 seconds
Started Sep 01 09:42:49 AM UTC 24
Finished Sep 01 09:43:08 AM UTC 24
Peak memory 226536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062351028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_tl_access.4062351028
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/14.rv_dm_sba_tl_access.2433357433
Short name T270
Test name
Test status
Simulation time 6382846385 ps
CPU time 27.66 seconds
Started Sep 01 09:42:48 AM UTC 24
Finished Sep 01 09:43:17 AM UTC 24
Peak memory 226492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433357433 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.2433357433
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/14.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/14.rv_dm_stress_all.3179911862
Short name T176
Test name
Test status
Simulation time 3297672710 ps
CPU time 7.22 seconds
Started Sep 01 09:42:55 AM UTC 24
Finished Sep 01 09:43:03 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179911862 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.3179911862
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/14.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/15.rv_dm_alert_test.1366275083
Short name T173
Test name
Test status
Simulation time 39160397 ps
CPU time 1.04 seconds
Started Sep 01 09:42:59 AM UTC 24
Finished Sep 01 09:43:01 AM UTC 24
Peak memory 215864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366275083 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.1366275083
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/15.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/15.rv_dm_autoincr_sba_tl_access.464134771
Short name T183
Test name
Test status
Simulation time 26808401916 ps
CPU time 42.71 seconds
Started Sep 01 09:42:57 AM UTC 24
Finished Sep 01 09:43:42 AM UTC 24
Peak memory 228596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464134771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.464134771
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/15.rv_dm_bad_sba_tl_access.298233592
Short name T174
Test name
Test status
Simulation time 1228074682 ps
CPU time 5.04 seconds
Started Sep 01 09:42:56 AM UTC 24
Finished Sep 01 09:43:02 AM UTC 24
Peak memory 216252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298233592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.298233592
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/15.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2595276914
Short name T172
Test name
Test status
Simulation time 1380939013 ps
CPU time 3.74 seconds
Started Sep 01 09:42:55 AM UTC 24
Finished Sep 01 09:43:00 AM UTC 24
Peak memory 216320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595276914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_tl_access.2595276914
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/15.rv_dm_sba_tl_access.2807127712
Short name T266
Test name
Test status
Simulation time 7465732655 ps
CPU time 18.33 seconds
Started Sep 01 09:42:55 AM UTC 24
Finished Sep 01 09:43:14 AM UTC 24
Peak memory 226592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807127712 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.2807127712
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/15.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/15.rv_dm_stress_all.325119941
Short name T189
Test name
Test status
Simulation time 3930238667 ps
CPU time 18.3 seconds
Started Sep 01 09:42:58 AM UTC 24
Finished Sep 01 09:43:18 AM UTC 24
Peak memory 216072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325119941 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.325119941
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/15.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/16.rv_dm_alert_test.2121806157
Short name T258
Test name
Test status
Simulation time 54910851 ps
CPU time 1.04 seconds
Started Sep 01 09:43:04 AM UTC 24
Finished Sep 01 09:43:07 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121806157 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.2121806157
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/16.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/16.rv_dm_autoincr_sba_tl_access.4155412970
Short name T329
Test name
Test status
Simulation time 16899447139 ps
CPU time 59.4 seconds
Started Sep 01 09:43:03 AM UTC 24
Finished Sep 01 09:44:04 AM UTC 24
Peak memory 226696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155412970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.4155412970
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/16.rv_dm_bad_sba_tl_access.1529702991
Short name T188
Test name
Test status
Simulation time 2342784347 ps
CPU time 6.95 seconds
Started Sep 01 09:43:03 AM UTC 24
Finished Sep 01 09:43:11 AM UTC 24
Peak memory 216208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529702991 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.1529702991
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/16.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.2210699047
Short name T278
Test name
Test status
Simulation time 11366175306 ps
CPU time 18.3 seconds
Started Sep 01 09:43:03 AM UTC 24
Finished Sep 01 09:43:23 AM UTC 24
Peak memory 226548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210699047 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_tl_access.2210699047
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/16.rv_dm_sba_tl_access.3282729318
Short name T177
Test name
Test status
Simulation time 1971452444 ps
CPU time 5.03 seconds
Started Sep 01 09:43:00 AM UTC 24
Finished Sep 01 09:43:06 AM UTC 24
Peak memory 216320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282729318 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.3282729318
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/16.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/16.rv_dm_stress_all.3639746968
Short name T260
Test name
Test status
Simulation time 1659877788 ps
CPU time 4.97 seconds
Started Sep 01 09:43:03 AM UTC 24
Finished Sep 01 09:43:09 AM UTC 24
Peak memory 226188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639746968 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.3639746968
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/16.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/17.rv_dm_alert_test.3484863012
Short name T263
Test name
Test status
Simulation time 64457376 ps
CPU time 1.29 seconds
Started Sep 01 09:43:10 AM UTC 24
Finished Sep 01 09:43:12 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484863012 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.3484863012
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/17.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/17.rv_dm_autoincr_sba_tl_access.3961761042
Short name T196
Test name
Test status
Simulation time 10665516443 ps
CPU time 9.25 seconds
Started Sep 01 09:43:08 AM UTC 24
Finished Sep 01 09:43:18 AM UTC 24
Peak memory 226556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961761042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.3961761042
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/17.rv_dm_bad_sba_tl_access.2196512691
Short name T265
Test name
Test status
Simulation time 5493539026 ps
CPU time 4.85 seconds
Started Sep 01 09:43:07 AM UTC 24
Finished Sep 01 09:43:13 AM UTC 24
Peak memory 226500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196512691 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.2196512691
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/17.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.2253506141
Short name T264
Test name
Test status
Simulation time 2473556500 ps
CPU time 4.89 seconds
Started Sep 01 09:43:06 AM UTC 24
Finished Sep 01 09:43:13 AM UTC 24
Peak memory 216320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253506141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_tl_access.2253506141
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/17.rv_dm_sba_tl_access.3488403529
Short name T276
Test name
Test status
Simulation time 3258876069 ps
CPU time 15.56 seconds
Started Sep 01 09:43:04 AM UTC 24
Finished Sep 01 09:43:22 AM UTC 24
Peak memory 216316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488403529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.3488403529
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/17.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/17.rv_dm_stress_all.998815046
Short name T35
Test name
Test status
Simulation time 3849561248 ps
CPU time 6.31 seconds
Started Sep 01 09:43:09 AM UTC 24
Finished Sep 01 09:43:17 AM UTC 24
Peak memory 226312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998815046 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.998815046
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/17.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/18.rv_dm_alert_test.4226248595
Short name T268
Test name
Test status
Simulation time 29387805 ps
CPU time 1 seconds
Started Sep 01 09:43:15 AM UTC 24
Finished Sep 01 09:43:17 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226248595 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.4226248595
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/18.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/18.rv_dm_bad_sba_tl_access.3258714268
Short name T267
Test name
Test status
Simulation time 2422538712 ps
CPU time 3.81 seconds
Started Sep 01 09:43:11 AM UTC 24
Finished Sep 01 09:43:16 AM UTC 24
Peak memory 216328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258714268 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.3258714268
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/18.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.469912263
Short name T269
Test name
Test status
Simulation time 5706208941 ps
CPU time 4.81 seconds
Started Sep 01 09:43:11 AM UTC 24
Finished Sep 01 09:43:17 AM UTC 24
Peak memory 216384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469912263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_tl_access.469912263
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/18.rv_dm_sba_tl_access.2993904952
Short name T273
Test name
Test status
Simulation time 5554831062 ps
CPU time 8.5 seconds
Started Sep 01 09:43:11 AM UTC 24
Finished Sep 01 09:43:21 AM UTC 24
Peak memory 216264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993904952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.2993904952
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/18.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/18.rv_dm_stress_all.1421428108
Short name T28
Test name
Test status
Simulation time 2919205685 ps
CPU time 4.15 seconds
Started Sep 01 09:43:15 AM UTC 24
Finished Sep 01 09:43:20 AM UTC 24
Peak memory 216072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421428108 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.1421428108
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/18.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/19.rv_dm_alert_test.1685481115
Short name T271
Test name
Test status
Simulation time 60678189 ps
CPU time 1.17 seconds
Started Sep 01 09:43:17 AM UTC 24
Finished Sep 01 09:43:20 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685481115 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.1685481115
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/19.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.3894952985
Short name T333
Test name
Test status
Simulation time 24162587347 ps
CPU time 165.63 seconds
Started Sep 01 09:43:16 AM UTC 24
Finished Sep 01 09:46:05 AM UTC 24
Peak memory 216316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894952985 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.3894952985
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/19.rv_dm_bad_sba_tl_access.2250734188
Short name T295
Test name
Test status
Simulation time 3417250911 ps
CPU time 18.09 seconds
Started Sep 01 09:43:15 AM UTC 24
Finished Sep 01 09:43:34 AM UTC 24
Peak memory 226628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250734188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.2250734188
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/19.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2752549664
Short name T272
Test name
Test status
Simulation time 1531592394 ps
CPU time 3.89 seconds
Started Sep 01 09:43:15 AM UTC 24
Finished Sep 01 09:43:20 AM UTC 24
Peak memory 216252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752549664 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_tl_access.2752549664
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/19.rv_dm_sba_tl_access.1119990915
Short name T283
Test name
Test status
Simulation time 2888983063 ps
CPU time 10.68 seconds
Started Sep 01 09:43:15 AM UTC 24
Finished Sep 01 09:43:27 AM UTC 24
Peak memory 216276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119990915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.1119990915
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/19.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.722767463
Short name T36
Test name
Test status
Simulation time 4184252187 ps
CPU time 6.18 seconds
Started Sep 01 09:43:17 AM UTC 24
Finished Sep 01 09:43:25 AM UTC 24
Peak memory 226324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722767463 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.722767463
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/19.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.2560227133
Short name T66
Test name
Test status
Simulation time 66431690 ps
CPU time 1.49 seconds
Started Sep 01 09:41:33 AM UTC 24
Finished Sep 01 09:41:36 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560227133 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.2560227133
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/2.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.2707962053
Short name T24
Test name
Test status
Simulation time 11223548427 ps
CPU time 41.74 seconds
Started Sep 01 09:41:33 AM UTC 24
Finished Sep 01 09:42:16 AM UTC 24
Peak memory 226560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707962053 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.2707962053
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.2648651187
Short name T113
Test name
Test status
Simulation time 11434975743 ps
CPU time 26.75 seconds
Started Sep 01 09:41:33 AM UTC 24
Finished Sep 01 09:42:01 AM UTC 24
Peak memory 226556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648651187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.2648651187
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/2.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.2067927544
Short name T57
Test name
Test status
Simulation time 161199924 ps
CPU time 1.25 seconds
Started Sep 01 09:41:33 AM UTC 24
Finished Sep 01 09:41:35 AM UTC 24
Peak memory 252352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067927544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_buffered_enable.2067927544
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/2.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.848045698
Short name T130
Test name
Test status
Simulation time 2847230223 ps
CPU time 4.43 seconds
Started Sep 01 09:41:26 AM UTC 24
Finished Sep 01 09:41:32 AM UTC 24
Peak memory 226500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848045698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_tl_access.848045698
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.585519052
Short name T50
Test name
Test status
Simulation time 215598411 ps
CPU time 2.43 seconds
Started Sep 01 09:41:33 AM UTC 24
Finished Sep 01 09:41:36 AM UTC 24
Peak memory 216000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585519052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_halt_resume_whereto.585519052
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/2.rv_dm_halt_resume_whereto/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.2065253768
Short name T93
Test name
Test status
Simulation time 396502720 ps
CPU time 3.27 seconds
Started Sep 01 09:41:33 AM UTC 24
Finished Sep 01 09:41:37 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065253768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.2065253768
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/2.rv_dm_hart_unavail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.4267322275
Short name T94
Test name
Test status
Simulation time 16509640869 ps
CPU time 11.16 seconds
Started Sep 01 09:41:25 AM UTC 24
Finished Sep 01 09:41:38 AM UTC 24
Peak memory 226512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267322275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.4267322275
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/2.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.3783415824
Short name T82
Test name
Test status
Simulation time 951673634 ps
CPU time 3.27 seconds
Started Sep 01 09:41:33 AM UTC 24
Finished Sep 01 09:41:37 AM UTC 24
Peak memory 254556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783415824 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.3783415824
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/2.rv_dm_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all.1164144575
Short name T47
Test name
Test status
Simulation time 3583587229 ps
CPU time 5.38 seconds
Started Sep 01 09:41:33 AM UTC 24
Finished Sep 01 09:41:39 AM UTC 24
Peak memory 226248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164144575 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.1164144575
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/2.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/20.rv_dm_alert_test.1278483750
Short name T274
Test name
Test status
Simulation time 43143481 ps
CPU time 1.23 seconds
Started Sep 01 09:43:19 AM UTC 24
Finished Sep 01 09:43:21 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278483750 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.1278483750
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/20.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.3287765613
Short name T286
Test name
Test status
Simulation time 4206275348 ps
CPU time 9.96 seconds
Started Sep 01 09:43:17 AM UTC 24
Finished Sep 01 09:43:29 AM UTC 24
Peak memory 216064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287765613 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.3287765613
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/20.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/21.rv_dm_alert_test.3226699635
Short name T275
Test name
Test status
Simulation time 66476938 ps
CPU time 1.31 seconds
Started Sep 01 09:43:19 AM UTC 24
Finished Sep 01 09:43:21 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226699635 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.3226699635
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/21.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/21.rv_dm_stress_all.2211672177
Short name T207
Test name
Test status
Simulation time 4884130697 ps
CPU time 6.87 seconds
Started Sep 01 09:43:19 AM UTC 24
Finished Sep 01 09:43:27 AM UTC 24
Peak memory 216140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211672177 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.2211672177
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/21.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/22.rv_dm_alert_test.45425950
Short name T277
Test name
Test status
Simulation time 90475772 ps
CPU time 1.01 seconds
Started Sep 01 09:43:20 AM UTC 24
Finished Sep 01 09:43:22 AM UTC 24
Peak memory 215932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45425950 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.45425950
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/22.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.713295069
Short name T198
Test name
Test status
Simulation time 6358753445 ps
CPU time 7.88 seconds
Started Sep 01 09:43:19 AM UTC 24
Finished Sep 01 09:43:28 AM UTC 24
Peak memory 226384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713295069 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.713295069
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/22.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/23.rv_dm_alert_test.1884488642
Short name T279
Test name
Test status
Simulation time 45765092 ps
CPU time 1.12 seconds
Started Sep 01 09:43:22 AM UTC 24
Finished Sep 01 09:43:24 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884488642 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.1884488642
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/23.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/23.rv_dm_stress_all.1042886335
Short name T203
Test name
Test status
Simulation time 4943051342 ps
CPU time 11.21 seconds
Started Sep 01 09:43:22 AM UTC 24
Finished Sep 01 09:43:34 AM UTC 24
Peak memory 216204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042886335 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.1042886335
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/23.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/24.rv_dm_alert_test.1029865106
Short name T280
Test name
Test status
Simulation time 125593277 ps
CPU time 1.59 seconds
Started Sep 01 09:43:22 AM UTC 24
Finished Sep 01 09:43:24 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029865106 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.1029865106
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/24.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/24.rv_dm_stress_all.3671019516
Short name T39
Test name
Test status
Simulation time 5425685228 ps
CPU time 12.47 seconds
Started Sep 01 09:43:22 AM UTC 24
Finished Sep 01 09:43:35 AM UTC 24
Peak memory 216072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671019516 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.3671019516
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/24.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/25.rv_dm_alert_test.1730893093
Short name T281
Test name
Test status
Simulation time 59476083 ps
CPU time 0.91 seconds
Started Sep 01 09:43:23 AM UTC 24
Finished Sep 01 09:43:25 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730893093 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.1730893093
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/25.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.2800061510
Short name T287
Test name
Test status
Simulation time 1503404897 ps
CPU time 5.86 seconds
Started Sep 01 09:43:23 AM UTC 24
Finished Sep 01 09:43:30 AM UTC 24
Peak memory 226304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800061510 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.2800061510
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/25.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/26.rv_dm_alert_test.3360633439
Short name T282
Test name
Test status
Simulation time 165268731 ps
CPU time 1.46 seconds
Started Sep 01 09:43:24 AM UTC 24
Finished Sep 01 09:43:27 AM UTC 24
Peak memory 215860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360633439 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.3360633439
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/26.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/26.rv_dm_stress_all.1437374005
Short name T19
Test name
Test status
Simulation time 4148968946 ps
CPU time 15.78 seconds
Started Sep 01 09:43:23 AM UTC 24
Finished Sep 01 09:43:40 AM UTC 24
Peak memory 216076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437374005 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.1437374005
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/26.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/27.rv_dm_alert_test.2666952407
Short name T284
Test name
Test status
Simulation time 48327131 ps
CPU time 1.09 seconds
Started Sep 01 09:43:26 AM UTC 24
Finished Sep 01 09:43:28 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666952407 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.2666952407
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/27.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.2545851181
Short name T303
Test name
Test status
Simulation time 2615911648 ps
CPU time 12.63 seconds
Started Sep 01 09:43:24 AM UTC 24
Finished Sep 01 09:43:38 AM UTC 24
Peak memory 216260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545851181 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.2545851181
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/27.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/28.rv_dm_alert_test.4164988636
Short name T285
Test name
Test status
Simulation time 93381039 ps
CPU time 1.03 seconds
Started Sep 01 09:43:26 AM UTC 24
Finished Sep 01 09:43:28 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164988636 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.4164988636
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/28.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/28.rv_dm_stress_all.1493491280
Short name T291
Test name
Test status
Simulation time 2171893540 ps
CPU time 5.53 seconds
Started Sep 01 09:43:26 AM UTC 24
Finished Sep 01 09:43:33 AM UTC 24
Peak memory 226324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493491280 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.1493491280
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/28.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/29.rv_dm_alert_test.3720902712
Short name T288
Test name
Test status
Simulation time 66778996 ps
CPU time 1.11 seconds
Started Sep 01 09:43:28 AM UTC 24
Finished Sep 01 09:43:31 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720902712 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.3720902712
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/29.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.446897418
Short name T85
Test name
Test status
Simulation time 130458923 ps
CPU time 1.74 seconds
Started Sep 01 09:41:40 AM UTC 24
Finished Sep 01 09:41:43 AM UTC 24
Peak memory 215996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446897418 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.446897418
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/3.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.1714653895
Short name T111
Test name
Test status
Simulation time 7273257978 ps
CPU time 34.07 seconds
Started Sep 01 09:41:36 AM UTC 24
Finished Sep 01 09:42:12 AM UTC 24
Peak memory 216332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714653895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.1714653895
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.744289412
Short name T95
Test name
Test status
Simulation time 1985690754 ps
CPU time 5.39 seconds
Started Sep 01 09:41:36 AM UTC 24
Finished Sep 01 09:41:43 AM UTC 24
Peak memory 216264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744289412 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.744289412
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/3.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.2600682580
Short name T131
Test name
Test status
Simulation time 148371256 ps
CPU time 1.48 seconds
Started Sep 01 09:41:37 AM UTC 24
Finished Sep 01 09:41:40 AM UTC 24
Peak memory 257144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600682580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_buffered_enable.2600682580
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/3.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1128127358
Short name T232
Test name
Test status
Simulation time 3119896590 ps
CPU time 11.42 seconds
Started Sep 01 09:41:33 AM UTC 24
Finished Sep 01 09:41:46 AM UTC 24
Peak memory 226556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128127358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_tl_access.1128127358
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.1442982013
Short name T52
Test name
Test status
Simulation time 352346236 ps
CPU time 1.67 seconds
Started Sep 01 09:41:36 AM UTC 24
Finished Sep 01 09:41:39 AM UTC 24
Peak memory 213452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442982013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_halt_resume_whereto.1442982013
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/3.rv_dm_halt_resume_whereto/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/3.rv_dm_hart_unavail.1332277561
Short name T96
Test name
Test status
Simulation time 292644966 ps
CPU time 1.87 seconds
Started Sep 01 09:41:36 AM UTC 24
Finished Sep 01 09:41:39 AM UTC 24
Peak memory 213452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332277561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.1332277561
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/3.rv_dm_hart_unavail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.402126804
Short name T223
Test name
Test status
Simulation time 5271514729 ps
CPU time 12.49 seconds
Started Sep 01 09:41:33 AM UTC 24
Finished Sep 01 09:41:47 AM UTC 24
Peak memory 226496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402126804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.402126804
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/3.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/3.rv_dm_sec_cm.1598147449
Short name T89
Test name
Test status
Simulation time 2862560691 ps
CPU time 15.93 seconds
Started Sep 01 09:41:40 AM UTC 24
Finished Sep 01 09:41:57 AM UTC 24
Peak memory 257004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598147449 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.1598147449
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/3.rv_dm_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.334067148
Short name T78
Test name
Test status
Simulation time 62464818 ps
CPU time 1.11 seconds
Started Sep 01 09:41:37 AM UTC 24
Finished Sep 01 09:41:40 AM UTC 24
Peak memory 225856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334067148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sparse_lc_gate_fsm.334067148
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/3.rv_dm_sparse_lc_gate_fsm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.2983997033
Short name T84
Test name
Test status
Simulation time 2014636635 ps
CPU time 10.28 seconds
Started Sep 01 09:41:39 AM UTC 24
Finished Sep 01 09:41:50 AM UTC 24
Peak memory 226188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983997033 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.2983997033
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/3.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/30.rv_dm_alert_test.1601877135
Short name T289
Test name
Test status
Simulation time 130148462 ps
CPU time 1.06 seconds
Started Sep 01 09:43:28 AM UTC 24
Finished Sep 01 09:43:31 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601877135 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.1601877135
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/30.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.1969377496
Short name T293
Test name
Test status
Simulation time 3725062992 ps
CPU time 4.28 seconds
Started Sep 01 09:43:28 AM UTC 24
Finished Sep 01 09:43:34 AM UTC 24
Peak memory 226444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969377496 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.1969377496
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/30.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/31.rv_dm_alert_test.142671557
Short name T290
Test name
Test status
Simulation time 42774200 ps
CPU time 1.08 seconds
Started Sep 01 09:43:30 AM UTC 24
Finished Sep 01 09:43:32 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142671557 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.142671557
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/31.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/31.rv_dm_stress_all.36166300
Short name T294
Test name
Test status
Simulation time 2105102096 ps
CPU time 2.99 seconds
Started Sep 01 09:43:30 AM UTC 24
Finished Sep 01 09:43:34 AM UTC 24
Peak memory 216080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36166300 -assert nopostproc +UVM_TESTNAME=rv_
dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.36166300
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/31.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/32.rv_dm_alert_test.728508140
Short name T292
Test name
Test status
Simulation time 35648811 ps
CPU time 1.2 seconds
Started Sep 01 09:43:30 AM UTC 24
Finished Sep 01 09:43:33 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728508140 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.728508140
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/32.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/32.rv_dm_stress_all.2090977574
Short name T302
Test name
Test status
Simulation time 3215720346 ps
CPU time 6.55 seconds
Started Sep 01 09:43:30 AM UTC 24
Finished Sep 01 09:43:38 AM UTC 24
Peak memory 216080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090977574 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.2090977574
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/32.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/33.rv_dm_alert_test.349249667
Short name T298
Test name
Test status
Simulation time 114268418 ps
CPU time 1.47 seconds
Started Sep 01 09:43:32 AM UTC 24
Finished Sep 01 09:43:35 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349249667 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.349249667
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/33.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.2433545321
Short name T297
Test name
Test status
Simulation time 1031299910 ps
CPU time 2.7 seconds
Started Sep 01 09:43:31 AM UTC 24
Finished Sep 01 09:43:35 AM UTC 24
Peak memory 215804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433545321 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.2433545321
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/33.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/34.rv_dm_alert_test.1024393767
Short name T299
Test name
Test status
Simulation time 80255220 ps
CPU time 1.01 seconds
Started Sep 01 09:43:34 AM UTC 24
Finished Sep 01 09:43:36 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024393767 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.1024393767
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/34.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/34.rv_dm_stress_all.1916228647
Short name T313
Test name
Test status
Simulation time 4754198509 ps
CPU time 8.87 seconds
Started Sep 01 09:43:32 AM UTC 24
Finished Sep 01 09:43:43 AM UTC 24
Peak memory 216140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916228647 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.1916228647
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/34.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/35.rv_dm_alert_test.1337834508
Short name T300
Test name
Test status
Simulation time 130719902 ps
CPU time 1.09 seconds
Started Sep 01 09:43:34 AM UTC 24
Finished Sep 01 09:43:36 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337834508 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.1337834508
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/35.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/35.rv_dm_stress_all.91398063
Short name T309
Test name
Test status
Simulation time 5819053092 ps
CPU time 6.87 seconds
Started Sep 01 09:43:34 AM UTC 24
Finished Sep 01 09:43:42 AM UTC 24
Peak memory 216196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91398063 -assert nopostproc +UVM_TESTNAME=rv_
dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.91398063
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/35.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/36.rv_dm_alert_test.1862338303
Short name T301
Test name
Test status
Simulation time 61882650 ps
CPU time 0.99 seconds
Started Sep 01 09:43:35 AM UTC 24
Finished Sep 01 09:43:38 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862338303 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.1862338303
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/36.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/36.rv_dm_stress_all.1413860377
Short name T311
Test name
Test status
Simulation time 5344782800 ps
CPU time 5.98 seconds
Started Sep 01 09:43:35 AM UTC 24
Finished Sep 01 09:43:42 AM UTC 24
Peak memory 216084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413860377 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.1413860377
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/36.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/37.rv_dm_alert_test.3328649403
Short name T304
Test name
Test status
Simulation time 92962578 ps
CPU time 1.01 seconds
Started Sep 01 09:43:37 AM UTC 24
Finished Sep 01 09:43:39 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328649403 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.3328649403
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/37.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/37.rv_dm_stress_all.538493685
Short name T323
Test name
Test status
Simulation time 2471959222 ps
CPU time 10.85 seconds
Started Sep 01 09:43:35 AM UTC 24
Finished Sep 01 09:43:48 AM UTC 24
Peak memory 226432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538493685 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.538493685
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/37.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/38.rv_dm_alert_test.1756565471
Short name T306
Test name
Test status
Simulation time 58307790 ps
CPU time 1.33 seconds
Started Sep 01 09:43:37 AM UTC 24
Finished Sep 01 09:43:39 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756565471 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.1756565471
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/38.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/38.rv_dm_stress_all.3807687289
Short name T312
Test name
Test status
Simulation time 3397848098 ps
CPU time 4.58 seconds
Started Sep 01 09:43:37 AM UTC 24
Finished Sep 01 09:43:42 AM UTC 24
Peak memory 216148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807687289 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.3807687289
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/38.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/39.rv_dm_alert_test.2380673784
Short name T307
Test name
Test status
Simulation time 130603214 ps
CPU time 1.34 seconds
Started Sep 01 09:43:37 AM UTC 24
Finished Sep 01 09:43:39 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380673784 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.2380673784
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/39.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/4.rv_dm_bad_sba_tl_access.4257401073
Short name T226
Test name
Test status
Simulation time 3515251502 ps
CPU time 11.41 seconds
Started Sep 01 09:41:41 AM UTC 24
Finished Sep 01 09:41:54 AM UTC 24
Peak memory 226696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257401073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.4257401073
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/4.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/4.rv_dm_buffered_enable.2422010263
Short name T208
Test name
Test status
Simulation time 618297990 ps
CPU time 3.09 seconds
Started Sep 01 09:41:47 AM UTC 24
Finished Sep 01 09:41:52 AM UTC 24
Peak memory 252588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422010263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_buffered_enable.2422010263
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/4.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.1850574325
Short name T116
Test name
Test status
Simulation time 8625809848 ps
CPU time 22.25 seconds
Started Sep 01 09:41:41 AM UTC 24
Finished Sep 01 09:42:05 AM UTC 24
Peak memory 216308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850574325 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_tl_access.1850574325
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.448389415
Short name T51
Test name
Test status
Simulation time 200874289 ps
CPU time 1.34 seconds
Started Sep 01 09:41:46 AM UTC 24
Finished Sep 01 09:41:49 AM UTC 24
Peak memory 213456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448389415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_halt_resume_whereto.448389415
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/4.rv_dm_halt_resume_whereto/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.228157525
Short name T233
Test name
Test status
Simulation time 154440946 ps
CPU time 1.87 seconds
Started Sep 01 09:41:43 AM UTC 24
Finished Sep 01 09:41:46 AM UTC 24
Peak memory 213396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228157525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.228157525
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/4.rv_dm_hart_unavail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/4.rv_dm_sba_tl_access.2657956664
Short name T115
Test name
Test status
Simulation time 4211665458 ps
CPU time 21.75 seconds
Started Sep 01 09:41:40 AM UTC 24
Finished Sep 01 09:42:03 AM UTC 24
Peak memory 226456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657956664 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.2657956664
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/4.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/4.rv_dm_sec_cm.201830818
Short name T88
Test name
Test status
Simulation time 807519440 ps
CPU time 2.8 seconds
Started Sep 01 09:41:51 AM UTC 24
Finished Sep 01 09:41:55 AM UTC 24
Peak memory 254908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201830818 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.201830818
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/4.rv_dm_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.3533858676
Short name T112
Test name
Test status
Simulation time 9255922923 ps
CPU time 138.89 seconds
Started Sep 01 09:41:50 AM UTC 24
Finished Sep 01 09:44:12 AM UTC 24
Peak memory 233168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=3533858676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stres
s_all_with_rand_reset.3533858676
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/40.rv_dm_alert_test.1560732093
Short name T305
Test name
Test status
Simulation time 41721885 ps
CPU time 1.07 seconds
Started Sep 01 09:43:37 AM UTC 24
Finished Sep 01 09:43:39 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560732093 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.1560732093
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/40.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/40.rv_dm_stress_all.400252649
Short name T316
Test name
Test status
Simulation time 2332698796 ps
CPU time 6.49 seconds
Started Sep 01 09:43:37 AM UTC 24
Finished Sep 01 09:43:45 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400252649 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.400252649
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/40.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/41.rv_dm_alert_test.2535192640
Short name T308
Test name
Test status
Simulation time 185036911 ps
CPU time 1.22 seconds
Started Sep 01 09:43:40 AM UTC 24
Finished Sep 01 09:43:42 AM UTC 24
Peak memory 215812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535192640 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.2535192640
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/41.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/42.rv_dm_alert_test.1535660775
Short name T310
Test name
Test status
Simulation time 41461709 ps
CPU time 1.22 seconds
Started Sep 01 09:43:40 AM UTC 24
Finished Sep 01 09:43:42 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535660775 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.1535660775
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/42.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/42.rv_dm_stress_all.1594191468
Short name T199
Test name
Test status
Simulation time 2414769841 ps
CPU time 5.55 seconds
Started Sep 01 09:43:40 AM UTC 24
Finished Sep 01 09:43:46 AM UTC 24
Peak memory 216008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594191468 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.1594191468
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/42.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/43.rv_dm_alert_test.3425933985
Short name T315
Test name
Test status
Simulation time 49158931 ps
CPU time 1.07 seconds
Started Sep 01 09:43:41 AM UTC 24
Finished Sep 01 09:43:43 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425933985 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.3425933985
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/43.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/43.rv_dm_stress_all.3624501930
Short name T326
Test name
Test status
Simulation time 4191678193 ps
CPU time 10.8 seconds
Started Sep 01 09:43:40 AM UTC 24
Finished Sep 01 09:43:52 AM UTC 24
Peak memory 216008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624501930 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.3624501930
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/43.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/44.rv_dm_alert_test.71778394
Short name T314
Test name
Test status
Simulation time 113089610 ps
CPU time 0.92 seconds
Started Sep 01 09:43:41 AM UTC 24
Finished Sep 01 09:43:43 AM UTC 24
Peak memory 215932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71778394 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.71778394
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/44.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.1699000995
Short name T330
Test name
Test status
Simulation time 8026444357 ps
CPU time 32.75 seconds
Started Sep 01 09:43:41 AM UTC 24
Finished Sep 01 09:44:15 AM UTC 24
Peak memory 226392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699000995 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.1699000995
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/44.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/45.rv_dm_alert_test.1243398056
Short name T317
Test name
Test status
Simulation time 81528574 ps
CPU time 1.19 seconds
Started Sep 01 09:43:43 AM UTC 24
Finished Sep 01 09:43:45 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243398056 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.1243398056
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/45.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/45.rv_dm_stress_all.3010061248
Short name T325
Test name
Test status
Simulation time 3826721828 ps
CPU time 7.98 seconds
Started Sep 01 09:43:43 AM UTC 24
Finished Sep 01 09:43:52 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010061248 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.3010061248
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/45.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/46.rv_dm_alert_test.772334190
Short name T318
Test name
Test status
Simulation time 129121882 ps
CPU time 1.37 seconds
Started Sep 01 09:43:43 AM UTC 24
Finished Sep 01 09:43:45 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772334190 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.772334190
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/46.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.103544776
Short name T327
Test name
Test status
Simulation time 3783278314 ps
CPU time 14.56 seconds
Started Sep 01 09:43:43 AM UTC 24
Finished Sep 01 09:43:59 AM UTC 24
Peak memory 226368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103544776 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.103544776
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/46.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/47.rv_dm_alert_test.816761472
Short name T320
Test name
Test status
Simulation time 85980805 ps
CPU time 1.14 seconds
Started Sep 01 09:43:44 AM UTC 24
Finished Sep 01 09:43:47 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816761472 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.816761472
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/47.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/47.rv_dm_stress_all.116693316
Short name T322
Test name
Test status
Simulation time 1268062292 ps
CPU time 3.05 seconds
Started Sep 01 09:43:43 AM UTC 24
Finished Sep 01 09:43:47 AM UTC 24
Peak memory 216016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116693316 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.116693316
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/47.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/48.rv_dm_alert_test.704615747
Short name T319
Test name
Test status
Simulation time 72924881 ps
CPU time 1 seconds
Started Sep 01 09:43:44 AM UTC 24
Finished Sep 01 09:43:46 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704615747 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.704615747
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/48.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/48.rv_dm_stress_all.2553730617
Short name T328
Test name
Test status
Simulation time 7185191657 ps
CPU time 14.65 seconds
Started Sep 01 09:43:44 AM UTC 24
Finished Sep 01 09:44:00 AM UTC 24
Peak memory 216264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553730617 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.2553730617
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/48.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/49.rv_dm_alert_test.2054428320
Short name T321
Test name
Test status
Simulation time 100852148 ps
CPU time 1.12 seconds
Started Sep 01 09:43:45 AM UTC 24
Finished Sep 01 09:43:47 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054428320 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.2054428320
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/49.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/49.rv_dm_stress_all.1863458202
Short name T324
Test name
Test status
Simulation time 2219963602 ps
CPU time 3.21 seconds
Started Sep 01 09:43:44 AM UTC 24
Finished Sep 01 09:43:49 AM UTC 24
Peak memory 216072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863458202 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.1863458202
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/49.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/5.rv_dm_alert_test.4108653187
Short name T117
Test name
Test status
Simulation time 53385485 ps
CPU time 1.05 seconds
Started Sep 01 09:42:03 AM UTC 24
Finished Sep 01 09:42:05 AM UTC 24
Peak memory 215796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108653187 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.4108653187
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/5.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.2524195702
Short name T170
Test name
Test status
Simulation time 17032509207 ps
CPU time 57.88 seconds
Started Sep 01 09:41:58 AM UTC 24
Finished Sep 01 09:42:58 AM UTC 24
Peak memory 226568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524195702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.2524195702
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.3467548462
Short name T182
Test name
Test status
Simulation time 3360578030 ps
CPU time 12.29 seconds
Started Sep 01 09:41:56 AM UTC 24
Finished Sep 01 09:42:10 AM UTC 24
Peak memory 226620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467548462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.3467548462
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/5.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/5.rv_dm_buffered_enable.428676421
Short name T114
Test name
Test status
Simulation time 149813504 ps
CPU time 1.58 seconds
Started Sep 01 09:41:59 AM UTC 24
Finished Sep 01 09:42:01 AM UTC 24
Peak memory 257536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428676421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_buffered_enable.428676421
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/5.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.1520629122
Short name T235
Test name
Test status
Simulation time 10010855014 ps
CPU time 12.15 seconds
Started Sep 01 09:41:55 AM UTC 24
Finished Sep 01 09:42:08 AM UTC 24
Peak memory 226488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520629122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl_access.1520629122
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/5.rv_dm_halt_resume_whereto.2996691511
Short name T60
Test name
Test status
Simulation time 223522750 ps
CPU time 1.55 seconds
Started Sep 01 09:41:59 AM UTC 24
Finished Sep 01 09:42:01 AM UTC 24
Peak memory 213452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996691511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_halt_resume_whereto.2996691511
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/5.rv_dm_halt_resume_whereto/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/5.rv_dm_sba_tl_access.358735686
Short name T204
Test name
Test status
Simulation time 3730184021 ps
CPU time 13.68 seconds
Started Sep 01 09:41:54 AM UTC 24
Finished Sep 01 09:42:09 AM UTC 24
Peak memory 216196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358735686 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.358735686
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/5.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.2751984991
Short name T118
Test name
Test status
Simulation time 2519487930 ps
CPU time 4.38 seconds
Started Sep 01 09:42:01 AM UTC 24
Finished Sep 01 09:42:06 AM UTC 24
Peak memory 226236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751984991 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.2751984991
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/5.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.2138136437
Short name T108
Test name
Test status
Simulation time 2627809257 ps
CPU time 24.77 seconds
Started Sep 01 09:42:03 AM UTC 24
Finished Sep 01 09:42:29 AM UTC 24
Peak memory 230588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=2138136437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stres
s_all_with_rand_reset.2138136437
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/6.rv_dm_alert_test.1811195785
Short name T163
Test name
Test status
Simulation time 73465615 ps
CPU time 1.19 seconds
Started Sep 01 09:42:10 AM UTC 24
Finished Sep 01 09:42:12 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811195785 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.1811195785
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/6.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/6.rv_dm_autoincr_sba_tl_access.2661730790
Short name T195
Test name
Test status
Simulation time 13094279510 ps
CPU time 29.31 seconds
Started Sep 01 09:42:05 AM UTC 24
Finished Sep 01 09:42:36 AM UTC 24
Peak memory 226504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661730790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.2661730790
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/6.rv_dm_bad_sba_tl_access.73979004
Short name T248
Test name
Test status
Simulation time 12971362784 ps
CPU time 34.91 seconds
Started Sep 01 09:42:04 AM UTC 24
Finished Sep 01 09:42:41 AM UTC 24
Peak memory 226572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73979004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv
_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.73979004
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/6.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/6.rv_dm_buffered_enable.44753608
Short name T222
Test name
Test status
Simulation time 144699525 ps
CPU time 1.39 seconds
Started Sep 01 09:42:06 AM UTC 24
Finished Sep 01 09:42:09 AM UTC 24
Peak memory 252120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44753608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv
_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_buffered_enable.44753608
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/6.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.4159077019
Short name T237
Test name
Test status
Simulation time 2157365779 ps
CPU time 9.68 seconds
Started Sep 01 09:42:03 AM UTC 24
Finished Sep 01 09:42:14 AM UTC 24
Peak memory 226488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159077019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_tl_access.4159077019
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/6.rv_dm_halt_resume_whereto.19178118
Short name T61
Test name
Test status
Simulation time 296659392 ps
CPU time 2.4 seconds
Started Sep 01 09:42:05 AM UTC 24
Finished Sep 01 09:42:09 AM UTC 24
Peak memory 215804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19178118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv
_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_halt_resume_whereto.19178118
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/6.rv_dm_halt_resume_whereto/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/6.rv_dm_sba_tl_access.2921738681
Short name T236
Test name
Test status
Simulation time 3010437871 ps
CPU time 8.31 seconds
Started Sep 01 09:42:03 AM UTC 24
Finished Sep 01 09:42:12 AM UTC 24
Peak memory 216204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921738681 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.2921738681
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/6.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all.2448517097
Short name T8
Test name
Test status
Simulation time 1650851635 ps
CPU time 11.71 seconds
Started Sep 01 09:42:10 AM UTC 24
Finished Sep 01 09:42:23 AM UTC 24
Peak memory 216008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448517097 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.2448517097
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/6.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all_with_rand_reset.419497605
Short name T105
Test name
Test status
Simulation time 4023517476 ps
CPU time 125.18 seconds
Started Sep 01 09:42:10 AM UTC 24
Finished Sep 01 09:44:17 AM UTC 24
Peak memory 245560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=419497605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress
_all_with_rand_reset.419497605
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/7.rv_dm_alert_test.1537914849
Short name T164
Test name
Test status
Simulation time 65996356 ps
CPU time 1.09 seconds
Started Sep 01 09:42:18 AM UTC 24
Finished Sep 01 09:42:20 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537914849 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.1537914849
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/7.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.1078586393
Short name T253
Test name
Test status
Simulation time 50596735064 ps
CPU time 34.04 seconds
Started Sep 01 09:42:13 AM UTC 24
Finished Sep 01 09:42:49 AM UTC 24
Peak memory 226636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078586393 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.1078586393
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.3664414739
Short name T238
Test name
Test status
Simulation time 1291239127 ps
CPU time 3.03 seconds
Started Sep 01 09:42:13 AM UTC 24
Finished Sep 01 09:42:17 AM UTC 24
Peak memory 216196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664414739 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.3664414739
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/7.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/7.rv_dm_buffered_enable.4247482233
Short name T228
Test name
Test status
Simulation time 162364028 ps
CPU time 1.47 seconds
Started Sep 01 09:42:15 AM UTC 24
Finished Sep 01 09:42:18 AM UTC 24
Peak memory 245300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247482233 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_buffered_enable.4247482233
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/7.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.170105672
Short name T242
Test name
Test status
Simulation time 5256387532 ps
CPU time 22.27 seconds
Started Sep 01 09:42:11 AM UTC 24
Finished Sep 01 09:42:34 AM UTC 24
Peak memory 216316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170105672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_tl_access.170105672
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.3713113458
Short name T190
Test name
Test status
Simulation time 191733745 ps
CPU time 2.01 seconds
Started Sep 01 09:42:13 AM UTC 24
Finished Sep 01 09:42:16 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713113458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_halt_resume_whereto.3713113458
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/7.rv_dm_halt_resume_whereto/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/7.rv_dm_sba_tl_access.3566093139
Short name T193
Test name
Test status
Simulation time 14526948688 ps
CPU time 20.61 seconds
Started Sep 01 09:42:10 AM UTC 24
Finished Sep 01 09:42:32 AM UTC 24
Peak memory 226704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566093139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.3566093139
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/7.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all.536805140
Short name T185
Test name
Test status
Simulation time 3443887048 ps
CPU time 18.54 seconds
Started Sep 01 09:42:15 AM UTC 24
Finished Sep 01 09:42:35 AM UTC 24
Peak memory 216212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536805140 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.536805140
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/7.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/8.rv_dm_alert_test.4234495333
Short name T165
Test name
Test status
Simulation time 36291362 ps
CPU time 1.07 seconds
Started Sep 01 09:42:26 AM UTC 24
Finished Sep 01 09:42:28 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234495333 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.4234495333
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/8.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.1149133879
Short name T331
Test name
Test status
Simulation time 40143757460 ps
CPU time 131.54 seconds
Started Sep 01 09:42:22 AM UTC 24
Finished Sep 01 09:44:36 AM UTC 24
Peak memory 226440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149133879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.1149133879
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/8.rv_dm_bad_sba_tl_access.499034489
Short name T227
Test name
Test status
Simulation time 5481725998 ps
CPU time 8.29 seconds
Started Sep 01 09:42:22 AM UTC 24
Finished Sep 01 09:42:31 AM UTC 24
Peak memory 226568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499034489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.499034489
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/8.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/8.rv_dm_buffered_enable.3114628949
Short name T201
Test name
Test status
Simulation time 558616694 ps
CPU time 4.48 seconds
Started Sep 01 09:42:24 AM UTC 24
Finished Sep 01 09:42:29 AM UTC 24
Peak memory 252696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114628949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_buffered_enable.3114628949
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/8.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.567277662
Short name T239
Test name
Test status
Simulation time 2669915240 ps
CPU time 9.81 seconds
Started Sep 01 09:42:19 AM UTC 24
Finished Sep 01 09:42:30 AM UTC 24
Peak memory 216204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567277662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl_access.567277662
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/8.rv_dm_sba_tl_access.380359755
Short name T225
Test name
Test status
Simulation time 1882337741 ps
CPU time 4.05 seconds
Started Sep 01 09:42:18 AM UTC 24
Finished Sep 01 09:42:23 AM UTC 24
Peak memory 216392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380359755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.380359755
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/8.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.877844884
Short name T27
Test name
Test status
Simulation time 4930558052 ps
CPU time 3.01 seconds
Started Sep 01 09:42:24 AM UTC 24
Finished Sep 01 09:42:28 AM UTC 24
Peak memory 216016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877844884 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.877844884
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/8.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.3671111242
Short name T74
Test name
Test status
Simulation time 12656134459 ps
CPU time 76.88 seconds
Started Sep 01 09:42:26 AM UTC 24
Finished Sep 01 09:43:45 AM UTC 24
Peak memory 243428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=3671111242 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stres
s_all_with_rand_reset.3671111242
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.1610725920
Short name T243
Test name
Test status
Simulation time 37697245 ps
CPU time 1.08 seconds
Started Sep 01 09:42:33 AM UTC 24
Finished Sep 01 09:42:35 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610725920 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.1610725920
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/9.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/9.rv_dm_autoincr_sba_tl_access.2178019220
Short name T184
Test name
Test status
Simulation time 10430059583 ps
CPU time 39.66 seconds
Started Sep 01 09:42:29 AM UTC 24
Finished Sep 01 09:43:10 AM UTC 24
Peak memory 233240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178019220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.2178019220
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.2836399944
Short name T244
Test name
Test status
Simulation time 1510730714 ps
CPU time 7.55 seconds
Started Sep 01 09:42:29 AM UTC 24
Finished Sep 01 09:42:38 AM UTC 24
Peak memory 216204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836399944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.2836399944
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/9.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/9.rv_dm_buffered_enable.426862322
Short name T132
Test name
Test status
Simulation time 243732236 ps
CPU time 1.84 seconds
Started Sep 01 09:42:31 AM UTC 24
Finished Sep 01 09:42:33 AM UTC 24
Peak memory 252300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426862322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_buffered_enable.426862322
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/9.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.3989456769
Short name T240
Test name
Test status
Simulation time 2213257072 ps
CPU time 2.8 seconds
Started Sep 01 09:42:28 AM UTC 24
Finished Sep 01 09:42:32 AM UTC 24
Peak memory 226488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989456769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_tl_access.3989456769
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.2111710175
Short name T175
Test name
Test status
Simulation time 8213946715 ps
CPU time 34.73 seconds
Started Sep 01 09:42:27 AM UTC 24
Finished Sep 01 09:43:03 AM UTC 24
Peak memory 226576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111710175 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.2111710175
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/9.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.408029134
Short name T186
Test name
Test status
Simulation time 1962618311 ps
CPU time 5.63 seconds
Started Sep 01 09:42:31 AM UTC 24
Finished Sep 01 09:42:37 AM UTC 24
Peak memory 215956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408029134 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.408029134
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/9.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.1321602746
Short name T38
Test name
Test status
Simulation time 4040837924 ps
CPU time 52.91 seconds
Started Sep 01 09:42:32 AM UTC 24
Finished Sep 01 09:43:26 AM UTC 24
Peak memory 233300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=1321602746 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stres
s_all_with_rand_reset.1321602746
Directory /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest
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