| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 88.10 | 96.32 | 89.53 | 92.10 | 93.33 | 90.44 | 98.63 | 56.31 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 54.08 | 54.08 | 84.84 | 84.84 | 49.79 | 49.79 | 29.50 | 29.50 | 53.33 | 53.33 | 65.02 | 65.02 | 93.59 | 93.59 | 2.53 | 2.53 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.1862400464 |
| 63.73 | 9.64 | 88.06 | 3.22 | 62.23 | 12.45 | 32.52 | 3.03 | 62.67 | 9.33 | 73.89 | 8.87 | 94.64 | 1.05 | 32.07 | 29.55 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.3150757175 |
| 70.64 | 6.91 | 91.79 | 3.73 | 72.84 | 10.61 | 48.53 | 16.01 | 69.33 | 6.67 | 81.57 | 7.68 | 95.79 | 1.16 | 34.60 | 2.53 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.2424476423 |
| 76.34 | 5.71 | 91.84 | 0.05 | 77.79 | 4.95 | 82.56 | 34.03 | 69.33 | 0.00 | 81.74 | 0.17 | 95.90 | 0.11 | 35.23 | 0.63 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.3511310439 |
| 78.80 | 2.46 | 92.49 | 0.65 | 80.34 | 2.55 | 84.58 | 2.02 | 78.67 | 9.33 | 83.79 | 2.05 | 95.90 | 0.00 | 35.86 | 0.63 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.3597426441 |
| 80.94 | 2.14 | 92.95 | 0.45 | 80.91 | 0.57 | 84.75 | 0.17 | 80.00 | 1.33 | 84.13 | 0.34 | 95.90 | 0.00 | 47.98 | 12.12 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.2105927308 |
| 81.76 | 0.82 | 93.00 | 0.05 | 82.32 | 1.41 | 85.38 | 0.63 | 80.00 | 0.00 | 84.47 | 0.34 | 95.90 | 0.00 | 51.26 | 3.28 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.4226669976 |
| 82.48 | 0.72 | 93.15 | 0.15 | 82.60 | 0.28 | 89.29 | 3.91 | 80.00 | 0.00 | 85.15 | 0.68 | 95.90 | 0.00 | 51.26 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/4.rv_dm_autoincr_sba_tl_access.3960091193 |
| 83.05 | 0.57 | 93.15 | 0.00 | 82.60 | 0.00 | 89.29 | 0.00 | 84.00 | 4.00 | 85.15 | 0.00 | 95.90 | 0.00 | 51.26 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.1468862986 |
| 83.56 | 0.51 | 93.95 | 0.81 | 83.03 | 0.42 | 89.58 | 0.29 | 84.00 | 0.00 | 86.35 | 1.19 | 96.11 | 0.21 | 51.89 | 0.63 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.2641334596 |
| 84.01 | 0.45 | 94.26 | 0.30 | 83.59 | 0.57 | 89.87 | 0.29 | 85.33 | 1.33 | 86.86 | 0.51 | 96.11 | 0.00 | 52.02 | 0.13 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.129915846 |
| 84.43 | 0.43 | 94.46 | 0.20 | 83.88 | 0.28 | 90.88 | 1.01 | 86.67 | 1.33 | 87.03 | 0.17 | 96.11 | 0.00 | 52.02 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.2264903617 |
| 84.82 | 0.38 | 95.06 | 0.60 | 85.01 | 1.13 | 91.05 | 0.17 | 86.67 | 0.00 | 87.54 | 0.51 | 96.11 | 0.00 | 52.27 | 0.25 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.1577411245 |
| 85.20 | 0.38 | 95.06 | 0.00 | 85.01 | 0.00 | 91.05 | 0.00 | 89.33 | 2.67 | 87.54 | 0.00 | 96.11 | 0.00 | 52.27 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1321715130 |
| 85.54 | 0.35 | 95.06 | 0.00 | 87.27 | 2.26 | 91.05 | 0.00 | 89.33 | 0.00 | 87.71 | 0.17 | 96.11 | 0.00 | 52.27 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.2466982293 |
| 85.83 | 0.28 | 95.11 | 0.05 | 87.69 | 0.42 | 91.05 | 0.00 | 90.67 | 1.33 | 87.88 | 0.17 | 96.11 | 0.00 | 52.27 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.3557229363 |
| 86.02 | 0.20 | 95.42 | 0.30 | 87.84 | 0.14 | 91.13 | 0.08 | 90.67 | 0.00 | 88.23 | 0.34 | 96.11 | 0.00 | 52.78 | 0.51 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.128799145 |
| 86.21 | 0.19 | 95.42 | 0.00 | 87.84 | 0.00 | 91.13 | 0.00 | 92.00 | 1.33 | 88.23 | 0.00 | 96.11 | 0.00 | 52.78 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.608072462 |
| 86.40 | 0.19 | 95.42 | 0.00 | 87.84 | 0.00 | 91.13 | 0.00 | 93.33 | 1.33 | 88.23 | 0.00 | 96.11 | 0.00 | 52.78 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3038102097 |
| 86.59 | 0.19 | 95.72 | 0.30 | 88.12 | 0.28 | 91.13 | 0.00 | 93.33 | 0.00 | 88.57 | 0.34 | 96.11 | 0.00 | 53.16 | 0.38 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/41.rv_dm_stress_all.3157166903 |
| 86.76 | 0.17 | 95.77 | 0.05 | 88.40 | 0.28 | 91.47 | 0.34 | 93.33 | 0.00 | 89.08 | 0.51 | 96.11 | 0.00 | 53.16 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.2227659900 |
| 86.92 | 0.16 | 95.82 | 0.05 | 88.40 | 0.00 | 91.47 | 0.00 | 93.33 | 0.00 | 89.25 | 0.17 | 96.11 | 0.00 | 54.04 | 0.88 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_autoincr_sba_tl_access.4269044922 |
| 87.07 | 0.15 | 95.82 | 0.00 | 88.40 | 0.00 | 91.47 | 0.00 | 93.33 | 0.00 | 89.25 | 0.00 | 97.16 | 1.05 | 54.04 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.63469713 |
| 87.20 | 0.13 | 96.07 | 0.25 | 88.54 | 0.14 | 91.47 | 0.00 | 93.33 | 0.00 | 89.76 | 0.51 | 97.16 | 0.00 | 54.04 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.2650811848 |
| 87.31 | 0.11 | 96.07 | 0.00 | 88.54 | 0.00 | 91.72 | 0.25 | 93.33 | 0.00 | 89.76 | 0.00 | 97.16 | 0.00 | 54.55 | 0.51 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3872573581 |
| 87.40 | 0.10 | 96.07 | 0.00 | 89.11 | 0.57 | 91.85 | 0.13 | 93.33 | 0.00 | 89.76 | 0.00 | 97.16 | 0.00 | 54.55 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/4.rv_dm_alert_test.387772627 |
| 87.50 | 0.10 | 96.22 | 0.15 | 89.25 | 0.14 | 91.85 | 0.00 | 93.33 | 0.00 | 89.93 | 0.17 | 97.37 | 0.21 | 54.55 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.799337842 |
| 87.59 | 0.09 | 96.22 | 0.00 | 89.25 | 0.00 | 91.85 | 0.00 | 93.33 | 0.00 | 89.93 | 0.00 | 97.37 | 0.00 | 55.18 | 0.63 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/18.rv_dm_autoincr_sba_tl_access.970220988 |
| 87.67 | 0.08 | 96.22 | 0.00 | 89.25 | 0.00 | 91.85 | 0.00 | 93.33 | 0.00 | 89.93 | 0.00 | 97.90 | 0.53 | 55.18 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_rw.332078403 |
| 87.73 | 0.06 | 96.22 | 0.00 | 89.25 | 0.00 | 92.02 | 0.17 | 93.33 | 0.00 | 89.93 | 0.00 | 97.90 | 0.00 | 55.43 | 0.25 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.4017570224 |
| 87.77 | 0.05 | 96.22 | 0.00 | 89.25 | 0.00 | 92.02 | 0.00 | 93.33 | 0.00 | 89.93 | 0.00 | 98.21 | 0.32 | 55.43 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2897813271 |
| 87.82 | 0.04 | 96.22 | 0.00 | 89.39 | 0.14 | 92.02 | 0.00 | 93.33 | 0.00 | 90.10 | 0.17 | 98.21 | 0.00 | 55.43 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.322246498 |
| 87.85 | 0.04 | 96.22 | 0.00 | 89.39 | 0.00 | 92.02 | 0.00 | 93.33 | 0.00 | 90.10 | 0.00 | 98.21 | 0.00 | 55.68 | 0.25 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_intg_err.967970706 |
| 87.89 | 0.04 | 96.22 | 0.00 | 89.39 | 0.00 | 92.02 | 0.00 | 93.33 | 0.00 | 90.10 | 0.00 | 98.21 | 0.00 | 55.93 | 0.25 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/29.rv_dm_stress_all.1485552586 |
| 87.92 | 0.04 | 96.22 | 0.00 | 89.39 | 0.00 | 92.02 | 0.00 | 93.33 | 0.00 | 90.10 | 0.00 | 98.21 | 0.00 | 56.19 | 0.25 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/39.rv_dm_stress_all.2861260800 |
| 87.96 | 0.03 | 96.27 | 0.05 | 89.39 | 0.00 | 92.02 | 0.00 | 93.33 | 0.00 | 90.27 | 0.17 | 98.21 | 0.00 | 56.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1029803924 |
| 87.99 | 0.03 | 96.32 | 0.05 | 89.39 | 0.00 | 92.02 | 0.00 | 93.33 | 0.00 | 90.44 | 0.17 | 98.21 | 0.00 | 56.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.12914952 |
| 88.02 | 0.03 | 96.32 | 0.00 | 89.39 | 0.00 | 92.02 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 98.42 | 0.21 | 56.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2387132008 |
| 88.04 | 0.02 | 96.32 | 0.00 | 89.53 | 0.14 | 92.02 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 98.42 | 0.00 | 56.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.2874118407 |
| 88.06 | 0.02 | 96.32 | 0.00 | 89.53 | 0.00 | 92.02 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 98.42 | 0.00 | 56.31 | 0.13 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1464847053 |
| 88.07 | 0.02 | 96.32 | 0.00 | 89.53 | 0.00 | 92.02 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 98.53 | 0.11 | 56.31 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.3981531193 |
| 88.09 | 0.02 | 96.32 | 0.00 | 89.53 | 0.00 | 92.02 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 98.63 | 0.11 | 56.31 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/2.rv_dm_sparse_lc_gate_fsm.3027503736 |
| 88.10 | 0.01 | 96.32 | 0.00 | 89.53 | 0.00 | 92.10 | 0.08 | 93.33 | 0.00 | 90.44 | 0.00 | 98.63 | 0.00 | 56.31 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3964415141 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.4048556078 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.152406551 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.66836134 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3712239939 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.4139533653 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3710066521 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1804574485 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.4259395637 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.917186096 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2412608107 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.1723717464 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2984537468 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.4060989364 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.220594176 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3972140383 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1876993982 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.513338114 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1236747645 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.639465968 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3525426649 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1553245947 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.504233467 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.772284820 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2791317085 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3852049812 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3808195341 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3640978723 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.4156738551 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.26649566 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2090291898 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.916353292 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.907507625 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.4204370690 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.1801942160 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2685168540 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1319361729 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1890028646 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.1446952265 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1445765340 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3699002890 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_rw.4217960869 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.959362462 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1450017849 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2913766543 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2509728373 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_errors.1022459703 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1589787688 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3491746640 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_rw.654931082 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.4207448235 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1547371042 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3327273499 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.220660179 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_errors.207355507 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3797470019 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1308293270 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_rw.2187937267 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.3529584097 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.48848275 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2383822350 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2817260480 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_errors.259283939 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3442121096 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_rw.855385900 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.78256763 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1454826153 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.4048699505 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3281344942 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_errors.1955195347 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1430454889 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_rw.3260980464 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.980219267 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3889128129 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.924527169 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.536199144 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_errors.1667681682 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1536005785 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.541415751 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2340959687 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.569678425 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3518956004 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3937066420 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_errors.603923599 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.332256592 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.676469621 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_rw.1806280595 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1736970405 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2553377462 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.516669971 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2700481078 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_errors.1351748040 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3236741197 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_rw.1575171360 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1732752260 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.800586169 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.187666693 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1749872530 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_errors.1297833264 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3458496595 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3658713609 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_rw.1604044105 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.290664488 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.381310369 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.892357326 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.4147885944 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_errors.4228247306 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_intg_err.531400581 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_aliasing.936926998 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2038500222 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1979950010 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1439488912 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_rw.3175864478 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2237346325 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3567097752 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3927117847 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1975581545 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3846885102 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3007860148 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2110893258 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2594859642 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3612035946 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_walk.3731718446 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2530685168 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_errors.19919240 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3925549278 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2910512866 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1530735153 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3917862640 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.458554087 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_rw.1337362931 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1185040028 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.690439417 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1263372133 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2561080311 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.4179932882 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3430183459 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3115156024 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3257881339 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3671439708 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_walk.140102290 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2489274277 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.1433266416 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_errors.619852885 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3724883889 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_aliasing.920662998 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.304744802 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2263365933 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2052959430 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_rw.841024292 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.4193480186 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.575056841 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3852737518 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.172972326 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1443175616 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1654379636 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2836876306 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2082125268 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_partial_access.973771264 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_walk.496623599 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2876318280 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3609208823 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_errors.2508485428 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.872404299 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_rw.1819701950 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.661435544 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1786318517 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3090785299 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1327877551 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.211726368 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_errors.761069943 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3405083959 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2107061836 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_rw.1420759347 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.4026054816 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1725294070 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1025442546 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.213859218 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.2406817629 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_errors.2896655813 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3230499661 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3505752372 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_rw.565211272 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.832407188 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.292964680 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3423661815 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.318178707 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.2821794687 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_errors.756136796 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_intg_err.4175929622 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.792647908 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_rw.3117787189 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.3161974241 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1505131573 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3175556056 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.848306612 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_errors.3779612146 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3755088203 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.582499414 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_rw.2932807745 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.4194294585 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1090880475 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.6585403 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.671385670 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_errors.2903391464 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2193902703 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.1152601510 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.2459839249 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_busy.2973793281 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.7071917 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_dataaddr_rw_access.2532241496 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_debug_disabled.4037896481 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.3255268854 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_hart_unavail.1678384809 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_hartsel_warl.3733086547 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.3819260167 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.4173940690 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_hard_reset.3693972893 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_idle_hint.12447547 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_halted.2400623284 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_resuming.361896485 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.3250515367 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.700179903 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_tl_access.1747759196 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_smoke.3882210142 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_abstractcmd_status.3688138614 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_alert_test.4041819713 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_bad_sba_tl_access.889475364 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_buffered_enable.2974771358 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_busy.2135209209 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.494547874 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.117134864 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_not_supported.1612279148 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_dataaddr_rw_access.2531605710 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_debug_disabled.4266265760 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.46205840 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.661557859 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_halt_resume_whereto.2324081234 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_hart_unavail.3896248305 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.2057497533 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.2064109031 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_hard_reset.4255775514 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_idle_hint.710076417 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_halted.3045726375 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_resuming.1848307183 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_ndmreset_req.2621974844 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_progbuf_read_write_execute.481730644 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_rom_read_access.3629075214 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_debug_disabled.793427186 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_tl_access.2935618263 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_sec_cm.4178708379 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_smoke.1562237400 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.3668914778 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.967185522 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/10.rv_dm_alert_test.1390696088 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/10.rv_dm_autoincr_sba_tl_access.3964956202 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/10.rv_dm_bad_sba_tl_access.1434892151 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.1880005597 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/10.rv_dm_sba_tl_access.451564160 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/10.rv_dm_stress_all.4022280012 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/11.rv_dm_alert_test.2459320583 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/11.rv_dm_autoincr_sba_tl_access.1734956336 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/11.rv_dm_bad_sba_tl_access.4038574749 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.2367190809 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/11.rv_dm_sba_tl_access.546702777 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/11.rv_dm_stress_all.2406371403 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/12.rv_dm_alert_test.1969415250 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/12.rv_dm_autoincr_sba_tl_access.3972770387 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/12.rv_dm_bad_sba_tl_access.315147020 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.625111 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/12.rv_dm_sba_tl_access.2639892040 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/12.rv_dm_stress_all.1613041405 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/13.rv_dm_alert_test.1405317563 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/13.rv_dm_autoincr_sba_tl_access.3639718258 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/13.rv_dm_bad_sba_tl_access.1377621427 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.2543824793 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/13.rv_dm_sba_tl_access.186996616 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/13.rv_dm_stress_all.606807576 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/14.rv_dm_alert_test.3531754984 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/14.rv_dm_autoincr_sba_tl_access.668463283 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/14.rv_dm_bad_sba_tl_access.3327958978 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.4062351028 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/14.rv_dm_sba_tl_access.2433357433 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/14.rv_dm_stress_all.3179911862 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/15.rv_dm_alert_test.1366275083 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/15.rv_dm_autoincr_sba_tl_access.464134771 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/15.rv_dm_bad_sba_tl_access.298233592 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2595276914 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/15.rv_dm_sba_tl_access.2807127712 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/15.rv_dm_stress_all.325119941 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/16.rv_dm_alert_test.2121806157 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/16.rv_dm_autoincr_sba_tl_access.4155412970 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/16.rv_dm_bad_sba_tl_access.1529702991 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.2210699047 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/16.rv_dm_sba_tl_access.3282729318 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/16.rv_dm_stress_all.3639746968 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/17.rv_dm_alert_test.3484863012 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/17.rv_dm_autoincr_sba_tl_access.3961761042 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/17.rv_dm_bad_sba_tl_access.2196512691 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.2253506141 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/17.rv_dm_sba_tl_access.3488403529 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/17.rv_dm_stress_all.998815046 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/18.rv_dm_alert_test.4226248595 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/18.rv_dm_bad_sba_tl_access.3258714268 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.469912263 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/18.rv_dm_sba_tl_access.2993904952 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/18.rv_dm_stress_all.1421428108 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/19.rv_dm_alert_test.1685481115 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.3894952985 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/19.rv_dm_bad_sba_tl_access.2250734188 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2752549664 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/19.rv_dm_sba_tl_access.1119990915 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.722767463 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.2560227133 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.2707962053 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.2648651187 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.2067927544 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.848045698 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.585519052 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.2065253768 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.4267322275 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.3783415824 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all.1164144575 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/20.rv_dm_alert_test.1278483750 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.3287765613 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/21.rv_dm_alert_test.3226699635 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/21.rv_dm_stress_all.2211672177 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/22.rv_dm_alert_test.45425950 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.713295069 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/23.rv_dm_alert_test.1884488642 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/23.rv_dm_stress_all.1042886335 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/24.rv_dm_alert_test.1029865106 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/24.rv_dm_stress_all.3671019516 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/25.rv_dm_alert_test.1730893093 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.2800061510 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/26.rv_dm_alert_test.3360633439 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/26.rv_dm_stress_all.1437374005 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/27.rv_dm_alert_test.2666952407 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.2545851181 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/28.rv_dm_alert_test.4164988636 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/28.rv_dm_stress_all.1493491280 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/29.rv_dm_alert_test.3720902712 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.446897418 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.1714653895 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.744289412 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.2600682580 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1128127358 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.1442982013 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/3.rv_dm_hart_unavail.1332277561 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.402126804 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/3.rv_dm_sec_cm.1598147449 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.334067148 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.2983997033 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/30.rv_dm_alert_test.1601877135 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.1969377496 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/31.rv_dm_alert_test.142671557 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/31.rv_dm_stress_all.36166300 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/32.rv_dm_alert_test.728508140 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/32.rv_dm_stress_all.2090977574 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/33.rv_dm_alert_test.349249667 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.2433545321 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/34.rv_dm_alert_test.1024393767 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/34.rv_dm_stress_all.1916228647 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/35.rv_dm_alert_test.1337834508 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/35.rv_dm_stress_all.91398063 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/36.rv_dm_alert_test.1862338303 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/36.rv_dm_stress_all.1413860377 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/37.rv_dm_alert_test.3328649403 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/37.rv_dm_stress_all.538493685 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/38.rv_dm_alert_test.1756565471 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/38.rv_dm_stress_all.3807687289 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/39.rv_dm_alert_test.2380673784 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/4.rv_dm_bad_sba_tl_access.4257401073 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/4.rv_dm_buffered_enable.2422010263 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.1850574325 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.448389415 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.228157525 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/4.rv_dm_sba_tl_access.2657956664 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/4.rv_dm_sec_cm.201830818 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.3533858676 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/40.rv_dm_alert_test.1560732093 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/40.rv_dm_stress_all.400252649 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/41.rv_dm_alert_test.2535192640 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/42.rv_dm_alert_test.1535660775 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/42.rv_dm_stress_all.1594191468 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/43.rv_dm_alert_test.3425933985 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/43.rv_dm_stress_all.3624501930 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/44.rv_dm_alert_test.71778394 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.1699000995 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/45.rv_dm_alert_test.1243398056 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/45.rv_dm_stress_all.3010061248 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/46.rv_dm_alert_test.772334190 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.103544776 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/47.rv_dm_alert_test.816761472 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/47.rv_dm_stress_all.116693316 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/48.rv_dm_alert_test.704615747 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/48.rv_dm_stress_all.2553730617 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/49.rv_dm_alert_test.2054428320 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/49.rv_dm_stress_all.1863458202 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/5.rv_dm_alert_test.4108653187 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.2524195702 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.3467548462 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/5.rv_dm_buffered_enable.428676421 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.1520629122 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/5.rv_dm_halt_resume_whereto.2996691511 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/5.rv_dm_sba_tl_access.358735686 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.2751984991 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.2138136437 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/6.rv_dm_alert_test.1811195785 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/6.rv_dm_autoincr_sba_tl_access.2661730790 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/6.rv_dm_bad_sba_tl_access.73979004 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/6.rv_dm_buffered_enable.44753608 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.4159077019 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/6.rv_dm_halt_resume_whereto.19178118 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/6.rv_dm_sba_tl_access.2921738681 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all.2448517097 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all_with_rand_reset.419497605 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/7.rv_dm_alert_test.1537914849 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.1078586393 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.3664414739 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/7.rv_dm_buffered_enable.4247482233 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.170105672 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.3713113458 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/7.rv_dm_sba_tl_access.3566093139 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all.536805140 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/8.rv_dm_alert_test.4234495333 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.1149133879 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/8.rv_dm_bad_sba_tl_access.499034489 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/8.rv_dm_buffered_enable.3114628949 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.567277662 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/8.rv_dm_sba_tl_access.380359755 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.877844884 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.3671111242 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.1610725920 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/9.rv_dm_autoincr_sba_tl_access.2178019220 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.2836399944 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/9.rv_dm_buffered_enable.426862322 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.3989456769 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.2111710175 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.408029134 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.1321602746 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_smoke.3882210142 | Sep 01 09:40:06 AM UTC 24 | Sep 01 09:40:17 AM UTC 24 | 2461392661 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_tl_access.1747759196 | Sep 01 09:40:20 AM UTC 24 | Sep 01 09:40:30 AM UTC 24 | 3620788309 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.3597426441 | Sep 01 09:40:18 AM UTC 24 | Sep 01 09:40:38 AM UTC 24 | 4387383877 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_busy.2973793281 | Sep 01 09:40:39 AM UTC 24 | Sep 01 09:40:41 AM UTC 24 | 317070993 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.7071917 | Sep 01 09:40:40 AM UTC 24 | Sep 01 09:40:43 AM UTC 24 | 188656566 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.2650811848 | Sep 01 09:40:49 AM UTC 24 | Sep 01 09:40:52 AM UTC 24 | 577181061 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.2874118407 | Sep 01 09:40:49 AM UTC 24 | Sep 01 09:40:53 AM UTC 24 | 775088000 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_resuming.361896485 | Sep 01 09:40:49 AM UTC 24 | Sep 01 09:40:53 AM UTC 24 | 366149208 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_hart_unavail.1678384809 | Sep 01 09:40:49 AM UTC 24 | Sep 01 09:40:53 AM UTC 24 | 112709558 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.1862400464 | Sep 01 09:40:34 AM UTC 24 | Sep 01 09:40:54 AM UTC 24 | 3162454658 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_halted.2400623284 | Sep 01 09:40:49 AM UTC 24 | Sep 01 09:40:54 AM UTC 24 | 428275889 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.3250515367 | Sep 01 09:40:54 AM UTC 24 | Sep 01 09:40:56 AM UTC 24 | 408503065 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_dataaddr_rw_access.2532241496 | Sep 01 09:40:53 AM UTC 24 | Sep 01 09:40:57 AM UTC 24 | 269098016 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.3255268854 | Sep 01 09:40:30 AM UTC 24 | Sep 01 09:40:58 AM UTC 24 | 8465441810 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.3819260167 | Sep 01 09:40:56 AM UTC 24 | Sep 01 09:40:58 AM UTC 24 | 374748114 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.2459839249 | Sep 01 09:40:39 AM UTC 24 | Sep 01 09:40:58 AM UTC 24 | 22881100169 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.2424476423 | Sep 01 09:40:53 AM UTC 24 | Sep 01 09:40:59 AM UTC 24 | 1264795587 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_idle_hint.12447547 | Sep 01 09:40:56 AM UTC 24 | Sep 01 09:40:59 AM UTC 24 | 209448016 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_hard_reset.3693972893 | Sep 01 09:40:57 AM UTC 24 | Sep 01 09:40:59 AM UTC 24 | 106165160 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.12914952 | Sep 01 09:40:58 AM UTC 24 | Sep 01 09:41:00 AM UTC 24 | 158242164 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.2227659900 | Sep 01 09:40:58 AM UTC 24 | Sep 01 09:41:01 AM UTC 24 | 124657379 ps | ||
| T83 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_debug_disabled.4037896481 | Sep 01 09:40:59 AM UTC 24 | Sep 01 09:41:01 AM UTC 24 | 63436114 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.700179903 | Sep 01 09:40:59 AM UTC 24 | Sep 01 09:41:01 AM UTC 24 | 251861214 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.322246498 | Sep 01 09:40:54 AM UTC 24 | Sep 01 09:41:01 AM UTC 24 | 2625660754 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_hartsel_warl.3733086547 | Sep 01 09:40:59 AM UTC 24 | Sep 01 09:41:02 AM UTC 24 | 101896275 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.3557229363 | Sep 01 09:40:59 AM UTC 24 | Sep 01 09:41:03 AM UTC 24 | 445907512 ps | ||
| T97 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.2466982293 | Sep 01 09:41:02 AM UTC 24 | Sep 01 09:41:04 AM UTC 24 | 26617570 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.3981531193 | Sep 01 09:41:02 AM UTC 24 | Sep 01 09:41:04 AM UTC 24 | 58012287 ps | ||
| T76 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.129915846 | Sep 01 09:41:01 AM UTC 24 | Sep 01 09:41:04 AM UTC 24 | 556217615 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.1152601510 | Sep 01 09:41:03 AM UTC 24 | Sep 01 09:41:05 AM UTC 24 | 80891688 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.4173940690 | Sep 01 09:40:56 AM UTC 24 | Sep 01 09:41:06 AM UTC 24 | 2064764210 ps | ||
| T86 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.46205840 | Sep 01 09:41:05 AM UTC 24 | Sep 01 09:41:10 AM UTC 24 | 1596303815 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.2641334596 | Sep 01 09:41:02 AM UTC 24 | Sep 01 09:41:10 AM UTC 24 | 1711687925 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.3511310439 | Sep 01 09:41:03 AM UTC 24 | Sep 01 09:41:11 AM UTC 24 | 845075969 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_not_supported.1612279148 | Sep 01 09:41:10 AM UTC 24 | Sep 01 09:41:12 AM UTC 24 | 144100642 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_smoke.1562237400 | Sep 01 09:41:03 AM UTC 24 | Sep 01 09:41:14 AM UTC 24 | 3138628086 ps | ||
| T87 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_bad_sba_tl_access.889475364 | Sep 01 09:41:06 AM UTC 24 | Sep 01 09:41:14 AM UTC 24 | 1914386431 ps | ||
| T90 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_hart_unavail.3896248305 | Sep 01 09:41:13 AM UTC 24 | Sep 01 09:41:15 AM UTC 24 | 122847653 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.494547874 | Sep 01 09:41:11 AM UTC 24 | Sep 01 09:41:15 AM UTC 24 | 367242524 ps | ||
| T91 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_resuming.1848307183 | Sep 01 09:41:13 AM UTC 24 | Sep 01 09:41:15 AM UTC 24 | 654776703 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_busy.2135209209 | Sep 01 09:41:09 AM UTC 24 | Sep 01 09:41:16 AM UTC 24 | 1088774727 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.117134864 | Sep 01 09:41:14 AM UTC 24 | Sep 01 09:41:16 AM UTC 24 | 455263758 ps | ||
| T92 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_dataaddr_rw_access.2531605710 | Sep 01 09:41:15 AM UTC 24 | Sep 01 09:41:17 AM UTC 24 | 451415883 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_halt_resume_whereto.2324081234 | Sep 01 09:41:15 AM UTC 24 | Sep 01 09:41:18 AM UTC 24 | 177946070 ps | ||
| T229 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_halted.3045726375 | Sep 01 09:41:13 AM UTC 24 | Sep 01 09:41:18 AM UTC 24 | 569564682 ps | ||
| T72 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_idle_hint.710076417 | Sep 01 09:41:16 AM UTC 24 | Sep 01 09:41:20 AM UTC 24 | 268365988 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_autoincr_sba_tl_access.4269044922 | Sep 01 09:41:07 AM UTC 24 | Sep 01 09:41:20 AM UTC 24 | 5046812017 ps | ||
| T178 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_debug_disabled.793427186 | Sep 01 09:41:16 AM UTC 24 | Sep 01 09:41:20 AM UTC 24 | 2450347529 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_abstractcmd_status.3688138614 | Sep 01 09:41:19 AM UTC 24 | Sep 01 09:41:21 AM UTC 24 | 92964974 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_hard_reset.4255775514 | Sep 01 09:41:19 AM UTC 24 | Sep 01 09:41:21 AM UTC 24 | 174381606 ps | ||
| T59 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_rom_read_access.3629075214 | Sep 01 09:41:19 AM UTC 24 | Sep 01 09:41:21 AM UTC 24 | 194848382 ps | ||
| T230 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.2057497533 | Sep 01 09:41:17 AM UTC 24 | Sep 01 09:41:22 AM UTC 24 | 702451237 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_ndmreset_req.2621974844 | Sep 01 09:41:16 AM UTC 24 | Sep 01 09:41:23 AM UTC 24 | 708797168 ps | ||
| T231 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.2064109031 | Sep 01 09:41:17 AM UTC 24 | Sep 01 09:41:25 AM UTC 24 | 1938438668 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_alert_test.4041819713 | Sep 01 09:41:25 AM UTC 24 | Sep 01 09:41:27 AM UTC 24 | 129255755 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.3668914778 | Sep 01 09:41:25 AM UTC 24 | Sep 01 09:41:27 AM UTC 24 | 138995759 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_progbuf_read_write_execute.481730644 | Sep 01 09:41:25 AM UTC 24 | Sep 01 09:41:27 AM UTC 24 | 203148699 ps | ||
| T79 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_debug_disabled.4266265760 | Sep 01 09:41:25 AM UTC 24 | Sep 01 09:41:27 AM UTC 24 | 280035619 ps | ||
| T70 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.661557859 | Sep 01 09:41:25 AM UTC 24 | Sep 01 09:41:28 AM UTC 24 | 146386238 ps | ||
| T81 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_sec_cm.4178708379 | Sep 01 09:41:25 AM UTC 24 | Sep 01 09:41:29 AM UTC 24 | 744030436 ps | ||
| T80 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_buffered_enable.2974771358 | Sep 01 09:41:25 AM UTC 24 | Sep 01 09:41:29 AM UTC 24 | 250459860 ps | ||
| T129 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_tl_access.2935618263 | Sep 01 09:41:04 AM UTC 24 | Sep 01 09:41:30 AM UTC 24 | 5584430583 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.1577411245 | Sep 01 09:41:25 AM UTC 24 | Sep 01 09:41:31 AM UTC 24 | 2047438501 ps | ||
| T130 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.848045698 | Sep 01 09:41:26 AM UTC 24 | Sep 01 09:41:32 AM UTC 24 | 2847230223 ps | ||
| T77 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/2.rv_dm_sparse_lc_gate_fsm.3027503736 | Sep 01 09:41:33 AM UTC 24 | Sep 01 09:41:35 AM UTC 24 | 75852772 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.2067927544 | Sep 01 09:41:33 AM UTC 24 | Sep 01 09:41:35 AM UTC 24 | 161199924 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.2560227133 | Sep 01 09:41:33 AM UTC 24 | Sep 01 09:41:36 AM UTC 24 | 66431690 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.585519052 | Sep 01 09:41:33 AM UTC 24 | Sep 01 09:41:36 AM UTC 24 | 215598411 ps | ||
| T93 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.2065253768 | Sep 01 09:41:33 AM UTC 24 | Sep 01 09:41:37 AM UTC 24 | 396502720 ps | ||
| T82 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.3783415824 | Sep 01 09:41:33 AM UTC 24 | Sep 01 09:41:37 AM UTC 24 | 951673634 ps | ||
| T94 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.4267322275 | Sep 01 09:41:25 AM UTC 24 | Sep 01 09:41:38 AM UTC 24 | 16509640869 ps | ||
| T52 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.1442982013 | Sep 01 09:41:36 AM UTC 24 | Sep 01 09:41:39 AM UTC 24 | 352346236 ps | ||
| T95 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.744289412 | Sep 01 09:41:36 AM UTC 24 | Sep 01 09:41:43 AM UTC 24 | 1985690754 ps | ||
| T96 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/3.rv_dm_hart_unavail.1332277561 | Sep 01 09:41:36 AM UTC 24 | Sep 01 09:41:39 AM UTC 24 | 292644966 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all.1164144575 | Sep 01 09:41:33 AM UTC 24 | Sep 01 09:41:39 AM UTC 24 | 3583587229 ps | ||
| T78 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.334067148 | Sep 01 09:41:37 AM UTC 24 | Sep 01 09:41:40 AM UTC 24 | 62464818 ps | ||
| T131 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.2600682580 | Sep 01 09:41:37 AM UTC 24 | Sep 01 09:41:40 AM UTC 24 | 148371256 ps | ||
| T85 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.446897418 | Sep 01 09:41:40 AM UTC 24 | Sep 01 09:41:43 AM UTC 24 | 130458923 ps | ||
| T232 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1128127358 | Sep 01 09:41:33 AM UTC 24 | Sep 01 09:41:46 AM UTC 24 | 3119896590 ps | ||
| T233 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.228157525 | Sep 01 09:41:43 AM UTC 24 | Sep 01 09:41:46 AM UTC 24 | 154440946 ps | ||
| T223 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.402126804 | Sep 01 09:41:33 AM UTC 24 | Sep 01 09:41:47 AM UTC 24 | 5271514729 ps | ||
| T51 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.448389415 | Sep 01 09:41:46 AM UTC 24 | Sep 01 09:41:49 AM UTC 24 | 200874289 ps | ||
| T84 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.2983997033 | Sep 01 09:41:39 AM UTC 24 | Sep 01 09:41:50 AM UTC 24 | 2014636635 ps | ||
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| T226 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/4.rv_dm_bad_sba_tl_access.4257401073 | Sep 01 09:41:41 AM UTC 24 | Sep 01 09:41:54 AM UTC 24 | 3515251502 ps | ||
| T88 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/4.rv_dm_sec_cm.201830818 | Sep 01 09:41:51 AM UTC 24 | Sep 01 09:41:55 AM UTC 24 | 807519440 ps | ||
| T234 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/4.rv_dm_alert_test.387772627 | Sep 01 09:41:53 AM UTC 24 | Sep 01 09:41:55 AM UTC 24 | 160694443 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.967185522 | Sep 01 09:41:25 AM UTC 24 | Sep 01 09:41:56 AM UTC 24 | 684201156 ps | ||
| T89 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/3.rv_dm_sec_cm.1598147449 | Sep 01 09:41:40 AM UTC 24 | Sep 01 09:41:57 AM UTC 24 | 2862560691 ps | ||
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| T60 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/5.rv_dm_halt_resume_whereto.2996691511 | Sep 01 09:41:59 AM UTC 24 | Sep 01 09:42:01 AM UTC 24 | 223522750 ps | ||
| T114 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/5.rv_dm_buffered_enable.428676421 | Sep 01 09:41:59 AM UTC 24 | Sep 01 09:42:01 AM UTC 24 | 149813504 ps | ||
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| T116 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.1850574325 | Sep 01 09:41:41 AM UTC 24 | Sep 01 09:42:05 AM UTC 24 | 8625809848 ps | ||
| T117 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/5.rv_dm_alert_test.4108653187 | Sep 01 09:42:03 AM UTC 24 | Sep 01 09:42:05 AM UTC 24 | 53385485 ps | ||
| T118 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.2751984991 | Sep 01 09:42:01 AM UTC 24 | Sep 01 09:42:06 AM UTC 24 | 2519487930 ps | ||
| T235 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.1520629122 | Sep 01 09:41:55 AM UTC 24 | Sep 01 09:42:08 AM UTC 24 | 10010855014 ps | ||
| T61 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/6.rv_dm_halt_resume_whereto.19178118 | Sep 01 09:42:05 AM UTC 24 | Sep 01 09:42:09 AM UTC 24 | 296659392 ps | ||
| T204 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/5.rv_dm_sba_tl_access.358735686 | Sep 01 09:41:54 AM UTC 24 | Sep 01 09:42:09 AM UTC 24 | 3730184021 ps | ||
| T222 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/6.rv_dm_buffered_enable.44753608 | Sep 01 09:42:06 AM UTC 24 | Sep 01 09:42:09 AM UTC 24 | 144699525 ps | ||
| T182 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.3467548462 | Sep 01 09:41:56 AM UTC 24 | Sep 01 09:42:10 AM UTC 24 | 3360578030 ps | ||
| T111 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.1714653895 | Sep 01 09:41:36 AM UTC 24 | Sep 01 09:42:12 AM UTC 24 | 7273257978 ps | ||
| T163 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/6.rv_dm_alert_test.1811195785 | Sep 01 09:42:10 AM UTC 24 | Sep 01 09:42:12 AM UTC 24 | 73465615 ps | ||
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| T237 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.4159077019 | Sep 01 09:42:03 AM UTC 24 | Sep 01 09:42:14 AM UTC 24 | 2157365779 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.2707962053 | Sep 01 09:41:33 AM UTC 24 | Sep 01 09:42:16 AM UTC 24 | 11223548427 ps | ||
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| T238 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.3664414739 | Sep 01 09:42:13 AM UTC 24 | Sep 01 09:42:17 AM UTC 24 | 1291239127 ps | ||
| T228 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/7.rv_dm_buffered_enable.4247482233 | Sep 01 09:42:15 AM UTC 24 | Sep 01 09:42:18 AM UTC 24 | 162364028 ps | ||
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| T8 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all.2448517097 | Sep 01 09:42:10 AM UTC 24 | Sep 01 09:42:23 AM UTC 24 | 1650851635 ps | ||
| T225 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/8.rv_dm_sba_tl_access.380359755 | Sep 01 09:42:18 AM UTC 24 | Sep 01 09:42:23 AM UTC 24 | 1882337741 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.3150757175 | Sep 01 09:41:33 AM UTC 24 | Sep 01 09:42:25 AM UTC 24 | 11796039026 ps | ||
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| T27 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.877844884 | Sep 01 09:42:24 AM UTC 24 | Sep 01 09:42:28 AM UTC 24 | 4930558052 ps | ||
| T165 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/8.rv_dm_alert_test.4234495333 | Sep 01 09:42:26 AM UTC 24 | Sep 01 09:42:28 AM UTC 24 | 36291362 ps | ||
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| T201 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/8.rv_dm_buffered_enable.3114628949 | Sep 01 09:42:24 AM UTC 24 | Sep 01 09:42:29 AM UTC 24 | 558616694 ps | ||
| T239 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.567277662 | Sep 01 09:42:19 AM UTC 24 | Sep 01 09:42:30 AM UTC 24 | 2669915240 ps | ||
| T227 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/8.rv_dm_bad_sba_tl_access.499034489 | Sep 01 09:42:22 AM UTC 24 | Sep 01 09:42:31 AM UTC 24 | 5481725998 ps | ||
| T193 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/7.rv_dm_sba_tl_access.3566093139 | Sep 01 09:42:10 AM UTC 24 | Sep 01 09:42:32 AM UTC 24 | 14526948688 ps | ||
| T240 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.3989456769 | Sep 01 09:42:28 AM UTC 24 | Sep 01 09:42:32 AM UTC 24 | 2213257072 ps | ||
| T241 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/4.rv_dm_autoincr_sba_tl_access.3960091193 | Sep 01 09:41:43 AM UTC 24 | Sep 01 09:42:33 AM UTC 24 | 81961569939 ps | ||
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| T242 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.170105672 | Sep 01 09:42:11 AM UTC 24 | Sep 01 09:42:34 AM UTC 24 | 5256387532 ps | ||
| T243 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.1610725920 | Sep 01 09:42:33 AM UTC 24 | Sep 01 09:42:35 AM UTC 24 | 37697245 ps | ||
| T185 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all.536805140 | Sep 01 09:42:15 AM UTC 24 | Sep 01 09:42:35 AM UTC 24 | 3443887048 ps | ||
| T195 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/6.rv_dm_autoincr_sba_tl_access.2661730790 | Sep 01 09:42:05 AM UTC 24 | Sep 01 09:42:36 AM UTC 24 | 13094279510 ps | ||
| T186 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.408029134 | Sep 01 09:42:31 AM UTC 24 | Sep 01 09:42:37 AM UTC 24 | 1962618311 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.2264903617 | Sep 01 09:41:03 AM UTC 24 | Sep 01 09:42:38 AM UTC 24 | 14719990528 ps | ||
| T244 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.2836399944 | Sep 01 09:42:29 AM UTC 24 | Sep 01 09:42:38 AM UTC 24 | 1510730714 ps | ||
| T245 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/10.rv_dm_alert_test.1390696088 | Sep 01 09:42:36 AM UTC 24 | Sep 01 09:42:38 AM UTC 24 | 61808984 ps | ||
| T246 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/10.rv_dm_autoincr_sba_tl_access.3964956202 | Sep 01 09:42:35 AM UTC 24 | Sep 01 09:42:38 AM UTC 24 | 957632488 ps | ||
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| T247 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/10.rv_dm_sba_tl_access.451564160 | Sep 01 09:42:33 AM UTC 24 | Sep 01 09:42:40 AM UTC 24 | 3302315890 ps | ||
| T248 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/6.rv_dm_bad_sba_tl_access.73979004 | Sep 01 09:42:04 AM UTC 24 | Sep 01 09:42:41 AM UTC 24 | 12971362784 ps | ||
| T249 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/11.rv_dm_alert_test.2459320583 | Sep 01 09:42:39 AM UTC 24 | Sep 01 09:42:41 AM UTC 24 | 77151862 ps | ||
| T205 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.1880005597 | Sep 01 09:42:34 AM UTC 24 | Sep 01 09:42:42 AM UTC 24 | 3036203181 ps | ||
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| T187 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.2367190809 | Sep 01 09:42:39 AM UTC 24 | Sep 01 09:42:45 AM UTC 24 | 3530959951 ps | ||
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| T251 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.625111 | Sep 01 09:42:40 AM UTC 24 | Sep 01 09:42:46 AM UTC 24 | 2457678810 ps | ||
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| T252 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/12.rv_dm_sba_tl_access.2639892040 | Sep 01 09:42:40 AM UTC 24 | Sep 01 09:42:48 AM UTC 24 | 1179356110 ps | ||
| T253 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.1078586393 | Sep 01 09:42:13 AM UTC 24 | Sep 01 09:42:49 AM UTC 24 | 50596735064 ps | ||
| T224 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/13.rv_dm_alert_test.1405317563 | Sep 01 09:42:48 AM UTC 24 | Sep 01 09:42:51 AM UTC 24 | 118073441 ps | ||
| T192 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/13.rv_dm_bad_sba_tl_access.1377621427 | Sep 01 09:42:46 AM UTC 24 | Sep 01 09:42:52 AM UTC 24 | 2154214620 ps | ||
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| T254 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/13.rv_dm_sba_tl_access.186996616 | Sep 01 09:42:44 AM UTC 24 | Sep 01 09:42:54 AM UTC 24 | 3354967571 ps | ||
| T255 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/10.rv_dm_bad_sba_tl_access.1434892151 | Sep 01 09:42:34 AM UTC 24 | Sep 01 09:42:54 AM UTC 24 | 11735643099 ps | ||
| T256 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/13.rv_dm_autoincr_sba_tl_access.3639718258 | Sep 01 09:42:46 AM UTC 24 | Sep 01 09:42:55 AM UTC 24 | 4442801913 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.799337842 | Sep 01 09:42:16 AM UTC 24 | Sep 01 09:42:57 AM UTC 24 | 9400276493 ps | ||
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| T172 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2595276914 | Sep 01 09:42:55 AM UTC 24 | Sep 01 09:43:00 AM UTC 24 | 1380939013 ps | ||
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| T258 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/16.rv_dm_alert_test.2121806157 | Sep 01 09:43:04 AM UTC 24 | Sep 01 09:43:07 AM UTC 24 | 54910851 ps | ||
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| T260 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/16.rv_dm_stress_all.3639746968 | Sep 01 09:43:03 AM UTC 24 | Sep 01 09:43:09 AM UTC 24 | 1659877788 ps | ||
| T261 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/12.rv_dm_autoincr_sba_tl_access.3972770387 | Sep 01 09:42:41 AM UTC 24 | Sep 01 09:43:10 AM UTC 24 | 6154949785 ps | ||
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| T275 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/21.rv_dm_alert_test.3226699635 | Sep 01 09:43:19 AM UTC 24 | Sep 01 09:43:21 AM UTC 24 | 66476938 ps | ||
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| T277 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/22.rv_dm_alert_test.45425950 | Sep 01 09:43:20 AM UTC 24 | Sep 01 09:43:22 AM UTC 24 | 90475772 ps | ||
| T278 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.2210699047 | Sep 01 09:43:03 AM UTC 24 | Sep 01 09:43:23 AM UTC 24 | 11366175306 ps | ||
| T279 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/23.rv_dm_alert_test.1884488642 | Sep 01 09:43:22 AM UTC 24 | Sep 01 09:43:24 AM UTC 24 | 45765092 ps | ||
| T280 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/24.rv_dm_alert_test.1029865106 | Sep 01 09:43:22 AM UTC 24 | Sep 01 09:43:24 AM UTC 24 | 125593277 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.722767463 | Sep 01 09:43:17 AM UTC 24 | Sep 01 09:43:25 AM UTC 24 | 4184252187 ps | ||
| T281 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/25.rv_dm_alert_test.1730893093 | Sep 01 09:43:23 AM UTC 24 | Sep 01 09:43:25 AM UTC 24 | 59476083 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.1321602746 | Sep 01 09:42:32 AM UTC 24 | Sep 01 09:43:26 AM UTC 24 | 4040837924 ps | ||
| T207 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/21.rv_dm_stress_all.2211672177 | Sep 01 09:43:19 AM UTC 24 | Sep 01 09:43:27 AM UTC 24 | 4884130697 ps | ||
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| T287 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.2800061510 | Sep 01 09:43:23 AM UTC 24 | Sep 01 09:43:30 AM UTC 24 | 1503404897 ps | ||
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| T291 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/28.rv_dm_stress_all.1493491280 | Sep 01 09:43:26 AM UTC 24 | Sep 01 09:43:33 AM UTC 24 | 2171893540 ps | ||
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| T293 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.1969377496 | Sep 01 09:43:28 AM UTC 24 | Sep 01 09:43:34 AM UTC 24 | 3725062992 ps | ||
| T294 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/31.rv_dm_stress_all.36166300 | Sep 01 09:43:30 AM UTC 24 | Sep 01 09:43:34 AM UTC 24 | 2105102096 ps | ||
| T295 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/19.rv_dm_bad_sba_tl_access.2250734188 | Sep 01 09:43:15 AM UTC 24 | Sep 01 09:43:34 AM UTC 24 | 3417250911 ps | ||
| T296 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/18.rv_dm_autoincr_sba_tl_access.970220988 | Sep 01 09:43:15 AM UTC 24 | Sep 01 09:43:35 AM UTC 24 | 16669999054 ps | ||
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| T39 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/24.rv_dm_stress_all.3671019516 | Sep 01 09:43:22 AM UTC 24 | Sep 01 09:43:35 AM UTC 24 | 5425685228 ps | ||
| T299 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/34.rv_dm_alert_test.1024393767 | Sep 01 09:43:34 AM UTC 24 | Sep 01 09:43:36 AM UTC 24 | 80255220 ps | ||
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| T302 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/32.rv_dm_stress_all.2090977574 | Sep 01 09:43:30 AM UTC 24 | Sep 01 09:43:38 AM UTC 24 | 3215720346 ps | ||
| T303 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.2545851181 | Sep 01 09:43:24 AM UTC 24 | Sep 01 09:43:38 AM UTC 24 | 2615911648 ps | ||
| T304 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/37.rv_dm_alert_test.3328649403 | Sep 01 09:43:37 AM UTC 24 | Sep 01 09:43:39 AM UTC 24 | 92962578 ps | ||
| T305 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/40.rv_dm_alert_test.1560732093 | Sep 01 09:43:37 AM UTC 24 | Sep 01 09:43:39 AM UTC 24 | 41721885 ps | ||
| T306 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/38.rv_dm_alert_test.1756565471 | Sep 01 09:43:37 AM UTC 24 | Sep 01 09:43:39 AM UTC 24 | 58307790 ps | ||
| T307 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/39.rv_dm_alert_test.2380673784 | Sep 01 09:43:37 AM UTC 24 | Sep 01 09:43:39 AM UTC 24 | 130603214 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/26.rv_dm_stress_all.1437374005 | Sep 01 09:43:23 AM UTC 24 | Sep 01 09:43:40 AM UTC 24 | 4148968946 ps | ||
| T183 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/15.rv_dm_autoincr_sba_tl_access.464134771 | Sep 01 09:42:57 AM UTC 24 | Sep 01 09:43:42 AM UTC 24 | 26808401916 ps | ||
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| T308 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/41.rv_dm_alert_test.2535192640 | Sep 01 09:43:40 AM UTC 24 | Sep 01 09:43:42 AM UTC 24 | 185036911 ps | ||
| T309 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/35.rv_dm_stress_all.91398063 | Sep 01 09:43:34 AM UTC 24 | Sep 01 09:43:42 AM UTC 24 | 5819053092 ps | ||
| T310 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/42.rv_dm_alert_test.1535660775 | Sep 01 09:43:40 AM UTC 24 | Sep 01 09:43:42 AM UTC 24 | 41461709 ps | ||
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| T315 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/43.rv_dm_alert_test.3425933985 | Sep 01 09:43:41 AM UTC 24 | Sep 01 09:43:43 AM UTC 24 | 49158931 ps | ||
| T316 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/40.rv_dm_stress_all.400252649 | Sep 01 09:43:37 AM UTC 24 | Sep 01 09:43:45 AM UTC 24 | 2332698796 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.3671111242 | Sep 01 09:42:26 AM UTC 24 | Sep 01 09:43:45 AM UTC 24 | 12656134459 ps | ||
| T317 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/45.rv_dm_alert_test.1243398056 | Sep 01 09:43:43 AM UTC 24 | Sep 01 09:43:45 AM UTC 24 | 81528574 ps | ||
| T318 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/46.rv_dm_alert_test.772334190 | Sep 01 09:43:43 AM UTC 24 | Sep 01 09:43:45 AM UTC 24 | 129121882 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/41.rv_dm_stress_all.3157166903 | Sep 01 09:43:38 AM UTC 24 | Sep 01 09:43:45 AM UTC 24 | 8237828769 ps | ||
| T199 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/42.rv_dm_stress_all.1594191468 | Sep 01 09:43:40 AM UTC 24 | Sep 01 09:43:46 AM UTC 24 | 2414769841 ps | ||
| T319 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/48.rv_dm_alert_test.704615747 | Sep 01 09:43:44 AM UTC 24 | Sep 01 09:43:46 AM UTC 24 | 72924881 ps | ||
| T320 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/47.rv_dm_alert_test.816761472 | Sep 01 09:43:44 AM UTC 24 | Sep 01 09:43:47 AM UTC 24 | 85980805 ps | ||
| T321 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/49.rv_dm_alert_test.2054428320 | Sep 01 09:43:45 AM UTC 24 | Sep 01 09:43:47 AM UTC 24 | 100852148 ps | ||
| T322 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/47.rv_dm_stress_all.116693316 | Sep 01 09:43:43 AM UTC 24 | Sep 01 09:43:47 AM UTC 24 | 1268062292 ps | ||
| T323 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/37.rv_dm_stress_all.538493685 | Sep 01 09:43:35 AM UTC 24 | Sep 01 09:43:48 AM UTC 24 | 2471959222 ps | ||
| T200 | /workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/coverage/default/39.rv_dm_stress_all.2861260800 | Sep 01 09:43:37 AM UTC 24 | Sep 01 09:43:48 AM UTC 24 | 7048020109 ps |
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