| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 88.98 | 96.27 | 89.82 | 92.10 | 94.67 | 90.10 | 98.74 | 61.18 |
| T10 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.1562051541 | Sep 04 02:25:45 AM UTC 24 | Sep 04 02:26:38 AM UTC 24 | 12575457194 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.2683195943 | Sep 04 02:25:50 AM UTC 24 | Sep 04 02:26:39 AM UTC 24 | 2061099077 ps | ||
| T321 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.2220288935 | Sep 04 02:26:25 AM UTC 24 | Sep 04 02:26:39 AM UTC 24 | 6087088869 ps | ||
| T81 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.864654713 | Sep 04 02:25:42 AM UTC 24 | Sep 04 02:26:57 AM UTC 24 | 6184011069 ps | ||
| T322 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.1759887273 | Sep 04 02:26:12 AM UTC 24 | Sep 04 02:26:59 AM UTC 24 | 15549653329 ps | ||
| T323 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/6.rv_dm_autoincr_sba_tl_access.3119453711 | Sep 04 02:25:47 AM UTC 24 | Sep 04 02:27:06 AM UTC 24 | 32530565857 ps | ||
| T324 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.4070628889 | Sep 04 02:25:45 AM UTC 24 | Sep 04 02:27:08 AM UTC 24 | 32188256297 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.905470136 | Sep 04 02:25:44 AM UTC 24 | Sep 04 02:27:10 AM UTC 24 | 6958367445 ps | ||
| T112 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.3166942002 | Sep 04 02:25:52 AM UTC 24 | Sep 04 02:27:10 AM UTC 24 | 6109373983 ps | ||
| T325 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.938765428 | Sep 04 02:25:41 AM UTC 24 | Sep 04 02:27:22 AM UTC 24 | 44564504794 ps | ||
| T326 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/11.rv_dm_autoincr_sba_tl_access.897669972 | Sep 04 02:25:55 AM UTC 24 | Sep 04 02:27:37 AM UTC 24 | 62702509194 ps | ||
| T327 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/17.rv_dm_autoincr_sba_tl_access.591566830 | Sep 04 02:26:06 AM UTC 24 | Sep 04 02:29:10 AM UTC 24 | 63638987249 ps | ||
| T103 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3720156338 | Sep 04 02:24:07 AM UTC 24 | Sep 04 02:24:10 AM UTC 24 | 128592652 ps | ||
| T104 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2700930879 | Sep 04 02:24:08 AM UTC 24 | Sep 04 02:24:13 AM UTC 24 | 598046729 ps | ||
| T328 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.1735823459 | Sep 04 02:24:12 AM UTC 24 | Sep 04 02:24:14 AM UTC 24 | 41518473 ps | ||
| T329 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3323701446 | Sep 04 02:24:13 AM UTC 24 | Sep 04 02:24:15 AM UTC 24 | 110566962 ps | ||
| T121 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.4160857895 | Sep 04 02:24:12 AM UTC 24 | Sep 04 02:24:15 AM UTC 24 | 107306013 ps | ||
| T130 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.2719582987 | Sep 04 02:24:13 AM UTC 24 | Sep 04 02:24:17 AM UTC 24 | 120568179 ps | ||
| T131 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.420146013 | Sep 04 02:24:13 AM UTC 24 | Sep 04 02:24:17 AM UTC 24 | 207545555 ps | ||
| T330 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1543985181 | Sep 04 02:24:09 AM UTC 24 | Sep 04 02:24:17 AM UTC 24 | 1619326943 ps | ||
| T105 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2624379255 | Sep 04 02:24:09 AM UTC 24 | Sep 04 02:24:17 AM UTC 24 | 2053546515 ps | ||
| T331 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2845682658 | Sep 04 02:24:16 AM UTC 24 | Sep 04 02:24:18 AM UTC 24 | 116732173 ps | ||
| T332 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1681192040 | Sep 04 02:24:16 AM UTC 24 | Sep 04 02:24:18 AM UTC 24 | 161612975 ps | ||
| T114 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.784407528 | Sep 04 02:24:14 AM UTC 24 | Sep 04 02:24:18 AM UTC 24 | 115663363 ps | ||
| T132 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.77505533 | Sep 04 02:24:14 AM UTC 24 | Sep 04 02:24:20 AM UTC 24 | 882948700 ps | ||
| T333 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.3901621255 | Sep 04 02:24:18 AM UTC 24 | Sep 04 02:24:20 AM UTC 24 | 54279034 ps | ||
| T334 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3408772299 | Sep 04 02:24:17 AM UTC 24 | Sep 04 02:24:21 AM UTC 24 | 1008603019 ps | ||
| T335 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.982976267 | Sep 04 02:24:11 AM UTC 24 | Sep 04 02:24:21 AM UTC 24 | 7830940652 ps | ||
| T336 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3056394415 | Sep 04 02:24:18 AM UTC 24 | Sep 04 02:24:21 AM UTC 24 | 183926395 ps | ||
| T133 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.408391960 | Sep 04 02:24:18 AM UTC 24 | Sep 04 02:24:22 AM UTC 24 | 91982649 ps | ||
| T134 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.1480610917 | Sep 04 02:24:18 AM UTC 24 | Sep 04 02:24:22 AM UTC 24 | 98843980 ps | ||
| T337 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.4154866429 | Sep 04 02:24:18 AM UTC 24 | Sep 04 02:24:23 AM UTC 24 | 70950535 ps | ||
| T338 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3815406232 | Sep 04 02:24:22 AM UTC 24 | Sep 04 02:24:24 AM UTC 24 | 302149835 ps | ||
| T174 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2704766561 | Sep 04 02:24:20 AM UTC 24 | Sep 04 02:24:24 AM UTC 24 | 62071315 ps | ||
| T339 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2648526821 | Sep 04 02:24:22 AM UTC 24 | Sep 04 02:24:24 AM UTC 24 | 505534972 ps | ||
| T135 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.588221558 | Sep 04 02:24:19 AM UTC 24 | Sep 04 02:24:24 AM UTC 24 | 1088004064 ps | ||
| T340 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.422410064 | Sep 04 02:24:22 AM UTC 24 | Sep 04 02:24:25 AM UTC 24 | 1460696689 ps | ||
| T341 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1741861832 | Sep 04 02:24:17 AM UTC 24 | Sep 04 02:24:26 AM UTC 24 | 2091620694 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.4259092510 | Sep 04 02:24:12 AM UTC 24 | Sep 04 02:24:26 AM UTC 24 | 1955046785 ps | ||
| T342 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.501115778 | Sep 04 02:24:22 AM UTC 24 | Sep 04 02:24:27 AM UTC 24 | 2834719816 ps | ||
| T343 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3101982019 | Sep 04 02:24:23 AM UTC 24 | Sep 04 02:24:27 AM UTC 24 | 1893255352 ps | ||
| T344 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_walk.3796700896 | Sep 04 02:24:25 AM UTC 24 | Sep 04 02:24:27 AM UTC 24 | 62579880 ps | ||
| T345 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_partial_access.916643140 | Sep 04 02:24:25 AM UTC 24 | Sep 04 02:24:27 AM UTC 24 | 50865272 ps | ||
| T136 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_rw.278882495 | Sep 04 02:24:26 AM UTC 24 | Sep 04 02:24:29 AM UTC 24 | 92305167 ps | ||
| T346 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.440185646 | Sep 04 02:24:11 AM UTC 24 | Sep 04 02:24:30 AM UTC 24 | 46923901889 ps | ||
| T347 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1838914936 | Sep 04 02:24:28 AM UTC 24 | Sep 04 02:24:30 AM UTC 24 | 276576273 ps | ||
| T137 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3267749085 | Sep 04 02:24:26 AM UTC 24 | Sep 04 02:24:31 AM UTC 24 | 218524072 ps | ||
| T348 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1661277154 | Sep 04 02:24:28 AM UTC 24 | Sep 04 02:24:31 AM UTC 24 | 1126288174 ps | ||
| T188 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1251307533 | Sep 04 02:24:18 AM UTC 24 | Sep 04 02:24:31 AM UTC 24 | 3433646000 ps | ||
| T176 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_errors.2466183717 | Sep 04 02:24:25 AM UTC 24 | Sep 04 02:24:32 AM UTC 24 | 654118952 ps | ||
| T349 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3265875198 | Sep 04 02:24:29 AM UTC 24 | Sep 04 02:24:33 AM UTC 24 | 765181889 ps | ||
| T350 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1382873397 | Sep 04 02:24:28 AM UTC 24 | Sep 04 02:24:33 AM UTC 24 | 160150891 ps | ||
| T351 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_walk.2890773539 | Sep 04 02:24:32 AM UTC 24 | Sep 04 02:24:34 AM UTC 24 | 64264379 ps | ||
| T138 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1463035480 | Sep 04 02:24:26 AM UTC 24 | Sep 04 02:24:35 AM UTC 24 | 575551070 ps | ||
| T352 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_errors.2109536088 | Sep 04 02:24:31 AM UTC 24 | Sep 04 02:24:35 AM UTC 24 | 69660892 ps | ||
| T353 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2947769065 | Sep 04 02:24:33 AM UTC 24 | Sep 04 02:24:36 AM UTC 24 | 70736332 ps | ||
| T139 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2495833231 | Sep 04 02:24:33 AM UTC 24 | Sep 04 02:24:37 AM UTC 24 | 55529316 ps | ||
| T354 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.584442014 | Sep 04 02:24:30 AM UTC 24 | Sep 04 02:24:37 AM UTC 24 | 1157453967 ps | ||
| T144 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.82630631 | Sep 04 02:24:23 AM UTC 24 | Sep 04 02:24:37 AM UTC 24 | 3657564318 ps | ||
| T355 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.91240848 | Sep 04 02:24:17 AM UTC 24 | Sep 04 02:24:38 AM UTC 24 | 12653006906 ps | ||
| T356 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_rw.1211337243 | Sep 04 02:24:35 AM UTC 24 | Sep 04 02:24:39 AM UTC 24 | 120892167 ps | ||
| T357 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1615589254 | Sep 04 02:24:36 AM UTC 24 | Sep 04 02:24:39 AM UTC 24 | 78144042 ps | ||
| T358 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2849615913 | Sep 04 02:24:37 AM UTC 24 | Sep 04 02:24:39 AM UTC 24 | 213662909 ps | ||
| T359 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3366487694 | Sep 04 02:24:38 AM UTC 24 | Sep 04 02:24:40 AM UTC 24 | 260305149 ps | ||
| T360 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1574720615 | Sep 04 02:24:38 AM UTC 24 | Sep 04 02:24:41 AM UTC 24 | 233090847 ps | ||
| T189 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2652056287 | Sep 04 02:24:25 AM UTC 24 | Sep 04 02:24:42 AM UTC 24 | 6937392720 ps | ||
| T361 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3082391983 | Sep 04 02:24:31 AM UTC 24 | Sep 04 02:24:43 AM UTC 24 | 1035174656 ps | ||
| T146 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3696580890 | Sep 04 02:24:36 AM UTC 24 | Sep 04 02:24:43 AM UTC 24 | 336219617 ps | ||
| T362 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_walk.1613699744 | Sep 04 02:24:42 AM UTC 24 | Sep 04 02:24:44 AM UTC 24 | 62659517 ps | ||
| T363 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_partial_access.659282692 | Sep 04 02:24:42 AM UTC 24 | Sep 04 02:24:44 AM UTC 24 | 46082276 ps | ||
| T364 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3160792480 | Sep 04 02:24:28 AM UTC 24 | Sep 04 02:24:45 AM UTC 24 | 16266107833 ps | ||
| T365 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_errors.2468892127 | Sep 04 02:24:40 AM UTC 24 | Sep 04 02:24:45 AM UTC 24 | 120457939 ps | ||
| T147 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1188577405 | Sep 04 02:24:43 AM UTC 24 | Sep 04 02:24:46 AM UTC 24 | 329419449 ps | ||
| T366 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2773234745 | Sep 04 02:24:29 AM UTC 24 | Sep 04 02:24:47 AM UTC 24 | 6505499659 ps | ||
| T148 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.357206210 | Sep 04 02:24:18 AM UTC 24 | Sep 04 02:24:47 AM UTC 24 | 1520759938 ps | ||
| T367 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2202165112 | Sep 04 02:24:45 AM UTC 24 | Sep 04 02:24:48 AM UTC 24 | 132155233 ps | ||
| T368 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2627249657 | Sep 04 02:24:09 AM UTC 24 | Sep 04 02:24:48 AM UTC 24 | 20302841161 ps | ||
| T149 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_rw.2266633855 | Sep 04 02:24:43 AM UTC 24 | Sep 04 02:24:48 AM UTC 24 | 185374113 ps | ||
| T369 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1036757670 | Sep 04 02:24:45 AM UTC 24 | Sep 04 02:24:49 AM UTC 24 | 80776974 ps | ||
| T370 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1479858407 | Sep 04 02:24:13 AM UTC 24 | Sep 04 02:24:49 AM UTC 24 | 2567907906 ps | ||
| T150 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_rw.1339331507 | Sep 04 02:24:48 AM UTC 24 | Sep 04 02:24:52 AM UTC 24 | 167715309 ps | ||
| T371 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.1344944170 | Sep 04 02:24:46 AM UTC 24 | Sep 04 02:24:52 AM UTC 24 | 2015528506 ps | ||
| T372 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_errors.84516949 | Sep 04 02:24:47 AM UTC 24 | Sep 04 02:24:53 AM UTC 24 | 694543812 ps | ||
| T373 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.744503618 | Sep 04 02:24:49 AM UTC 24 | Sep 04 02:24:53 AM UTC 24 | 122625372 ps | ||
| T208 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2644415869 | Sep 04 02:24:32 AM UTC 24 | Sep 04 02:24:53 AM UTC 24 | 1861926994 ps | ||
| T374 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.4248374382 | Sep 04 02:24:50 AM UTC 24 | Sep 04 02:24:54 AM UTC 24 | 895042732 ps | ||
| T151 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.4282850168 | Sep 04 02:24:48 AM UTC 24 | Sep 04 02:24:55 AM UTC 24 | 806560912 ps | ||
| T375 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.293534936 | Sep 04 02:24:40 AM UTC 24 | Sep 04 02:24:56 AM UTC 24 | 11776407425 ps | ||
| T376 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1625722714 | Sep 04 02:24:16 AM UTC 24 | Sep 04 02:24:56 AM UTC 24 | 39212554320 ps | ||
| T164 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1658812045 | Sep 04 02:24:44 AM UTC 24 | Sep 04 02:24:57 AM UTC 24 | 483035087 ps | ||
| T377 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3771251202 | Sep 04 02:24:55 AM UTC 24 | Sep 04 02:24:58 AM UTC 24 | 526381947 ps | ||
| T156 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_rw.3028718990 | Sep 04 02:24:54 AM UTC 24 | Sep 04 02:24:58 AM UTC 24 | 129056171 ps | ||
| T378 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1644815765 | Sep 04 02:24:26 AM UTC 24 | Sep 04 02:24:58 AM UTC 24 | 729744585 ps | ||
| T379 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3152743499 | Sep 04 02:24:55 AM UTC 24 | Sep 04 02:24:59 AM UTC 24 | 141185592 ps | ||
| T380 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2228552224 | Sep 04 02:24:39 AM UTC 24 | Sep 04 02:24:59 AM UTC 24 | 9520437230 ps | ||
| T381 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_errors.1557322007 | Sep 04 02:24:54 AM UTC 24 | Sep 04 02:25:00 AM UTC 24 | 128087725 ps | ||
| T382 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3864645192 | Sep 04 02:24:24 AM UTC 24 | Sep 04 02:25:00 AM UTC 24 | 35232600588 ps | ||
| T383 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3353978618 | Sep 04 02:24:56 AM UTC 24 | Sep 04 02:25:01 AM UTC 24 | 2199753593 ps | ||
| T210 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_intg_err.166379043 | Sep 04 02:24:47 AM UTC 24 | Sep 04 02:25:01 AM UTC 24 | 3372451896 ps | ||
| T384 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2318811339 | Sep 04 02:24:38 AM UTC 24 | Sep 04 02:25:01 AM UTC 24 | 16655875427 ps | ||
| T385 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_errors.3150212292 | Sep 04 02:24:57 AM UTC 24 | Sep 04 02:25:02 AM UTC 24 | 198870526 ps | ||
| T165 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.203321782 | Sep 04 02:24:55 AM UTC 24 | Sep 04 02:25:02 AM UTC 24 | 258506261 ps | ||
| T157 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_rw.184372983 | Sep 04 02:24:59 AM UTC 24 | Sep 04 02:25:03 AM UTC 24 | 426583031 ps | ||
| T213 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1799519463 | Sep 04 02:24:42 AM UTC 24 | Sep 04 02:25:04 AM UTC 24 | 5067237806 ps | ||
| T386 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.373153464 | Sep 04 02:25:00 AM UTC 24 | Sep 04 02:25:04 AM UTC 24 | 535342065 ps | ||
| T387 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1291528481 | Sep 04 02:24:57 AM UTC 24 | Sep 04 02:25:04 AM UTC 24 | 5539169981 ps | ||
| T166 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3812385312 | Sep 04 02:25:00 AM UTC 24 | Sep 04 02:25:05 AM UTC 24 | 603433246 ps | ||
| T388 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1268903752 | Sep 04 02:25:03 AM UTC 24 | Sep 04 02:25:05 AM UTC 24 | 175416008 ps | ||
| T211 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2537158930 | Sep 04 02:24:54 AM UTC 24 | Sep 04 02:25:05 AM UTC 24 | 742151525 ps | ||
| T158 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_rw.4187608106 | Sep 04 02:25:02 AM UTC 24 | Sep 04 02:25:06 AM UTC 24 | 102759505 ps | ||
| T110 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2467360004 | Sep 04 02:25:00 AM UTC 24 | Sep 04 02:25:07 AM UTC 24 | 118098806 ps | ||
| T159 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_rw.2238727732 | Sep 04 02:25:21 AM UTC 24 | Sep 04 02:25:25 AM UTC 24 | 729027939 ps | ||
| T113 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1367145830 | Sep 04 02:25:02 AM UTC 24 | Sep 04 02:25:07 AM UTC 24 | 61465239 ps | ||
| T389 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_errors.1308434629 | Sep 04 02:25:01 AM UTC 24 | Sep 04 02:25:07 AM UTC 24 | 533349750 ps | ||
| T390 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2125000652 | Sep 04 02:25:03 AM UTC 24 | Sep 04 02:25:08 AM UTC 24 | 3669320986 ps | ||
| T391 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3589500973 | Sep 04 02:25:06 AM UTC 24 | Sep 04 02:25:08 AM UTC 24 | 193012663 ps | ||
| T167 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3543617934 | Sep 04 02:25:02 AM UTC 24 | Sep 04 02:25:08 AM UTC 24 | 1423726370 ps | ||
| T392 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_rw.2715367700 | Sep 04 02:25:05 AM UTC 24 | Sep 04 02:25:08 AM UTC 24 | 228286115 ps | ||
| T393 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.503347664 | Sep 04 02:25:05 AM UTC 24 | Sep 04 02:25:09 AM UTC 24 | 268504838 ps | ||
| T394 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.1711627314 | Sep 04 02:24:53 AM UTC 24 | Sep 04 02:25:09 AM UTC 24 | 14232405307 ps | ||
| T395 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.4266899500 | Sep 04 02:24:50 AM UTC 24 | Sep 04 02:25:10 AM UTC 24 | 4959171814 ps | ||
| T396 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.2185673002 | Sep 04 02:25:01 AM UTC 24 | Sep 04 02:25:10 AM UTC 24 | 7627906476 ps | ||
| T397 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.1258452896 | Sep 04 02:24:25 AM UTC 24 | Sep 04 02:25:11 AM UTC 24 | 5098807276 ps | ||
| T398 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3770014008 | Sep 04 02:25:09 AM UTC 24 | Sep 04 02:25:11 AM UTC 24 | 206788487 ps | ||
| T399 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_errors.3192180332 | Sep 04 02:25:04 AM UTC 24 | Sep 04 02:25:11 AM UTC 24 | 1347196230 ps | ||
| T400 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3890416827 | Sep 04 02:24:35 AM UTC 24 | Sep 04 02:25:12 AM UTC 24 | 2657924418 ps | ||
| T160 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.1774668377 | Sep 04 02:25:08 AM UTC 24 | Sep 04 02:25:12 AM UTC 24 | 141516292 ps | ||
| T401 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2294588244 | Sep 04 02:25:09 AM UTC 24 | Sep 04 02:25:13 AM UTC 24 | 95812553 ps | ||
| T402 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3933021438 | Sep 04 02:25:03 AM UTC 24 | Sep 04 02:25:13 AM UTC 24 | 2865154448 ps | ||
| T403 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.657842411 | Sep 04 02:24:57 AM UTC 24 | Sep 04 02:25:14 AM UTC 24 | 3335623137 ps | ||
| T404 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2502494054 | Sep 04 02:24:31 AM UTC 24 | Sep 04 02:25:15 AM UTC 24 | 30713720772 ps | ||
| T215 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2266235684 | Sep 04 02:24:58 AM UTC 24 | Sep 04 02:25:15 AM UTC 24 | 2917947526 ps | ||
| T405 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.4046907438 | Sep 04 02:25:08 AM UTC 24 | Sep 04 02:25:15 AM UTC 24 | 601145620 ps | ||
| T163 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_rw.1416652221 | Sep 04 02:25:11 AM UTC 24 | Sep 04 02:25:16 AM UTC 24 | 578597067 ps | ||
| T406 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3075049882 | Sep 04 02:25:12 AM UTC 24 | Sep 04 02:25:16 AM UTC 24 | 381116660 ps | ||
| T168 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1141030234 | Sep 04 02:25:05 AM UTC 24 | Sep 04 02:25:16 AM UTC 24 | 3064912491 ps | ||
| T145 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.4149778532 | Sep 04 02:24:39 AM UTC 24 | Sep 04 02:25:16 AM UTC 24 | 19840486229 ps | ||
| T106 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.1515818301 | Sep 04 02:24:46 AM UTC 24 | Sep 04 02:25:16 AM UTC 24 | 4178615469 ps | ||
| T407 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3655976998 | Sep 04 02:25:07 AM UTC 24 | Sep 04 02:25:17 AM UTC 24 | 4006915439 ps | ||
| T408 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1847515562 | Sep 04 02:25:12 AM UTC 24 | Sep 04 02:25:17 AM UTC 24 | 88577944 ps | ||
| T216 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_intg_err.697682192 | Sep 04 02:25:04 AM UTC 24 | Sep 04 02:25:17 AM UTC 24 | 2014182760 ps | ||
| T409 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2839820230 | Sep 04 02:25:11 AM UTC 24 | Sep 04 02:25:17 AM UTC 24 | 289841126 ps | ||
| T410 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3048434314 | Sep 04 02:25:12 AM UTC 24 | Sep 04 02:25:18 AM UTC 24 | 3120574107 ps | ||
| T411 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_errors.397969282 | Sep 04 02:25:10 AM UTC 24 | Sep 04 02:25:18 AM UTC 24 | 272370268 ps | ||
| T412 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_errors.2258691598 | Sep 04 02:25:14 AM UTC 24 | Sep 04 02:25:18 AM UTC 24 | 617047723 ps | ||
| T152 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_rw.807741095 | Sep 04 02:25:14 AM UTC 24 | Sep 04 02:25:18 AM UTC 24 | 145335258 ps | ||
| T153 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.817562585 | Sep 04 02:25:09 AM UTC 24 | Sep 04 02:25:18 AM UTC 24 | 2372022923 ps | ||
| T212 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1350595470 | Sep 04 02:25:08 AM UTC 24 | Sep 04 02:25:19 AM UTC 24 | 1894374404 ps | ||
| T413 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1435737404 | Sep 04 02:25:16 AM UTC 24 | Sep 04 02:25:19 AM UTC 24 | 358604194 ps | ||
| T414 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3785809189 | Sep 04 02:25:16 AM UTC 24 | Sep 04 02:25:19 AM UTC 24 | 159556249 ps | ||
| T415 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.231032400 | Sep 04 02:25:07 AM UTC 24 | Sep 04 02:25:19 AM UTC 24 | 13115076374 ps | ||
| T416 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2068889604 | Sep 04 02:25:09 AM UTC 24 | Sep 04 02:25:19 AM UTC 24 | 3002297521 ps | ||
| T417 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3097935265 | Sep 04 02:25:01 AM UTC 24 | Sep 04 02:25:20 AM UTC 24 | 4406629082 ps | ||
| T418 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1834204759 | Sep 04 02:25:17 AM UTC 24 | Sep 04 02:25:20 AM UTC 24 | 387180967 ps | ||
| T154 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3214237358 | Sep 04 02:25:15 AM UTC 24 | Sep 04 02:25:24 AM UTC 24 | 1920908050 ps | ||
| T419 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1623976677 | Sep 04 02:25:19 AM UTC 24 | Sep 04 02:25:20 AM UTC 24 | 54851361 ps | ||
| T420 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2104546097 | Sep 04 02:24:45 AM UTC 24 | Sep 04 02:25:21 AM UTC 24 | 11550523383 ps | ||
| T421 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.34884618 | Sep 04 02:25:16 AM UTC 24 | Sep 04 02:25:21 AM UTC 24 | 4133774452 ps | ||
| T116 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.867571208 | Sep 04 02:25:17 AM UTC 24 | Sep 04 02:25:21 AM UTC 24 | 101933166 ps | ||
| T422 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_rw.1465274790 | Sep 04 02:25:17 AM UTC 24 | Sep 04 02:25:21 AM UTC 24 | 318291055 ps | ||
| T423 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_rw.244979923 | Sep 04 02:25:19 AM UTC 24 | Sep 04 02:25:22 AM UTC 24 | 48773350 ps | ||
| T424 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.1110414437 | Sep 04 02:25:19 AM UTC 24 | Sep 04 02:25:22 AM UTC 24 | 860298840 ps | ||
| T425 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.4139920232 | Sep 04 02:25:09 AM UTC 24 | Sep 04 02:25:22 AM UTC 24 | 13652348689 ps | ||
| T426 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.347113009 | Sep 04 02:24:11 AM UTC 24 | Sep 04 02:25:22 AM UTC 24 | 65024129580 ps | ||
| T427 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.4016748425 | Sep 04 02:25:20 AM UTC 24 | Sep 04 02:25:22 AM UTC 24 | 90423289 ps | ||
| T428 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3311569586 | Sep 04 02:25:17 AM UTC 24 | Sep 04 02:25:23 AM UTC 24 | 528114739 ps | ||
| T429 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_rw.605080206 | Sep 04 02:25:20 AM UTC 24 | Sep 04 02:25:23 AM UTC 24 | 297800644 ps | ||
| T430 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3353860048 | Sep 04 02:25:19 AM UTC 24 | Sep 04 02:25:23 AM UTC 24 | 330752187 ps | ||
| T109 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2694845905 | Sep 04 02:24:40 AM UTC 24 | Sep 04 02:25:23 AM UTC 24 | 9522451800 ps | ||
| T431 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2985424155 | Sep 04 02:25:19 AM UTC 24 | Sep 04 02:25:23 AM UTC 24 | 465174940 ps | ||
| T432 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1649106618 | Sep 04 02:25:20 AM UTC 24 | Sep 04 02:25:24 AM UTC 24 | 371759023 ps | ||
| T433 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_errors.2602243765 | Sep 04 02:25:16 AM UTC 24 | Sep 04 02:25:24 AM UTC 24 | 349008975 ps | ||
| T434 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.963659987 | Sep 04 02:25:22 AM UTC 24 | Sep 04 02:25:25 AM UTC 24 | 156269139 ps | ||
| T435 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_errors.2040447310 | Sep 04 02:25:20 AM UTC 24 | Sep 04 02:25:25 AM UTC 24 | 253137753 ps | ||
| T436 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_errors.2453061600 | Sep 04 02:25:21 AM UTC 24 | Sep 04 02:25:25 AM UTC 24 | 64397243 ps | ||
| T437 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_errors.3759551071 | Sep 04 02:25:19 AM UTC 24 | Sep 04 02:25:25 AM UTC 24 | 295129484 ps | ||
| T438 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3527801026 | Sep 04 02:25:02 AM UTC 24 | Sep 04 02:25:26 AM UTC 24 | 3530527612 ps | ||
| T439 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3466541589 | Sep 04 02:25:22 AM UTC 24 | Sep 04 02:25:26 AM UTC 24 | 78825708 ps | ||
| T440 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_intg_err.4284830038 | Sep 04 02:25:17 AM UTC 24 | Sep 04 02:25:26 AM UTC 24 | 1655828983 ps | ||
| T155 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.4041076802 | Sep 04 02:24:07 AM UTC 24 | Sep 04 02:25:26 AM UTC 24 | 56120116037 ps | ||
| T441 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2719268884 | Sep 04 02:25:24 AM UTC 24 | Sep 04 02:25:27 AM UTC 24 | 1120667651 ps | ||
| T442 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_rw.2591761523 | Sep 04 02:25:24 AM UTC 24 | Sep 04 02:25:27 AM UTC 24 | 227705964 ps | ||
| T108 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.270917981 | Sep 04 02:25:24 AM UTC 24 | Sep 04 02:25:27 AM UTC 24 | 180901783 ps | ||
| T443 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_errors.1058722238 | Sep 04 02:25:25 AM UTC 24 | Sep 04 02:25:28 AM UTC 24 | 154375290 ps | ||
| T444 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_rw.213538244 | Sep 04 02:25:25 AM UTC 24 | Sep 04 02:25:29 AM UTC 24 | 121436699 ps | ||
| T445 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2936966715 | Sep 04 02:25:03 AM UTC 24 | Sep 04 02:25:29 AM UTC 24 | 1355281393 ps | ||
| T446 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_errors.665737326 | Sep 04 02:25:23 AM UTC 24 | Sep 04 02:25:30 AM UTC 24 | 1050409083 ps | ||
| T447 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1820277936 | Sep 04 02:25:26 AM UTC 24 | Sep 04 02:25:30 AM UTC 24 | 663349299 ps | ||
| T448 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2143818416 | Sep 04 02:25:20 AM UTC 24 | Sep 04 02:25:30 AM UTC 24 | 3763267624 ps | ||
| T449 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_rw.2521284749 | Sep 04 02:25:28 AM UTC 24 | Sep 04 02:25:31 AM UTC 24 | 245079673 ps | ||
| T450 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3527765365 | Sep 04 02:25:19 AM UTC 24 | Sep 04 02:25:31 AM UTC 24 | 5957872036 ps | ||
| T115 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1591104133 | Sep 04 02:24:12 AM UTC 24 | Sep 04 02:25:31 AM UTC 24 | 26742722519 ps | ||
| T451 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_errors.1902059145 | Sep 04 02:25:26 AM UTC 24 | Sep 04 02:25:31 AM UTC 24 | 319704806 ps | ||
| T452 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2841319943 | Sep 04 02:25:24 AM UTC 24 | Sep 04 02:25:32 AM UTC 24 | 898268175 ps | ||
| T453 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.840732352 | Sep 04 02:25:21 AM UTC 24 | Sep 04 02:25:32 AM UTC 24 | 2665385416 ps | ||
| T454 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3165884238 | Sep 04 02:25:25 AM UTC 24 | Sep 04 02:25:32 AM UTC 24 | 1126083003 ps | ||
| T455 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1005012142 | Sep 04 02:24:24 AM UTC 24 | Sep 04 02:25:32 AM UTC 24 | 24056086644 ps | ||
| T456 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3946904937 | Sep 04 02:25:19 AM UTC 24 | Sep 04 02:25:32 AM UTC 24 | 3176644092 ps | ||
| T457 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_intg_err.817046981 | Sep 04 02:25:20 AM UTC 24 | Sep 04 02:25:32 AM UTC 24 | 1346792943 ps | ||
| T458 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3941830183 | Sep 04 02:25:26 AM UTC 24 | Sep 04 02:25:32 AM UTC 24 | 71365490 ps | ||
| T217 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2326537585 | Sep 04 02:25:21 AM UTC 24 | Sep 04 02:25:33 AM UTC 24 | 3051673728 ps | ||
| T459 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1957878259 | Sep 04 02:25:22 AM UTC 24 | Sep 04 02:25:33 AM UTC 24 | 1120659521 ps | ||
| T460 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.508173210 | Sep 04 02:25:28 AM UTC 24 | Sep 04 02:25:33 AM UTC 24 | 636164767 ps | ||
| T461 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.873067674 | Sep 04 02:25:28 AM UTC 24 | Sep 04 02:25:33 AM UTC 24 | 614014718 ps | ||
| T214 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_intg_err.295750515 | Sep 04 02:25:19 AM UTC 24 | Sep 04 02:25:34 AM UTC 24 | 3626310397 ps | ||
| T462 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3211503852 | Sep 04 02:25:23 AM UTC 24 | Sep 04 02:25:34 AM UTC 24 | 3020806270 ps | ||
| T463 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3366958895 | Sep 04 02:24:40 AM UTC 24 | Sep 04 02:25:34 AM UTC 24 | 50255159009 ps | ||
| T209 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1822145114 | Sep 04 02:25:10 AM UTC 24 | Sep 04 02:25:35 AM UTC 24 | 4793059536 ps | ||
| T464 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1877843811 | Sep 04 02:25:14 AM UTC 24 | Sep 04 02:25:35 AM UTC 24 | 3651812276 ps | ||
| T465 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2514111318 | Sep 04 02:25:24 AM UTC 24 | Sep 04 02:25:35 AM UTC 24 | 862191496 ps | ||
| T466 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2528609864 | Sep 04 02:25:26 AM UTC 24 | Sep 04 02:25:36 AM UTC 24 | 4674234891 ps | ||
| T111 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.4209587372 | Sep 04 02:24:53 AM UTC 24 | Sep 04 02:25:37 AM UTC 24 | 3321777560 ps | ||
| T467 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3368646790 | Sep 04 02:25:23 AM UTC 24 | Sep 04 02:25:38 AM UTC 24 | 9188666455 ps | ||
| T468 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.817263539 | Sep 04 02:25:16 AM UTC 24 | Sep 04 02:25:38 AM UTC 24 | 13305416960 ps | ||
| T469 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_intg_err.583772477 | Sep 04 02:25:27 AM UTC 24 | Sep 04 02:25:39 AM UTC 24 | 1666779107 ps | ||
| T470 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3879482833 | Sep 04 02:24:20 AM UTC 24 | Sep 04 02:25:39 AM UTC 24 | 3387756309 ps | ||
| T161 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3272759765 | Sep 04 02:24:28 AM UTC 24 | Sep 04 02:25:41 AM UTC 24 | 42087541732 ps | ||
| T162 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1238881303 | Sep 04 02:24:14 AM UTC 24 | Sep 04 02:25:43 AM UTC 24 | 4434705520 ps | ||
| T471 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3862184625 | Sep 04 02:24:44 AM UTC 24 | Sep 04 02:25:43 AM UTC 24 | 1484090889 ps | ||
| T472 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2955052972 | Sep 04 02:25:25 AM UTC 24 | Sep 04 02:25:45 AM UTC 24 | 2821931309 ps | ||
| T473 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.4159650546 | Sep 04 02:24:17 AM UTC 24 | Sep 04 02:25:47 AM UTC 24 | 23065286215 ps | ||
| T474 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3012125770 | Sep 04 02:24:30 AM UTC 24 | Sep 04 02:25:56 AM UTC 24 | 23443269576 ps | ||
| T84 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3740205040 | Sep 04 02:25:01 AM UTC 24 | Sep 04 02:25:56 AM UTC 24 | 8938321315 ps | ||
| T107 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.298767787 | Sep 04 02:24:18 AM UTC 24 | Sep 04 02:25:59 AM UTC 24 | 53956049046 ps | ||
| T475 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3515950001 | Sep 04 02:24:36 AM UTC 24 | Sep 04 02:26:00 AM UTC 24 | 5529469684 ps | ||
| T476 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3143180561 | Sep 04 02:25:24 AM UTC 24 | Sep 04 02:26:10 AM UTC 24 | 14154522164 ps | ||
| T477 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.3789806205 | Sep 04 02:25:24 AM UTC 24 | Sep 04 02:26:21 AM UTC 24 | 23607405988 ps | ||
| T478 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.2457944596 | Sep 04 02:25:26 AM UTC 24 | Sep 04 02:26:37 AM UTC 24 | 25949728043 ps | ||
| T479 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2899447113 | Sep 04 02:25:19 AM UTC 24 | Sep 04 02:26:48 AM UTC 24 | 30608358976 ps | ||
| T480 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1049277964 | Sep 04 02:25:13 AM UTC 24 | Sep 04 02:27:09 AM UTC 24 | 43784046432 ps | ||
| T481 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1958951082 | Sep 04 02:24:18 AM UTC 24 | Sep 04 02:27:10 AM UTC 24 | 46345783777 ps | ||
| T482 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.3911742848 | Sep 04 02:25:21 AM UTC 24 | Sep 04 02:27:42 AM UTC 24 | 51756159016 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_dataaddr_rw_access.3045264652 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 72396932 ps |
| CPU time | 0.9 seconds |
| Started | Sep 04 02:25:32 AM UTC 24 |
| Finished | Sep 04 02:25:33 AM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045264652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.3045264652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_dataaddr_rw_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.2140272994 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 35683788216 ps |
| CPU time | 53.57 seconds |
| Started | Sep 04 02:25:41 AM UTC 24 |
| Finished | Sep 04 02:26:36 AM UTC 24 |
| Peak memory | 232576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2140272994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stres s_all_with_rand_reset.2140272994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.1676644251 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 9106981901 ps |
| CPU time | 8.98 seconds |
| Started | Sep 04 02:25:29 AM UTC 24 |
| Finished | Sep 04 02:25:40 AM UTC 24 |
| Peak memory | 228564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676644251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.1676644251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.3017130685 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 2123052319 ps |
| CPU time | 1.75 seconds |
| Started | Sep 04 02:25:35 AM UTC 24 |
| Finished | Sep 04 02:25:39 AM UTC 24 |
| Peak memory | 215880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017130685 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.3017130685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_busy.3622922411 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 423093091 ps |
| CPU time | 2.78 seconds |
| Started | Sep 04 02:25:30 AM UTC 24 |
| Finished | Sep 04 02:25:34 AM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622922411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.3622922411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_cmderr_busy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.2305336110 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 3052185681 ps |
| CPU time | 29.64 seconds |
| Started | Sep 04 02:25:48 AM UTC 24 |
| Finished | Sep 04 02:26:19 AM UTC 24 |
| Peak memory | 233312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2305336110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stres s_all_with_rand_reset.2305336110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.471356190 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 8308624261 ps |
| CPU time | 8.59 seconds |
| Started | Sep 04 02:25:28 AM UTC 24 |
| Finished | Sep 04 02:25:38 AM UTC 24 |
| Peak memory | 215964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471356190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.471356190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1251307533 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 3433646000 ps |
| CPU time | 12.24 seconds |
| Started | Sep 04 02:24:18 AM UTC 24 |
| Finished | Sep 04 02:24:31 AM UTC 24 |
| Peak memory | 225868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251307533 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.1251307533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.3491880276 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 165345099 ps |
| CPU time | 1.07 seconds |
| Started | Sep 04 02:25:41 AM UTC 24 |
| Finished | Sep 04 02:25:43 AM UTC 24 |
| Peak memory | 252172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491880276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_buffered_enable.3491880276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/2.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.2041569154 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1497426315 ps |
| CPU time | 3.55 seconds |
| Started | Sep 04 02:25:44 AM UTC 24 |
| Finished | Sep 04 02:25:48 AM UTC 24 |
| Peak memory | 226316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041569154 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.2041569154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/4.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.905470136 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 6958367445 ps |
| CPU time | 83.92 seconds |
| Started | Sep 04 02:25:44 AM UTC 24 |
| Finished | Sep 04 02:27:10 AM UTC 24 |
| Peak memory | 233208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=905470136 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress _all_with_rand_reset.905470136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.2493458201 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 117142645 ps |
| CPU time | 0.85 seconds |
| Started | Sep 04 02:25:34 AM UTC 24 |
| Finished | Sep 04 02:25:37 AM UTC 24 |
| Peak memory | 213464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493458201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.2493458201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_dmi_failed_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.4202317164 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 102885129 ps |
| CPU time | 1.18 seconds |
| Started | Sep 04 02:25:35 AM UTC 24 |
| Finished | Sep 04 02:25:38 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202317164 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.4202317164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.2683195943 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 2061099077 ps |
| CPU time | 47.2 seconds |
| Started | Sep 04 02:25:50 AM UTC 24 |
| Finished | Sep 04 02:26:39 AM UTC 24 |
| Peak memory | 243208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2683195943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stres s_all_with_rand_reset.2683195943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.251291963 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 47225929 ps |
| CPU time | 0.71 seconds |
| Started | Sep 04 02:25:35 AM UTC 24 |
| Finished | Sep 04 02:25:38 AM UTC 24 |
| Peak memory | 215936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251291963 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_scanmode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 0.rv_dm_scanmode.251291963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_scanmode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.1323014293 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 45722585749 ps |
| CPU time | 29.13 seconds |
| Started | Sep 04 02:25:48 AM UTC 24 |
| Finished | Sep 04 02:26:19 AM UTC 24 |
| Peak memory | 226120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323014293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.1323014293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/8.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.420146013 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 207545555 ps |
| CPU time | 2.55 seconds |
| Started | Sep 04 02:24:13 AM UTC 24 |
| Finished | Sep 04 02:24:17 AM UTC 24 |
| Peak memory | 225528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420146013 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.420146013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.2321075721 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 125243804 ps |
| CPU time | 0.91 seconds |
| Started | Sep 04 02:25:38 AM UTC 24 |
| Finished | Sep 04 02:25:40 AM UTC 24 |
| Peak memory | 213464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321075721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.2321075721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_dmi_failed_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.2708705727 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 531376503 ps |
| CPU time | 1.93 seconds |
| Started | Sep 04 02:25:35 AM UTC 24 |
| Finished | Sep 04 02:25:39 AM UTC 24 |
| Peak memory | 253612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708705727 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.2708705727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.1637925272 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 403378699 ps |
| CPU time | 1.8 seconds |
| Started | Sep 04 02:25:37 AM UTC 24 |
| Finished | Sep 04 02:25:40 AM UTC 24 |
| Peak memory | 215940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637925272 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.1637925272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_cmderr_exception/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.867571208 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 101933166 ps |
| CPU time | 2.88 seconds |
| Started | Sep 04 02:25:17 AM UTC 24 |
| Finished | Sep 04 02:25:21 AM UTC 24 |
| Peak memory | 229976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=867571208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_r and_reset.867571208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/13.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2694845905 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 9522451800 ps |
| CPU time | 41.18 seconds |
| Started | Sep 04 02:24:40 AM UTC 24 |
| Finished | Sep 04 02:25:23 AM UTC 24 |
| Peak memory | 229880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2694845905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_re set.2694845905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/4.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/13.rv_dm_stress_all.3104637193 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 7739506956 ps |
| CPU time | 9.06 seconds |
| Started | Sep 04 02:25:59 AM UTC 24 |
| Finished | Sep 04 02:26:09 AM UTC 24 |
| Peak memory | 216136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104637193 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.3104637193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/13.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.2964524097 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 70251451 ps |
| CPU time | 0.88 seconds |
| Started | Sep 04 02:25:34 AM UTC 24 |
| Finished | Sep 04 02:25:37 AM UTC 24 |
| Peak memory | 225792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964524097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_rom_read_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.2964524097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_rom_read_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.957414563 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 6512042139 ps |
| CPU time | 9.95 seconds |
| Started | Sep 04 02:26:12 AM UTC 24 |
| Finished | Sep 04 02:26:23 AM UTC 24 |
| Peak memory | 226392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957414563 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.957414563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/19.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.3038498633 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 970310892 ps |
| CPU time | 1.59 seconds |
| Started | Sep 04 02:25:33 AM UTC 24 |
| Finished | Sep 04 02:25:36 AM UTC 24 |
| Peak memory | 216008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038498633 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.3038498633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_sba_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.636026897 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 5847146419 ps |
| CPU time | 11.12 seconds |
| Started | Sep 04 02:25:51 AM UTC 24 |
| Finished | Sep 04 02:26:03 AM UTC 24 |
| Peak memory | 226548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636026897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.636026897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/9.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1822145114 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 4793059536 ps |
| CPU time | 23.25 seconds |
| Started | Sep 04 02:25:10 AM UTC 24 |
| Finished | Sep 04 02:25:35 AM UTC 24 |
| Peak memory | 229760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822145114 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.1822145114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/11.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2652056287 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 6937392720 ps |
| CPU time | 15.4 seconds |
| Started | Sep 04 02:24:25 AM UTC 24 |
| Finished | Sep 04 02:24:42 AM UTC 24 |
| Peak memory | 225856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652056287 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.2652056287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/2.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.3129627404 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 68813543 ps |
| CPU time | 1.18 seconds |
| Started | Sep 04 02:25:42 AM UTC 24 |
| Finished | Sep 04 02:25:45 AM UTC 24 |
| Peak memory | 225856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129627404 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sparse_lc_gate_fsm.3129627404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/3.rv_dm_sparse_lc_gate_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.2765547967 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 466793071 ps |
| CPU time | 2.08 seconds |
| Started | Sep 04 02:25:42 AM UTC 24 |
| Finished | Sep 04 02:25:45 AM UTC 24 |
| Peak memory | 258704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765547967 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_buffered_enable.2765547967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/3.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/5.rv_dm_buffered_enable.1823595563 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 205966657 ps |
| CPU time | 1.13 seconds |
| Started | Sep 04 02:25:45 AM UTC 24 |
| Finished | Sep 04 02:25:47 AM UTC 24 |
| Peak memory | 257220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823595563 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_buffered_enable.1823595563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/5.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_halt_resume_whereto.2480666059 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 427170057 ps |
| CPU time | 1.21 seconds |
| Started | Sep 04 02:25:37 AM UTC 24 |
| Finished | Sep 04 02:25:39 AM UTC 24 |
| Peak memory | 213452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480666059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.2480666059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/17.rv_dm_stress_all.1337215820 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 4985172701 ps |
| CPU time | 14.68 seconds |
| Started | Sep 04 02:26:06 AM UTC 24 |
| Finished | Sep 04 02:26:22 AM UTC 24 |
| Peak memory | 226332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337215820 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.1337215820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/17.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/17.rv_dm_bad_sba_tl_access.716207047 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 3249073800 ps |
| CPU time | 2.87 seconds |
| Started | Sep 04 02:26:06 AM UTC 24 |
| Finished | Sep 04 02:26:10 AM UTC 24 |
| Peak memory | 226564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716207047 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.716207047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/17.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2624379255 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 2053546515 ps |
| CPU time | 7.1 seconds |
| Started | Sep 04 02:24:09 AM UTC 24 |
| Finished | Sep 04 02:24:17 AM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624379255 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_aliasing.2624379255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.77505533 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 882948700 ps |
| CPU time | 4.12 seconds |
| Started | Sep 04 02:24:14 AM UTC 24 |
| Finished | Sep 04 02:24:20 AM UTC 24 |
| Peak memory | 215500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77505533 -assert nopostproc +UVM _TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_csr_outstanding.77505533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_rw.807741095 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 145335258 ps |
| CPU time | 3.18 seconds |
| Started | Sep 04 02:25:14 AM UTC 24 |
| Finished | Sep 04 02:25:18 AM UTC 24 |
| Peak memory | 229688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807741095 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.807741095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/12.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.3660142900 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 874648154 ps |
| CPU time | 1.63 seconds |
| Started | Sep 04 02:25:32 AM UTC 24 |
| Finished | Sep 04 02:25:34 AM UTC 24 |
| Peak memory | 213188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660142900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.3660142900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_cmderr_halt_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.3121394017 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 17659878255 ps |
| CPU time | 55.14 seconds |
| Started | Sep 04 02:25:39 AM UTC 24 |
| Finished | Sep 04 02:26:36 AM UTC 24 |
| Peak memory | 233328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3121394017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stres s_all_with_rand_reset.3121394017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1877843811 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 3651812276 ps |
| CPU time | 20.14 seconds |
| Started | Sep 04 02:25:14 AM UTC 24 |
| Finished | Sep 04 02:25:35 AM UTC 24 |
| Peak memory | 227880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877843811 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.1877843811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/12.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.3808091124 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 366120290 ps |
| CPU time | 1.46 seconds |
| Started | Sep 04 02:25:34 AM UTC 24 |
| Finished | Sep 04 02:25:37 AM UTC 24 |
| Peak memory | 213416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808091124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_progbuf_read_write_execute_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_d m-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.3808091124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_progbuf_read_write_execute/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/14.rv_dm_bad_sba_tl_access.3306357567 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 2857681294 ps |
| CPU time | 11.78 seconds |
| Started | Sep 04 02:26:00 AM UTC 24 |
| Finished | Sep 04 02:26:13 AM UTC 24 |
| Peak memory | 216260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306357567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.3306357567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/14.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.4290410770 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 3076856703 ps |
| CPU time | 5.17 seconds |
| Started | Sep 04 02:26:14 AM UTC 24 |
| Finished | Sep 04 02:26:20 AM UTC 24 |
| Peak memory | 216008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290410770 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.4290410770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/22.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3272759765 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 42087541732 ps |
| CPU time | 71.89 seconds |
| Started | Sep 04 02:24:28 AM UTC 24 |
| Finished | Sep 04 02:25:41 AM UTC 24 |
| Peak memory | 225728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272759765 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_aliasing.3272759765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/3.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.4245480204 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 61435833 ps |
| CPU time | 0.94 seconds |
| Started | Sep 04 02:25:39 AM UTC 24 |
| Finished | Sep 04 02:25:41 AM UTC 24 |
| Peak memory | 225856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245480204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sparse_lc_gate_fsm.4245480204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_sparse_lc_gate_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2173240546 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 6634413724 ps |
| CPU time | 11.89 seconds |
| Started | Sep 04 02:25:28 AM UTC 24 |
| Finished | Sep 04 02:25:41 AM UTC 24 |
| Peak memory | 216304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173240546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_tl_access.2173240546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.4041076802 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 56120116037 ps |
| CPU time | 76.95 seconds |
| Started | Sep 04 02:24:07 AM UTC 24 |
| Finished | Sep 04 02:25:26 AM UTC 24 |
| Peak memory | 225728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041076802 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_aliasing.4041076802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1479858407 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 2567907906 ps |
| CPU time | 34.07 seconds |
| Started | Sep 04 02:24:13 AM UTC 24 |
| Finished | Sep 04 02:24:49 AM UTC 24 |
| Peak memory | 215524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479858407 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.1479858407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.784407528 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 115663363 ps |
| CPU time | 2.55 seconds |
| Started | Sep 04 02:24:14 AM UTC 24 |
| Finished | Sep 04 02:24:18 AM UTC 24 |
| Peak memory | 225804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=784407528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_ra nd_reset.784407528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.2719582987 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 120568179 ps |
| CPU time | 2.23 seconds |
| Started | Sep 04 02:24:13 AM UTC 24 |
| Finished | Sep 04 02:24:17 AM UTC 24 |
| Peak memory | 225600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719582987 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.2719582987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.440185646 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 46923901889 ps |
| CPU time | 17.48 seconds |
| Started | Sep 04 02:24:11 AM UTC 24 |
| Finished | Sep 04 02:24:30 AM UTC 24 |
| Peak memory | 215424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440185646 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_aliasing.440185646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.347113009 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 65024129580 ps |
| CPU time | 69.77 seconds |
| Started | Sep 04 02:24:11 AM UTC 24 |
| Finished | Sep 04 02:25:22 AM UTC 24 |
| Peak memory | 215360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347113009 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_bit_bash.347113009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1543985181 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 1619326943 ps |
| CPU time | 6.97 seconds |
| Started | Sep 04 02:24:09 AM UTC 24 |
| Finished | Sep 04 02:24:17 AM UTC 24 |
| Peak memory | 215232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543985181 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_hw_reset.1543985181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.982976267 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 7830940652 ps |
| CPU time | 9.07 seconds |
| Started | Sep 04 02:24:11 AM UTC 24 |
| Finished | Sep 04 02:24:21 AM UTC 24 |
| Peak memory | 215432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982976267 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.982976267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2627249657 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 20302841161 ps |
| CPU time | 37.34 seconds |
| Started | Sep 04 02:24:09 AM UTC 24 |
| Finished | Sep 04 02:24:48 AM UTC 24 |
| Peak memory | 215524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627249657 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_bit_bash.2627249657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3720156338 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 128592652 ps |
| CPU time | 1.4 seconds |
| Started | Sep 04 02:24:07 AM UTC 24 |
| Finished | Sep 04 02:24:10 AM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720156338 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_hw_reset.3720156338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2700930879 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 598046729 ps |
| CPU time | 3.9 seconds |
| Started | Sep 04 02:24:08 AM UTC 24 |
| Finished | Sep 04 02:24:13 AM UTC 24 |
| Peak memory | 215140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700930879 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.2700930879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3323701446 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 110566962 ps |
| CPU time | 1.04 seconds |
| Started | Sep 04 02:24:13 AM UTC 24 |
| Finished | Sep 04 02:24:15 AM UTC 24 |
| Peak memory | 215140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323701446 -assert nopostproc +UVM _TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_partial_access.3323701446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.1735823459 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 41518473 ps |
| CPU time | 1.15 seconds |
| Started | Sep 04 02:24:12 AM UTC 24 |
| Finished | Sep 04 02:24:14 AM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735823459 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.1735823459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1591104133 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 26742722519 ps |
| CPU time | 76.75 seconds |
| Started | Sep 04 02:24:12 AM UTC 24 |
| Finished | Sep 04 02:25:31 AM UTC 24 |
| Peak memory | 225920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1591104133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_re set.1591104133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.4160857895 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 107306013 ps |
| CPU time | 2.26 seconds |
| Started | Sep 04 02:24:12 AM UTC 24 |
| Finished | Sep 04 02:24:15 AM UTC 24 |
| Peak memory | 225856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160857895 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.4160857895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.4259092510 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 1955046785 ps |
| CPU time | 12.69 seconds |
| Started | Sep 04 02:24:12 AM UTC 24 |
| Finished | Sep 04 02:24:26 AM UTC 24 |
| Peak memory | 232420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259092510 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.4259092510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1238881303 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 4434705520 ps |
| CPU time | 86.08 seconds |
| Started | Sep 04 02:24:14 AM UTC 24 |
| Finished | Sep 04 02:25:43 AM UTC 24 |
| Peak memory | 225728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238881303 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_aliasing.1238881303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.357206210 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 1520759938 ps |
| CPU time | 27.34 seconds |
| Started | Sep 04 02:24:18 AM UTC 24 |
| Finished | Sep 04 02:24:47 AM UTC 24 |
| Peak memory | 215264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357206210 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.357206210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.408391960 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 91982649 ps |
| CPU time | 2.49 seconds |
| Started | Sep 04 02:24:18 AM UTC 24 |
| Finished | Sep 04 02:24:22 AM UTC 24 |
| Peak memory | 225668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408391960 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.408391960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2704766561 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 62071315 ps |
| CPU time | 2.61 seconds |
| Started | Sep 04 02:24:20 AM UTC 24 |
| Finished | Sep 04 02:24:24 AM UTC 24 |
| Peak memory | 225736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2704766561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_r and_reset.2704766561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.1480610917 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 98843980 ps |
| CPU time | 3.13 seconds |
| Started | Sep 04 02:24:18 AM UTC 24 |
| Finished | Sep 04 02:24:22 AM UTC 24 |
| Peak memory | 229724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480610917 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.1480610917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1958951082 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 46345783777 ps |
| CPU time | 168.91 seconds |
| Started | Sep 04 02:24:18 AM UTC 24 |
| Finished | Sep 04 02:27:10 AM UTC 24 |
| Peak memory | 215424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958951082 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_aliasing.1958951082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.4159650546 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 23065286215 ps |
| CPU time | 88.13 seconds |
| Started | Sep 04 02:24:17 AM UTC 24 |
| Finished | Sep 04 02:25:47 AM UTC 24 |
| Peak memory | 215424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159650546 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_bit_bash.4159650546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1741861832 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 2091620694 ps |
| CPU time | 8 seconds |
| Started | Sep 04 02:24:17 AM UTC 24 |
| Finished | Sep 04 02:24:26 AM UTC 24 |
| Peak memory | 215228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741861832 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_hw_reset.1741861832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.91240848 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 12653006906 ps |
| CPU time | 20.39 seconds |
| Started | Sep 04 02:24:17 AM UTC 24 |
| Finished | Sep 04 02:24:38 AM UTC 24 |
| Peak memory | 215376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91240848 -assert nopostproc +UVM_TESTNAME=rv_dm_ba se_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.91240848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3408772299 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 1008603019 ps |
| CPU time | 3.01 seconds |
| Started | Sep 04 02:24:17 AM UTC 24 |
| Finished | Sep 04 02:24:21 AM UTC 24 |
| Peak memory | 215148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408772299 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_aliasing.3408772299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1625722714 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 39212554320 ps |
| CPU time | 39.39 seconds |
| Started | Sep 04 02:24:16 AM UTC 24 |
| Finished | Sep 04 02:24:56 AM UTC 24 |
| Peak memory | 215364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625722714 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_bit_bash.1625722714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1681192040 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 161612975 ps |
| CPU time | 1.12 seconds |
| Started | Sep 04 02:24:16 AM UTC 24 |
| Finished | Sep 04 02:24:18 AM UTC 24 |
| Peak memory | 215100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681192040 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_hw_reset.1681192040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2845682658 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 116732173 ps |
| CPU time | 0.98 seconds |
| Started | Sep 04 02:24:16 AM UTC 24 |
| Finished | Sep 04 02:24:18 AM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845682658 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.2845682658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3056394415 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 183926395 ps |
| CPU time | 2.06 seconds |
| Started | Sep 04 02:24:18 AM UTC 24 |
| Finished | Sep 04 02:24:21 AM UTC 24 |
| Peak memory | 215208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056394415 -assert nopostproc +UVM _TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_partial_access.3056394415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.3901621255 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 54279034 ps |
| CPU time | 1.07 seconds |
| Started | Sep 04 02:24:18 AM UTC 24 |
| Finished | Sep 04 02:24:20 AM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901621255 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.3901621255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.588221558 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 1088004064 ps |
| CPU time | 4.11 seconds |
| Started | Sep 04 02:24:19 AM UTC 24 |
| Finished | Sep 04 02:24:24 AM UTC 24 |
| Peak memory | 215556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588221558 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_csr_outstanding.588221558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.298767787 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 53956049046 ps |
| CPU time | 98.84 seconds |
| Started | Sep 04 02:24:18 AM UTC 24 |
| Finished | Sep 04 02:25:59 AM UTC 24 |
| Peak memory | 225720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=298767787 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.298767787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.4154866429 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 70950535 ps |
| CPU time | 3.87 seconds |
| Started | Sep 04 02:24:18 AM UTC 24 |
| Finished | Sep 04 02:24:23 AM UTC 24 |
| Peak memory | 225752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154866429 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.4154866429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2294588244 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 95812553 ps |
| CPU time | 3 seconds |
| Started | Sep 04 02:25:09 AM UTC 24 |
| Finished | Sep 04 02:25:13 AM UTC 24 |
| Peak memory | 225804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2294588244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_ rand_reset.2294588244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/10.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.1774668377 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 141516292 ps |
| CPU time | 2.79 seconds |
| Started | Sep 04 02:25:08 AM UTC 24 |
| Finished | Sep 04 02:25:12 AM UTC 24 |
| Peak memory | 225460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774668377 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.1774668377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/10.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3655976998 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 4006915439 ps |
| CPU time | 9.44 seconds |
| Started | Sep 04 02:25:07 AM UTC 24 |
| Finished | Sep 04 02:25:17 AM UTC 24 |
| Peak memory | 215432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655976998 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_bit_bash.3655976998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/10.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.231032400 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 13115076374 ps |
| CPU time | 11.54 seconds |
| Started | Sep 04 02:25:07 AM UTC 24 |
| Finished | Sep 04 02:25:19 AM UTC 24 |
| Peak memory | 215368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231032400 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.231032400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/10.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3589500973 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 193012663 ps |
| CPU time | 1.32 seconds |
| Started | Sep 04 02:25:06 AM UTC 24 |
| Finished | Sep 04 02:25:08 AM UTC 24 |
| Peak memory | 214884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589500973 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.3589500973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/10.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.817562585 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 2372022923 ps |
| CPU time | 8.2 seconds |
| Started | Sep 04 02:25:09 AM UTC 24 |
| Finished | Sep 04 02:25:18 AM UTC 24 |
| Peak memory | 215520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817562585 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_csr_outstanding.817562585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/10.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.4046907438 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 601145620 ps |
| CPU time | 6.55 seconds |
| Started | Sep 04 02:25:08 AM UTC 24 |
| Finished | Sep 04 02:25:15 AM UTC 24 |
| Peak memory | 225788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046907438 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.4046907438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/10.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1350595470 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 1894374404 ps |
| CPU time | 9.81 seconds |
| Started | Sep 04 02:25:08 AM UTC 24 |
| Finished | Sep 04 02:25:19 AM UTC 24 |
| Peak memory | 232420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350595470 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.1350595470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/10.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1847515562 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 88577944 ps |
| CPU time | 3.83 seconds |
| Started | Sep 04 02:25:12 AM UTC 24 |
| Finished | Sep 04 02:25:17 AM UTC 24 |
| Peak memory | 229784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1847515562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_ rand_reset.1847515562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/11.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_rw.1416652221 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 578597067 ps |
| CPU time | 3.37 seconds |
| Started | Sep 04 02:25:11 AM UTC 24 |
| Finished | Sep 04 02:25:16 AM UTC 24 |
| Peak memory | 225588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416652221 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.1416652221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/11.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.4139920232 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 13652348689 ps |
| CPU time | 11.67 seconds |
| Started | Sep 04 02:25:09 AM UTC 24 |
| Finished | Sep 04 02:25:22 AM UTC 24 |
| Peak memory | 215432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139920232 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_bit_bash.4139920232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/11.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2068889604 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 3002297521 ps |
| CPU time | 9.15 seconds |
| Started | Sep 04 02:25:09 AM UTC 24 |
| Finished | Sep 04 02:25:19 AM UTC 24 |
| Peak memory | 215376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068889604 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.2068889604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/11.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3770014008 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 206788487 ps |
| CPU time | 1.16 seconds |
| Started | Sep 04 02:25:09 AM UTC 24 |
| Finished | Sep 04 02:25:11 AM UTC 24 |
| Peak memory | 214952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770014008 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.3770014008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/11.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2839820230 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 289841126 ps |
| CPU time | 5.15 seconds |
| Started | Sep 04 02:25:11 AM UTC 24 |
| Finished | Sep 04 02:25:17 AM UTC 24 |
| Peak memory | 215432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839820230 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_csr_outstanding.2839820230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/11.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_errors.397969282 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 272370268 ps |
| CPU time | 6.57 seconds |
| Started | Sep 04 02:25:10 AM UTC 24 |
| Finished | Sep 04 02:25:18 AM UTC 24 |
| Peak memory | 225804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397969282 -assert nopostproc +UVM_TESTNAME=rv_dm_base _test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.397969282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/11.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3785809189 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 159556249 ps |
| CPU time | 1.94 seconds |
| Started | Sep 04 02:25:16 AM UTC 24 |
| Finished | Sep 04 02:25:19 AM UTC 24 |
| Peak memory | 227196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3785809189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_ rand_reset.3785809189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/12.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1049277964 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 43784046432 ps |
| CPU time | 114 seconds |
| Started | Sep 04 02:25:13 AM UTC 24 |
| Finished | Sep 04 02:27:09 AM UTC 24 |
| Peak memory | 215388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049277964 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_bit_bash.1049277964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/12.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3048434314 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 3120574107 ps |
| CPU time | 4.08 seconds |
| Started | Sep 04 02:25:12 AM UTC 24 |
| Finished | Sep 04 02:25:18 AM UTC 24 |
| Peak memory | 215356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048434314 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.3048434314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/12.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3075049882 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 381116660 ps |
| CPU time | 2.49 seconds |
| Started | Sep 04 02:25:12 AM UTC 24 |
| Finished | Sep 04 02:25:16 AM UTC 24 |
| Peak memory | 214992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075049882 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.3075049882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/12.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3214237358 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 1920908050 ps |
| CPU time | 7.71 seconds |
| Started | Sep 04 02:25:15 AM UTC 24 |
| Finished | Sep 04 02:25:24 AM UTC 24 |
| Peak memory | 215444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214237358 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same_csr_outstanding.3214237358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/12.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_errors.2258691598 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 617047723 ps |
| CPU time | 3.15 seconds |
| Started | Sep 04 02:25:14 AM UTC 24 |
| Finished | Sep 04 02:25:18 AM UTC 24 |
| Peak memory | 225784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258691598 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.2258691598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/12.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_rw.1465274790 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 318291055 ps |
| CPU time | 3.08 seconds |
| Started | Sep 04 02:25:17 AM UTC 24 |
| Finished | Sep 04 02:25:21 AM UTC 24 |
| Peak memory | 229852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465274790 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.1465274790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/13.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.817263539 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 13305416960 ps |
| CPU time | 21.18 seconds |
| Started | Sep 04 02:25:16 AM UTC 24 |
| Finished | Sep 04 02:25:38 AM UTC 24 |
| Peak memory | 215424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817263539 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_bit_bash.817263539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/13.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.34884618 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 4133774452 ps |
| CPU time | 4.19 seconds |
| Started | Sep 04 02:25:16 AM UTC 24 |
| Finished | Sep 04 02:25:21 AM UTC 24 |
| Peak memory | 215420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34884618 -assert nopostproc +UVM_TESTNAME=rv_dm_ba se_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.34884618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/13.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1435737404 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 358604194 ps |
| CPU time | 1.81 seconds |
| Started | Sep 04 02:25:16 AM UTC 24 |
| Finished | Sep 04 02:25:19 AM UTC 24 |
| Peak memory | 215100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435737404 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.1435737404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/13.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3311569586 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 528114739 ps |
| CPU time | 4.18 seconds |
| Started | Sep 04 02:25:17 AM UTC 24 |
| Finished | Sep 04 02:25:23 AM UTC 24 |
| Peak memory | 215628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311569586 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_csr_outstanding.3311569586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/13.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_errors.2602243765 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 349008975 ps |
| CPU time | 7.08 seconds |
| Started | Sep 04 02:25:16 AM UTC 24 |
| Finished | Sep 04 02:25:24 AM UTC 24 |
| Peak memory | 225816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602243765 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.2602243765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/13.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_intg_err.4284830038 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 1655828983 ps |
| CPU time | 7.82 seconds |
| Started | Sep 04 02:25:17 AM UTC 24 |
| Finished | Sep 04 02:25:26 AM UTC 24 |
| Peak memory | 225796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284830038 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.4284830038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/13.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3353860048 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 330752187 ps |
| CPU time | 3.22 seconds |
| Started | Sep 04 02:25:19 AM UTC 24 |
| Finished | Sep 04 02:25:23 AM UTC 24 |
| Peak memory | 232028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3353860048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_ rand_reset.3353860048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/14.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_rw.244979923 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 48773350 ps |
| CPU time | 1.97 seconds |
| Started | Sep 04 02:25:19 AM UTC 24 |
| Finished | Sep 04 02:25:22 AM UTC 24 |
| Peak memory | 229232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244979923 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.244979923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/14.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1623976677 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 54851361 ps |
| CPU time | 0.89 seconds |
| Started | Sep 04 02:25:19 AM UTC 24 |
| Finished | Sep 04 02:25:20 AM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623976677 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_bit_bash.1623976677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/14.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3527765365 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 5957872036 ps |
| CPU time | 10.99 seconds |
| Started | Sep 04 02:25:19 AM UTC 24 |
| Finished | Sep 04 02:25:31 AM UTC 24 |
| Peak memory | 215424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527765365 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.3527765365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/14.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1834204759 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 387180967 ps |
| CPU time | 1.89 seconds |
| Started | Sep 04 02:25:17 AM UTC 24 |
| Finished | Sep 04 02:25:20 AM UTC 24 |
| Peak memory | 215136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834204759 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.1834204759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/14.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2985424155 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 465174940 ps |
| CPU time | 3.57 seconds |
| Started | Sep 04 02:25:19 AM UTC 24 |
| Finished | Sep 04 02:25:23 AM UTC 24 |
| Peak memory | 215592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985424155 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same_csr_outstanding.2985424155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/14.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_errors.3759551071 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 295129484 ps |
| CPU time | 5.66 seconds |
| Started | Sep 04 02:25:19 AM UTC 24 |
| Finished | Sep 04 02:25:25 AM UTC 24 |
| Peak memory | 225788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759551071 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.3759551071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/14.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_intg_err.295750515 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 3626310397 ps |
| CPU time | 14.21 seconds |
| Started | Sep 04 02:25:19 AM UTC 24 |
| Finished | Sep 04 02:25:34 AM UTC 24 |
| Peak memory | 225828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295750515 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.295750515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/14.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1649106618 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 371759023 ps |
| CPU time | 2.72 seconds |
| Started | Sep 04 02:25:20 AM UTC 24 |
| Finished | Sep 04 02:25:24 AM UTC 24 |
| Peak memory | 225680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1649106618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_ rand_reset.1649106618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/15.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_rw.605080206 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 297800644 ps |
| CPU time | 1.67 seconds |
| Started | Sep 04 02:25:20 AM UTC 24 |
| Finished | Sep 04 02:25:23 AM UTC 24 |
| Peak memory | 229232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605080206 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.605080206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/15.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2899447113 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 30608358976 ps |
| CPU time | 87.17 seconds |
| Started | Sep 04 02:25:19 AM UTC 24 |
| Finished | Sep 04 02:26:48 AM UTC 24 |
| Peak memory | 215432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899447113 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_bit_bash.2899447113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/15.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3946904937 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 3176644092 ps |
| CPU time | 12.41 seconds |
| Started | Sep 04 02:25:19 AM UTC 24 |
| Finished | Sep 04 02:25:32 AM UTC 24 |
| Peak memory | 215356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946904937 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.3946904937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/15.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.1110414437 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 860298840 ps |
| CPU time | 2.07 seconds |
| Started | Sep 04 02:25:19 AM UTC 24 |
| Finished | Sep 04 02:25:22 AM UTC 24 |
| Peak memory | 215064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110414437 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.1110414437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/15.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2143818416 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 3763267624 ps |
| CPU time | 9.12 seconds |
| Started | Sep 04 02:25:20 AM UTC 24 |
| Finished | Sep 04 02:25:30 AM UTC 24 |
| Peak memory | 215556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143818416 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_csr_outstanding.2143818416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/15.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_errors.2040447310 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 253137753 ps |
| CPU time | 3.97 seconds |
| Started | Sep 04 02:25:20 AM UTC 24 |
| Finished | Sep 04 02:25:25 AM UTC 24 |
| Peak memory | 225724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040447310 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.2040447310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/15.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_intg_err.817046981 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 1346792943 ps |
| CPU time | 11.33 seconds |
| Started | Sep 04 02:25:20 AM UTC 24 |
| Finished | Sep 04 02:25:32 AM UTC 24 |
| Peak memory | 225708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817046981 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.817046981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/15.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3466541589 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 78825708 ps |
| CPU time | 2.38 seconds |
| Started | Sep 04 02:25:22 AM UTC 24 |
| Finished | Sep 04 02:25:26 AM UTC 24 |
| Peak memory | 225752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3466541589 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_ rand_reset.3466541589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/16.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_rw.2238727732 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 729027939 ps |
| CPU time | 2.53 seconds |
| Started | Sep 04 02:25:21 AM UTC 24 |
| Finished | Sep 04 02:25:25 AM UTC 24 |
| Peak memory | 231808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238727732 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.2238727732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/16.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.3911742848 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 51756159016 ps |
| CPU time | 138.6 seconds |
| Started | Sep 04 02:25:21 AM UTC 24 |
| Finished | Sep 04 02:27:42 AM UTC 24 |
| Peak memory | 215524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911742848 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_bit_bash.3911742848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/16.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.840732352 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 2665385416 ps |
| CPU time | 9.25 seconds |
| Started | Sep 04 02:25:21 AM UTC 24 |
| Finished | Sep 04 02:25:32 AM UTC 24 |
| Peak memory | 215528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840732352 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.840732352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/16.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.4016748425 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 90423289 ps |
| CPU time | 1.36 seconds |
| Started | Sep 04 02:25:20 AM UTC 24 |
| Finished | Sep 04 02:25:22 AM UTC 24 |
| Peak memory | 215076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016748425 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.4016748425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/16.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1957878259 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 1120659521 ps |
| CPU time | 9.48 seconds |
| Started | Sep 04 02:25:22 AM UTC 24 |
| Finished | Sep 04 02:25:33 AM UTC 24 |
| Peak memory | 215500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957878259 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_csr_outstanding.1957878259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/16.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_errors.2453061600 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 64397243 ps |
| CPU time | 2.69 seconds |
| Started | Sep 04 02:25:21 AM UTC 24 |
| Finished | Sep 04 02:25:25 AM UTC 24 |
| Peak memory | 225784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453061600 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.2453061600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/16.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2326537585 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 3051673728 ps |
| CPU time | 10.21 seconds |
| Started | Sep 04 02:25:21 AM UTC 24 |
| Finished | Sep 04 02:25:33 AM UTC 24 |
| Peak memory | 225800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326537585 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.2326537585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/16.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.270917981 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 180901783 ps |
| CPU time | 2.4 seconds |
| Started | Sep 04 02:25:24 AM UTC 24 |
| Finished | Sep 04 02:25:27 AM UTC 24 |
| Peak memory | 225904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=270917981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_r and_reset.270917981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/17.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_rw.2591761523 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 227705964 ps |
| CPU time | 2.31 seconds |
| Started | Sep 04 02:25:24 AM UTC 24 |
| Finished | Sep 04 02:25:27 AM UTC 24 |
| Peak memory | 225588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591761523 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.2591761523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/17.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3368646790 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 9188666455 ps |
| CPU time | 13.85 seconds |
| Started | Sep 04 02:25:23 AM UTC 24 |
| Finished | Sep 04 02:25:38 AM UTC 24 |
| Peak memory | 215368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368646790 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_bit_bash.3368646790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/17.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3211503852 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 3020806270 ps |
| CPU time | 10.31 seconds |
| Started | Sep 04 02:25:23 AM UTC 24 |
| Finished | Sep 04 02:25:34 AM UTC 24 |
| Peak memory | 215356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211503852 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.3211503852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/17.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.963659987 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 156269139 ps |
| CPU time | 1.14 seconds |
| Started | Sep 04 02:25:22 AM UTC 24 |
| Finished | Sep 04 02:25:25 AM UTC 24 |
| Peak memory | 215084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963659987 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.963659987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/17.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2841319943 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 898268175 ps |
| CPU time | 6.83 seconds |
| Started | Sep 04 02:25:24 AM UTC 24 |
| Finished | Sep 04 02:25:32 AM UTC 24 |
| Peak memory | 215432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841319943 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same_csr_outstanding.2841319943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/17.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_errors.665737326 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 1050409083 ps |
| CPU time | 6.05 seconds |
| Started | Sep 04 02:25:23 AM UTC 24 |
| Finished | Sep 04 02:25:30 AM UTC 24 |
| Peak memory | 225800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665737326 -assert nopostproc +UVM_TESTNAME=rv_dm_base _test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.665737326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/17.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2514111318 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 862191496 ps |
| CPU time | 10.19 seconds |
| Started | Sep 04 02:25:24 AM UTC 24 |
| Finished | Sep 04 02:25:35 AM UTC 24 |
| Peak memory | 225804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514111318 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.2514111318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/17.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3941830183 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 71365490 ps |
| CPU time | 4.97 seconds |
| Started | Sep 04 02:25:26 AM UTC 24 |
| Finished | Sep 04 02:25:32 AM UTC 24 |
| Peak memory | 231952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3941830183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_ rand_reset.3941830183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/18.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_rw.213538244 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 121436699 ps |
| CPU time | 2.29 seconds |
| Started | Sep 04 02:25:25 AM UTC 24 |
| Finished | Sep 04 02:25:29 AM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213538244 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.213538244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/18.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.3789806205 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 23607405988 ps |
| CPU time | 55.34 seconds |
| Started | Sep 04 02:25:24 AM UTC 24 |
| Finished | Sep 04 02:26:21 AM UTC 24 |
| Peak memory | 215496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789806205 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_bit_bash.3789806205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/18.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3143180561 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 14154522164 ps |
| CPU time | 44.98 seconds |
| Started | Sep 04 02:25:24 AM UTC 24 |
| Finished | Sep 04 02:26:10 AM UTC 24 |
| Peak memory | 215388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143180561 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.3143180561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/18.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2719268884 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 1120667651 ps |
| CPU time | 1.8 seconds |
| Started | Sep 04 02:25:24 AM UTC 24 |
| Finished | Sep 04 02:25:27 AM UTC 24 |
| Peak memory | 215076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719268884 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.2719268884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/18.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3165884238 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 1126083003 ps |
| CPU time | 5.75 seconds |
| Started | Sep 04 02:25:25 AM UTC 24 |
| Finished | Sep 04 02:25:32 AM UTC 24 |
| Peak memory | 215528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165884238 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same_csr_outstanding.3165884238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/18.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_errors.1058722238 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 154375290 ps |
| CPU time | 2.22 seconds |
| Started | Sep 04 02:25:25 AM UTC 24 |
| Finished | Sep 04 02:25:28 AM UTC 24 |
| Peak memory | 225796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058722238 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.1058722238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/18.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2955052972 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 2821931309 ps |
| CPU time | 18.86 seconds |
| Started | Sep 04 02:25:25 AM UTC 24 |
| Finished | Sep 04 02:25:45 AM UTC 24 |
| Peak memory | 225736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955052972 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.2955052972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/18.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.508173210 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 636164767 ps |
| CPU time | 4.2 seconds |
| Started | Sep 04 02:25:28 AM UTC 24 |
| Finished | Sep 04 02:25:33 AM UTC 24 |
| Peak memory | 229868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=508173210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_r and_reset.508173210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/19.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_rw.2521284749 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 245079673 ps |
| CPU time | 1.7 seconds |
| Started | Sep 04 02:25:28 AM UTC 24 |
| Finished | Sep 04 02:25:31 AM UTC 24 |
| Peak memory | 225256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521284749 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.2521284749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/19.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.2457944596 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 25949728043 ps |
| CPU time | 68.6 seconds |
| Started | Sep 04 02:25:26 AM UTC 24 |
| Finished | Sep 04 02:26:37 AM UTC 24 |
| Peak memory | 215460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457944596 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_bit_bash.2457944596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/19.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2528609864 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 4674234891 ps |
| CPU time | 8.68 seconds |
| Started | Sep 04 02:25:26 AM UTC 24 |
| Finished | Sep 04 02:25:36 AM UTC 24 |
| Peak memory | 215400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528609864 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.2528609864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/19.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1820277936 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 663349299 ps |
| CPU time | 2.71 seconds |
| Started | Sep 04 02:25:26 AM UTC 24 |
| Finished | Sep 04 02:25:30 AM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820277936 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.1820277936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/19.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.873067674 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 614014718 ps |
| CPU time | 4.44 seconds |
| Started | Sep 04 02:25:28 AM UTC 24 |
| Finished | Sep 04 02:25:33 AM UTC 24 |
| Peak memory | 215372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873067674 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_csr_outstanding.873067674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/19.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_errors.1902059145 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 319704806 ps |
| CPU time | 3.28 seconds |
| Started | Sep 04 02:25:26 AM UTC 24 |
| Finished | Sep 04 02:25:31 AM UTC 24 |
| Peak memory | 225684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902059145 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.1902059145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/19.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_intg_err.583772477 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 1666779107 ps |
| CPU time | 10.94 seconds |
| Started | Sep 04 02:25:27 AM UTC 24 |
| Finished | Sep 04 02:25:39 AM UTC 24 |
| Peak memory | 225676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583772477 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.583772477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/19.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3879482833 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 3387756309 ps |
| CPU time | 76.03 seconds |
| Started | Sep 04 02:24:20 AM UTC 24 |
| Finished | Sep 04 02:25:39 AM UTC 24 |
| Peak memory | 215648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879482833 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_aliasing.3879482833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/2.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1644815765 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 729744585 ps |
| CPU time | 30.5 seconds |
| Started | Sep 04 02:24:26 AM UTC 24 |
| Finished | Sep 04 02:24:58 AM UTC 24 |
| Peak memory | 215340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644815765 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.1644815765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/2.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3267749085 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 218524072 ps |
| CPU time | 3.26 seconds |
| Started | Sep 04 02:24:26 AM UTC 24 |
| Finished | Sep 04 02:24:31 AM UTC 24 |
| Peak memory | 225700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267749085 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3267749085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/2.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1382873397 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 160150891 ps |
| CPU time | 4.52 seconds |
| Started | Sep 04 02:24:28 AM UTC 24 |
| Finished | Sep 04 02:24:33 AM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1382873397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_r and_reset.1382873397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/2.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_rw.278882495 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 92305167 ps |
| CPU time | 2.12 seconds |
| Started | Sep 04 02:24:26 AM UTC 24 |
| Finished | Sep 04 02:24:29 AM UTC 24 |
| Peak memory | 225696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278882495 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.278882495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/2.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1005012142 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 24056086644 ps |
| CPU time | 66.51 seconds |
| Started | Sep 04 02:24:24 AM UTC 24 |
| Finished | Sep 04 02:25:32 AM UTC 24 |
| Peak memory | 215424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005012142 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_aliasing.1005012142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3864645192 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 35232600588 ps |
| CPU time | 34.77 seconds |
| Started | Sep 04 02:24:24 AM UTC 24 |
| Finished | Sep 04 02:25:00 AM UTC 24 |
| Peak memory | 215488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864645192 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_bit_bash.3864645192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.82630631 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 3657564318 ps |
| CPU time | 13.41 seconds |
| Started | Sep 04 02:24:23 AM UTC 24 |
| Finished | Sep 04 02:24:37 AM UTC 24 |
| Peak memory | 215460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82630631 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_hw_reset.82630631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3101982019 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 1893255352 ps |
| CPU time | 3.29 seconds |
| Started | Sep 04 02:24:23 AM UTC 24 |
| Finished | Sep 04 02:24:27 AM UTC 24 |
| Peak memory | 215296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101982019 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.3101982019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3815406232 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 302149835 ps |
| CPU time | 1.16 seconds |
| Started | Sep 04 02:24:22 AM UTC 24 |
| Finished | Sep 04 02:24:24 AM UTC 24 |
| Peak memory | 215084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815406232 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_aliasing.3815406232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.501115778 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 2834719816 ps |
| CPU time | 4.02 seconds |
| Started | Sep 04 02:24:22 AM UTC 24 |
| Finished | Sep 04 02:24:27 AM UTC 24 |
| Peak memory | 215320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501115778 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_bit_bash.501115778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.422410064 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 1460696689 ps |
| CPU time | 2.47 seconds |
| Started | Sep 04 02:24:22 AM UTC 24 |
| Finished | Sep 04 02:24:25 AM UTC 24 |
| Peak memory | 215068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422410064 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_hw_reset.422410064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2648526821 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 505534972 ps |
| CPU time | 1.65 seconds |
| Started | Sep 04 02:24:22 AM UTC 24 |
| Finished | Sep 04 02:24:24 AM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648526821 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.2648526821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_partial_access.916643140 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 50865272 ps |
| CPU time | 1.07 seconds |
| Started | Sep 04 02:24:25 AM UTC 24 |
| Finished | Sep 04 02:24:27 AM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916643140 -assert nopostproc +UVM_ TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_partial_access.916643140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/2.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_walk.3796700896 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 62579880 ps |
| CPU time | 1.03 seconds |
| Started | Sep 04 02:24:25 AM UTC 24 |
| Finished | Sep 04 02:24:27 AM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796700896 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.3796700896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/2.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1463035480 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 575551070 ps |
| CPU time | 7.24 seconds |
| Started | Sep 04 02:24:26 AM UTC 24 |
| Finished | Sep 04 02:24:35 AM UTC 24 |
| Peak memory | 215584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463035480 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_csr_outstanding.1463035480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/2.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.1258452896 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 5098807276 ps |
| CPU time | 44.12 seconds |
| Started | Sep 04 02:24:25 AM UTC 24 |
| Finished | Sep 04 02:25:11 AM UTC 24 |
| Peak memory | 229820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1258452896 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_re set.1258452896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/2.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_errors.2466183717 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 654118952 ps |
| CPU time | 5.47 seconds |
| Started | Sep 04 02:24:25 AM UTC 24 |
| Finished | Sep 04 02:24:32 AM UTC 24 |
| Peak memory | 225720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466183717 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.2466183717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/2.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3890416827 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 2657924418 ps |
| CPU time | 35.54 seconds |
| Started | Sep 04 02:24:35 AM UTC 24 |
| Finished | Sep 04 02:25:12 AM UTC 24 |
| Peak memory | 225044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890416827 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.3890416827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/3.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2495833231 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 55529316 ps |
| CPU time | 2.31 seconds |
| Started | Sep 04 02:24:33 AM UTC 24 |
| Finished | Sep 04 02:24:37 AM UTC 24 |
| Peak memory | 225696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495833231 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.2495833231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/3.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1615589254 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 78144042 ps |
| CPU time | 2.25 seconds |
| Started | Sep 04 02:24:36 AM UTC 24 |
| Finished | Sep 04 02:24:39 AM UTC 24 |
| Peak memory | 229836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1615589254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_r and_reset.1615589254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/3.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_rw.1211337243 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 120892167 ps |
| CPU time | 3.24 seconds |
| Started | Sep 04 02:24:35 AM UTC 24 |
| Finished | Sep 04 02:24:39 AM UTC 24 |
| Peak memory | 231284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211337243 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.1211337243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/3.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2502494054 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 30713720772 ps |
| CPU time | 42.55 seconds |
| Started | Sep 04 02:24:31 AM UTC 24 |
| Finished | Sep 04 02:25:15 AM UTC 24 |
| Peak memory | 215460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502494054 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_aliasing.2502494054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3012125770 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 23443269576 ps |
| CPU time | 83.54 seconds |
| Started | Sep 04 02:24:30 AM UTC 24 |
| Finished | Sep 04 02:25:56 AM UTC 24 |
| Peak memory | 215488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012125770 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_bit_bash.3012125770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2773234745 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 6505499659 ps |
| CPU time | 16.46 seconds |
| Started | Sep 04 02:24:29 AM UTC 24 |
| Finished | Sep 04 02:24:47 AM UTC 24 |
| Peak memory | 215364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773234745 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_hw_reset.2773234745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.584442014 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 1157453967 ps |
| CPU time | 5.7 seconds |
| Started | Sep 04 02:24:30 AM UTC 24 |
| Finished | Sep 04 02:24:37 AM UTC 24 |
| Peak memory | 215224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584442014 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.584442014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3265875198 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 765181889 ps |
| CPU time | 2.99 seconds |
| Started | Sep 04 02:24:29 AM UTC 24 |
| Finished | Sep 04 02:24:33 AM UTC 24 |
| Peak memory | 215084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265875198 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_aliasing.3265875198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3160792480 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 16266107833 ps |
| CPU time | 15.58 seconds |
| Started | Sep 04 02:24:28 AM UTC 24 |
| Finished | Sep 04 02:24:45 AM UTC 24 |
| Peak memory | 215520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160792480 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_bit_bash.3160792480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1661277154 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 1126288174 ps |
| CPU time | 1.98 seconds |
| Started | Sep 04 02:24:28 AM UTC 24 |
| Finished | Sep 04 02:24:31 AM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661277154 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_hw_reset.1661277154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1838914936 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 276576273 ps |
| CPU time | 1.39 seconds |
| Started | Sep 04 02:24:28 AM UTC 24 |
| Finished | Sep 04 02:24:30 AM UTC 24 |
| Peak memory | 215140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838914936 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.1838914936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2947769065 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 70736332 ps |
| CPU time | 1.05 seconds |
| Started | Sep 04 02:24:33 AM UTC 24 |
| Finished | Sep 04 02:24:36 AM UTC 24 |
| Peak memory | 215140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947769065 -assert nopostproc +UVM _TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_partial_access.2947769065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/3.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_walk.2890773539 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 64264379 ps |
| CPU time | 1.03 seconds |
| Started | Sep 04 02:24:32 AM UTC 24 |
| Finished | Sep 04 02:24:34 AM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890773539 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.2890773539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/3.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3696580890 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 336219617 ps |
| CPU time | 6.45 seconds |
| Started | Sep 04 02:24:36 AM UTC 24 |
| Finished | Sep 04 02:24:43 AM UTC 24 |
| Peak memory | 215492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696580890 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_csr_outstanding.3696580890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/3.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3082391983 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 1035174656 ps |
| CPU time | 10.32 seconds |
| Started | Sep 04 02:24:31 AM UTC 24 |
| Finished | Sep 04 02:24:43 AM UTC 24 |
| Peak memory | 225752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3082391983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_re set.3082391983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/3.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_errors.2109536088 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 69660892 ps |
| CPU time | 2.8 seconds |
| Started | Sep 04 02:24:31 AM UTC 24 |
| Finished | Sep 04 02:24:35 AM UTC 24 |
| Peak memory | 225724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109536088 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.2109536088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/3.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2644415869 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 1861926994 ps |
| CPU time | 19.46 seconds |
| Started | Sep 04 02:24:32 AM UTC 24 |
| Finished | Sep 04 02:24:53 AM UTC 24 |
| Peak memory | 225604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644415869 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.2644415869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/3.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3515950001 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 5529469684 ps |
| CPU time | 81.93 seconds |
| Started | Sep 04 02:24:36 AM UTC 24 |
| Finished | Sep 04 02:26:00 AM UTC 24 |
| Peak memory | 215552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515950001 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_aliasing.3515950001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/4.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3862184625 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 1484090889 ps |
| CPU time | 57.56 seconds |
| Started | Sep 04 02:24:44 AM UTC 24 |
| Finished | Sep 04 02:25:43 AM UTC 24 |
| Peak memory | 215340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862184625 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.3862184625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/4.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1188577405 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 329419449 ps |
| CPU time | 2.02 seconds |
| Started | Sep 04 02:24:43 AM UTC 24 |
| Finished | Sep 04 02:24:46 AM UTC 24 |
| Peak memory | 225668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188577405 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.1188577405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/4.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1036757670 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 80776974 ps |
| CPU time | 2.57 seconds |
| Started | Sep 04 02:24:45 AM UTC 24 |
| Finished | Sep 04 02:24:49 AM UTC 24 |
| Peak memory | 225900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1036757670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_r and_reset.1036757670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/4.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_rw.2266633855 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 185374113 ps |
| CPU time | 3.85 seconds |
| Started | Sep 04 02:24:43 AM UTC 24 |
| Finished | Sep 04 02:24:48 AM UTC 24 |
| Peak memory | 225612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266633855 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.2266633855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/4.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3366958895 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 50255159009 ps |
| CPU time | 52.67 seconds |
| Started | Sep 04 02:24:40 AM UTC 24 |
| Finished | Sep 04 02:25:34 AM UTC 24 |
| Peak memory | 215428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366958895 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_aliasing.3366958895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.293534936 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 11776407425 ps |
| CPU time | 14.58 seconds |
| Started | Sep 04 02:24:40 AM UTC 24 |
| Finished | Sep 04 02:24:56 AM UTC 24 |
| Peak memory | 215288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293534936 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_bit_bash.293534936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.4149778532 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 19840486229 ps |
| CPU time | 35.42 seconds |
| Started | Sep 04 02:24:39 AM UTC 24 |
| Finished | Sep 04 02:25:16 AM UTC 24 |
| Peak memory | 215432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149778532 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_hw_reset.4149778532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2228552224 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 9520437230 ps |
| CPU time | 18.87 seconds |
| Started | Sep 04 02:24:39 AM UTC 24 |
| Finished | Sep 04 02:24:59 AM UTC 24 |
| Peak memory | 215360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228552224 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.2228552224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3366487694 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 260305149 ps |
| CPU time | 1.36 seconds |
| Started | Sep 04 02:24:38 AM UTC 24 |
| Finished | Sep 04 02:24:40 AM UTC 24 |
| Peak memory | 215084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366487694 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_aliasing.3366487694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2318811339 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 16655875427 ps |
| CPU time | 22.25 seconds |
| Started | Sep 04 02:24:38 AM UTC 24 |
| Finished | Sep 04 02:25:01 AM UTC 24 |
| Peak memory | 215324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318811339 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_bit_bash.2318811339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2849615913 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 213662909 ps |
| CPU time | 1.55 seconds |
| Started | Sep 04 02:24:37 AM UTC 24 |
| Finished | Sep 04 02:24:39 AM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849615913 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_hw_reset.2849615913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1574720615 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 233090847 ps |
| CPU time | 1.74 seconds |
| Started | Sep 04 02:24:38 AM UTC 24 |
| Finished | Sep 04 02:24:41 AM UTC 24 |
| Peak memory | 215140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574720615 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.1574720615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_partial_access.659282692 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 46082276 ps |
| CPU time | 1.01 seconds |
| Started | Sep 04 02:24:42 AM UTC 24 |
| Finished | Sep 04 02:24:44 AM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659282692 -assert nopostproc +UVM_ TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_partial_access.659282692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/4.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_walk.1613699744 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 62659517 ps |
| CPU time | 1.02 seconds |
| Started | Sep 04 02:24:42 AM UTC 24 |
| Finished | Sep 04 02:24:44 AM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613699744 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.1613699744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/4.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1658812045 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 483035087 ps |
| CPU time | 11.53 seconds |
| Started | Sep 04 02:24:44 AM UTC 24 |
| Finished | Sep 04 02:24:57 AM UTC 24 |
| Peak memory | 215520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658812045 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_csr_outstanding.1658812045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/4.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_errors.2468892127 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 120457939 ps |
| CPU time | 3.78 seconds |
| Started | Sep 04 02:24:40 AM UTC 24 |
| Finished | Sep 04 02:24:45 AM UTC 24 |
| Peak memory | 225740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468892127 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2468892127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/4.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1799519463 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 5067237806 ps |
| CPU time | 20.99 seconds |
| Started | Sep 04 02:24:42 AM UTC 24 |
| Finished | Sep 04 02:25:04 AM UTC 24 |
| Peak memory | 225720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799519463 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.1799519463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/4.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.744503618 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 122625372 ps |
| CPU time | 3.43 seconds |
| Started | Sep 04 02:24:49 AM UTC 24 |
| Finished | Sep 04 02:24:53 AM UTC 24 |
| Peak memory | 225772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=744503618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_ra nd_reset.744503618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/5.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_rw.1339331507 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 167715309 ps |
| CPU time | 2.18 seconds |
| Started | Sep 04 02:24:48 AM UTC 24 |
| Finished | Sep 04 02:24:52 AM UTC 24 |
| Peak memory | 225576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339331507 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.1339331507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/5.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.1344944170 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 2015528506 ps |
| CPU time | 4.77 seconds |
| Started | Sep 04 02:24:46 AM UTC 24 |
| Finished | Sep 04 02:24:52 AM UTC 24 |
| Peak memory | 215364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344944170 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_bit_bash.1344944170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/5.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2104546097 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 11550523383 ps |
| CPU time | 34.24 seconds |
| Started | Sep 04 02:24:45 AM UTC 24 |
| Finished | Sep 04 02:25:21 AM UTC 24 |
| Peak memory | 215420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104546097 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.2104546097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/5.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2202165112 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 132155233 ps |
| CPU time | 1.46 seconds |
| Started | Sep 04 02:24:45 AM UTC 24 |
| Finished | Sep 04 02:24:48 AM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202165112 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.2202165112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/5.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.4282850168 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 806560912 ps |
| CPU time | 5.92 seconds |
| Started | Sep 04 02:24:48 AM UTC 24 |
| Finished | Sep 04 02:24:55 AM UTC 24 |
| Peak memory | 215428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282850168 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_csr_outstanding.4282850168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/5.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.1515818301 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 4178615469 ps |
| CPU time | 28.63 seconds |
| Started | Sep 04 02:24:46 AM UTC 24 |
| Finished | Sep 04 02:25:16 AM UTC 24 |
| Peak memory | 232524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1515818301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_re set.1515818301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/5.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_errors.84516949 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 694543812 ps |
| CPU time | 4.24 seconds |
| Started | Sep 04 02:24:47 AM UTC 24 |
| Finished | Sep 04 02:24:53 AM UTC 24 |
| Peak memory | 227840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84516949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_ test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.84516949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/5.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_intg_err.166379043 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 3372451896 ps |
| CPU time | 12.56 seconds |
| Started | Sep 04 02:24:47 AM UTC 24 |
| Finished | Sep 04 02:25:01 AM UTC 24 |
| Peak memory | 227880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166379043 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.166379043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/5.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3152743499 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 141185592 ps |
| CPU time | 3.03 seconds |
| Started | Sep 04 02:24:55 AM UTC 24 |
| Finished | Sep 04 02:24:59 AM UTC 24 |
| Peak memory | 227732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3152743499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_r and_reset.3152743499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/6.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_rw.3028718990 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 129056171 ps |
| CPU time | 3.29 seconds |
| Started | Sep 04 02:24:54 AM UTC 24 |
| Finished | Sep 04 02:24:58 AM UTC 24 |
| Peak memory | 225620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028718990 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.3028718990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/6.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.1711627314 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 14232405307 ps |
| CPU time | 15.17 seconds |
| Started | Sep 04 02:24:53 AM UTC 24 |
| Finished | Sep 04 02:25:09 AM UTC 24 |
| Peak memory | 215424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711627314 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_bit_bash.1711627314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/6.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.4266899500 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 4959171814 ps |
| CPU time | 18.76 seconds |
| Started | Sep 04 02:24:50 AM UTC 24 |
| Finished | Sep 04 02:25:10 AM UTC 24 |
| Peak memory | 215488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266899500 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.4266899500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/6.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.4248374382 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 895042732 ps |
| CPU time | 3.47 seconds |
| Started | Sep 04 02:24:50 AM UTC 24 |
| Finished | Sep 04 02:24:54 AM UTC 24 |
| Peak memory | 215072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248374382 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.4248374382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/6.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.203321782 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 258506261 ps |
| CPU time | 6.09 seconds |
| Started | Sep 04 02:24:55 AM UTC 24 |
| Finished | Sep 04 02:25:02 AM UTC 24 |
| Peak memory | 215488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203321782 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_csr_outstanding.203321782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/6.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.4209587372 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 3321777560 ps |
| CPU time | 43.17 seconds |
| Started | Sep 04 02:24:53 AM UTC 24 |
| Finished | Sep 04 02:25:37 AM UTC 24 |
| Peak memory | 232552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=4209587372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_re set.4209587372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/6.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_errors.1557322007 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 128087725 ps |
| CPU time | 4.72 seconds |
| Started | Sep 04 02:24:54 AM UTC 24 |
| Finished | Sep 04 02:25:00 AM UTC 24 |
| Peak memory | 225660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557322007 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.1557322007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/6.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2537158930 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 742151525 ps |
| CPU time | 10.27 seconds |
| Started | Sep 04 02:24:54 AM UTC 24 |
| Finished | Sep 04 02:25:05 AM UTC 24 |
| Peak memory | 225888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537158930 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.2537158930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/6.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2467360004 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 118098806 ps |
| CPU time | 5.96 seconds |
| Started | Sep 04 02:25:00 AM UTC 24 |
| Finished | Sep 04 02:25:07 AM UTC 24 |
| Peak memory | 232040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2467360004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_r and_reset.2467360004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/7.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_rw.184372983 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 426583031 ps |
| CPU time | 2.24 seconds |
| Started | Sep 04 02:24:59 AM UTC 24 |
| Finished | Sep 04 02:25:03 AM UTC 24 |
| Peak memory | 229760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184372983 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.184372983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/7.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1291528481 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 5539169981 ps |
| CPU time | 6.13 seconds |
| Started | Sep 04 02:24:57 AM UTC 24 |
| Finished | Sep 04 02:25:04 AM UTC 24 |
| Peak memory | 215024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291528481 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_bit_bash.1291528481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/7.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3353978618 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 2199753593 ps |
| CPU time | 3.39 seconds |
| Started | Sep 04 02:24:56 AM UTC 24 |
| Finished | Sep 04 02:25:01 AM UTC 24 |
| Peak memory | 215552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353978618 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.3353978618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/7.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3771251202 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 526381947 ps |
| CPU time | 1.77 seconds |
| Started | Sep 04 02:24:55 AM UTC 24 |
| Finished | Sep 04 02:24:58 AM UTC 24 |
| Peak memory | 215140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771251202 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.3771251202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/7.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3812385312 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 603433246 ps |
| CPU time | 4.35 seconds |
| Started | Sep 04 02:25:00 AM UTC 24 |
| Finished | Sep 04 02:25:05 AM UTC 24 |
| Peak memory | 215568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812385312 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_csr_outstanding.3812385312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/7.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.657842411 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 3335623137 ps |
| CPU time | 15.1 seconds |
| Started | Sep 04 02:24:57 AM UTC 24 |
| Finished | Sep 04 02:25:14 AM UTC 24 |
| Peak memory | 227640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=657842411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.657842411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/7.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_errors.3150212292 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 198870526 ps |
| CPU time | 3.67 seconds |
| Started | Sep 04 02:24:57 AM UTC 24 |
| Finished | Sep 04 02:25:02 AM UTC 24 |
| Peak memory | 225800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150212292 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.3150212292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/7.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2266235684 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 2917947526 ps |
| CPU time | 15.81 seconds |
| Started | Sep 04 02:24:58 AM UTC 24 |
| Finished | Sep 04 02:25:15 AM UTC 24 |
| Peak memory | 225668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266235684 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2266235684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/7.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1367145830 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 61465239 ps |
| CPU time | 4.03 seconds |
| Started | Sep 04 02:25:02 AM UTC 24 |
| Finished | Sep 04 02:25:07 AM UTC 24 |
| Peak memory | 231896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1367145830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_r and_reset.1367145830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/8.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_rw.4187608106 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 102759505 ps |
| CPU time | 2.79 seconds |
| Started | Sep 04 02:25:02 AM UTC 24 |
| Finished | Sep 04 02:25:06 AM UTC 24 |
| Peak memory | 231712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187608106 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.4187608106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/8.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.2185673002 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 7627906476 ps |
| CPU time | 8.14 seconds |
| Started | Sep 04 02:25:01 AM UTC 24 |
| Finished | Sep 04 02:25:10 AM UTC 24 |
| Peak memory | 215356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185673002 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_bit_bash.2185673002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/8.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3097935265 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 4406629082 ps |
| CPU time | 18.3 seconds |
| Started | Sep 04 02:25:01 AM UTC 24 |
| Finished | Sep 04 02:25:20 AM UTC 24 |
| Peak memory | 215352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097935265 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.3097935265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/8.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.373153464 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 535342065 ps |
| CPU time | 3.72 seconds |
| Started | Sep 04 02:25:00 AM UTC 24 |
| Finished | Sep 04 02:25:04 AM UTC 24 |
| Peak memory | 215152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373153464 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.373153464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/8.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3543617934 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 1423726370 ps |
| CPU time | 5.12 seconds |
| Started | Sep 04 02:25:02 AM UTC 24 |
| Finished | Sep 04 02:25:08 AM UTC 24 |
| Peak memory | 215488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543617934 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_csr_outstanding.3543617934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/8.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3740205040 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 8938321315 ps |
| CPU time | 53.92 seconds |
| Started | Sep 04 02:25:01 AM UTC 24 |
| Finished | Sep 04 02:25:56 AM UTC 24 |
| Peak memory | 225920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3740205040 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_re set.3740205040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/8.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_errors.1308434629 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 533349750 ps |
| CPU time | 5.45 seconds |
| Started | Sep 04 02:25:01 AM UTC 24 |
| Finished | Sep 04 02:25:07 AM UTC 24 |
| Peak memory | 225860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308434629 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.1308434629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/8.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3527801026 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 3530527612 ps |
| CPU time | 22.68 seconds |
| Started | Sep 04 02:25:02 AM UTC 24 |
| Finished | Sep 04 02:25:26 AM UTC 24 |
| Peak memory | 229756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527801026 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.3527801026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/8.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.503347664 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 268504838 ps |
| CPU time | 2.05 seconds |
| Started | Sep 04 02:25:05 AM UTC 24 |
| Finished | Sep 04 02:25:09 AM UTC 24 |
| Peak memory | 225556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=503347664 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_ra nd_reset.503347664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/9.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_rw.2715367700 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 228286115 ps |
| CPU time | 1.93 seconds |
| Started | Sep 04 02:25:05 AM UTC 24 |
| Finished | Sep 04 02:25:08 AM UTC 24 |
| Peak memory | 225264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715367700 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.2715367700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/9.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2125000652 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 3669320986 ps |
| CPU time | 3.74 seconds |
| Started | Sep 04 02:25:03 AM UTC 24 |
| Finished | Sep 04 02:25:08 AM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125000652 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_bit_bash.2125000652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/9.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3933021438 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 2865154448 ps |
| CPU time | 8.83 seconds |
| Started | Sep 04 02:25:03 AM UTC 24 |
| Finished | Sep 04 02:25:13 AM UTC 24 |
| Peak memory | 215452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933021438 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.3933021438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/9.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1268903752 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 175416008 ps |
| CPU time | 1.07 seconds |
| Started | Sep 04 02:25:03 AM UTC 24 |
| Finished | Sep 04 02:25:05 AM UTC 24 |
| Peak memory | 215140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268903752 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.1268903752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/9.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1141030234 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 3064912491 ps |
| CPU time | 9.32 seconds |
| Started | Sep 04 02:25:05 AM UTC 24 |
| Finished | Sep 04 02:25:16 AM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141030234 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_csr_outstanding.1141030234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/9.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2936966715 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 1355281393 ps |
| CPU time | 24.54 seconds |
| Started | Sep 04 02:25:03 AM UTC 24 |
| Finished | Sep 04 02:25:29 AM UTC 24 |
| Peak memory | 227872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2936966715 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_re set.2936966715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/9.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_errors.3192180332 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 1347196230 ps |
| CPU time | 6.13 seconds |
| Started | Sep 04 02:25:04 AM UTC 24 |
| Finished | Sep 04 02:25:11 AM UTC 24 |
| Peak memory | 225696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192180332 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.3192180332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/9.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_intg_err.697682192 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 2014182760 ps |
| CPU time | 11.89 seconds |
| Started | Sep 04 02:25:04 AM UTC 24 |
| Finished | Sep 04 02:25:17 AM UTC 24 |
| Peak memory | 227708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697682192 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.697682192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/9.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.3674989388 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 156144102 ps |
| CPU time | 0.88 seconds |
| Started | Sep 04 02:25:34 AM UTC 24 |
| Finished | Sep 04 02:25:36 AM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674989388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_abstractcmd_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.3674989388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_abstractcmd_status/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.2260118555 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1279794468 ps |
| CPU time | 2.43 seconds |
| Started | Sep 04 02:25:29 AM UTC 24 |
| Finished | Sep 04 02:25:33 AM UTC 24 |
| Peak memory | 226428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260118555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.2260118555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.2719503417 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 105897890 ps |
| CPU time | 1.14 seconds |
| Started | Sep 04 02:25:34 AM UTC 24 |
| Finished | Sep 04 02:25:37 AM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719503417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_buffered_enable.2719503417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.1396775498 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 573444446 ps |
| CPU time | 2.17 seconds |
| Started | Sep 04 02:25:31 AM UTC 24 |
| Finished | Sep 04 02:25:35 AM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396775498 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.1396775498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_cmderr_exception/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.3347609031 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 164080814 ps |
| CPU time | 1.14 seconds |
| Started | Sep 04 02:25:31 AM UTC 24 |
| Finished | Sep 04 02:25:33 AM UTC 24 |
| Peak memory | 213340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347609031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.3347609031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_cmderr_not_supported/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_debug_disabled.3866958522 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 43139098 ps |
| CPU time | 0.84 seconds |
| Started | Sep 04 02:25:34 AM UTC 24 |
| Finished | Sep 04 02:25:37 AM UTC 24 |
| Peak memory | 236104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866958522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.3866958522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.3405509476 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 239924254 ps |
| CPU time | 1.2 seconds |
| Started | Sep 04 02:25:33 AM UTC 24 |
| Finished | Sep 04 02:25:35 AM UTC 24 |
| Peak memory | 214972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405509476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.3405509476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_hart_unavail.524163034 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 96000716 ps |
| CPU time | 1.12 seconds |
| Started | Sep 04 02:25:31 AM UTC 24 |
| Finished | Sep 04 02:25:34 AM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524163034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.524163034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_hartsel_warl.1378453144 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 77528643 ps |
| CPU time | 0.95 seconds |
| Started | Sep 04 02:25:34 AM UTC 24 |
| Finished | Sep 04 02:25:37 AM UTC 24 |
| Peak memory | 213452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378453144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.1378453144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_hartsel_warl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.1832843720 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 270892912 ps |
| CPU time | 0.81 seconds |
| Started | Sep 04 02:25:33 AM UTC 24 |
| Finished | Sep 04 02:25:35 AM UTC 24 |
| Peak memory | 213460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832843720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.1832843720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2649261142 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 711103622 ps |
| CPU time | 1.47 seconds |
| Started | Sep 04 02:25:33 AM UTC 24 |
| Finished | Sep 04 02:25:36 AM UTC 24 |
| Peak memory | 213460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649261142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.2649261142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_dm_inactive/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2847435683 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 319248597 ps |
| CPU time | 1.81 seconds |
| Started | Sep 04 02:25:34 AM UTC 24 |
| Finished | Sep 04 02:25:37 AM UTC 24 |
| Peak memory | 213452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847435683 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.2847435683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_hard_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_idle_hint.3229506472 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 92357431 ps |
| CPU time | 0.82 seconds |
| Started | Sep 04 02:25:33 AM UTC 24 |
| Finished | Sep 04 02:25:35 AM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229506472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.3229506472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_idle_hint/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_halted.606809980 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 182715410 ps |
| CPU time | 1.3 seconds |
| Started | Sep 04 02:25:31 AM UTC 24 |
| Finished | Sep 04 02:25:34 AM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606809980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.606809980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_halted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_resuming.2516480752 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 625424562 ps |
| CPU time | 1.81 seconds |
| Started | Sep 04 02:25:31 AM UTC 24 |
| Finished | Sep 04 02:25:34 AM UTC 24 |
| Peak memory | 213464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516480752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.2516480752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_resuming/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.3525430007 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 191895598 ps |
| CPU time | 1.03 seconds |
| Started | Sep 04 02:25:33 AM UTC 24 |
| Finished | Sep 04 02:25:35 AM UTC 24 |
| Peak memory | 225124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525430007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.3525430007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_ndmreset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_tl_access.2153808450 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 1999673401 ps |
| CPU time | 7.3 seconds |
| Started | Sep 04 02:25:28 AM UTC 24 |
| Finished | Sep 04 02:25:37 AM UTC 24 |
| Peak memory | 216124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153808450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2153808450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_smoke.2903360391 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 502353147 ps |
| CPU time | 3.48 seconds |
| Started | Sep 04 02:25:28 AM UTC 24 |
| Finished | Sep 04 02:25:33 AM UTC 24 |
| Peak memory | 215936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903360391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.2903360391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.1707828715 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 94663635 ps |
| CPU time | 1.02 seconds |
| Started | Sep 04 02:25:35 AM UTC 24 |
| Finished | Sep 04 02:25:38 AM UTC 24 |
| Peak memory | 225856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707828715 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sparse_lc_gate_fsm.1707828715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_sparse_lc_gate_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.3247832226 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 3345289112 ps |
| CPU time | 51.78 seconds |
| Started | Sep 04 02:25:35 AM UTC 24 |
| Finished | Sep 04 02:26:29 AM UTC 24 |
| Peak memory | 232432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3247832226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stres s_all_with_rand_reset.3247832226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_abstractcmd_status.1734778348 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 290761864 ps |
| CPU time | 1.04 seconds |
| Started | Sep 04 02:25:38 AM UTC 24 |
| Finished | Sep 04 02:25:40 AM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734778348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_abstractcmd_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.1734778348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_abstractcmd_status/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_alert_test.1014461067 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 142314631 ps |
| CPU time | 0.73 seconds |
| Started | Sep 04 02:25:39 AM UTC 24 |
| Finished | Sep 04 02:25:41 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014461067 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.1014461067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_autoincr_sba_tl_access.2135215664 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 8138308002 ps |
| CPU time | 22.85 seconds |
| Started | Sep 04 02:25:36 AM UTC 24 |
| Finished | Sep 04 02:26:00 AM UTC 24 |
| Peak memory | 233228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135215664 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.2135215664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_bad_sba_tl_access.2983340201 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 1253215738 ps |
| CPU time | 4.55 seconds |
| Started | Sep 04 02:25:35 AM UTC 24 |
| Finished | Sep 04 02:25:42 AM UTC 24 |
| Peak memory | 216316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983340201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.2983340201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_buffered_enable.2529976767 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 110789303 ps |
| CPU time | 1.28 seconds |
| Started | Sep 04 02:25:39 AM UTC 24 |
| Finished | Sep 04 02:25:42 AM UTC 24 |
| Peak memory | 258844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529976767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_buffered_enable.2529976767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_busy.3941417333 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 288932765 ps |
| CPU time | 1.13 seconds |
| Started | Sep 04 02:25:37 AM UTC 24 |
| Finished | Sep 04 02:25:39 AM UTC 24 |
| Peak memory | 213460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941417333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.3941417333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_cmderr_busy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.3625391866 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1218862730 ps |
| CPU time | 4.87 seconds |
| Started | Sep 04 02:25:37 AM UTC 24 |
| Finished | Sep 04 02:25:43 AM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625391866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.3625391866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_cmderr_halt_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_not_supported.2176577044 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 518106912 ps |
| CPU time | 1.24 seconds |
| Started | Sep 04 02:25:37 AM UTC 24 |
| Finished | Sep 04 02:25:39 AM UTC 24 |
| Peak memory | 213460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176577044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.2176577044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_cmderr_not_supported/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_dataaddr_rw_access.2276438425 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 274578727 ps |
| CPU time | 1.14 seconds |
| Started | Sep 04 02:25:37 AM UTC 24 |
| Finished | Sep 04 02:25:39 AM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276438425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.2276438425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_dataaddr_rw_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_debug_disabled.2265818701 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 87868877 ps |
| CPU time | 0.91 seconds |
| Started | Sep 04 02:25:38 AM UTC 24 |
| Finished | Sep 04 02:25:40 AM UTC 24 |
| Peak memory | 237484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265818701 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.2265818701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.4140375647 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 5992421672 ps |
| CPU time | 17.48 seconds |
| Started | Sep 04 02:25:35 AM UTC 24 |
| Finished | Sep 04 02:25:55 AM UTC 24 |
| Peak memory | 226556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140375647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_tl_access.4140375647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_hart_unavail.2650298260 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 103572727 ps |
| CPU time | 0.94 seconds |
| Started | Sep 04 02:25:37 AM UTC 24 |
| Finished | Sep 04 02:25:39 AM UTC 24 |
| Peak memory | 213452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650298260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.2650298260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.267813428 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 445250213 ps |
| CPU time | 1.31 seconds |
| Started | Sep 04 02:25:38 AM UTC 24 |
| Finished | Sep 04 02:25:41 AM UTC 24 |
| Peak memory | 213452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267813428 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.267813428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.2492281597 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 672912803 ps |
| CPU time | 2.65 seconds |
| Started | Sep 04 02:25:38 AM UTC 24 |
| Finished | Sep 04 02:25:42 AM UTC 24 |
| Peak memory | 215876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492281597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.2492281597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_dm_inactive/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3077125079 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 162119894 ps |
| CPU time | 0.96 seconds |
| Started | Sep 04 02:25:38 AM UTC 24 |
| Finished | Sep 04 02:25:40 AM UTC 24 |
| Peak memory | 213452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077125079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.3077125079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_hard_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_idle_hint.3315303243 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 371366129 ps |
| CPU time | 1.57 seconds |
| Started | Sep 04 02:25:38 AM UTC 24 |
| Finished | Sep 04 02:25:41 AM UTC 24 |
| Peak memory | 215696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315303243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.3315303243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_idle_hint/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_halted.3237794184 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 323179560 ps |
| CPU time | 0.91 seconds |
| Started | Sep 04 02:25:37 AM UTC 24 |
| Finished | Sep 04 02:25:39 AM UTC 24 |
| Peak memory | 213460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237794184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.3237794184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_mem_tl_access_halted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_resuming.1146808014 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 165310745 ps |
| CPU time | 1.07 seconds |
| Started | Sep 04 02:25:37 AM UTC 24 |
| Finished | Sep 04 02:25:39 AM UTC 24 |
| Peak memory | 213464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146808014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.1146808014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_mem_tl_access_resuming/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_ndmreset_req.1307864050 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 773157357 ps |
| CPU time | 3.11 seconds |
| Started | Sep 04 02:25:38 AM UTC 24 |
| Finished | Sep 04 02:25:42 AM UTC 24 |
| Peak memory | 225492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307864050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.1307864050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_ndmreset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_progbuf_read_write_execute.797772581 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 560567986 ps |
| CPU time | 0.88 seconds |
| Started | Sep 04 02:25:38 AM UTC 24 |
| Finished | Sep 04 02:25:40 AM UTC 24 |
| Peak memory | 215944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797772581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_progbuf_read_write_execute_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.797772581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_progbuf_read_write_execute/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_rom_read_access.2705900610 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 44097887 ps |
| CPU time | 0.89 seconds |
| Started | Sep 04 02:25:38 AM UTC 24 |
| Finished | Sep 04 02:25:40 AM UTC 24 |
| Peak memory | 225792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705900610 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_rom_read_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.2705900610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_rom_read_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_debug_disabled.1690190199 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 3529194468 ps |
| CPU time | 9.87 seconds |
| Started | Sep 04 02:25:38 AM UTC 24 |
| Finished | Sep 04 02:25:49 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690190199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.1690190199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_sba_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_tl_access.1942503369 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 2475348791 ps |
| CPU time | 3.06 seconds |
| Started | Sep 04 02:25:35 AM UTC 24 |
| Finished | Sep 04 02:25:40 AM UTC 24 |
| Peak memory | 216344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942503369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.1942503369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_sec_cm.130801666 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 1681510339 ps |
| CPU time | 6.15 seconds |
| Started | Sep 04 02:25:39 AM UTC 24 |
| Finished | Sep 04 02:25:47 AM UTC 24 |
| Peak memory | 254884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130801666 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.130801666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_smoke.3930403142 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 2313916555 ps |
| CPU time | 8.21 seconds |
| Started | Sep 04 02:25:35 AM UTC 24 |
| Finished | Sep 04 02:25:45 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930403142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.3930403142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.4271873530 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 8189455777 ps |
| CPU time | 11.46 seconds |
| Started | Sep 04 02:25:39 AM UTC 24 |
| Finished | Sep 04 02:25:52 AM UTC 24 |
| Peak memory | 216132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271873530 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.4271873530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/1.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/10.rv_dm_alert_test.3155945812 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 73051061 ps |
| CPU time | 1.35 seconds |
| Started | Sep 04 02:25:54 AM UTC 24 |
| Finished | Sep 04 02:25:56 AM UTC 24 |
| Peak memory | 214252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155945812 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.3155945812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/10.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/10.rv_dm_autoincr_sba_tl_access.929874243 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 2398743343 ps |
| CPU time | 3.91 seconds |
| Started | Sep 04 02:25:52 AM UTC 24 |
| Finished | Sep 04 02:25:58 AM UTC 24 |
| Peak memory | 216320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929874243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.929874243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/10.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/10.rv_dm_bad_sba_tl_access.2692884351 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 8198922581 ps |
| CPU time | 13.67 seconds |
| Started | Sep 04 02:25:52 AM UTC 24 |
| Finished | Sep 04 02:26:08 AM UTC 24 |
| Peak memory | 226432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692884351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.2692884351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/10.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.3568874825 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 9776751134 ps |
| CPU time | 14.71 seconds |
| Started | Sep 04 02:25:52 AM UTC 24 |
| Finished | Sep 04 02:26:09 AM UTC 24 |
| Peak memory | 226688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568874825 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_tl_access.3568874825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/10.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/10.rv_dm_sba_tl_access.3263553613 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 1848718259 ps |
| CPU time | 5.2 seconds |
| Started | Sep 04 02:25:52 AM UTC 24 |
| Finished | Sep 04 02:25:59 AM UTC 24 |
| Peak memory | 216148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263553613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.3263553613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/10.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/10.rv_dm_stress_all.2984560779 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 2786650799 ps |
| CPU time | 4.93 seconds |
| Started | Sep 04 02:25:54 AM UTC 24 |
| Finished | Sep 04 02:26:00 AM UTC 24 |
| Peak memory | 225500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984560779 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.2984560779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/10.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/11.rv_dm_alert_test.1018334784 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 125482858 ps |
| CPU time | 1.05 seconds |
| Started | Sep 04 02:25:55 AM UTC 24 |
| Finished | Sep 04 02:25:57 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018334784 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.1018334784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/11.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/11.rv_dm_autoincr_sba_tl_access.897669972 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 62702509194 ps |
| CPU time | 99.84 seconds |
| Started | Sep 04 02:25:55 AM UTC 24 |
| Finished | Sep 04 02:27:37 AM UTC 24 |
| Peak memory | 226556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897669972 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.897669972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/11.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/11.rv_dm_bad_sba_tl_access.2577015018 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 2843083702 ps |
| CPU time | 3.73 seconds |
| Started | Sep 04 02:25:54 AM UTC 24 |
| Finished | Sep 04 02:25:59 AM UTC 24 |
| Peak memory | 226636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577015018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.2577015018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/11.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.797445253 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 3480353860 ps |
| CPU time | 3.89 seconds |
| Started | Sep 04 02:25:54 AM UTC 24 |
| Finished | Sep 04 02:25:59 AM UTC 24 |
| Peak memory | 216252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797445253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_tl_access.797445253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/11.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/11.rv_dm_sba_tl_access.3602010309 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 2384808977 ps |
| CPU time | 4.55 seconds |
| Started | Sep 04 02:25:54 AM UTC 24 |
| Finished | Sep 04 02:25:59 AM UTC 24 |
| Peak memory | 215684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602010309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.3602010309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/11.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/11.rv_dm_stress_all.2363184889 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 4417545668 ps |
| CPU time | 10.24 seconds |
| Started | Sep 04 02:25:55 AM UTC 24 |
| Finished | Sep 04 02:26:06 AM UTC 24 |
| Peak memory | 216204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363184889 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.2363184889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/11.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/12.rv_dm_alert_test.2297320554 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 60188450 ps |
| CPU time | 1.17 seconds |
| Started | Sep 04 02:25:56 AM UTC 24 |
| Finished | Sep 04 02:25:59 AM UTC 24 |
| Peak memory | 215552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297320554 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.2297320554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/12.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/12.rv_dm_autoincr_sba_tl_access.1626183715 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 6699596589 ps |
| CPU time | 4.57 seconds |
| Started | Sep 04 02:25:56 AM UTC 24 |
| Finished | Sep 04 02:26:02 AM UTC 24 |
| Peak memory | 226640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626183715 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.1626183715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/12.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/12.rv_dm_bad_sba_tl_access.181786561 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 3448014522 ps |
| CPU time | 14.92 seconds |
| Started | Sep 04 02:25:56 AM UTC 24 |
| Finished | Sep 04 02:26:12 AM UTC 24 |
| Peak memory | 226072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181786561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.181786561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/12.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.2256913414 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 2520538957 ps |
| CPU time | 8.46 seconds |
| Started | Sep 04 02:25:55 AM UTC 24 |
| Finished | Sep 04 02:26:05 AM UTC 24 |
| Peak memory | 226676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256913414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_tl_access.2256913414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/12.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/12.rv_dm_sba_tl_access.2255381616 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 7185657123 ps |
| CPU time | 28 seconds |
| Started | Sep 04 02:25:55 AM UTC 24 |
| Finished | Sep 04 02:26:24 AM UTC 24 |
| Peak memory | 226580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255381616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.2255381616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/12.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/12.rv_dm_stress_all.923902419 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 5989111258 ps |
| CPU time | 4.59 seconds |
| Started | Sep 04 02:25:56 AM UTC 24 |
| Finished | Sep 04 02:26:02 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923902419 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.923902419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/12.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/13.rv_dm_alert_test.4089197719 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 43264002 ps |
| CPU time | 1.06 seconds |
| Started | Sep 04 02:25:59 AM UTC 24 |
| Finished | Sep 04 02:26:01 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089197719 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.4089197719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/13.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/13.rv_dm_autoincr_sba_tl_access.3189921616 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 15995414502 ps |
| CPU time | 31.67 seconds |
| Started | Sep 04 02:25:59 AM UTC 24 |
| Finished | Sep 04 02:26:32 AM UTC 24 |
| Peak memory | 226568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189921616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.3189921616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/13.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/13.rv_dm_bad_sba_tl_access.2654832479 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 9468686194 ps |
| CPU time | 14.47 seconds |
| Started | Sep 04 02:25:58 AM UTC 24 |
| Finished | Sep 04 02:26:13 AM UTC 24 |
| Peak memory | 226492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654832479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.2654832479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/13.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.2142818892 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 8558107836 ps |
| CPU time | 21.11 seconds |
| Started | Sep 04 02:25:58 AM UTC 24 |
| Finished | Sep 04 02:26:20 AM UTC 24 |
| Peak memory | 226624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142818892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_tl_access.2142818892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/13.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/13.rv_dm_sba_tl_access.3771657017 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 9721259174 ps |
| CPU time | 13.35 seconds |
| Started | Sep 04 02:25:58 AM UTC 24 |
| Finished | Sep 04 02:26:12 AM UTC 24 |
| Peak memory | 216128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771657017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.3771657017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/13.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/14.rv_dm_alert_test.3836990958 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 107081224 ps |
| CPU time | 0.93 seconds |
| Started | Sep 04 02:26:00 AM UTC 24 |
| Finished | Sep 04 02:26:02 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836990958 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.3836990958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/14.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/14.rv_dm_autoincr_sba_tl_access.3403166005 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 15077774016 ps |
| CPU time | 20.72 seconds |
| Started | Sep 04 02:26:00 AM UTC 24 |
| Finished | Sep 04 02:26:22 AM UTC 24 |
| Peak memory | 226632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403166005 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.3403166005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/14.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.3528988341 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 5318283615 ps |
| CPU time | 19.35 seconds |
| Started | Sep 04 02:26:00 AM UTC 24 |
| Finished | Sep 04 02:26:21 AM UTC 24 |
| Peak memory | 226480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528988341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_tl_access.3528988341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/14.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/14.rv_dm_sba_tl_access.1937023032 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 2434682789 ps |
| CPU time | 5.76 seconds |
| Started | Sep 04 02:25:59 AM UTC 24 |
| Finished | Sep 04 02:26:06 AM UTC 24 |
| Peak memory | 216260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937023032 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.1937023032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/14.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/14.rv_dm_stress_all.1955692546 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 2256683459 ps |
| CPU time | 4.71 seconds |
| Started | Sep 04 02:26:00 AM UTC 24 |
| Finished | Sep 04 02:26:06 AM UTC 24 |
| Peak memory | 226316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955692546 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.1955692546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/14.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/15.rv_dm_alert_test.2326099641 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 209979720 ps |
| CPU time | 1.13 seconds |
| Started | Sep 04 02:26:02 AM UTC 24 |
| Finished | Sep 04 02:26:04 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326099641 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.2326099641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/15.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/15.rv_dm_autoincr_sba_tl_access.3272449714 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 10779115526 ps |
| CPU time | 25.2 seconds |
| Started | Sep 04 02:26:02 AM UTC 24 |
| Finished | Sep 04 02:26:28 AM UTC 24 |
| Peak memory | 226556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272449714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.3272449714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/15.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/15.rv_dm_bad_sba_tl_access.467424980 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 5639560450 ps |
| CPU time | 11.23 seconds |
| Started | Sep 04 02:26:00 AM UTC 24 |
| Finished | Sep 04 02:26:13 AM UTC 24 |
| Peak memory | 233220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467424980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.467424980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/15.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2188728513 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 6240460094 ps |
| CPU time | 6.87 seconds |
| Started | Sep 04 02:26:00 AM UTC 24 |
| Finished | Sep 04 02:26:08 AM UTC 24 |
| Peak memory | 226504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188728513 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_tl_access.2188728513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/15.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/15.rv_dm_sba_tl_access.773408682 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 13708293228 ps |
| CPU time | 24.05 seconds |
| Started | Sep 04 02:26:00 AM UTC 24 |
| Finished | Sep 04 02:26:26 AM UTC 24 |
| Peak memory | 226512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773408682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.773408682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/15.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/15.rv_dm_stress_all.1350110633 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 2450157881 ps |
| CPU time | 8.69 seconds |
| Started | Sep 04 02:26:02 AM UTC 24 |
| Finished | Sep 04 02:26:11 AM UTC 24 |
| Peak memory | 226316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350110633 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.1350110633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/15.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/16.rv_dm_alert_test.1393333168 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 68766276 ps |
| CPU time | 1.35 seconds |
| Started | Sep 04 02:26:04 AM UTC 24 |
| Finished | Sep 04 02:26:06 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393333168 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.1393333168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/16.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/16.rv_dm_autoincr_sba_tl_access.763709802 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 1758210393 ps |
| CPU time | 6.98 seconds |
| Started | Sep 04 02:26:04 AM UTC 24 |
| Finished | Sep 04 02:26:12 AM UTC 24 |
| Peak memory | 226440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763709802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.763709802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/16.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/16.rv_dm_bad_sba_tl_access.1096477123 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 2147107010 ps |
| CPU time | 6.74 seconds |
| Started | Sep 04 02:26:03 AM UTC 24 |
| Finished | Sep 04 02:26:11 AM UTC 24 |
| Peak memory | 216256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096477123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.1096477123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/16.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.3310268148 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 8344134877 ps |
| CPU time | 7.59 seconds |
| Started | Sep 04 02:26:03 AM UTC 24 |
| Finished | Sep 04 02:26:11 AM UTC 24 |
| Peak memory | 226504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310268148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_tl_access.3310268148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/16.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/16.rv_dm_sba_tl_access.2367257594 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 4172378686 ps |
| CPU time | 6.84 seconds |
| Started | Sep 04 02:26:03 AM UTC 24 |
| Finished | Sep 04 02:26:11 AM UTC 24 |
| Peak memory | 216328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367257594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.2367257594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/16.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/16.rv_dm_stress_all.681986038 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 4479014305 ps |
| CPU time | 14.56 seconds |
| Started | Sep 04 02:26:04 AM UTC 24 |
| Finished | Sep 04 02:26:20 AM UTC 24 |
| Peak memory | 226304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681986038 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.681986038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/16.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/17.rv_dm_alert_test.118164892 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 147685078 ps |
| CPU time | 1.1 seconds |
| Started | Sep 04 02:26:08 AM UTC 24 |
| Finished | Sep 04 02:26:10 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118164892 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.118164892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/17.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/17.rv_dm_autoincr_sba_tl_access.591566830 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 63638987249 ps |
| CPU time | 180.82 seconds |
| Started | Sep 04 02:26:06 AM UTC 24 |
| Finished | Sep 04 02:29:10 AM UTC 24 |
| Peak memory | 228036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591566830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.591566830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/17.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.3128820494 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 10302607119 ps |
| CPU time | 17.5 seconds |
| Started | Sep 04 02:26:05 AM UTC 24 |
| Finished | Sep 04 02:26:24 AM UTC 24 |
| Peak memory | 226492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128820494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_tl_access.3128820494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/17.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/17.rv_dm_sba_tl_access.2325206285 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 2838029520 ps |
| CPU time | 7.25 seconds |
| Started | Sep 04 02:26:05 AM UTC 24 |
| Finished | Sep 04 02:26:13 AM UTC 24 |
| Peak memory | 216324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325206285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.2325206285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/17.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/18.rv_dm_alert_test.1980166647 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 133782199 ps |
| CPU time | 1.58 seconds |
| Started | Sep 04 02:26:11 AM UTC 24 |
| Finished | Sep 04 02:26:14 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980166647 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.1980166647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/18.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/18.rv_dm_autoincr_sba_tl_access.2120105758 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 1536658723 ps |
| CPU time | 3.73 seconds |
| Started | Sep 04 02:26:10 AM UTC 24 |
| Finished | Sep 04 02:26:15 AM UTC 24 |
| Peak memory | 233224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120105758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.2120105758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/18.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/18.rv_dm_bad_sba_tl_access.622898358 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 7188661428 ps |
| CPU time | 5.57 seconds |
| Started | Sep 04 02:26:09 AM UTC 24 |
| Finished | Sep 04 02:26:15 AM UTC 24 |
| Peak memory | 226512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622898358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.622898358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/18.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.1114580249 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 5743041830 ps |
| CPU time | 7 seconds |
| Started | Sep 04 02:26:09 AM UTC 24 |
| Finished | Sep 04 02:26:17 AM UTC 24 |
| Peak memory | 226032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114580249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_tl_access.1114580249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/18.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/18.rv_dm_sba_tl_access.2428657792 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 1067577563 ps |
| CPU time | 4.04 seconds |
| Started | Sep 04 02:26:08 AM UTC 24 |
| Finished | Sep 04 02:26:13 AM UTC 24 |
| Peak memory | 216316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428657792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.2428657792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/18.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/18.rv_dm_stress_all.3161441746 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 1037707759 ps |
| CPU time | 1.8 seconds |
| Started | Sep 04 02:26:10 AM UTC 24 |
| Finished | Sep 04 02:26:13 AM UTC 24 |
| Peak memory | 225740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161441746 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.3161441746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/18.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/19.rv_dm_alert_test.1253000538 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 119037608 ps |
| CPU time | 1.34 seconds |
| Started | Sep 04 02:26:12 AM UTC 24 |
| Finished | Sep 04 02:26:15 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253000538 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.1253000538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/19.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.1759887273 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 15549653329 ps |
| CPU time | 45.32 seconds |
| Started | Sep 04 02:26:12 AM UTC 24 |
| Finished | Sep 04 02:26:59 AM UTC 24 |
| Peak memory | 226512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759887273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.1759887273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/19.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/19.rv_dm_bad_sba_tl_access.3435281731 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 2197354725 ps |
| CPU time | 2.64 seconds |
| Started | Sep 04 02:26:11 AM UTC 24 |
| Finished | Sep 04 02:26:15 AM UTC 24 |
| Peak memory | 226632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435281731 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.3435281731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/19.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2622876114 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 5140328968 ps |
| CPU time | 8.85 seconds |
| Started | Sep 04 02:26:11 AM UTC 24 |
| Finished | Sep 04 02:26:21 AM UTC 24 |
| Peak memory | 226548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622876114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_tl_access.2622876114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/19.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/19.rv_dm_sba_tl_access.1794679649 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 3306538086 ps |
| CPU time | 4 seconds |
| Started | Sep 04 02:26:11 AM UTC 24 |
| Finished | Sep 04 02:26:16 AM UTC 24 |
| Peak memory | 216264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794679649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.1794679649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/19.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.1234473966 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 106166333 ps |
| CPU time | 1.1 seconds |
| Started | Sep 04 02:25:41 AM UTC 24 |
| Finished | Sep 04 02:25:43 AM UTC 24 |
| Peak memory | 215876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234473966 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.1234473966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/2.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.938765428 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 44564504794 ps |
| CPU time | 99.21 seconds |
| Started | Sep 04 02:25:41 AM UTC 24 |
| Finished | Sep 04 02:27:22 AM UTC 24 |
| Peak memory | 226484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938765428 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.938765428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/2.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.1558744193 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 4763198135 ps |
| CPU time | 16.1 seconds |
| Started | Sep 04 02:25:41 AM UTC 24 |
| Finished | Sep 04 02:25:58 AM UTC 24 |
| Peak memory | 216260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558744193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.1558744193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/2.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.2506875059 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 1347739076 ps |
| CPU time | 3.65 seconds |
| Started | Sep 04 02:25:39 AM UTC 24 |
| Finished | Sep 04 02:25:44 AM UTC 24 |
| Peak memory | 216132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506875059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_tl_access.2506875059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/2.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.472665159 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 326548016 ps |
| CPU time | 1.16 seconds |
| Started | Sep 04 02:25:41 AM UTC 24 |
| Finished | Sep 04 02:25:43 AM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472665159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_halt_resume_whereto.472665159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/2.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.2434064343 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 92088770 ps |
| CPU time | 0.8 seconds |
| Started | Sep 04 02:25:41 AM UTC 24 |
| Finished | Sep 04 02:25:42 AM UTC 24 |
| Peak memory | 213452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434064343 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.2434064343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/2.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.3327334573 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 1190849401 ps |
| CPU time | 4.02 seconds |
| Started | Sep 04 02:25:39 AM UTC 24 |
| Finished | Sep 04 02:25:45 AM UTC 24 |
| Peak memory | 216268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327334573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.3327334573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/2.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.1622849003 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 1295328670 ps |
| CPU time | 4.71 seconds |
| Started | Sep 04 02:25:41 AM UTC 24 |
| Finished | Sep 04 02:25:47 AM UTC 24 |
| Peak memory | 252572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622849003 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.1622849003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/2.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/2.rv_dm_sparse_lc_gate_fsm.3562789608 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 86984991 ps |
| CPU time | 0.91 seconds |
| Started | Sep 04 02:25:41 AM UTC 24 |
| Finished | Sep 04 02:25:43 AM UTC 24 |
| Peak memory | 225856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562789608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sparse_lc_gate_fsm.3562789608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/2.rv_dm_sparse_lc_gate_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all.1684843820 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 2280589140 ps |
| CPU time | 7.82 seconds |
| Started | Sep 04 02:25:41 AM UTC 24 |
| Finished | Sep 04 02:25:50 AM UTC 24 |
| Peak memory | 226444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684843820 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.1684843820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/2.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/20.rv_dm_alert_test.3892743868 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 111249431 ps |
| CPU time | 1.01 seconds |
| Started | Sep 04 02:26:14 AM UTC 24 |
| Finished | Sep 04 02:26:16 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892743868 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.3892743868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/20.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.38891158 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 3701476793 ps |
| CPU time | 6.45 seconds |
| Started | Sep 04 02:26:12 AM UTC 24 |
| Finished | Sep 04 02:26:20 AM UTC 24 |
| Peak memory | 216088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38891158 -assert nopostproc +UVM_TESTNAME=rv_ dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.38891158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/20.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/21.rv_dm_alert_test.2029207407 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 62635458 ps |
| CPU time | 1.05 seconds |
| Started | Sep 04 02:26:14 AM UTC 24 |
| Finished | Sep 04 02:26:16 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029207407 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.2029207407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/21.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/21.rv_dm_stress_all.524826073 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 2654305422 ps |
| CPU time | 4.3 seconds |
| Started | Sep 04 02:26:14 AM UTC 24 |
| Finished | Sep 04 02:26:19 AM UTC 24 |
| Peak memory | 226424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524826073 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.524826073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/21.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/22.rv_dm_alert_test.670018540 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 36436833 ps |
| CPU time | 1.22 seconds |
| Started | Sep 04 02:26:14 AM UTC 24 |
| Finished | Sep 04 02:26:16 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670018540 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.670018540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/22.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/23.rv_dm_alert_test.2044274885 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 132040566 ps |
| CPU time | 1.14 seconds |
| Started | Sep 04 02:26:14 AM UTC 24 |
| Finished | Sep 04 02:26:16 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044274885 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.2044274885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/23.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/23.rv_dm_stress_all.118098942 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 5347590403 ps |
| CPU time | 14.56 seconds |
| Started | Sep 04 02:26:14 AM UTC 24 |
| Finished | Sep 04 02:26:30 AM UTC 24 |
| Peak memory | 216204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118098942 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.118098942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/23.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/24.rv_dm_alert_test.3122323276 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 128371983 ps |
| CPU time | 1.35 seconds |
| Started | Sep 04 02:26:15 AM UTC 24 |
| Finished | Sep 04 02:26:18 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122323276 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.3122323276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/24.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/24.rv_dm_stress_all.2740219215 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 3402617343 ps |
| CPU time | 11.47 seconds |
| Started | Sep 04 02:26:14 AM UTC 24 |
| Finished | Sep 04 02:26:27 AM UTC 24 |
| Peak memory | 226380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740219215 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.2740219215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/24.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/25.rv_dm_alert_test.201314370 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 60185616 ps |
| CPU time | 0.93 seconds |
| Started | Sep 04 02:26:15 AM UTC 24 |
| Finished | Sep 04 02:26:17 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201314370 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.201314370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/25.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.1505210783 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 4156250383 ps |
| CPU time | 13 seconds |
| Started | Sep 04 02:26:15 AM UTC 24 |
| Finished | Sep 04 02:26:29 AM UTC 24 |
| Peak memory | 226436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505210783 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.1505210783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/25.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/26.rv_dm_alert_test.661114176 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 64526199 ps |
| CPU time | 1.33 seconds |
| Started | Sep 04 02:26:15 AM UTC 24 |
| Finished | Sep 04 02:26:18 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661114176 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.661114176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/26.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/26.rv_dm_stress_all.2226719760 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 1755439653 ps |
| CPU time | 7.2 seconds |
| Started | Sep 04 02:26:15 AM UTC 24 |
| Finished | Sep 04 02:26:24 AM UTC 24 |
| Peak memory | 216072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226719760 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.2226719760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/26.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/27.rv_dm_alert_test.3923237744 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 27329063 ps |
| CPU time | 1.08 seconds |
| Started | Sep 04 02:26:16 AM UTC 24 |
| Finished | Sep 04 02:26:19 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923237744 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.3923237744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/27.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.1532367492 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 3318537315 ps |
| CPU time | 4.39 seconds |
| Started | Sep 04 02:26:16 AM UTC 24 |
| Finished | Sep 04 02:26:22 AM UTC 24 |
| Peak memory | 216072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532367492 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.1532367492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/27.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/28.rv_dm_alert_test.3038453576 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 72321071 ps |
| CPU time | 1.24 seconds |
| Started | Sep 04 02:26:17 AM UTC 24 |
| Finished | Sep 04 02:26:19 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038453576 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.3038453576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/28.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/28.rv_dm_stress_all.1371824540 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 4063232675 ps |
| CPU time | 5.78 seconds |
| Started | Sep 04 02:26:17 AM UTC 24 |
| Finished | Sep 04 02:26:23 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371824540 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.1371824540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/28.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/29.rv_dm_alert_test.1910422217 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 123516891 ps |
| CPU time | 0.84 seconds |
| Started | Sep 04 02:26:17 AM UTC 24 |
| Finished | Sep 04 02:26:18 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910422217 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.1910422217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/29.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/29.rv_dm_stress_all.2642263111 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 3686277068 ps |
| CPU time | 14.03 seconds |
| Started | Sep 04 02:26:17 AM UTC 24 |
| Finished | Sep 04 02:26:32 AM UTC 24 |
| Peak memory | 226380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642263111 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.2642263111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/29.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.3489530241 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 86926327 ps |
| CPU time | 1.02 seconds |
| Started | Sep 04 02:25:42 AM UTC 24 |
| Finished | Sep 04 02:25:45 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489530241 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.3489530241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/3.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.3001341198 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 2458830803 ps |
| CPU time | 3.78 seconds |
| Started | Sep 04 02:25:42 AM UTC 24 |
| Finished | Sep 04 02:25:47 AM UTC 24 |
| Peak memory | 226532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001341198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.3001341198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/3.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.620212979 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 2627654723 ps |
| CPU time | 2.9 seconds |
| Started | Sep 04 02:25:41 AM UTC 24 |
| Finished | Sep 04 02:25:45 AM UTC 24 |
| Peak memory | 226572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620212979 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.620212979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/3.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.3355601509 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 3626433593 ps |
| CPU time | 4.79 seconds |
| Started | Sep 04 02:25:41 AM UTC 24 |
| Finished | Sep 04 02:25:47 AM UTC 24 |
| Peak memory | 216184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355601509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_tl_access.3355601509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/3.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.2008759741 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 589487090 ps |
| CPU time | 1.53 seconds |
| Started | Sep 04 02:25:42 AM UTC 24 |
| Finished | Sep 04 02:25:45 AM UTC 24 |
| Peak memory | 213452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008759741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_halt_resume_whereto.2008759741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/3.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/3.rv_dm_hart_unavail.3346704107 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 215135962 ps |
| CPU time | 1.28 seconds |
| Started | Sep 04 02:25:42 AM UTC 24 |
| Finished | Sep 04 02:25:44 AM UTC 24 |
| Peak memory | 213420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346704107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.3346704107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/3.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.760806282 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 1582084405 ps |
| CPU time | 2.84 seconds |
| Started | Sep 04 02:25:41 AM UTC 24 |
| Finished | Sep 04 02:25:45 AM UTC 24 |
| Peak memory | 216196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760806282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.760806282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/3.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/3.rv_dm_sec_cm.2948887534 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 1128741032 ps |
| CPU time | 1.83 seconds |
| Started | Sep 04 02:25:42 AM UTC 24 |
| Finished | Sep 04 02:25:45 AM UTC 24 |
| Peak memory | 253560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948887534 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.2948887534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/3.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.522917586 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1443222518 ps |
| CPU time | 2.52 seconds |
| Started | Sep 04 02:25:42 AM UTC 24 |
| Finished | Sep 04 02:25:46 AM UTC 24 |
| Peak memory | 226268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522917586 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.522917586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/3.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.864654713 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 6184011069 ps |
| CPU time | 72.45 seconds |
| Started | Sep 04 02:25:42 AM UTC 24 |
| Finished | Sep 04 02:26:57 AM UTC 24 |
| Peak memory | 230536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=864654713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress _all_with_rand_reset.864654713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/30.rv_dm_alert_test.2303805893 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 79639774 ps |
| CPU time | 1.23 seconds |
| Started | Sep 04 02:26:18 AM UTC 24 |
| Finished | Sep 04 02:26:20 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303805893 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.2303805893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/30.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.1493199856 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4745372834 ps |
| CPU time | 4.65 seconds |
| Started | Sep 04 02:26:18 AM UTC 24 |
| Finished | Sep 04 02:26:23 AM UTC 24 |
| Peak memory | 226368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493199856 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.1493199856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/30.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/31.rv_dm_alert_test.3528023875 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 76014755 ps |
| CPU time | 1.35 seconds |
| Started | Sep 04 02:26:19 AM UTC 24 |
| Finished | Sep 04 02:26:21 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528023875 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.3528023875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/31.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/31.rv_dm_stress_all.813034732 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 4545419157 ps |
| CPU time | 4.03 seconds |
| Started | Sep 04 02:26:19 AM UTC 24 |
| Finished | Sep 04 02:26:24 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813034732 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.813034732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/31.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/32.rv_dm_alert_test.3030770289 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 45008476 ps |
| CPU time | 1.17 seconds |
| Started | Sep 04 02:26:19 AM UTC 24 |
| Finished | Sep 04 02:26:21 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030770289 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.3030770289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/32.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/32.rv_dm_stress_all.1763587061 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 5620262646 ps |
| CPU time | 2.8 seconds |
| Started | Sep 04 02:26:19 AM UTC 24 |
| Finished | Sep 04 02:26:23 AM UTC 24 |
| Peak memory | 216072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763587061 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.1763587061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/32.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/33.rv_dm_alert_test.165349524 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 94468207 ps |
| CPU time | 0.98 seconds |
| Started | Sep 04 02:26:20 AM UTC 24 |
| Finished | Sep 04 02:26:22 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165349524 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.165349524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/33.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.3515737659 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 4088355419 ps |
| CPU time | 3.87 seconds |
| Started | Sep 04 02:26:20 AM UTC 24 |
| Finished | Sep 04 02:26:25 AM UTC 24 |
| Peak memory | 216148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515737659 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.3515737659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/33.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/34.rv_dm_alert_test.840895221 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 62021196 ps |
| CPU time | 0.87 seconds |
| Started | Sep 04 02:26:20 AM UTC 24 |
| Finished | Sep 04 02:26:22 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840895221 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.840895221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/34.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/34.rv_dm_stress_all.3742576862 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 2616987468 ps |
| CPU time | 8.25 seconds |
| Started | Sep 04 02:26:20 AM UTC 24 |
| Finished | Sep 04 02:26:30 AM UTC 24 |
| Peak memory | 226308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742576862 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.3742576862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/34.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/35.rv_dm_alert_test.3663376290 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 66826244 ps |
| CPU time | 0.99 seconds |
| Started | Sep 04 02:26:20 AM UTC 24 |
| Finished | Sep 04 02:26:22 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663376290 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.3663376290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/35.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/35.rv_dm_stress_all.1724711590 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 6808463877 ps |
| CPU time | 12.19 seconds |
| Started | Sep 04 02:26:20 AM UTC 24 |
| Finished | Sep 04 02:26:34 AM UTC 24 |
| Peak memory | 216136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724711590 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.1724711590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/35.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/36.rv_dm_alert_test.2155203246 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 93439887 ps |
| CPU time | 1 seconds |
| Started | Sep 04 02:26:22 AM UTC 24 |
| Finished | Sep 04 02:26:24 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155203246 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.2155203246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/36.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/36.rv_dm_stress_all.4010148848 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 1404208631 ps |
| CPU time | 2.99 seconds |
| Started | Sep 04 02:26:22 AM UTC 24 |
| Finished | Sep 04 02:26:26 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010148848 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.4010148848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/36.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/37.rv_dm_alert_test.245272853 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 68465707 ps |
| CPU time | 1.05 seconds |
| Started | Sep 04 02:26:22 AM UTC 24 |
| Finished | Sep 04 02:26:24 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245272853 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.245272853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/37.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/37.rv_dm_stress_all.3723572706 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 3990651641 ps |
| CPU time | 7 seconds |
| Started | Sep 04 02:26:22 AM UTC 24 |
| Finished | Sep 04 02:26:30 AM UTC 24 |
| Peak memory | 216272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723572706 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.3723572706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/37.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/38.rv_dm_alert_test.3915419870 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 82543004 ps |
| CPU time | 0.95 seconds |
| Started | Sep 04 02:26:22 AM UTC 24 |
| Finished | Sep 04 02:26:24 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915419870 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.3915419870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/38.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/38.rv_dm_stress_all.2705561389 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 2035953054 ps |
| CPU time | 6.36 seconds |
| Started | Sep 04 02:26:22 AM UTC 24 |
| Finished | Sep 04 02:26:29 AM UTC 24 |
| Peak memory | 226184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705561389 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.2705561389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/38.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/39.rv_dm_alert_test.231639898 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 65732475 ps |
| CPU time | 0.89 seconds |
| Started | Sep 04 02:26:22 AM UTC 24 |
| Finished | Sep 04 02:26:24 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231639898 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.231639898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/39.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/39.rv_dm_stress_all.501106437 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 4704037627 ps |
| CPU time | 4.93 seconds |
| Started | Sep 04 02:26:22 AM UTC 24 |
| Finished | Sep 04 02:26:28 AM UTC 24 |
| Peak memory | 216128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501106437 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.501106437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/39.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/4.rv_dm_alert_test.3836760332 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 70318127 ps |
| CPU time | 0.83 seconds |
| Started | Sep 04 02:25:44 AM UTC 24 |
| Finished | Sep 04 02:25:46 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836760332 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.3836760332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/4.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/4.rv_dm_autoincr_sba_tl_access.1349552611 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 3052387976 ps |
| CPU time | 10.3 seconds |
| Started | Sep 04 02:25:44 AM UTC 24 |
| Finished | Sep 04 02:25:55 AM UTC 24 |
| Peak memory | 216264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349552611 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.1349552611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/4.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/4.rv_dm_bad_sba_tl_access.2610223157 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 1659216936 ps |
| CPU time | 3.12 seconds |
| Started | Sep 04 02:25:42 AM UTC 24 |
| Finished | Sep 04 02:25:47 AM UTC 24 |
| Peak memory | 226444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610223157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.2610223157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/4.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/4.rv_dm_buffered_enable.3305862697 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 229190732 ps |
| CPU time | 1.17 seconds |
| Started | Sep 04 02:25:44 AM UTC 24 |
| Finished | Sep 04 02:25:46 AM UTC 24 |
| Peak memory | 252412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305862697 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_buffered_enable.3305862697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/4.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3673240168 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 2232796488 ps |
| CPU time | 7.85 seconds |
| Started | Sep 04 02:25:42 AM UTC 24 |
| Finished | Sep 04 02:25:51 AM UTC 24 |
| Peak memory | 216320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673240168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_tl_access.3673240168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/4.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.1123921572 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 316753084 ps |
| CPU time | 1.03 seconds |
| Started | Sep 04 02:25:44 AM UTC 24 |
| Finished | Sep 04 02:25:46 AM UTC 24 |
| Peak memory | 213452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123921572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_halt_resume_whereto.1123921572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/4.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.1501958257 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 52513092 ps |
| CPU time | 0.91 seconds |
| Started | Sep 04 02:25:44 AM UTC 24 |
| Finished | Sep 04 02:25:45 AM UTC 24 |
| Peak memory | 213452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501958257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.1501958257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/4.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/4.rv_dm_sba_tl_access.4225168342 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 2882973183 ps |
| CPU time | 9.72 seconds |
| Started | Sep 04 02:25:42 AM UTC 24 |
| Finished | Sep 04 02:25:53 AM UTC 24 |
| Peak memory | 216276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225168342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.4225168342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/4.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/4.rv_dm_sec_cm.2598766374 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 691659047 ps |
| CPU time | 2.2 seconds |
| Started | Sep 04 02:25:44 AM UTC 24 |
| Finished | Sep 04 02:25:47 AM UTC 24 |
| Peak memory | 254840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598766374 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.2598766374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/4.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/40.rv_dm_alert_test.1614301113 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 130616212 ps |
| CPU time | 0.9 seconds |
| Started | Sep 04 02:26:22 AM UTC 24 |
| Finished | Sep 04 02:26:24 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614301113 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.1614301113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/40.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/40.rv_dm_stress_all.4081959232 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 2367570804 ps |
| CPU time | 5.98 seconds |
| Started | Sep 04 02:26:22 AM UTC 24 |
| Finished | Sep 04 02:26:29 AM UTC 24 |
| Peak memory | 216072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081959232 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.4081959232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/40.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/41.rv_dm_alert_test.3910374332 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 149694613 ps |
| CPU time | 1.2 seconds |
| Started | Sep 04 02:26:23 AM UTC 24 |
| Finished | Sep 04 02:26:25 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910374332 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.3910374332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/41.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/41.rv_dm_stress_all.3023358748 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 2200487851 ps |
| CPU time | 7 seconds |
| Started | Sep 04 02:26:23 AM UTC 24 |
| Finished | Sep 04 02:26:31 AM UTC 24 |
| Peak memory | 216180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023358748 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.3023358748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/41.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/42.rv_dm_alert_test.2262330730 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 58107966 ps |
| CPU time | 1.12 seconds |
| Started | Sep 04 02:26:23 AM UTC 24 |
| Finished | Sep 04 02:26:25 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262330730 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.2262330730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/42.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/42.rv_dm_stress_all.3856828821 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 3503211084 ps |
| CPU time | 3.02 seconds |
| Started | Sep 04 02:26:23 AM UTC 24 |
| Finished | Sep 04 02:26:27 AM UTC 24 |
| Peak memory | 226300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856828821 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.3856828821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/42.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/43.rv_dm_alert_test.4044000577 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 149365097 ps |
| CPU time | 1.09 seconds |
| Started | Sep 04 02:26:23 AM UTC 24 |
| Finished | Sep 04 02:26:25 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044000577 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.4044000577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/43.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/43.rv_dm_stress_all.1251295757 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 4537578900 ps |
| CPU time | 5.85 seconds |
| Started | Sep 04 02:26:23 AM UTC 24 |
| Finished | Sep 04 02:26:30 AM UTC 24 |
| Peak memory | 226312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251295757 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.1251295757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/43.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/44.rv_dm_alert_test.376627640 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 127468608 ps |
| CPU time | 1.3 seconds |
| Started | Sep 04 02:26:23 AM UTC 24 |
| Finished | Sep 04 02:26:26 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376627640 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.376627640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/44.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.3346620680 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 2369017493 ps |
| CPU time | 8.32 seconds |
| Started | Sep 04 02:26:23 AM UTC 24 |
| Finished | Sep 04 02:26:33 AM UTC 24 |
| Peak memory | 226240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346620680 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.3346620680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/44.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/45.rv_dm_alert_test.3695439988 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 151929775 ps |
| CPU time | 1.35 seconds |
| Started | Sep 04 02:26:25 AM UTC 24 |
| Finished | Sep 04 02:26:27 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695439988 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.3695439988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/45.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/45.rv_dm_stress_all.1777826358 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 708872420 ps |
| CPU time | 2.19 seconds |
| Started | Sep 04 02:26:25 AM UTC 24 |
| Finished | Sep 04 02:26:28 AM UTC 24 |
| Peak memory | 226108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777826358 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.1777826358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/45.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/46.rv_dm_alert_test.2639399229 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 70335120 ps |
| CPU time | 1.04 seconds |
| Started | Sep 04 02:26:25 AM UTC 24 |
| Finished | Sep 04 02:26:27 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639399229 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.2639399229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/46.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.2220288935 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 6087088869 ps |
| CPU time | 13.19 seconds |
| Started | Sep 04 02:26:25 AM UTC 24 |
| Finished | Sep 04 02:26:39 AM UTC 24 |
| Peak memory | 216208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220288935 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.2220288935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/46.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/47.rv_dm_alert_test.3337052032 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 157282967 ps |
| CPU time | 0.96 seconds |
| Started | Sep 04 02:26:25 AM UTC 24 |
| Finished | Sep 04 02:26:27 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337052032 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.3337052032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/47.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/47.rv_dm_stress_all.3014175682 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 1522999944 ps |
| CPU time | 3.37 seconds |
| Started | Sep 04 02:26:25 AM UTC 24 |
| Finished | Sep 04 02:26:29 AM UTC 24 |
| Peak memory | 216020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014175682 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.3014175682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/47.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/48.rv_dm_alert_test.2624472945 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 152445284 ps |
| CPU time | 1.7 seconds |
| Started | Sep 04 02:26:25 AM UTC 24 |
| Finished | Sep 04 02:26:28 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624472945 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.2624472945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/48.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/48.rv_dm_stress_all.3058003257 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 4379840792 ps |
| CPU time | 5.29 seconds |
| Started | Sep 04 02:26:25 AM UTC 24 |
| Finished | Sep 04 02:26:31 AM UTC 24 |
| Peak memory | 226320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058003257 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.3058003257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/48.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/49.rv_dm_alert_test.2534082738 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 41975925 ps |
| CPU time | 1.05 seconds |
| Started | Sep 04 02:26:25 AM UTC 24 |
| Finished | Sep 04 02:26:27 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534082738 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.2534082738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/49.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/49.rv_dm_stress_all.3489698538 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 1737102832 ps |
| CPU time | 3.59 seconds |
| Started | Sep 04 02:26:25 AM UTC 24 |
| Finished | Sep 04 02:26:30 AM UTC 24 |
| Peak memory | 226316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489698538 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.3489698538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/49.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/5.rv_dm_alert_test.1020732917 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 54159653 ps |
| CPU time | 0.98 seconds |
| Started | Sep 04 02:25:45 AM UTC 24 |
| Finished | Sep 04 02:25:47 AM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020732917 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.1020732917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/5.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.4070628889 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 32188256297 ps |
| CPU time | 81.01 seconds |
| Started | Sep 04 02:25:45 AM UTC 24 |
| Finished | Sep 04 02:27:08 AM UTC 24 |
| Peak memory | 216252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070628889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.4070628889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/5.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.1331544741 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 6091336192 ps |
| CPU time | 7.92 seconds |
| Started | Sep 04 02:25:45 AM UTC 24 |
| Finished | Sep 04 02:25:54 AM UTC 24 |
| Peak memory | 216316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331544741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.1331544741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/5.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.3812987923 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 3301453695 ps |
| CPU time | 4.48 seconds |
| Started | Sep 04 02:25:45 AM UTC 24 |
| Finished | Sep 04 02:25:51 AM UTC 24 |
| Peak memory | 216180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812987923 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl_access.3812987923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/5.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/5.rv_dm_halt_resume_whereto.3465225518 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 251411980 ps |
| CPU time | 1.12 seconds |
| Started | Sep 04 02:25:45 AM UTC 24 |
| Finished | Sep 04 02:25:47 AM UTC 24 |
| Peak memory | 213452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465225518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_halt_resume_whereto.3465225518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/5.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/5.rv_dm_sba_tl_access.3977262927 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 4954069771 ps |
| CPU time | 4.76 seconds |
| Started | Sep 04 02:25:44 AM UTC 24 |
| Finished | Sep 04 02:25:50 AM UTC 24 |
| Peak memory | 226508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977262927 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.3977262927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/5.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.3529240951 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 2903592340 ps |
| CPU time | 7.18 seconds |
| Started | Sep 04 02:25:45 AM UTC 24 |
| Finished | Sep 04 02:25:53 AM UTC 24 |
| Peak memory | 226248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529240951 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.3529240951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/5.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.1562051541 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 12575457194 ps |
| CPU time | 51.68 seconds |
| Started | Sep 04 02:25:45 AM UTC 24 |
| Finished | Sep 04 02:26:38 AM UTC 24 |
| Peak memory | 233328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1562051541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stres s_all_with_rand_reset.1562051541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/6.rv_dm_alert_test.1351416989 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 69189907 ps |
| CPU time | 0.75 seconds |
| Started | Sep 04 02:25:47 AM UTC 24 |
| Finished | Sep 04 02:25:49 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351416989 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.1351416989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/6.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/6.rv_dm_autoincr_sba_tl_access.3119453711 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 32530565857 ps |
| CPU time | 77.04 seconds |
| Started | Sep 04 02:25:47 AM UTC 24 |
| Finished | Sep 04 02:27:06 AM UTC 24 |
| Peak memory | 230664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119453711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.3119453711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/6.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/6.rv_dm_bad_sba_tl_access.2901664301 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 11488567625 ps |
| CPU time | 22.97 seconds |
| Started | Sep 04 02:25:47 AM UTC 24 |
| Finished | Sep 04 02:26:11 AM UTC 24 |
| Peak memory | 233444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901664301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.2901664301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/6.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/6.rv_dm_buffered_enable.4055692088 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 576725707 ps |
| CPU time | 2.71 seconds |
| Started | Sep 04 02:25:47 AM UTC 24 |
| Finished | Sep 04 02:25:51 AM UTC 24 |
| Peak memory | 252680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055692088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_buffered_enable.4055692088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/6.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.1277469369 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 1387031275 ps |
| CPU time | 2.09 seconds |
| Started | Sep 04 02:25:47 AM UTC 24 |
| Finished | Sep 04 02:25:50 AM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277469369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_tl_access.1277469369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/6.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/6.rv_dm_halt_resume_whereto.1598205659 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1054657122 ps |
| CPU time | 2.27 seconds |
| Started | Sep 04 02:25:47 AM UTC 24 |
| Finished | Sep 04 02:25:50 AM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598205659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_halt_resume_whereto.1598205659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/6.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/6.rv_dm_sba_tl_access.25840474 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 14050632907 ps |
| CPU time | 16.76 seconds |
| Started | Sep 04 02:25:45 AM UTC 24 |
| Finished | Sep 04 02:26:03 AM UTC 24 |
| Peak memory | 226564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25840474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv _dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.25840474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/6.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all.2981721766 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 2230951156 ps |
| CPU time | 4.15 seconds |
| Started | Sep 04 02:25:47 AM UTC 24 |
| Finished | Sep 04 02:25:52 AM UTC 24 |
| Peak memory | 216132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981721766 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.2981721766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/6.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/7.rv_dm_alert_test.453654016 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 64629243 ps |
| CPU time | 1.42 seconds |
| Started | Sep 04 02:25:48 AM UTC 24 |
| Finished | Sep 04 02:25:51 AM UTC 24 |
| Peak memory | 215996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453654016 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.453654016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/7.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.2253060229 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 29990906450 ps |
| CPU time | 39.12 seconds |
| Started | Sep 04 02:25:47 AM UTC 24 |
| Finished | Sep 04 02:26:28 AM UTC 24 |
| Peak memory | 226636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253060229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.2253060229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/7.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.1064214121 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 2058211774 ps |
| CPU time | 6.35 seconds |
| Started | Sep 04 02:25:47 AM UTC 24 |
| Finished | Sep 04 02:25:55 AM UTC 24 |
| Peak memory | 226448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064214121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.1064214121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/7.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/7.rv_dm_buffered_enable.4243846709 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 86812842 ps |
| CPU time | 1.38 seconds |
| Started | Sep 04 02:25:48 AM UTC 24 |
| Finished | Sep 04 02:25:51 AM UTC 24 |
| Peak memory | 251692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243846709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_buffered_enable.4243846709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/7.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.2625830134 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 3025504463 ps |
| CPU time | 3.9 seconds |
| Started | Sep 04 02:25:47 AM UTC 24 |
| Finished | Sep 04 02:25:52 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625830134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_tl_access.2625830134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/7.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.4054064117 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1159732918 ps |
| CPU time | 1.79 seconds |
| Started | Sep 04 02:25:48 AM UTC 24 |
| Finished | Sep 04 02:25:51 AM UTC 24 |
| Peak memory | 213452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054064117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_halt_resume_whereto.4054064117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/7.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/7.rv_dm_sba_tl_access.2700349889 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 3177502916 ps |
| CPU time | 4.17 seconds |
| Started | Sep 04 02:25:47 AM UTC 24 |
| Finished | Sep 04 02:25:52 AM UTC 24 |
| Peak memory | 216324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700349889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.2700349889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/7.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all.2948267408 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 4335892337 ps |
| CPU time | 9.7 seconds |
| Started | Sep 04 02:25:48 AM UTC 24 |
| Finished | Sep 04 02:25:59 AM UTC 24 |
| Peak memory | 216004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948267408 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.2948267408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/7.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/8.rv_dm_alert_test.3345566566 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 137657064 ps |
| CPU time | 1.06 seconds |
| Started | Sep 04 02:25:50 AM UTC 24 |
| Finished | Sep 04 02:25:52 AM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345566566 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.3345566566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/8.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/8.rv_dm_bad_sba_tl_access.3899435589 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 1284735615 ps |
| CPU time | 1.88 seconds |
| Started | Sep 04 02:25:48 AM UTC 24 |
| Finished | Sep 04 02:25:51 AM UTC 24 |
| Peak memory | 215496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899435589 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.3899435589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/8.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/8.rv_dm_buffered_enable.3319014287 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 265553863 ps |
| CPU time | 1.76 seconds |
| Started | Sep 04 02:25:49 AM UTC 24 |
| Finished | Sep 04 02:25:51 AM UTC 24 |
| Peak memory | 258160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319014287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_buffered_enable.3319014287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/8.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.2386236116 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 8829057589 ps |
| CPU time | 30.28 seconds |
| Started | Sep 04 02:25:48 AM UTC 24 |
| Finished | Sep 04 02:26:20 AM UTC 24 |
| Peak memory | 216240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386236116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl_access.2386236116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/8.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/8.rv_dm_sba_tl_access.1813682096 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 5814106588 ps |
| CPU time | 12.97 seconds |
| Started | Sep 04 02:25:48 AM UTC 24 |
| Finished | Sep 04 02:26:03 AM UTC 24 |
| Peak memory | 216268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813682096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.1813682096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/8.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.3904966911 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 6473664103 ps |
| CPU time | 6.99 seconds |
| Started | Sep 04 02:25:50 AM UTC 24 |
| Finished | Sep 04 02:25:58 AM UTC 24 |
| Peak memory | 216068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904966911 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.3904966911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/8.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.653055717 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 38609451 ps |
| CPU time | 1.07 seconds |
| Started | Sep 04 02:25:52 AM UTC 24 |
| Finished | Sep 04 02:25:55 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653055717 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.653055717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/9.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/9.rv_dm_autoincr_sba_tl_access.2898806886 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 28812028169 ps |
| CPU time | 38.61 seconds |
| Started | Sep 04 02:25:51 AM UTC 24 |
| Finished | Sep 04 02:26:31 AM UTC 24 |
| Peak memory | 226560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898806886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.2898806886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/9.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/9.rv_dm_buffered_enable.649165073 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 683372453 ps |
| CPU time | 1.43 seconds |
| Started | Sep 04 02:25:52 AM UTC 24 |
| Finished | Sep 04 02:25:55 AM UTC 24 |
| Peak memory | 244528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649165073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_buffered_enable.649165073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/9.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.1900349425 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 7092452897 ps |
| CPU time | 29.2 seconds |
| Started | Sep 04 02:25:51 AM UTC 24 |
| Finished | Sep 04 02:26:22 AM UTC 24 |
| Peak memory | 226480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900349425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_tl_access.1900349425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/9.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.563115083 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 5530911713 ps |
| CPU time | 13.16 seconds |
| Started | Sep 04 02:25:51 AM UTC 24 |
| Finished | Sep 04 02:26:05 AM UTC 24 |
| Peak memory | 216272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563115083 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.563115083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/9.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.1781598029 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 2813939392 ps |
| CPU time | 5.04 seconds |
| Started | Sep 04 02:25:52 AM UTC 24 |
| Finished | Sep 04 02:25:58 AM UTC 24 |
| Peak memory | 216184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781598029 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.1781598029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/9.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.3166942002 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 6109373983 ps |
| CPU time | 75.69 seconds |
| Started | Sep 04 02:25:52 AM UTC 24 |
| Finished | Sep 04 02:27:10 AM UTC 24 |
| Peak memory | 230588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3166942002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stres s_all_with_rand_reset.3166942002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest |
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