Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.98 96.27 89.82 92.10 94.67 90.10 98.74 61.18


Total tests in report: 482
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
53.92 53.92 83.22 83.22 51.91 51.91 44.92 44.92 38.67 38.67 62.29 62.29 92.74 92.74 3.70 3.70 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_dataaddr_rw_access.3045264652
63.64 9.72 84.43 1.21 58.84 6.93 47.52 2.61 45.33 6.67 66.38 4.10 94.01 1.26 48.97 45.27 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.2140272994
72.06 8.42 87.91 3.48 65.21 6.36 72.31 24.79 58.67 13.33 73.55 7.17 95.90 1.89 50.89 1.92 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.1676644251
78.16 6.09 91.13 3.22 74.40 9.19 83.95 11.64 69.33 10.67 80.20 6.66 96.21 0.32 51.85 0.96 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.3017130685
80.57 2.41 92.44 1.31 77.23 2.83 85.84 1.89 77.33 8.00 82.94 2.73 96.21 0.00 51.99 0.14 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_busy.3622922411
81.51 0.94 92.85 0.40 77.79 0.57 87.14 1.30 81.33 4.00 83.11 0.17 96.21 0.00 52.13 0.14 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.2305336110
82.37 0.87 93.10 0.25 78.36 0.57 87.56 0.42 85.33 4.00 83.79 0.68 96.21 0.00 52.26 0.14 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.471356190
83.21 0.83 93.20 0.10 79.92 1.56 87.65 0.08 85.33 0.00 84.30 0.51 96.21 0.00 55.83 3.57 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1251307533
83.83 0.62 93.90 0.71 81.19 1.27 87.69 0.04 86.67 1.33 85.15 0.85 96.21 0.00 55.97 0.14 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.3491880276
84.29 0.46 94.41 0.50 82.18 0.99 87.82 0.13 86.67 0.00 86.35 1.19 96.21 0.00 56.38 0.41 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.2041569154
84.74 0.45 94.96 0.55 82.74 0.57 87.82 0.00 88.00 1.33 87.03 0.68 96.21 0.00 56.38 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.905470136
85.18 0.45 95.01 0.05 83.73 0.99 87.98 0.17 89.33 1.33 87.20 0.17 96.21 0.00 56.79 0.41 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.2493458201
85.60 0.41 95.47 0.45 84.58 0.85 88.66 0.67 89.33 0.00 87.71 0.51 96.21 0.00 57.20 0.41 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.4202317164
85.92 0.33 95.62 0.15 84.87 0.28 88.82 0.17 90.67 1.33 88.05 0.34 96.21 0.00 57.20 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.2683195943
86.24 0.32 95.62 0.00 87.13 2.26 88.82 0.00 90.67 0.00 88.05 0.00 96.21 0.00 57.20 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.251291963
86.53 0.29 95.62 0.00 87.13 0.00 90.84 2.02 90.67 0.00 88.05 0.00 96.21 0.00 57.20 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.1323014293
86.74 0.21 95.62 0.00 87.13 0.00 90.84 0.00 90.67 0.00 88.05 0.00 97.69 1.47 57.20 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.420146013
86.95 0.21 95.62 0.00 87.13 0.00 90.84 0.00 92.00 1.33 88.05 0.00 97.69 0.00 57.34 0.14 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.2321075721
87.16 0.21 95.62 0.00 87.69 0.57 91.34 0.50 92.00 0.00 88.05 0.00 97.79 0.11 57.61 0.27 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.2708705727
87.35 0.19 96.02 0.40 87.84 0.14 91.34 0.00 92.00 0.00 88.74 0.68 97.79 0.00 57.75 0.14 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.1637925272
87.54 0.19 96.02 0.00 87.84 0.00 91.34 0.00 93.33 1.33 88.74 0.00 97.79 0.00 57.75 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.867571208
87.74 0.19 96.02 0.00 87.84 0.00 91.34 0.00 94.67 1.33 88.74 0.00 97.79 0.00 57.75 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2694845905
87.89 0.15 96.07 0.05 88.26 0.42 91.34 0.00 94.67 0.00 88.91 0.17 97.79 0.00 58.16 0.41 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/13.rv_dm_stress_all.3104637193
88.02 0.13 96.12 0.05 88.40 0.14 91.72 0.38 94.67 0.00 89.25 0.34 97.79 0.00 58.16 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.2964524097
88.13 0.11 96.17 0.05 88.54 0.14 91.89 0.17 94.67 0.00 89.42 0.17 97.79 0.00 58.44 0.27 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.957414563
88.22 0.09 96.17 0.00 88.68 0.14 91.89 0.00 94.67 0.00 89.76 0.34 97.79 0.00 58.57 0.14 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.3038498633
88.30 0.08 96.17 0.00 88.83 0.14 92.06 0.17 94.67 0.00 89.76 0.00 97.79 0.00 58.85 0.27 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.636026897
88.38 0.08 96.17 0.00 88.83 0.00 92.06 0.00 94.67 0.00 89.76 0.00 97.79 0.00 59.40 0.55 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1822145114
88.46 0.08 96.17 0.00 88.83 0.00 92.06 0.00 94.67 0.00 89.76 0.00 97.79 0.00 59.95 0.55 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2652056287
88.51 0.05 96.17 0.00 88.83 0.00 92.06 0.00 94.67 0.00 89.76 0.00 97.90 0.11 60.22 0.27 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.3129627404
88.57 0.05 96.22 0.05 88.83 0.00 92.06 0.00 94.67 0.00 89.93 0.17 97.90 0.00 60.36 0.14 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.2765547967
88.62 0.05 96.22 0.00 88.97 0.14 92.06 0.00 94.67 0.00 89.93 0.00 98.11 0.21 60.36 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/5.rv_dm_buffered_enable.1823595563
88.66 0.04 96.22 0.00 89.25 0.28 92.06 0.00 94.67 0.00 89.93 0.00 98.11 0.00 60.36 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_halt_resume_whereto.2480666059
88.70 0.04 96.22 0.00 89.53 0.28 92.06 0.00 94.67 0.00 89.93 0.00 98.11 0.00 60.36 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/17.rv_dm_stress_all.1337215820
88.74 0.04 96.22 0.00 89.53 0.00 92.06 0.00 94.67 0.00 89.93 0.00 98.11 0.00 60.63 0.27 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/17.rv_dm_bad_sba_tl_access.716207047
88.77 0.03 96.27 0.05 89.53 0.00 92.06 0.00 94.67 0.00 90.10 0.17 98.11 0.00 60.63 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2624379255
88.80 0.03 96.27 0.00 89.53 0.00 92.06 0.00 94.67 0.00 90.10 0.00 98.32 0.21 60.63 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.77505533
88.83 0.03 96.27 0.00 89.53 0.00 92.06 0.00 94.67 0.00 90.10 0.00 98.53 0.21 60.63 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_rw.807741095
88.85 0.02 96.27 0.00 89.67 0.14 92.06 0.00 94.67 0.00 90.10 0.00 98.53 0.00 60.63 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.3660142900
88.87 0.02 96.27 0.00 89.82 0.14 92.06 0.00 94.67 0.00 90.10 0.00 98.53 0.00 60.63 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.3121394017
88.89 0.02 96.27 0.00 89.82 0.00 92.06 0.00 94.67 0.00 90.10 0.00 98.53 0.00 60.77 0.14 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1877843811
88.91 0.02 96.27 0.00 89.82 0.00 92.06 0.00 94.67 0.00 90.10 0.00 98.53 0.00 60.91 0.14 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.3808091124
88.93 0.02 96.27 0.00 89.82 0.00 92.06 0.00 94.67 0.00 90.10 0.00 98.53 0.00 61.04 0.14 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/14.rv_dm_bad_sba_tl_access.3306357567
88.95 0.02 96.27 0.00 89.82 0.00 92.06 0.00 94.67 0.00 90.10 0.00 98.53 0.00 61.18 0.14 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.4290410770
88.96 0.02 96.27 0.00 89.82 0.00 92.06 0.00 94.67 0.00 90.10 0.00 98.63 0.11 61.18 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3272759765
88.98 0.02 96.27 0.00 89.82 0.00 92.06 0.00 94.67 0.00 90.10 0.00 98.74 0.11 61.18 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.4245480204
88.98 0.01 96.27 0.00 89.82 0.00 92.10 0.04 94.67 0.00 90.10 0.00 98.74 0.00 61.18 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2173240546

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.4041076802
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1479858407
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.784407528
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.2719582987
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.440185646
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.347113009
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1543985181
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.982976267
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2627249657
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3720156338
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2700930879
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3323701446
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.1735823459
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1591104133
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.4160857895
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.4259092510
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1238881303
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.357206210
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.408391960
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2704766561
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.1480610917
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1958951082
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.4159650546
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1741861832
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.91240848
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3408772299
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1625722714
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1681192040
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2845682658
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3056394415
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.3901621255
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.588221558
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.298767787
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.4154866429
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2294588244
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.1774668377
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3655976998
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.231032400
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3589500973
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.817562585
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.4046907438
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1350595470
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1847515562
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_rw.1416652221
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.4139920232
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2068889604
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3770014008
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2839820230
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_errors.397969282
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3785809189
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/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.1331544741
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/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.653055717
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/9.rv_dm_autoincr_sba_tl_access.2898806886
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/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.1900349425
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.563115083
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.1781598029
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.3166942002



Total test records in report: 482
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_smoke.2903360391 Sep 04 02:25:28 AM UTC 24 Sep 04 02:25:33 AM UTC 24 502353147 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.2260118555 Sep 04 02:25:29 AM UTC 24 Sep 04 02:25:33 AM UTC 24 1279794468 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.3347609031 Sep 04 02:25:31 AM UTC 24 Sep 04 02:25:33 AM UTC 24 164080814 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_dataaddr_rw_access.3045264652 Sep 04 02:25:32 AM UTC 24 Sep 04 02:25:33 AM UTC 24 72396932 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_hart_unavail.524163034 Sep 04 02:25:31 AM UTC 24 Sep 04 02:25:34 AM UTC 24 96000716 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_halted.606809980 Sep 04 02:25:31 AM UTC 24 Sep 04 02:25:34 AM UTC 24 182715410 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_busy.3622922411 Sep 04 02:25:30 AM UTC 24 Sep 04 02:25:34 AM UTC 24 423093091 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.3660142900 Sep 04 02:25:32 AM UTC 24 Sep 04 02:25:34 AM UTC 24 874648154 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_resuming.2516480752 Sep 04 02:25:31 AM UTC 24 Sep 04 02:25:34 AM UTC 24 625424562 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.1396775498 Sep 04 02:25:31 AM UTC 24 Sep 04 02:25:35 AM UTC 24 573444446 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_idle_hint.3229506472 Sep 04 02:25:33 AM UTC 24 Sep 04 02:25:35 AM UTC 24 92357431 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.1832843720 Sep 04 02:25:33 AM UTC 24 Sep 04 02:25:35 AM UTC 24 270892912 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.3525430007 Sep 04 02:25:33 AM UTC 24 Sep 04 02:25:35 AM UTC 24 191895598 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.3405509476 Sep 04 02:25:33 AM UTC 24 Sep 04 02:25:35 AM UTC 24 239924254 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.3038498633 Sep 04 02:25:33 AM UTC 24 Sep 04 02:25:36 AM UTC 24 970310892 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2649261142 Sep 04 02:25:33 AM UTC 24 Sep 04 02:25:36 AM UTC 24 711103622 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.3674989388 Sep 04 02:25:34 AM UTC 24 Sep 04 02:25:36 AM UTC 24 156144102 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.2964524097 Sep 04 02:25:34 AM UTC 24 Sep 04 02:25:37 AM UTC 24 70251451 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.2493458201 Sep 04 02:25:34 AM UTC 24 Sep 04 02:25:37 AM UTC 24 117142645 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_debug_disabled.3866958522 Sep 04 02:25:34 AM UTC 24 Sep 04 02:25:37 AM UTC 24 43139098 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_hartsel_warl.1378453144 Sep 04 02:25:34 AM UTC 24 Sep 04 02:25:37 AM UTC 24 77528643 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_tl_access.2153808450 Sep 04 02:25:28 AM UTC 24 Sep 04 02:25:37 AM UTC 24 1999673401 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.2719503417 Sep 04 02:25:34 AM UTC 24 Sep 04 02:25:37 AM UTC 24 105897890 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.3808091124 Sep 04 02:25:34 AM UTC 24 Sep 04 02:25:37 AM UTC 24 366120290 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2847435683 Sep 04 02:25:34 AM UTC 24 Sep 04 02:25:37 AM UTC 24 319248597 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.251291963 Sep 04 02:25:35 AM UTC 24 Sep 04 02:25:38 AM UTC 24 47225929 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.1707828715 Sep 04 02:25:35 AM UTC 24 Sep 04 02:25:38 AM UTC 24 94663635 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.471356190 Sep 04 02:25:28 AM UTC 24 Sep 04 02:25:38 AM UTC 24 8308624261 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.4202317164 Sep 04 02:25:35 AM UTC 24 Sep 04 02:25:38 AM UTC 24 102885129 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.3017130685 Sep 04 02:25:35 AM UTC 24 Sep 04 02:25:39 AM UTC 24 2123052319 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_halted.3237794184 Sep 04 02:25:37 AM UTC 24 Sep 04 02:25:39 AM UTC 24 323179560 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_hart_unavail.2650298260 Sep 04 02:25:37 AM UTC 24 Sep 04 02:25:39 AM UTC 24 103572727 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_resuming.1146808014 Sep 04 02:25:37 AM UTC 24 Sep 04 02:25:39 AM UTC 24 165310745 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_busy.3941417333 Sep 04 02:25:37 AM UTC 24 Sep 04 02:25:39 AM UTC 24 288932765 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_dataaddr_rw_access.2276438425 Sep 04 02:25:37 AM UTC 24 Sep 04 02:25:39 AM UTC 24 274578727 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.2708705727 Sep 04 02:25:35 AM UTC 24 Sep 04 02:25:39 AM UTC 24 531376503 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_not_supported.2176577044 Sep 04 02:25:37 AM UTC 24 Sep 04 02:25:39 AM UTC 24 518106912 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_halt_resume_whereto.2480666059 Sep 04 02:25:37 AM UTC 24 Sep 04 02:25:39 AM UTC 24 427170057 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.1676644251 Sep 04 02:25:29 AM UTC 24 Sep 04 02:25:40 AM UTC 24 9106981901 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.522917586 Sep 04 02:25:42 AM UTC 24 Sep 04 02:25:46 AM UTC 24 1443222518 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.1637925272 Sep 04 02:25:37 AM UTC 24 Sep 04 02:25:40 AM UTC 24 403378699 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_rom_read_access.2705900610 Sep 04 02:25:38 AM UTC 24 Sep 04 02:25:40 AM UTC 24 44097887 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_progbuf_read_write_execute.797772581 Sep 04 02:25:38 AM UTC 24 Sep 04 02:25:40 AM UTC 24 560567986 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_tl_access.1942503369 Sep 04 02:25:35 AM UTC 24 Sep 04 02:25:40 AM UTC 24 2475348791 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3077125079 Sep 04 02:25:38 AM UTC 24 Sep 04 02:25:40 AM UTC 24 162119894 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_debug_disabled.2265818701 Sep 04 02:25:38 AM UTC 24 Sep 04 02:25:40 AM UTC 24 87868877 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.2321075721 Sep 04 02:25:38 AM UTC 24 Sep 04 02:25:40 AM UTC 24 125243804 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_abstractcmd_status.1734778348 Sep 04 02:25:38 AM UTC 24 Sep 04 02:25:40 AM UTC 24 290761864 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.267813428 Sep 04 02:25:38 AM UTC 24 Sep 04 02:25:41 AM UTC 24 445250213 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_idle_hint.3315303243 Sep 04 02:25:38 AM UTC 24 Sep 04 02:25:41 AM UTC 24 371366129 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_alert_test.1014461067 Sep 04 02:25:39 AM UTC 24 Sep 04 02:25:41 AM UTC 24 142314631 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.4245480204 Sep 04 02:25:39 AM UTC 24 Sep 04 02:25:41 AM UTC 24 61435833 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2173240546 Sep 04 02:25:28 AM UTC 24 Sep 04 02:25:41 AM UTC 24 6634413724 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_buffered_enable.2529976767 Sep 04 02:25:39 AM UTC 24 Sep 04 02:25:42 AM UTC 24 110789303 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_bad_sba_tl_access.2983340201 Sep 04 02:25:35 AM UTC 24 Sep 04 02:25:42 AM UTC 24 1253215738 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.2492281597 Sep 04 02:25:38 AM UTC 24 Sep 04 02:25:42 AM UTC 24 672912803 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_ndmreset_req.1307864050 Sep 04 02:25:38 AM UTC 24 Sep 04 02:25:42 AM UTC 24 773157357 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.2434064343 Sep 04 02:25:41 AM UTC 24 Sep 04 02:25:42 AM UTC 24 92088770 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.3489530241 Sep 04 02:25:42 AM UTC 24 Sep 04 02:25:45 AM UTC 24 86926327 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/2.rv_dm_sparse_lc_gate_fsm.3562789608 Sep 04 02:25:41 AM UTC 24 Sep 04 02:25:43 AM UTC 24 86984991 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.3491880276 Sep 04 02:25:41 AM UTC 24 Sep 04 02:25:43 AM UTC 24 165345099 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.3625391866 Sep 04 02:25:37 AM UTC 24 Sep 04 02:25:43 AM UTC 24 1218862730 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.472665159 Sep 04 02:25:41 AM UTC 24 Sep 04 02:25:43 AM UTC 24 326548016 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.1234473966 Sep 04 02:25:41 AM UTC 24 Sep 04 02:25:43 AM UTC 24 106166333 ps
T120 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.2506875059 Sep 04 02:25:39 AM UTC 24 Sep 04 02:25:44 AM UTC 24 1347739076 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/3.rv_dm_hart_unavail.3346704107 Sep 04 02:25:42 AM UTC 24 Sep 04 02:25:44 AM UTC 24 215135962 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.3129627404 Sep 04 02:25:42 AM UTC 24 Sep 04 02:25:45 AM UTC 24 68813543 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.3327334573 Sep 04 02:25:39 AM UTC 24 Sep 04 02:25:45 AM UTC 24 1190849401 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.2008759741 Sep 04 02:25:42 AM UTC 24 Sep 04 02:25:45 AM UTC 24 589487090 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.760806282 Sep 04 02:25:41 AM UTC 24 Sep 04 02:25:45 AM UTC 24 1582084405 ps
T117 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.620212979 Sep 04 02:25:41 AM UTC 24 Sep 04 02:25:45 AM UTC 24 2627654723 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/3.rv_dm_sec_cm.2948887534 Sep 04 02:25:42 AM UTC 24 Sep 04 02:25:45 AM UTC 24 1128741032 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.2765547967 Sep 04 02:25:42 AM UTC 24 Sep 04 02:25:45 AM UTC 24 466793071 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.1501958257 Sep 04 02:25:44 AM UTC 24 Sep 04 02:25:45 AM UTC 24 52513092 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_smoke.3930403142 Sep 04 02:25:35 AM UTC 24 Sep 04 02:25:45 AM UTC 24 2313916555 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.1123921572 Sep 04 02:25:44 AM UTC 24 Sep 04 02:25:46 AM UTC 24 316753084 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/4.rv_dm_alert_test.3836760332 Sep 04 02:25:44 AM UTC 24 Sep 04 02:25:46 AM UTC 24 70318127 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/4.rv_dm_buffered_enable.3305862697 Sep 04 02:25:44 AM UTC 24 Sep 04 02:25:46 AM UTC 24 229190732 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.1622849003 Sep 04 02:25:41 AM UTC 24 Sep 04 02:25:47 AM UTC 24 1295328670 ps
T118 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/4.rv_dm_bad_sba_tl_access.2610223157 Sep 04 02:25:42 AM UTC 24 Sep 04 02:25:47 AM UTC 24 1659216936 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_sec_cm.130801666 Sep 04 02:25:39 AM UTC 24 Sep 04 02:25:47 AM UTC 24 1681510339 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/15.rv_dm_stress_all.1350110633 Sep 04 02:26:02 AM UTC 24 Sep 04 02:26:11 AM UTC 24 2450157881 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.3355601509 Sep 04 02:25:41 AM UTC 24 Sep 04 02:25:47 AM UTC 24 3626433593 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.3001341198 Sep 04 02:25:42 AM UTC 24 Sep 04 02:25:47 AM UTC 24 2458830803 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/4.rv_dm_sec_cm.2598766374 Sep 04 02:25:44 AM UTC 24 Sep 04 02:25:47 AM UTC 24 691659047 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/5.rv_dm_alert_test.1020732917 Sep 04 02:25:45 AM UTC 24 Sep 04 02:25:47 AM UTC 24 54159653 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/5.rv_dm_halt_resume_whereto.3465225518 Sep 04 02:25:45 AM UTC 24 Sep 04 02:25:47 AM UTC 24 251411980 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/5.rv_dm_buffered_enable.1823595563 Sep 04 02:25:45 AM UTC 24 Sep 04 02:25:47 AM UTC 24 205966657 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.2041569154 Sep 04 02:25:44 AM UTC 24 Sep 04 02:25:48 AM UTC 24 1497426315 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/6.rv_dm_alert_test.1351416989 Sep 04 02:25:47 AM UTC 24 Sep 04 02:25:49 AM UTC 24 69189907 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_debug_disabled.1690190199 Sep 04 02:25:38 AM UTC 24 Sep 04 02:25:49 AM UTC 24 3529194468 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all.1684843820 Sep 04 02:25:41 AM UTC 24 Sep 04 02:25:50 AM UTC 24 2280589140 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/5.rv_dm_sba_tl_access.3977262927 Sep 04 02:25:44 AM UTC 24 Sep 04 02:25:50 AM UTC 24 4954069771 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.1277469369 Sep 04 02:25:47 AM UTC 24 Sep 04 02:25:50 AM UTC 24 1387031275 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/6.rv_dm_halt_resume_whereto.1598205659 Sep 04 02:25:47 AM UTC 24 Sep 04 02:25:50 AM UTC 24 1054657122 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.3812987923 Sep 04 02:25:45 AM UTC 24 Sep 04 02:25:51 AM UTC 24 3301453695 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/6.rv_dm_buffered_enable.4055692088 Sep 04 02:25:47 AM UTC 24 Sep 04 02:25:51 AM UTC 24 576725707 ps
T143 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/7.rv_dm_buffered_enable.4243846709 Sep 04 02:25:48 AM UTC 24 Sep 04 02:25:51 AM UTC 24 86812842 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/7.rv_dm_alert_test.453654016 Sep 04 02:25:48 AM UTC 24 Sep 04 02:25:51 AM UTC 24 64629243 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.4054064117 Sep 04 02:25:48 AM UTC 24 Sep 04 02:25:51 AM UTC 24 1159732918 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3673240168 Sep 04 02:25:42 AM UTC 24 Sep 04 02:25:51 AM UTC 24 2232796488 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/8.rv_dm_buffered_enable.3319014287 Sep 04 02:25:49 AM UTC 24 Sep 04 02:25:51 AM UTC 24 265553863 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/8.rv_dm_bad_sba_tl_access.3899435589 Sep 04 02:25:48 AM UTC 24 Sep 04 02:25:51 AM UTC 24 1284735615 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.4271873530 Sep 04 02:25:39 AM UTC 24 Sep 04 02:25:52 AM UTC 24 8189455777 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/8.rv_dm_alert_test.3345566566 Sep 04 02:25:50 AM UTC 24 Sep 04 02:25:52 AM UTC 24 137657064 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.2625830134 Sep 04 02:25:47 AM UTC 24 Sep 04 02:25:52 AM UTC 24 3025504463 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all.2981721766 Sep 04 02:25:47 AM UTC 24 Sep 04 02:25:52 AM UTC 24 2230951156 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/7.rv_dm_sba_tl_access.2700349889 Sep 04 02:25:47 AM UTC 24 Sep 04 02:25:52 AM UTC 24 3177502916 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/4.rv_dm_sba_tl_access.4225168342 Sep 04 02:25:42 AM UTC 24 Sep 04 02:25:53 AM UTC 24 2882973183 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.3529240951 Sep 04 02:25:45 AM UTC 24 Sep 04 02:25:53 AM UTC 24 2903592340 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.1331544741 Sep 04 02:25:45 AM UTC 24 Sep 04 02:25:54 AM UTC 24 6091336192 ps
T235 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.1064214121 Sep 04 02:25:47 AM UTC 24 Sep 04 02:25:55 AM UTC 24 2058211774 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.653055717 Sep 04 02:25:52 AM UTC 24 Sep 04 02:25:55 AM UTC 24 38609451 ps
T226 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.4140375647 Sep 04 02:25:35 AM UTC 24 Sep 04 02:25:55 AM UTC 24 5992421672 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/9.rv_dm_buffered_enable.649165073 Sep 04 02:25:52 AM UTC 24 Sep 04 02:25:55 AM UTC 24 683372453 ps
T119 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/4.rv_dm_autoincr_sba_tl_access.1349552611 Sep 04 02:25:44 AM UTC 24 Sep 04 02:25:55 AM UTC 24 3052387976 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/10.rv_dm_alert_test.3155945812 Sep 04 02:25:54 AM UTC 24 Sep 04 02:25:56 AM UTC 24 73051061 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/11.rv_dm_alert_test.1018334784 Sep 04 02:25:55 AM UTC 24 Sep 04 02:25:57 AM UTC 24 125482858 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/10.rv_dm_autoincr_sba_tl_access.929874243 Sep 04 02:25:52 AM UTC 24 Sep 04 02:25:58 AM UTC 24 2398743343 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.1558744193 Sep 04 02:25:41 AM UTC 24 Sep 04 02:25:58 AM UTC 24 4763198135 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.3904966911 Sep 04 02:25:50 AM UTC 24 Sep 04 02:25:58 AM UTC 24 6473664103 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.1781598029 Sep 04 02:25:52 AM UTC 24 Sep 04 02:25:58 AM UTC 24 2813939392 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/12.rv_dm_alert_test.2297320554 Sep 04 02:25:56 AM UTC 24 Sep 04 02:25:59 AM UTC 24 60188450 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/11.rv_dm_bad_sba_tl_access.2577015018 Sep 04 02:25:54 AM UTC 24 Sep 04 02:25:59 AM UTC 24 2843083702 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.797445253 Sep 04 02:25:54 AM UTC 24 Sep 04 02:25:59 AM UTC 24 3480353860 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/10.rv_dm_sba_tl_access.3263553613 Sep 04 02:25:52 AM UTC 24 Sep 04 02:25:59 AM UTC 24 1848718259 ps
T246 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.3310268148 Sep 04 02:26:03 AM UTC 24 Sep 04 02:26:11 AM UTC 24 8344134877 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all.2948267408 Sep 04 02:25:48 AM UTC 24 Sep 04 02:25:59 AM UTC 24 4335892337 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/11.rv_dm_sba_tl_access.3602010309 Sep 04 02:25:54 AM UTC 24 Sep 04 02:25:59 AM UTC 24 2384808977 ps
T224 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/10.rv_dm_stress_all.2984560779 Sep 04 02:25:54 AM UTC 24 Sep 04 02:26:00 AM UTC 24 2786650799 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/1.rv_dm_autoincr_sba_tl_access.2135215664 Sep 04 02:25:36 AM UTC 24 Sep 04 02:26:00 AM UTC 24 8138308002 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/13.rv_dm_alert_test.4089197719 Sep 04 02:25:59 AM UTC 24 Sep 04 02:26:01 AM UTC 24 43264002 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/13.rv_dm_sba_tl_access.3771657017 Sep 04 02:25:58 AM UTC 24 Sep 04 02:26:12 AM UTC 24 9721259174 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/12.rv_dm_stress_all.923902419 Sep 04 02:25:56 AM UTC 24 Sep 04 02:26:02 AM UTC 24 5989111258 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/12.rv_dm_autoincr_sba_tl_access.1626183715 Sep 04 02:25:56 AM UTC 24 Sep 04 02:26:02 AM UTC 24 6699596589 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/14.rv_dm_alert_test.3836990958 Sep 04 02:26:00 AM UTC 24 Sep 04 02:26:02 AM UTC 24 107081224 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/8.rv_dm_sba_tl_access.1813682096 Sep 04 02:25:48 AM UTC 24 Sep 04 02:26:03 AM UTC 24 5814106588 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/6.rv_dm_sba_tl_access.25840474 Sep 04 02:25:45 AM UTC 24 Sep 04 02:26:03 AM UTC 24 14050632907 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.636026897 Sep 04 02:25:51 AM UTC 24 Sep 04 02:26:03 AM UTC 24 5847146419 ps
T230 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/15.rv_dm_alert_test.2326099641 Sep 04 02:26:02 AM UTC 24 Sep 04 02:26:04 AM UTC 24 209979720 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.2256913414 Sep 04 02:25:55 AM UTC 24 Sep 04 02:26:05 AM UTC 24 2520538957 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.563115083 Sep 04 02:25:51 AM UTC 24 Sep 04 02:26:05 AM UTC 24 5530911713 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/14.rv_dm_sba_tl_access.1937023032 Sep 04 02:25:59 AM UTC 24 Sep 04 02:26:06 AM UTC 24 2434682789 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/14.rv_dm_stress_all.1955692546 Sep 04 02:26:00 AM UTC 24 Sep 04 02:26:06 AM UTC 24 2256683459 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/11.rv_dm_stress_all.2363184889 Sep 04 02:25:55 AM UTC 24 Sep 04 02:26:06 AM UTC 24 4417545668 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/16.rv_dm_alert_test.1393333168 Sep 04 02:26:04 AM UTC 24 Sep 04 02:26:06 AM UTC 24 68766276 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/10.rv_dm_bad_sba_tl_access.2692884351 Sep 04 02:25:52 AM UTC 24 Sep 04 02:26:08 AM UTC 24 8198922581 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2188728513 Sep 04 02:26:00 AM UTC 24 Sep 04 02:26:08 AM UTC 24 6240460094 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.3568874825 Sep 04 02:25:52 AM UTC 24 Sep 04 02:26:09 AM UTC 24 9776751134 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/13.rv_dm_stress_all.3104637193 Sep 04 02:25:59 AM UTC 24 Sep 04 02:26:09 AM UTC 24 7739506956 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/17.rv_dm_alert_test.118164892 Sep 04 02:26:08 AM UTC 24 Sep 04 02:26:10 AM UTC 24 147685078 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/17.rv_dm_bad_sba_tl_access.716207047 Sep 04 02:26:06 AM UTC 24 Sep 04 02:26:10 AM UTC 24 3249073800 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/16.rv_dm_bad_sba_tl_access.1096477123 Sep 04 02:26:03 AM UTC 24 Sep 04 02:26:11 AM UTC 24 2147107010 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/16.rv_dm_sba_tl_access.2367257594 Sep 04 02:26:03 AM UTC 24 Sep 04 02:26:11 AM UTC 24 4172378686 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/6.rv_dm_bad_sba_tl_access.2901664301 Sep 04 02:25:47 AM UTC 24 Sep 04 02:26:11 AM UTC 24 11488567625 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/16.rv_dm_autoincr_sba_tl_access.763709802 Sep 04 02:26:04 AM UTC 24 Sep 04 02:26:12 AM UTC 24 1758210393 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/12.rv_dm_bad_sba_tl_access.181786561 Sep 04 02:25:56 AM UTC 24 Sep 04 02:26:12 AM UTC 24 3448014522 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/18.rv_dm_sba_tl_access.2428657792 Sep 04 02:26:08 AM UTC 24 Sep 04 02:26:13 AM UTC 24 1067577563 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/18.rv_dm_stress_all.3161441746 Sep 04 02:26:10 AM UTC 24 Sep 04 02:26:13 AM UTC 24 1037707759 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/15.rv_dm_bad_sba_tl_access.467424980 Sep 04 02:26:00 AM UTC 24 Sep 04 02:26:13 AM UTC 24 5639560450 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/14.rv_dm_bad_sba_tl_access.3306357567 Sep 04 02:26:00 AM UTC 24 Sep 04 02:26:13 AM UTC 24 2857681294 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/13.rv_dm_bad_sba_tl_access.2654832479 Sep 04 02:25:58 AM UTC 24 Sep 04 02:26:13 AM UTC 24 9468686194 ps
T250 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/17.rv_dm_sba_tl_access.2325206285 Sep 04 02:26:05 AM UTC 24 Sep 04 02:26:13 AM UTC 24 2838029520 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/18.rv_dm_alert_test.1980166647 Sep 04 02:26:11 AM UTC 24 Sep 04 02:26:14 AM UTC 24 133782199 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/18.rv_dm_autoincr_sba_tl_access.2120105758 Sep 04 02:26:10 AM UTC 24 Sep 04 02:26:15 AM UTC 24 1536658723 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/19.rv_dm_alert_test.1253000538 Sep 04 02:26:12 AM UTC 24 Sep 04 02:26:15 AM UTC 24 119037608 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/19.rv_dm_bad_sba_tl_access.3435281731 Sep 04 02:26:11 AM UTC 24 Sep 04 02:26:15 AM UTC 24 2197354725 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/18.rv_dm_bad_sba_tl_access.622898358 Sep 04 02:26:09 AM UTC 24 Sep 04 02:26:15 AM UTC 24 7188661428 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/20.rv_dm_alert_test.3892743868 Sep 04 02:26:14 AM UTC 24 Sep 04 02:26:16 AM UTC 24 111249431 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/21.rv_dm_alert_test.2029207407 Sep 04 02:26:14 AM UTC 24 Sep 04 02:26:16 AM UTC 24 62635458 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/23.rv_dm_alert_test.2044274885 Sep 04 02:26:14 AM UTC 24 Sep 04 02:26:16 AM UTC 24 132040566 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/22.rv_dm_alert_test.670018540 Sep 04 02:26:14 AM UTC 24 Sep 04 02:26:16 AM UTC 24 36436833 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/19.rv_dm_sba_tl_access.1794679649 Sep 04 02:26:11 AM UTC 24 Sep 04 02:26:16 AM UTC 24 3306538086 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.1114580249 Sep 04 02:26:09 AM UTC 24 Sep 04 02:26:17 AM UTC 24 5743041830 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/25.rv_dm_alert_test.201314370 Sep 04 02:26:15 AM UTC 24 Sep 04 02:26:17 AM UTC 24 60185616 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/24.rv_dm_alert_test.3122323276 Sep 04 02:26:15 AM UTC 24 Sep 04 02:26:18 AM UTC 24 128371983 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/26.rv_dm_alert_test.661114176 Sep 04 02:26:15 AM UTC 24 Sep 04 02:26:18 AM UTC 24 64526199 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/29.rv_dm_alert_test.1910422217 Sep 04 02:26:17 AM UTC 24 Sep 04 02:26:18 AM UTC 24 123516891 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/27.rv_dm_alert_test.3923237744 Sep 04 02:26:16 AM UTC 24 Sep 04 02:26:19 AM UTC 24 27329063 ps
T248 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/28.rv_dm_alert_test.3038453576 Sep 04 02:26:17 AM UTC 24 Sep 04 02:26:19 AM UTC 24 72321071 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/21.rv_dm_stress_all.524826073 Sep 04 02:26:14 AM UTC 24 Sep 04 02:26:19 AM UTC 24 2654305422 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.1323014293 Sep 04 02:25:48 AM UTC 24 Sep 04 02:26:19 AM UTC 24 45722585749 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.2305336110 Sep 04 02:25:48 AM UTC 24 Sep 04 02:26:19 AM UTC 24 3052185681 ps
T122 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/16.rv_dm_stress_all.681986038 Sep 04 02:26:04 AM UTC 24 Sep 04 02:26:20 AM UTC 24 4479014305 ps
T123 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.2142818892 Sep 04 02:25:58 AM UTC 24 Sep 04 02:26:20 AM UTC 24 8558107836 ps
T124 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/30.rv_dm_alert_test.2303805893 Sep 04 02:26:18 AM UTC 24 Sep 04 02:26:20 AM UTC 24 79639774 ps
T125 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.38891158 Sep 04 02:26:12 AM UTC 24 Sep 04 02:26:20 AM UTC 24 3701476793 ps
T126 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.4290410770 Sep 04 02:26:14 AM UTC 24 Sep 04 02:26:20 AM UTC 24 3076856703 ps
T127 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.2386236116 Sep 04 02:25:48 AM UTC 24 Sep 04 02:26:20 AM UTC 24 8829057589 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/40.rv_dm_stress_all.4081959232 Sep 04 02:26:22 AM UTC 24 Sep 04 02:26:29 AM UTC 24 2367570804 ps
T128 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.3528988341 Sep 04 02:26:00 AM UTC 24 Sep 04 02:26:21 AM UTC 24 5318283615 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2622876114 Sep 04 02:26:11 AM UTC 24 Sep 04 02:26:21 AM UTC 24 5140328968 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/32.rv_dm_alert_test.3030770289 Sep 04 02:26:19 AM UTC 24 Sep 04 02:26:21 AM UTC 24 45008476 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/31.rv_dm_alert_test.3528023875 Sep 04 02:26:19 AM UTC 24 Sep 04 02:26:21 AM UTC 24 76014755 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.1900349425 Sep 04 02:25:51 AM UTC 24 Sep 04 02:26:22 AM UTC 24 7092452897 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.1532367492 Sep 04 02:26:16 AM UTC 24 Sep 04 02:26:22 AM UTC 24 3318537315 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/14.rv_dm_autoincr_sba_tl_access.3403166005 Sep 04 02:26:00 AM UTC 24 Sep 04 02:26:22 AM UTC 24 15077774016 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.1505210783 Sep 04 02:26:15 AM UTC 24 Sep 04 02:26:29 AM UTC 24 4156250383 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/34.rv_dm_alert_test.840895221 Sep 04 02:26:20 AM UTC 24 Sep 04 02:26:22 AM UTC 24 62021196 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/33.rv_dm_alert_test.165349524 Sep 04 02:26:20 AM UTC 24 Sep 04 02:26:22 AM UTC 24 94468207 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/17.rv_dm_stress_all.1337215820 Sep 04 02:26:06 AM UTC 24 Sep 04 02:26:22 AM UTC 24 4985172701 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/35.rv_dm_alert_test.3663376290 Sep 04 02:26:20 AM UTC 24 Sep 04 02:26:22 AM UTC 24 66826244 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/32.rv_dm_stress_all.1763587061 Sep 04 02:26:19 AM UTC 24 Sep 04 02:26:23 AM UTC 24 5620262646 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.957414563 Sep 04 02:26:12 AM UTC 24 Sep 04 02:26:23 AM UTC 24 6512042139 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/28.rv_dm_stress_all.1371824540 Sep 04 02:26:17 AM UTC 24 Sep 04 02:26:23 AM UTC 24 4063232675 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.1493199856 Sep 04 02:26:18 AM UTC 24 Sep 04 02:26:23 AM UTC 24 4745372834 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/36.rv_dm_alert_test.2155203246 Sep 04 02:26:22 AM UTC 24 Sep 04 02:26:24 AM UTC 24 93439887 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/38.rv_dm_stress_all.2705561389 Sep 04 02:26:22 AM UTC 24 Sep 04 02:26:29 AM UTC 24 2035953054 ps
T207 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/26.rv_dm_stress_all.2226719760 Sep 04 02:26:15 AM UTC 24 Sep 04 02:26:24 AM UTC 24 1755439653 ps
T233 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/39.rv_dm_alert_test.231639898 Sep 04 02:26:22 AM UTC 24 Sep 04 02:26:24 AM UTC 24 65732475 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/37.rv_dm_alert_test.245272853 Sep 04 02:26:22 AM UTC 24 Sep 04 02:26:24 AM UTC 24 68465707 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/38.rv_dm_alert_test.3915419870 Sep 04 02:26:22 AM UTC 24 Sep 04 02:26:24 AM UTC 24 82543004 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/40.rv_dm_alert_test.1614301113 Sep 04 02:26:22 AM UTC 24 Sep 04 02:26:24 AM UTC 24 130616212 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.3128820494 Sep 04 02:26:05 AM UTC 24 Sep 04 02:26:24 AM UTC 24 10302607119 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/31.rv_dm_stress_all.813034732 Sep 04 02:26:19 AM UTC 24 Sep 04 02:26:24 AM UTC 24 4545419157 ps
T312 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/12.rv_dm_sba_tl_access.2255381616 Sep 04 02:25:55 AM UTC 24 Sep 04 02:26:24 AM UTC 24 7185657123 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.3515737659 Sep 04 02:26:20 AM UTC 24 Sep 04 02:26:25 AM UTC 24 4088355419 ps
T313 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/43.rv_dm_alert_test.4044000577 Sep 04 02:26:23 AM UTC 24 Sep 04 02:26:25 AM UTC 24 149365097 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/42.rv_dm_alert_test.2262330730 Sep 04 02:26:23 AM UTC 24 Sep 04 02:26:25 AM UTC 24 58107966 ps
T251 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/41.rv_dm_alert_test.3910374332 Sep 04 02:26:23 AM UTC 24 Sep 04 02:26:25 AM UTC 24 149694613 ps
T252 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/15.rv_dm_sba_tl_access.773408682 Sep 04 02:26:00 AM UTC 24 Sep 04 02:26:26 AM UTC 24 13708293228 ps
T218 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/36.rv_dm_stress_all.4010148848 Sep 04 02:26:22 AM UTC 24 Sep 04 02:26:26 AM UTC 24 1404208631 ps
T227 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/44.rv_dm_alert_test.376627640 Sep 04 02:26:23 AM UTC 24 Sep 04 02:26:26 AM UTC 24 127468608 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/24.rv_dm_stress_all.2740219215 Sep 04 02:26:14 AM UTC 24 Sep 04 02:26:27 AM UTC 24 3402617343 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/47.rv_dm_alert_test.3337052032 Sep 04 02:26:25 AM UTC 24 Sep 04 02:26:27 AM UTC 24 157282967 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/46.rv_dm_alert_test.2639399229 Sep 04 02:26:25 AM UTC 24 Sep 04 02:26:27 AM UTC 24 70335120 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/45.rv_dm_alert_test.3695439988 Sep 04 02:26:25 AM UTC 24 Sep 04 02:26:27 AM UTC 24 151929775 ps
T317 /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/coverage/default/49.rv_dm_alert_test.2534082738 Sep 04 02:26:25 AM UTC 24 Sep 04 02:26:27 AM UTC 24 41975925 ps
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