| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 89.06 | 96.32 | 90.10 | 92.10 | 94.67 | 90.44 | 98.63 | 61.18 |
| T314 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/37.rv_dm_stress_all.3280040999 | Sep 09 09:54:59 AM UTC 24 | Sep 09 09:55:10 AM UTC 24 | 9180250961 ps | ||
| T315 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/43.rv_dm_stress_all.2018879081 | Sep 09 09:55:02 AM UTC 24 | Sep 09 09:55:10 AM UTC 24 | 4077288185 ps | ||
| T316 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.3424329065 | Sep 09 09:53:03 AM UTC 24 | Sep 09 09:55:11 AM UTC 24 | 34366823687 ps | ||
| T317 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/49.rv_dm_stress_all.1244356442 | Sep 09 09:55:05 AM UTC 24 | Sep 09 09:55:12 AM UTC 24 | 2978326313 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.3547952858 | Sep 09 09:55:03 AM UTC 24 | Sep 09 09:55:12 AM UTC 24 | 2613466594 ps | ||
| T318 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/40.rv_dm_stress_all.947676079 | Sep 09 09:55:01 AM UTC 24 | Sep 09 09:55:13 AM UTC 24 | 3228774834 ps | ||
| T195 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/48.rv_dm_stress_all.1780594912 | Sep 09 09:55:05 AM UTC 24 | Sep 09 09:55:14 AM UTC 24 | 4488615721 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/38.rv_dm_stress_all.2827311544 | Sep 09 09:55:00 AM UTC 24 | Sep 09 09:55:15 AM UTC 24 | 4609791458 ps | ||
| T319 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/23.rv_dm_stress_all.129651105 | Sep 09 09:54:51 AM UTC 24 | Sep 09 09:55:18 AM UTC 24 | 7535654289 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.2522687991 | Sep 09 09:55:02 AM UTC 24 | Sep 09 09:55:21 AM UTC 24 | 5600525981 ps | ||
| T320 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_autoincr_sba_tl_access.3576563422 | Sep 09 09:53:38 AM UTC 24 | Sep 09 09:55:36 AM UTC 24 | 24949933070 ps | ||
| T321 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.3727594043 | Sep 09 09:53:33 AM UTC 24 | Sep 09 09:55:50 AM UTC 24 | 36432229937 ps | ||
| T322 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.599932880 | Sep 09 09:54:45 AM UTC 24 | Sep 09 09:56:49 AM UTC 24 | 65160457909 ps | ||
| T98 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2724108116 | Sep 09 09:49:40 AM UTC 24 | Sep 09 09:49:43 AM UTC 24 | 103598592 ps | ||
| T99 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2279269768 | Sep 09 09:49:42 AM UTC 24 | Sep 09 09:49:45 AM UTC 24 | 223378328 ps | ||
| T100 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1827437249 | Sep 09 09:49:42 AM UTC 24 | Sep 09 09:49:47 AM UTC 24 | 534436814 ps | ||
| T323 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3699353930 | Sep 09 09:49:43 AM UTC 24 | Sep 09 09:49:52 AM UTC 24 | 1030127099 ps | ||
| T324 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2351597075 | Sep 09 09:49:42 AM UTC 24 | Sep 09 09:49:54 AM UTC 24 | 1631737507 ps | ||
| T325 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.543313974 | Sep 09 09:49:54 AM UTC 24 | Sep 09 09:49:56 AM UTC 24 | 82097822 ps | ||
| T326 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.3075736556 | Sep 09 09:49:48 AM UTC 24 | Sep 09 09:49:56 AM UTC 24 | 152816507 ps | ||
| T327 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1841992078 | Sep 09 09:49:56 AM UTC 24 | Sep 09 09:49:57 AM UTC 24 | 112639590 ps | ||
| T122 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2543408937 | Sep 09 09:49:57 AM UTC 24 | Sep 09 09:50:00 AM UTC 24 | 91404266 ps | ||
| T123 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.1930469294 | Sep 09 09:49:57 AM UTC 24 | Sep 09 09:50:02 AM UTC 24 | 229381550 ps | ||
| T328 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3453745962 | Sep 09 09:50:01 AM UTC 24 | Sep 09 09:50:07 AM UTC 24 | 390605261 ps | ||
| T329 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1123499033 | Sep 09 09:49:42 AM UTC 24 | Sep 09 09:50:08 AM UTC 24 | 33789603916 ps | ||
| T165 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.850844890 | Sep 09 09:49:53 AM UTC 24 | Sep 09 09:50:09 AM UTC 24 | 8487627067 ps | ||
| T330 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1102526234 | Sep 09 09:50:07 AM UTC 24 | Sep 09 09:50:10 AM UTC 24 | 207489819 ps | ||
| T331 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.133776050 | Sep 09 09:50:07 AM UTC 24 | Sep 09 09:50:10 AM UTC 24 | 297642665 ps | ||
| T124 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3876010946 | Sep 09 09:49:39 AM UTC 24 | Sep 09 09:50:14 AM UTC 24 | 1842027320 ps | ||
| T125 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.956624563 | Sep 09 09:50:00 AM UTC 24 | Sep 09 09:50:15 AM UTC 24 | 663643099 ps | ||
| T134 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2405375246 | Sep 09 09:50:10 AM UTC 24 | Sep 09 09:50:15 AM UTC 24 | 4649346447 ps | ||
| T82 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3426398841 | Sep 09 09:49:47 AM UTC 24 | Sep 09 09:50:16 AM UTC 24 | 816052313 ps | ||
| T332 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.1810244705 | Sep 09 09:50:16 AM UTC 24 | Sep 09 09:50:18 AM UTC 24 | 48298197 ps | ||
| T333 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1739523623 | Sep 09 09:50:16 AM UTC 24 | Sep 09 09:50:18 AM UTC 24 | 87892041 ps | ||
| T334 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2755075886 | Sep 09 09:50:10 AM UTC 24 | Sep 09 09:50:19 AM UTC 24 | 1322642192 ps | ||
| T335 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.863992513 | Sep 09 09:50:14 AM UTC 24 | Sep 09 09:50:20 AM UTC 24 | 251499783 ps | ||
| T126 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3960310163 | Sep 09 09:50:17 AM UTC 24 | Sep 09 09:50:21 AM UTC 24 | 232535238 ps | ||
| T127 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.3325429936 | Sep 09 09:50:20 AM UTC 24 | Sep 09 09:50:23 AM UTC 24 | 97290827 ps | ||
| T336 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2542706570 | Sep 09 09:50:11 AM UTC 24 | Sep 09 09:50:24 AM UTC 24 | 7606804864 ps | ||
| T105 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.4064371581 | Sep 09 09:50:21 AM UTC 24 | Sep 09 09:50:26 AM UTC 24 | 194414671 ps | ||
| T337 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.4047156489 | Sep 09 09:50:24 AM UTC 24 | Sep 09 09:50:28 AM UTC 24 | 397347456 ps | ||
| T128 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.530973952 | Sep 09 09:50:20 AM UTC 24 | Sep 09 09:50:28 AM UTC 24 | 146843087 ps | ||
| T338 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3481076403 | Sep 09 09:50:08 AM UTC 24 | Sep 09 09:50:29 AM UTC 24 | 10394742704 ps | ||
| T339 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.138957594 | Sep 09 09:50:10 AM UTC 24 | Sep 09 09:50:30 AM UTC 24 | 6519778840 ps | ||
| T340 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.4027216602 | Sep 09 09:50:24 AM UTC 24 | Sep 09 09:50:30 AM UTC 24 | 719382769 ps | ||
| T341 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3665710359 | Sep 09 09:50:28 AM UTC 24 | Sep 09 09:50:32 AM UTC 24 | 1322268866 ps | ||
| T342 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2045357758 | Sep 09 09:50:31 AM UTC 24 | Sep 09 09:50:34 AM UTC 24 | 57066023 ps | ||
| T343 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2025952534 | Sep 09 09:49:44 AM UTC 24 | Sep 09 09:50:35 AM UTC 24 | 9715401426 ps | ||
| T344 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_walk.2243482158 | Sep 09 09:50:35 AM UTC 24 | Sep 09 09:50:37 AM UTC 24 | 39727297 ps | ||
| T179 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.898244510 | Sep 09 09:50:15 AM UTC 24 | Sep 09 09:50:37 AM UTC 24 | 2320182849 ps | ||
| T129 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.4142790488 | Sep 09 09:49:58 AM UTC 24 | Sep 09 09:50:38 AM UTC 24 | 3389532008 ps | ||
| T345 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_errors.1456722819 | Sep 09 09:50:33 AM UTC 24 | Sep 09 09:50:38 AM UTC 24 | 79272305 ps | ||
| T346 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1619412503 | Sep 09 09:50:36 AM UTC 24 | Sep 09 09:50:38 AM UTC 24 | 50355525 ps | ||
| T347 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.814709886 | Sep 09 09:50:13 AM UTC 24 | Sep 09 09:50:40 AM UTC 24 | 4179027076 ps | ||
| T348 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3237237150 | Sep 09 09:50:27 AM UTC 24 | Sep 09 09:50:41 AM UTC 24 | 12076094308 ps | ||
| T130 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.429682805 | Sep 09 09:50:38 AM UTC 24 | Sep 09 09:50:41 AM UTC 24 | 433942516 ps | ||
| T131 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_rw.713573382 | Sep 09 09:50:38 AM UTC 24 | Sep 09 09:50:42 AM UTC 24 | 59675585 ps | ||
| T349 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1609815437 | Sep 09 09:50:41 AM UTC 24 | Sep 09 09:50:44 AM UTC 24 | 206516778 ps | ||
| T350 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3130293697 | Sep 09 09:50:41 AM UTC 24 | Sep 09 09:50:44 AM UTC 24 | 334575471 ps | ||
| T351 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1608852805 | Sep 09 09:50:42 AM UTC 24 | Sep 09 09:50:46 AM UTC 24 | 1937157494 ps | ||
| T138 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2791031018 | Sep 09 09:50:38 AM UTC 24 | Sep 09 09:50:46 AM UTC 24 | 177938741 ps | ||
| T352 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3184373863 | Sep 09 09:50:39 AM UTC 24 | Sep 09 09:50:46 AM UTC 24 | 59150359 ps | ||
| T353 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.942203169 | Sep 09 09:50:30 AM UTC 24 | Sep 09 09:50:47 AM UTC 24 | 9038004830 ps | ||
| T135 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.4005642152 | Sep 09 09:50:45 AM UTC 24 | Sep 09 09:50:49 AM UTC 24 | 1156747168 ps | ||
| T354 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_walk.385210556 | Sep 09 09:50:51 AM UTC 24 | Sep 09 09:50:53 AM UTC 24 | 139875337 ps | ||
| T355 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3761925350 | Sep 09 09:49:46 AM UTC 24 | Sep 09 09:50:54 AM UTC 24 | 36648731916 ps | ||
| T180 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.554246272 | Sep 09 09:50:35 AM UTC 24 | Sep 09 09:50:55 AM UTC 24 | 4133436972 ps | ||
| T356 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.544936432 | Sep 09 09:50:47 AM UTC 24 | Sep 09 09:50:57 AM UTC 24 | 5373598817 ps | ||
| T357 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_partial_access.424338547 | Sep 09 09:50:54 AM UTC 24 | Sep 09 09:50:57 AM UTC 24 | 100527422 ps | ||
| T358 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_errors.2945397421 | Sep 09 09:50:48 AM UTC 24 | Sep 09 09:50:57 AM UTC 24 | 385588178 ps | ||
| T139 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2597005732 | Sep 09 09:50:55 AM UTC 24 | Sep 09 09:51:00 AM UTC 24 | 653651615 ps | ||
| T359 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.101398777 | Sep 09 09:50:29 AM UTC 24 | Sep 09 09:51:01 AM UTC 24 | 14498731195 ps | ||
| T140 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_rw.1760276233 | Sep 09 09:50:56 AM UTC 24 | Sep 09 09:51:01 AM UTC 24 | 404858713 ps | ||
| T136 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.394193359 | Sep 09 09:51:06 AM UTC 24 | Sep 09 09:51:10 AM UTC 24 | 2287297081 ps | ||
| T360 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2032905525 | Sep 09 09:50:42 AM UTC 24 | Sep 09 09:51:03 AM UTC 24 | 4785572246 ps | ||
| T361 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2114398636 | Sep 09 09:51:02 AM UTC 24 | Sep 09 09:51:04 AM UTC 24 | 86181787 ps | ||
| T362 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2587505705 | Sep 09 09:51:02 AM UTC 24 | Sep 09 09:51:05 AM UTC 24 | 401281898 ps | ||
| T363 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2108966648 | Sep 09 09:50:59 AM UTC 24 | Sep 09 09:51:05 AM UTC 24 | 164579423 ps | ||
| T166 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1737102844 | Sep 09 09:50:50 AM UTC 24 | Sep 09 09:51:07 AM UTC 24 | 5022154520 ps | ||
| T141 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1824445758 | Sep 09 09:50:57 AM UTC 24 | Sep 09 09:51:09 AM UTC 24 | 1188720411 ps | ||
| T364 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1213927223 | Sep 09 09:51:04 AM UTC 24 | Sep 09 09:51:11 AM UTC 24 | 2988272839 ps | ||
| T365 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.302725953 | Sep 09 09:51:06 AM UTC 24 | Sep 09 09:51:12 AM UTC 24 | 1764098174 ps | ||
| T366 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2365260426 | Sep 09 09:51:05 AM UTC 24 | Sep 09 09:51:13 AM UTC 24 | 1365971035 ps | ||
| T142 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2169632076 | Sep 09 09:50:20 AM UTC 24 | Sep 09 09:51:13 AM UTC 24 | 2535211500 ps | ||
| T367 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3249284870 | Sep 09 09:51:14 AM UTC 24 | Sep 09 09:51:17 AM UTC 24 | 144487118 ps | ||
| T368 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_walk.2533932605 | Sep 09 09:51:14 AM UTC 24 | Sep 09 09:51:18 AM UTC 24 | 120964362 ps | ||
| T369 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2934408604 | Sep 09 09:50:31 AM UTC 24 | Sep 09 09:51:19 AM UTC 24 | 85667286386 ps | ||
| T370 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3539820459 | Sep 09 09:51:16 AM UTC 24 | Sep 09 09:51:19 AM UTC 24 | 348636375 ps | ||
| T143 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_rw.3599483508 | Sep 09 09:51:18 AM UTC 24 | Sep 09 09:51:23 AM UTC 24 | 772249900 ps | ||
| T371 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.392346794 | Sep 09 09:50:46 AM UTC 24 | Sep 09 09:51:24 AM UTC 24 | 7669632329 ps | ||
| T176 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_errors.2355124876 | Sep 09 09:51:12 AM UTC 24 | Sep 09 09:51:24 AM UTC 24 | 665828179 ps | ||
| T372 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.789361396 | Sep 09 09:51:22 AM UTC 24 | Sep 09 09:51:25 AM UTC 24 | 203563100 ps | ||
| T373 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.682361366 | Sep 09 09:50:38 AM UTC 24 | Sep 09 09:51:25 AM UTC 24 | 6205004734 ps | ||
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| T374 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2022932232 | Sep 09 09:51:21 AM UTC 24 | Sep 09 09:51:26 AM UTC 24 | 263357205 ps | ||
| T207 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1778020903 | Sep 09 09:51:13 AM UTC 24 | Sep 09 09:51:29 AM UTC 24 | 1931560587 ps | ||
| T375 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_rw.2931898152 | Sep 09 09:51:27 AM UTC 24 | Sep 09 09:51:30 AM UTC 24 | 94091905 ps | ||
| T155 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1208449533 | Sep 09 09:51:20 AM UTC 24 | Sep 09 09:51:31 AM UTC 24 | 331199501 ps | ||
| T376 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_errors.684382265 | Sep 09 09:51:25 AM UTC 24 | Sep 09 09:51:32 AM UTC 24 | 140974546 ps | ||
| T377 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.568964589 | Sep 09 09:51:32 AM UTC 24 | Sep 09 09:51:35 AM UTC 24 | 305194935 ps | ||
| T104 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1810325778 | Sep 09 09:51:30 AM UTC 24 | Sep 09 09:51:36 AM UTC 24 | 69628521 ps | ||
| T156 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.260940779 | Sep 09 09:51:27 AM UTC 24 | Sep 09 09:51:38 AM UTC 24 | 210902838 ps | ||
| T378 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.512339768 | Sep 09 09:51:23 AM UTC 24 | Sep 09 09:51:39 AM UTC 24 | 3247946064 ps | ||
| T379 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.4006807656 | Sep 09 09:50:33 AM UTC 24 | Sep 09 09:51:40 AM UTC 24 | 4569491232 ps | ||
| T144 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1047259592 | Sep 09 09:51:02 AM UTC 24 | Sep 09 09:51:41 AM UTC 24 | 958148865 ps | ||
| T380 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2715393774 | Sep 09 09:50:22 AM UTC 24 | Sep 09 09:51:41 AM UTC 24 | 1226309484 ps | ||
| T381 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_errors.1397252270 | Sep 09 09:51:37 AM UTC 24 | Sep 09 09:51:42 AM UTC 24 | 108187197 ps | ||
| T382 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_rw.867044536 | Sep 09 09:51:40 AM UTC 24 | Sep 09 09:51:43 AM UTC 24 | 59172859 ps | ||
| T383 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.69229523 | Sep 09 09:51:41 AM UTC 24 | Sep 09 09:51:44 AM UTC 24 | 225601165 ps | ||
| T384 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1269521076 | Sep 09 09:51:32 AM UTC 24 | Sep 09 09:51:45 AM UTC 24 | 5898863487 ps | ||
| T385 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1497006405 | Sep 09 09:51:41 AM UTC 24 | Sep 09 09:51:45 AM UTC 24 | 72695233 ps | ||
| T386 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3467997967 | Sep 09 09:51:33 AM UTC 24 | Sep 09 09:51:46 AM UTC 24 | 7332688118 ps | ||
| T387 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_rw.3389773379 | Sep 09 09:51:47 AM UTC 24 | Sep 09 09:51:50 AM UTC 24 | 253678438 ps | ||
| T388 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3406566974 | Sep 09 09:50:48 AM UTC 24 | Sep 09 09:51:50 AM UTC 24 | 3027975058 ps | ||
| T389 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.4285174531 | Sep 09 09:51:24 AM UTC 24 | Sep 09 09:51:51 AM UTC 24 | 5256696689 ps | ||
| T157 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.789940918 | Sep 09 09:51:41 AM UTC 24 | Sep 09 09:51:51 AM UTC 24 | 887565281 ps | ||
| T390 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3275272818 | Sep 09 09:51:43 AM UTC 24 | Sep 09 09:51:52 AM UTC 24 | 918985316 ps | ||
| T149 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1186911853 | Sep 09 09:50:39 AM UTC 24 | Sep 09 09:51:52 AM UTC 24 | 4643096189 ps | ||
| T209 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3181504461 | Sep 09 09:51:39 AM UTC 24 | Sep 09 09:51:53 AM UTC 24 | 2712628247 ps | ||
| T391 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_errors.3381953470 | Sep 09 09:51:45 AM UTC 24 | Sep 09 09:51:53 AM UTC 24 | 870970663 ps | ||
| T392 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2250581929 | Sep 09 09:51:51 AM UTC 24 | Sep 09 09:51:54 AM UTC 24 | 316679713 ps | ||
| T208 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3433103925 | Sep 09 09:51:26 AM UTC 24 | Sep 09 09:51:56 AM UTC 24 | 6162056353 ps | ||
| T152 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_rw.578222137 | Sep 09 09:51:53 AM UTC 24 | Sep 09 09:51:56 AM UTC 24 | 265879774 ps | ||
| T393 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1681725825 | Sep 09 09:51:51 AM UTC 24 | Sep 09 09:51:57 AM UTC 24 | 300990980 ps | ||
| T394 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_errors.323442822 | Sep 09 09:51:53 AM UTC 24 | Sep 09 09:52:00 AM UTC 24 | 701259054 ps | ||
| T395 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3096065347 | Sep 09 09:51:58 AM UTC 24 | Sep 09 09:52:00 AM UTC 24 | 132658958 ps | ||
| T396 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3604337010 | Sep 09 09:51:56 AM UTC 24 | Sep 09 09:52:01 AM UTC 24 | 95558604 ps | ||
| T145 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.4237705802 | Sep 09 09:51:47 AM UTC 24 | Sep 09 09:52:02 AM UTC 24 | 4557321768 ps | ||
| T158 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2947396198 | Sep 09 09:51:54 AM UTC 24 | Sep 09 09:52:05 AM UTC 24 | 177817136 ps | ||
| T210 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1524833878 | Sep 09 09:51:47 AM UTC 24 | Sep 09 09:52:06 AM UTC 24 | 3763435777 ps | ||
| T397 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3380921581 | Sep 09 09:51:58 AM UTC 24 | Sep 09 09:52:07 AM UTC 24 | 1492849722 ps | ||
| T398 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_rw.3445253277 | Sep 09 09:52:06 AM UTC 24 | Sep 09 09:52:09 AM UTC 24 | 105933845 ps | ||
| T399 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3919295296 | Sep 09 09:51:53 AM UTC 24 | Sep 09 09:52:09 AM UTC 24 | 2038379734 ps | ||
| T400 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_errors.2292490095 | Sep 09 09:52:02 AM UTC 24 | Sep 09 09:52:10 AM UTC 24 | 261411363 ps | ||
| T401 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.3957783079 | Sep 09 09:51:25 AM UTC 24 | Sep 09 09:52:12 AM UTC 24 | 2151779220 ps | ||
| T402 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2331913950 | Sep 09 09:52:08 AM UTC 24 | Sep 09 09:52:12 AM UTC 24 | 218142538 ps | ||
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| T404 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2969307773 | Sep 09 09:50:57 AM UTC 24 | Sep 09 09:52:13 AM UTC 24 | 1502320827 ps | ||
| T146 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3467228015 | Sep 09 09:52:07 AM UTC 24 | Sep 09 09:52:15 AM UTC 24 | 286465198 ps | ||
| T147 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.1995874282 | Sep 09 09:52:13 AM UTC 24 | Sep 09 09:52:18 AM UTC 24 | 174755890 ps | ||
| T405 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.4091989698 | Sep 09 09:51:52 AM UTC 24 | Sep 09 09:52:18 AM UTC 24 | 5165462838 ps | ||
| T406 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2737581757 | Sep 09 09:51:09 AM UTC 24 | Sep 09 09:52:20 AM UTC 24 | 54949591053 ps | ||
| T407 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.389476414 | Sep 09 09:52:01 AM UTC 24 | Sep 09 09:52:21 AM UTC 24 | 11496047346 ps | ||
| T408 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.2225194200 | Sep 09 09:52:13 AM UTC 24 | Sep 09 09:52:21 AM UTC 24 | 169730255 ps | ||
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| T410 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1567439694 | Sep 09 09:51:52 AM UTC 24 | Sep 09 09:52:22 AM UTC 24 | 11779419941 ps | ||
| T411 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1806121406 | Sep 09 09:52:16 AM UTC 24 | Sep 09 09:52:22 AM UTC 24 | 95610009 ps | ||
| T217 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1949255971 | Sep 09 09:52:03 AM UTC 24 | Sep 09 09:52:24 AM UTC 24 | 5207306664 ps | ||
| T151 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3043366251 | Sep 09 09:51:19 AM UTC 24 | Sep 09 09:52:25 AM UTC 24 | 2401060634 ps | ||
| T412 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_rw.3527088611 | Sep 09 09:52:22 AM UTC 24 | Sep 09 09:52:25 AM UTC 24 | 75079740 ps | ||
| T211 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1510733896 | Sep 09 09:52:13 AM UTC 24 | Sep 09 09:52:26 AM UTC 24 | 1862664586 ps | ||
| T413 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2115902936 | Sep 09 09:52:19 AM UTC 24 | Sep 09 09:52:26 AM UTC 24 | 7418421579 ps | ||
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| T415 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_errors.142549931 | Sep 09 09:52:22 AM UTC 24 | Sep 09 09:52:27 AM UTC 24 | 792294659 ps | ||
| T148 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3381248146 | Sep 09 09:52:15 AM UTC 24 | Sep 09 09:52:27 AM UTC 24 | 501920627 ps | ||
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| T101 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.729488518 | Sep 09 09:51:45 AM UTC 24 | Sep 09 09:52:30 AM UTC 24 | 18293558484 ps | ||
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| T419 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_errors.944914927 | Sep 09 09:52:26 AM UTC 24 | Sep 09 09:52:33 AM UTC 24 | 147726404 ps | ||
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| T423 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3640996098 | Sep 09 09:52:29 AM UTC 24 | Sep 09 09:52:35 AM UTC 24 | 561284739 ps | ||
| T424 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.3064706299 | Sep 09 09:52:21 AM UTC 24 | Sep 09 09:52:36 AM UTC 24 | 27628078485 ps | ||
| T102 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3337973821 | Sep 09 09:51:10 AM UTC 24 | Sep 09 09:52:36 AM UTC 24 | 25024916849 ps | ||
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| T426 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_errors.2839981685 | Sep 09 09:52:32 AM UTC 24 | Sep 09 09:52:37 AM UTC 24 | 655748934 ps | ||
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| T428 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.313382616 | Sep 09 09:52:35 AM UTC 24 | Sep 09 09:52:38 AM UTC 24 | 1206969570 ps | ||
| T153 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_rw.4268433093 | Sep 09 09:52:34 AM UTC 24 | Sep 09 09:52:39 AM UTC 24 | 654059059 ps | ||
| T429 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2630170915 | Sep 09 09:52:35 AM UTC 24 | Sep 09 09:52:40 AM UTC 24 | 312390249 ps | ||
| T430 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.774162956 | Sep 09 09:52:10 AM UTC 24 | Sep 09 09:52:41 AM UTC 24 | 6436271581 ps | ||
| T431 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.968273506 | Sep 09 09:51:44 AM UTC 24 | Sep 09 09:52:42 AM UTC 24 | 12690415407 ps | ||
| T432 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.997953287 | Sep 09 09:52:34 AM UTC 24 | Sep 09 09:52:42 AM UTC 24 | 966112924 ps | ||
| T433 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2382058553 | Sep 09 09:52:26 AM UTC 24 | Sep 09 09:52:42 AM UTC 24 | 9557641232 ps | ||
| T434 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1811080283 | Sep 09 09:52:36 AM UTC 24 | Sep 09 09:52:42 AM UTC 24 | 2162641046 ps | ||
| T435 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_errors.3961912871 | Sep 09 09:52:37 AM UTC 24 | Sep 09 09:52:43 AM UTC 24 | 81646946 ps | ||
| T150 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_rw.1305770410 | Sep 09 09:52:39 AM UTC 24 | Sep 09 09:52:43 AM UTC 24 | 389973261 ps | ||
| T436 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2073118934 | Sep 09 09:52:41 AM UTC 24 | Sep 09 09:52:43 AM UTC 24 | 169329566 ps | ||
| T437 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2564170156 | Sep 09 09:52:40 AM UTC 24 | Sep 09 09:52:43 AM UTC 24 | 126723434 ps | ||
| T438 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2617547859 | Sep 09 09:52:43 AM UTC 24 | Sep 09 09:52:46 AM UTC 24 | 171801018 ps | ||
| T439 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.379743192 | Sep 09 09:52:22 AM UTC 24 | Sep 09 09:52:46 AM UTC 24 | 3725186429 ps | ||
| T440 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.519446126 | Sep 09 09:52:43 AM UTC 24 | Sep 09 09:52:47 AM UTC 24 | 82149595 ps | ||
| T441 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_rw.4002839868 | Sep 09 09:52:43 AM UTC 24 | Sep 09 09:52:47 AM UTC 24 | 189308741 ps | ||
| T442 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.4180487382 | Sep 09 09:52:40 AM UTC 24 | Sep 09 09:52:48 AM UTC 24 | 321402387 ps | ||
| T443 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1006938348 | Sep 09 09:52:41 AM UTC 24 | Sep 09 09:52:48 AM UTC 24 | 1380347807 ps | ||
| T444 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2788503188 | Sep 09 09:52:31 AM UTC 24 | Sep 09 09:52:49 AM UTC 24 | 8588375877 ps | ||
| T445 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1383135216 | Sep 09 09:51:52 AM UTC 24 | Sep 09 09:52:49 AM UTC 24 | 36457305695 ps | ||
| T214 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3498014960 | Sep 09 09:52:38 AM UTC 24 | Sep 09 09:52:50 AM UTC 24 | 1571138532 ps | ||
| T446 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2223186546 | Sep 09 09:52:43 AM UTC 24 | Sep 09 09:52:50 AM UTC 24 | 262186970 ps | ||
| T154 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_rw.298906368 | Sep 09 09:52:48 AM UTC 24 | Sep 09 09:52:51 AM UTC 24 | 300778111 ps | ||
| T447 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1938187156 | Sep 09 09:52:49 AM UTC 24 | Sep 09 09:52:51 AM UTC 24 | 292135984 ps | ||
| T448 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_errors.468169214 | Sep 09 09:52:42 AM UTC 24 | Sep 09 09:52:51 AM UTC 24 | 1138503841 ps | ||
| T449 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_intg_err.480183873 | Sep 09 09:52:26 AM UTC 24 | Sep 09 09:52:52 AM UTC 24 | 15673889167 ps | ||
| T450 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_errors.415672171 | Sep 09 09:52:45 AM UTC 24 | Sep 09 09:52:52 AM UTC 24 | 448950007 ps | ||
| T451 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3948296194 | Sep 09 09:52:49 AM UTC 24 | Sep 09 09:52:53 AM UTC 24 | 89257119 ps | ||
| T452 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_errors.2674101516 | Sep 09 09:52:50 AM UTC 24 | Sep 09 09:52:54 AM UTC 24 | 140975136 ps | ||
| T215 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1001705821 | Sep 09 09:52:34 AM UTC 24 | Sep 09 09:52:54 AM UTC 24 | 5013340638 ps | ||
| T453 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_rw.3788884507 | Sep 09 09:52:51 AM UTC 24 | Sep 09 09:52:55 AM UTC 24 | 93441283 ps | ||
| T454 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3411900332 | Sep 09 09:52:52 AM UTC 24 | Sep 09 09:52:56 AM UTC 24 | 181941943 ps | ||
| T455 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2989742162 | Sep 09 09:52:52 AM UTC 24 | Sep 09 09:52:57 AM UTC 24 | 934477617 ps | ||
| T456 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3485806958 | Sep 09 09:52:48 AM UTC 24 | Sep 09 09:52:58 AM UTC 24 | 1218026667 ps | ||
| T457 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3117485276 | Sep 09 09:52:49 AM UTC 24 | Sep 09 09:52:58 AM UTC 24 | 6249310795 ps | ||
| T458 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_errors.940783464 | Sep 09 09:52:54 AM UTC 24 | Sep 09 09:52:58 AM UTC 24 | 153895521 ps | ||
| T459 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_rw.1968341255 | Sep 09 09:52:55 AM UTC 24 | Sep 09 09:52:59 AM UTC 24 | 230134616 ps | ||
| T460 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_intg_err.4263691788 | Sep 09 09:52:42 AM UTC 24 | Sep 09 09:53:00 AM UTC 24 | 958940054 ps | ||
| T461 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.557634107 | Sep 09 09:52:57 AM UTC 24 | Sep 09 09:53:00 AM UTC 24 | 170635890 ps | ||
| T462 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.139421311 | Sep 09 09:52:52 AM UTC 24 | Sep 09 09:53:00 AM UTC 24 | 3147917895 ps | ||
| T463 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1855233955 | Sep 09 09:52:36 AM UTC 24 | Sep 09 09:53:01 AM UTC 24 | 12232479866 ps | ||
| T213 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3986862996 | Sep 09 09:52:48 AM UTC 24 | Sep 09 09:53:01 AM UTC 24 | 1648811997 ps | ||
| T464 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3693997757 | Sep 09 09:52:58 AM UTC 24 | Sep 09 09:53:02 AM UTC 24 | 373117610 ps | ||
| T465 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1648182418 | Sep 09 09:52:56 AM UTC 24 | Sep 09 09:53:02 AM UTC 24 | 110226353 ps | ||
| T466 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_rw.1201527410 | Sep 09 09:52:59 AM UTC 24 | Sep 09 09:53:02 AM UTC 24 | 185353862 ps | ||
| T467 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.539864532 | Sep 09 09:52:52 AM UTC 24 | Sep 09 09:53:03 AM UTC 24 | 1671609356 ps | ||
| T468 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3216231059 | Sep 09 09:52:44 AM UTC 24 | Sep 09 09:53:03 AM UTC 24 | 5355920793 ps | ||
| T469 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1783689918 | Sep 09 09:50:47 AM UTC 24 | Sep 09 09:53:04 AM UTC 24 | 113750124662 ps | ||
| T470 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2293995794 | Sep 09 09:53:02 AM UTC 24 | Sep 09 09:53:05 AM UTC 24 | 229760449 ps | ||
| T471 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.1951052187 | Sep 09 09:51:36 AM UTC 24 | Sep 09 09:53:05 AM UTC 24 | 29003847261 ps | ||
| T472 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_errors.3439182566 | Sep 09 09:52:59 AM UTC 24 | Sep 09 09:53:06 AM UTC 24 | 247635204 ps | ||
| T473 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3896267603 | Sep 09 09:52:42 AM UTC 24 | Sep 09 09:53:07 AM UTC 24 | 23991713453 ps | ||
| T474 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.506320387 | Sep 09 09:52:58 AM UTC 24 | Sep 09 09:53:09 AM UTC 24 | 2247785412 ps | ||
| T475 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1646702883 | Sep 09 09:53:01 AM UTC 24 | Sep 09 09:53:11 AM UTC 24 | 1076002480 ps | ||
| T212 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3007643160 | Sep 09 09:52:55 AM UTC 24 | Sep 09 09:53:13 AM UTC 24 | 1185559490 ps | ||
| T476 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.244931840 | Sep 09 09:52:54 AM UTC 24 | Sep 09 09:53:17 AM UTC 24 | 33836126409 ps | ||
| T477 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.1923132087 | Sep 09 09:52:50 AM UTC 24 | Sep 09 09:53:20 AM UTC 24 | 1955792483 ps | ||
| T216 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2904697681 | Sep 09 09:52:59 AM UTC 24 | Sep 09 09:53:23 AM UTC 24 | 6503509800 ps | ||
| T478 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.3494490824 | Sep 09 09:52:44 AM UTC 24 | Sep 09 09:53:24 AM UTC 24 | 22805908735 ps | ||
| T479 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3438530224 | Sep 09 09:52:01 AM UTC 24 | Sep 09 09:53:36 AM UTC 24 | 13394085276 ps | ||
| T480 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.1273983589 | Sep 09 09:52:11 AM UTC 24 | Sep 09 09:53:38 AM UTC 24 | 23056950720 ps | ||
| T481 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.4238413047 | Sep 09 09:52:58 AM UTC 24 | Sep 09 09:54:27 AM UTC 24 | 26440510126 ps | ||
| T482 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.145335546 | Sep 09 09:52:50 AM UTC 24 | Sep 09 09:54:57 AM UTC 24 | 88517060047 ps | ||
| T483 | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1313527822 | Sep 09 09:50:11 AM UTC 24 | Sep 09 09:55:06 AM UTC 24 | 88318732056 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_resuming.3566593483 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 186709287 ps |
| CPU time | 1.64 seconds |
| Started | Sep 09 09:53:05 AM UTC 24 |
| Finished | Sep 09 09:53:07 AM UTC 24 |
| Peak memory | 213464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566593483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.3566593483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_resuming/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.1433836236 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1497021713 ps |
| CPU time | 24.91 seconds |
| Started | Sep 09 09:53:21 AM UTC 24 |
| Finished | Sep 09 09:53:47 AM UTC 24 |
| Peak memory | 233048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1433836236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stres s_all_with_rand_reset.1433836236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.3674973439 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 2752707800 ps |
| CPU time | 6.93 seconds |
| Started | Sep 09 09:53:02 AM UTC 24 |
| Finished | Sep 09 09:53:10 AM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674973439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.3674973439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_smoke.290819420 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 864721748 ps |
| CPU time | 1.32 seconds |
| Started | Sep 09 09:53:02 AM UTC 24 |
| Finished | Sep 09 09:53:04 AM UTC 24 |
| Peak memory | 215352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290819420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.290819420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.989185150 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 31659755399 ps |
| CPU time | 78.17 seconds |
| Started | Sep 09 09:53:30 AM UTC 24 |
| Finished | Sep 09 09:54:50 AM UTC 24 |
| Peak memory | 243576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=989185150 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress _all_with_rand_reset.989185150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.4190776768 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1111567240 ps |
| CPU time | 4.91 seconds |
| Started | Sep 09 09:53:21 AM UTC 24 |
| Finished | Sep 09 09:53:27 AM UTC 24 |
| Peak memory | 226340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190776768 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.4190776768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.1828040000 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 118226495 ps |
| CPU time | 1.2 seconds |
| Started | Sep 09 09:53:14 AM UTC 24 |
| Finished | Sep 09 09:53:16 AM UTC 24 |
| Peak memory | 215940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828040000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.1828040000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_cmderr_exception/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.898244510 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 2320182849 ps |
| CPU time | 20.65 seconds |
| Started | Sep 09 09:50:15 AM UTC 24 |
| Finished | Sep 09 09:50:37 AM UTC 24 |
| Peak memory | 232472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898244510 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.898244510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.3283134975 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 2989250550 ps |
| CPU time | 27.45 seconds |
| Started | Sep 09 09:53:27 AM UTC 24 |
| Finished | Sep 09 09:53:55 AM UTC 24 |
| Peak memory | 230736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3283134975 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stres s_all_with_rand_reset.3283134975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.3365173570 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 4961528314 ps |
| CPU time | 13.16 seconds |
| Started | Sep 09 09:53:02 AM UTC 24 |
| Finished | Sep 09 09:53:16 AM UTC 24 |
| Peak memory | 216196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365173570 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.3365173570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/13.rv_dm_autoincr_sba_tl_access.942722584 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 22027368961 ps |
| CPU time | 26.84 seconds |
| Started | Sep 09 09:54:22 AM UTC 24 |
| Finished | Sep 09 09:54:50 AM UTC 24 |
| Peak memory | 233344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942722584 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.942722584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/13.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_buffered_enable.4222137501 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 395537792 ps |
| CPU time | 1.12 seconds |
| Started | Sep 09 09:53:20 AM UTC 24 |
| Finished | Sep 09 09:53:22 AM UTC 24 |
| Peak memory | 252232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222137501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_buffered_enable.4222137501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.2232180724 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1391153604 ps |
| CPU time | 20.23 seconds |
| Started | Sep 09 09:53:53 AM UTC 24 |
| Finished | Sep 09 09:54:14 AM UTC 24 |
| Peak memory | 232584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2232180724 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stres s_all_with_rand_reset.2232180724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.3159857702 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 120967064 ps |
| CPU time | 1.08 seconds |
| Started | Sep 09 09:53:11 AM UTC 24 |
| Finished | Sep 09 09:53:13 AM UTC 24 |
| Peak memory | 213344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159857702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.3159857702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_dmi_failed_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.3443519601 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 358286622 ps |
| CPU time | 1.59 seconds |
| Started | Sep 09 09:53:24 AM UTC 24 |
| Finished | Sep 09 09:53:27 AM UTC 24 |
| Peak memory | 253440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443519601 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.3443519601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/2.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.2502052827 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 93753615 ps |
| CPU time | 0.83 seconds |
| Started | Sep 09 09:53:11 AM UTC 24 |
| Finished | Sep 09 09:53:13 AM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502052827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_scanmode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 0.rv_dm_scanmode.2502052827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_scanmode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.1418616984 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 593567325 ps |
| CPU time | 2.18 seconds |
| Started | Sep 09 09:53:07 AM UTC 24 |
| Finished | Sep 09 09:53:10 AM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418616984 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.1418616984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3876010946 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 1842027320 ps |
| CPU time | 32.99 seconds |
| Started | Sep 09 09:49:39 AM UTC 24 |
| Finished | Sep 09 09:50:14 AM UTC 24 |
| Peak memory | 215364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876010946 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_aliasing.3876010946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.3367222230 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 19855263359 ps |
| CPU time | 60.93 seconds |
| Started | Sep 09 09:53:23 AM UTC 24 |
| Finished | Sep 09 09:54:25 AM UTC 24 |
| Peak memory | 226560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367222230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.3367222230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/2.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.413307025 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 6275629553 ps |
| CPU time | 76.59 seconds |
| Started | Sep 09 09:53:13 AM UTC 24 |
| Finished | Sep 09 09:54:31 AM UTC 24 |
| Peak memory | 228756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=413307025 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress _all_with_rand_reset.413307025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.2387741104 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 155594787 ps |
| CPU time | 1.26 seconds |
| Started | Sep 09 09:53:20 AM UTC 24 |
| Finished | Sep 09 09:53:22 AM UTC 24 |
| Peak memory | 213464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387741104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.2387741104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_dmi_failed_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3337973821 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 25024916849 ps |
| CPU time | 83.8 seconds |
| Started | Sep 09 09:51:10 AM UTC 24 |
| Finished | Sep 09 09:52:36 AM UTC 24 |
| Peak memory | 232524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3337973821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_re set.3337973821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/4.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.1540106918 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 64134999 ps |
| CPU time | 0.86 seconds |
| Started | Sep 09 09:53:13 AM UTC 24 |
| Finished | Sep 09 09:53:15 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540106918 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.1540106918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.3763707023 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 5380308953 ps |
| CPU time | 9.47 seconds |
| Started | Sep 09 09:54:46 AM UTC 24 |
| Finished | Sep 09 09:54:57 AM UTC 24 |
| Peak memory | 216200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763707023 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.3763707023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/19.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3433103925 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 6162056353 ps |
| CPU time | 28.23 seconds |
| Started | Sep 09 09:51:26 AM UTC 24 |
| Finished | Sep 09 09:51:56 AM UTC 24 |
| Peak memory | 232484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433103925 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.3433103925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/5.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/26.rv_dm_stress_all.886511029 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 5171188404 ps |
| CPU time | 6.88 seconds |
| Started | Sep 09 09:54:52 AM UTC 24 |
| Finished | Sep 09 09:55:00 AM UTC 24 |
| Peak memory | 226108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886511029 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.886511029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/26.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.674822572 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 86751525 ps |
| CPU time | 0.92 seconds |
| Started | Sep 09 09:53:09 AM UTC 24 |
| Finished | Sep 09 09:53:11 AM UTC 24 |
| Peak memory | 225860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674822572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_rom_read_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.674822572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_rom_read_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/17.rv_dm_autoincr_sba_tl_access.918853522 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 3409062373 ps |
| CPU time | 12.94 seconds |
| Started | Sep 09 09:54:39 AM UTC 24 |
| Finished | Sep 09 09:54:53 AM UTC 24 |
| Peak memory | 226492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918853522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.918853522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/17.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.1006472624 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 1996901088 ps |
| CPU time | 4.09 seconds |
| Started | Sep 09 09:53:13 AM UTC 24 |
| Finished | Sep 09 09:53:18 AM UTC 24 |
| Peak memory | 226320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006472624 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.1006472624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.3547952858 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 2613466594 ps |
| CPU time | 7.74 seconds |
| Started | Sep 09 09:55:03 AM UTC 24 |
| Finished | Sep 09 09:55:12 AM UTC 24 |
| Peak memory | 216128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547952858 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.3547952858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/46.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.3829811424 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 3488012849 ps |
| CPU time | 12.24 seconds |
| Started | Sep 09 09:54:47 AM UTC 24 |
| Finished | Sep 09 09:55:00 AM UTC 24 |
| Peak memory | 216140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829811424 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.3829811424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/20.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.2211221079 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 5318011257 ps |
| CPU time | 6.21 seconds |
| Started | Sep 09 09:53:14 AM UTC 24 |
| Finished | Sep 09 09:53:21 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211221079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_tl_access.2211221079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.1939132694 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1573707863 ps |
| CPU time | 6.22 seconds |
| Started | Sep 09 09:53:07 AM UTC 24 |
| Finished | Sep 09 09:53:14 AM UTC 24 |
| Peak memory | 216020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939132694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.1939132694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_sba_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/11.rv_dm_stress_all.2104491297 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 2726212171 ps |
| CPU time | 2.99 seconds |
| Started | Sep 09 09:54:12 AM UTC 24 |
| Finished | Sep 09 09:54:16 AM UTC 24 |
| Peak memory | 226368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104491297 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.2104491297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/11.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3007643160 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 1185559490 ps |
| CPU time | 17.35 seconds |
| Started | Sep 09 09:52:55 AM UTC 24 |
| Finished | Sep 09 09:53:13 AM UTC 24 |
| Peak memory | 232196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007643160 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3007643160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/18.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.263149654 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 1920766242 ps |
| CPU time | 6.19 seconds |
| Started | Sep 09 09:54:51 AM UTC 24 |
| Finished | Sep 09 09:54:58 AM UTC 24 |
| Peak memory | 216000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263149654 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.263149654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/22.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2279269768 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 223378328 ps |
| CPU time | 2.5 seconds |
| Started | Sep 09 09:49:42 AM UTC 24 |
| Finished | Sep 09 09:49:45 AM UTC 24 |
| Peak memory | 215148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279269768 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_aliasing.2279269768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.956624563 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 663643099 ps |
| CPU time | 13.47 seconds |
| Started | Sep 09 09:50:00 AM UTC 24 |
| Finished | Sep 09 09:50:15 AM UTC 24 |
| Peak memory | 215520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956624563 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_csr_outstanding.956624563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2405375246 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 4649346447 ps |
| CPU time | 4.3 seconds |
| Started | Sep 09 09:50:10 AM UTC 24 |
| Finished | Sep 09 09:50:15 AM UTC 24 |
| Peak memory | 215360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405375246 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_hw_reset.2405375246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.3860634930 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 692048324 ps |
| CPU time | 3.27 seconds |
| Started | Sep 09 09:53:06 AM UTC 24 |
| Finished | Sep 09 09:53:10 AM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860634930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.3860634930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_cmderr_halt_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.554246272 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 4133436972 ps |
| CPU time | 19.52 seconds |
| Started | Sep 09 09:50:35 AM UTC 24 |
| Finished | Sep 09 09:50:55 AM UTC 24 |
| Peak memory | 232500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554246272 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.554246272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/2.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/23.rv_dm_stress_all.129651105 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 7535654289 ps |
| CPU time | 26.24 seconds |
| Started | Sep 09 09:54:51 AM UTC 24 |
| Finished | Sep 09 09:55:18 AM UTC 24 |
| Peak memory | 216076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129651105 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.129651105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/23.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_rw.1760276233 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 404858713 ps |
| CPU time | 3.45 seconds |
| Started | Sep 09 09:50:56 AM UTC 24 |
| Finished | Sep 09 09:51:01 AM UTC 24 |
| Peak memory | 225692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760276233 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.1760276233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/3.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.693149022 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 100431323 ps |
| CPU time | 1.1 seconds |
| Started | Sep 09 09:53:11 AM UTC 24 |
| Finished | Sep 09 09:53:14 AM UTC 24 |
| Peak memory | 225856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693149022 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sparse_lc_gate_fsm.693149022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_sparse_lc_gate_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.4142790488 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 3389532008 ps |
| CPU time | 38.51 seconds |
| Started | Sep 09 09:49:58 AM UTC 24 |
| Finished | Sep 09 09:50:38 AM UTC 24 |
| Peak memory | 225700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142790488 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.4142790488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2543408937 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 91404266 ps |
| CPU time | 2.36 seconds |
| Started | Sep 09 09:49:57 AM UTC 24 |
| Finished | Sep 09 09:50:00 AM UTC 24 |
| Peak memory | 225696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543408937 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.2543408937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3453745962 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 390605261 ps |
| CPU time | 4.41 seconds |
| Started | Sep 09 09:50:01 AM UTC 24 |
| Finished | Sep 09 09:50:07 AM UTC 24 |
| Peak memory | 232308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3453745962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_r and_reset.3453745962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.1930469294 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 229381550 ps |
| CPU time | 4.15 seconds |
| Started | Sep 09 09:49:57 AM UTC 24 |
| Finished | Sep 09 09:50:02 AM UTC 24 |
| Peak memory | 225600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930469294 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.1930469294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3761925350 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 36648731916 ps |
| CPU time | 65.96 seconds |
| Started | Sep 09 09:49:46 AM UTC 24 |
| Finished | Sep 09 09:50:54 AM UTC 24 |
| Peak memory | 215552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761925350 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_aliasing.3761925350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2025952534 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 9715401426 ps |
| CPU time | 49.13 seconds |
| Started | Sep 09 09:49:44 AM UTC 24 |
| Finished | Sep 09 09:50:35 AM UTC 24 |
| Peak memory | 215288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025952534 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_bit_bash.2025952534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2351597075 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 1631737507 ps |
| CPU time | 11.52 seconds |
| Started | Sep 09 09:49:42 AM UTC 24 |
| Finished | Sep 09 09:49:54 AM UTC 24 |
| Peak memory | 215300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351597075 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_hw_reset.2351597075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3699353930 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 1030127099 ps |
| CPU time | 8.28 seconds |
| Started | Sep 09 09:49:43 AM UTC 24 |
| Finished | Sep 09 09:49:52 AM UTC 24 |
| Peak memory | 215360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699353930 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.3699353930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1123499033 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 33789603916 ps |
| CPU time | 24.54 seconds |
| Started | Sep 09 09:49:42 AM UTC 24 |
| Finished | Sep 09 09:50:08 AM UTC 24 |
| Peak memory | 215364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123499033 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_bit_bash.1123499033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2724108116 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 103598592 ps |
| CPU time | 1.4 seconds |
| Started | Sep 09 09:49:40 AM UTC 24 |
| Finished | Sep 09 09:49:43 AM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724108116 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_hw_reset.2724108116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1827437249 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 534436814 ps |
| CPU time | 4.21 seconds |
| Started | Sep 09 09:49:42 AM UTC 24 |
| Finished | Sep 09 09:49:47 AM UTC 24 |
| Peak memory | 214996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827437249 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.1827437249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1841992078 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 112639590 ps |
| CPU time | 0.87 seconds |
| Started | Sep 09 09:49:56 AM UTC 24 |
| Finished | Sep 09 09:49:57 AM UTC 24 |
| Peak memory | 215140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841992078 -assert nopostproc +UVM _TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_partial_access.1841992078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.543313974 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 82097822 ps |
| CPU time | 1.01 seconds |
| Started | Sep 09 09:49:54 AM UTC 24 |
| Finished | Sep 09 09:49:56 AM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543313974 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.543313974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3426398841 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 816052313 ps |
| CPU time | 27.03 seconds |
| Started | Sep 09 09:49:47 AM UTC 24 |
| Finished | Sep 09 09:50:16 AM UTC 24 |
| Peak memory | 227840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3426398841 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_re set.3426398841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.3075736556 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 152816507 ps |
| CPU time | 6.52 seconds |
| Started | Sep 09 09:49:48 AM UTC 24 |
| Finished | Sep 09 09:49:56 AM UTC 24 |
| Peak memory | 225792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075736556 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.3075736556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.850844890 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 8487627067 ps |
| CPU time | 14.07 seconds |
| Started | Sep 09 09:49:53 AM UTC 24 |
| Finished | Sep 09 09:50:09 AM UTC 24 |
| Peak memory | 225828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850844890 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.850844890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2496462447 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 3656860504 ps |
| CPU time | 81.08 seconds |
| Started | Sep 09 09:50:03 AM UTC 24 |
| Finished | Sep 09 09:51:26 AM UTC 24 |
| Peak memory | 225728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496462447 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_aliasing.2496462447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2169632076 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 2535211500 ps |
| CPU time | 52.04 seconds |
| Started | Sep 09 09:50:20 AM UTC 24 |
| Finished | Sep 09 09:51:13 AM UTC 24 |
| Peak memory | 225628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169632076 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.2169632076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3960310163 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 232535238 ps |
| CPU time | 2.33 seconds |
| Started | Sep 09 09:50:17 AM UTC 24 |
| Finished | Sep 09 09:50:21 AM UTC 24 |
| Peak memory | 225604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960310163 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.3960310163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.4064371581 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 194414671 ps |
| CPU time | 4.53 seconds |
| Started | Sep 09 09:50:21 AM UTC 24 |
| Finished | Sep 09 09:50:26 AM UTC 24 |
| Peak memory | 229916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=4064371581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_r and_reset.4064371581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.3325429936 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 97290827 ps |
| CPU time | 2.69 seconds |
| Started | Sep 09 09:50:20 AM UTC 24 |
| Finished | Sep 09 09:50:23 AM UTC 24 |
| Peak memory | 225724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325429936 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.3325429936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1313527822 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 88318732056 ps |
| CPU time | 291.05 seconds |
| Started | Sep 09 09:50:11 AM UTC 24 |
| Finished | Sep 09 09:55:06 AM UTC 24 |
| Peak memory | 215396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313527822 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_aliasing.1313527822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2542706570 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 7606804864 ps |
| CPU time | 11.65 seconds |
| Started | Sep 09 09:50:11 AM UTC 24 |
| Finished | Sep 09 09:50:24 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542706570 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_bit_bash.2542706570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.138957594 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 6519778840 ps |
| CPU time | 19.05 seconds |
| Started | Sep 09 09:50:10 AM UTC 24 |
| Finished | Sep 09 09:50:30 AM UTC 24 |
| Peak memory | 215396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138957594 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.138957594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2755075886 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 1322642192 ps |
| CPU time | 8.11 seconds |
| Started | Sep 09 09:50:10 AM UTC 24 |
| Finished | Sep 09 09:50:19 AM UTC 24 |
| Peak memory | 215148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755075886 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_aliasing.2755075886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3481076403 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 10394742704 ps |
| CPU time | 19.42 seconds |
| Started | Sep 09 09:50:08 AM UTC 24 |
| Finished | Sep 09 09:50:29 AM UTC 24 |
| Peak memory | 215380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481076403 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_bit_bash.3481076403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1102526234 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 207489819 ps |
| CPU time | 1.6 seconds |
| Started | Sep 09 09:50:07 AM UTC 24 |
| Finished | Sep 09 09:50:10 AM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102526234 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_hw_reset.1102526234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.133776050 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 297642665 ps |
| CPU time | 2.01 seconds |
| Started | Sep 09 09:50:07 AM UTC 24 |
| Finished | Sep 09 09:50:10 AM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133776050 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.133776050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1739523623 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 87892041 ps |
| CPU time | 1.09 seconds |
| Started | Sep 09 09:50:16 AM UTC 24 |
| Finished | Sep 09 09:50:18 AM UTC 24 |
| Peak memory | 215140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739523623 -assert nopostproc +UVM _TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_partial_access.1739523623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.1810244705 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 48298197 ps |
| CPU time | 1.09 seconds |
| Started | Sep 09 09:50:16 AM UTC 24 |
| Finished | Sep 09 09:50:18 AM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810244705 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.1810244705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.530973952 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 146843087 ps |
| CPU time | 7.16 seconds |
| Started | Sep 09 09:50:20 AM UTC 24 |
| Finished | Sep 09 09:50:28 AM UTC 24 |
| Peak memory | 215424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530973952 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_csr_outstanding.530973952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.814709886 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 4179027076 ps |
| CPU time | 26.01 seconds |
| Started | Sep 09 09:50:13 AM UTC 24 |
| Finished | Sep 09 09:50:40 AM UTC 24 |
| Peak memory | 228044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=814709886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.814709886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.863992513 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 251499783 ps |
| CPU time | 4.72 seconds |
| Started | Sep 09 09:50:14 AM UTC 24 |
| Finished | Sep 09 09:50:20 AM UTC 24 |
| Peak memory | 225728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863992513 -assert nopostproc +UVM_TESTNAME=rv_dm_base _test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.863992513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1806121406 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 95610009 ps |
| CPU time | 5.46 seconds |
| Started | Sep 09 09:52:16 AM UTC 24 |
| Finished | Sep 09 09:52:22 AM UTC 24 |
| Peak memory | 231832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1806121406 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_ rand_reset.1806121406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/10.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.1995874282 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 174755890 ps |
| CPU time | 3.33 seconds |
| Started | Sep 09 09:52:13 AM UTC 24 |
| Finished | Sep 09 09:52:18 AM UTC 24 |
| Peak memory | 225620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995874282 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.1995874282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/10.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.1273983589 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 23056950720 ps |
| CPU time | 84.91 seconds |
| Started | Sep 09 09:52:11 AM UTC 24 |
| Finished | Sep 09 09:53:38 AM UTC 24 |
| Peak memory | 215388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273983589 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_bit_bash.1273983589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/10.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.774162956 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 6436271581 ps |
| CPU time | 29.8 seconds |
| Started | Sep 09 09:52:10 AM UTC 24 |
| Finished | Sep 09 09:52:41 AM UTC 24 |
| Peak memory | 215400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774162956 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.774162956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/10.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1517058060 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 401914482 ps |
| CPU time | 1.23 seconds |
| Started | Sep 09 09:52:10 AM UTC 24 |
| Finished | Sep 09 09:52:12 AM UTC 24 |
| Peak memory | 215136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517058060 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.1517058060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/10.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3381248146 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 501920627 ps |
| CPU time | 11.8 seconds |
| Started | Sep 09 09:52:15 AM UTC 24 |
| Finished | Sep 09 09:52:27 AM UTC 24 |
| Peak memory | 215432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381248146 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_csr_outstanding.3381248146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/10.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.2225194200 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 169730255 ps |
| CPU time | 6.36 seconds |
| Started | Sep 09 09:52:13 AM UTC 24 |
| Finished | Sep 09 09:52:21 AM UTC 24 |
| Peak memory | 225772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225194200 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.2225194200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/10.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1510733896 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 1862664586 ps |
| CPU time | 11.19 seconds |
| Started | Sep 09 09:52:13 AM UTC 24 |
| Finished | Sep 09 09:52:26 AM UTC 24 |
| Peak memory | 232424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510733896 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.1510733896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/10.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2185894572 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 103744639 ps |
| CPU time | 3.92 seconds |
| Started | Sep 09 09:52:23 AM UTC 24 |
| Finished | Sep 09 09:52:28 AM UTC 24 |
| Peak memory | 229936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2185894572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_ rand_reset.2185894572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/11.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_rw.3527088611 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 75079740 ps |
| CPU time | 2.16 seconds |
| Started | Sep 09 09:52:22 AM UTC 24 |
| Finished | Sep 09 09:52:25 AM UTC 24 |
| Peak memory | 225632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527088611 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.3527088611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/11.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.3064706299 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 27628078485 ps |
| CPU time | 13.55 seconds |
| Started | Sep 09 09:52:21 AM UTC 24 |
| Finished | Sep 09 09:52:36 AM UTC 24 |
| Peak memory | 215432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064706299 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_bit_bash.3064706299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/11.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2115902936 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 7418421579 ps |
| CPU time | 5.95 seconds |
| Started | Sep 09 09:52:19 AM UTC 24 |
| Finished | Sep 09 09:52:26 AM UTC 24 |
| Peak memory | 215316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115902936 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.2115902936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/11.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3151933410 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 137087502 ps |
| CPU time | 1.36 seconds |
| Started | Sep 09 09:52:19 AM UTC 24 |
| Finished | Sep 09 09:52:21 AM UTC 24 |
| Peak memory | 215076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151933410 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.3151933410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/11.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1250563996 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 1558288241 ps |
| CPU time | 11.87 seconds |
| Started | Sep 09 09:52:23 AM UTC 24 |
| Finished | Sep 09 09:52:36 AM UTC 24 |
| Peak memory | 215504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250563996 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_csr_outstanding.1250563996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/11.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_errors.142549931 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 792294659 ps |
| CPU time | 4.38 seconds |
| Started | Sep 09 09:52:22 AM UTC 24 |
| Finished | Sep 09 09:52:27 AM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142549931 -assert nopostproc +UVM_TESTNAME=rv_dm_base _test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.142549931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/11.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.379743192 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 3725186429 ps |
| CPU time | 23.34 seconds |
| Started | Sep 09 09:52:22 AM UTC 24 |
| Finished | Sep 09 09:52:46 AM UTC 24 |
| Peak memory | 225728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379743192 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.379743192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/11.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2376264079 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 177295679 ps |
| CPU time | 4.05 seconds |
| Started | Sep 09 09:52:29 AM UTC 24 |
| Finished | Sep 09 09:52:34 AM UTC 24 |
| Peak memory | 225816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2376264079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_ rand_reset.2376264079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/12.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_rw.3789419887 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 111172528 ps |
| CPU time | 2.38 seconds |
| Started | Sep 09 09:52:29 AM UTC 24 |
| Finished | Sep 09 09:52:32 AM UTC 24 |
| Peak memory | 225588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789419887 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.3789419887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/12.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2382058553 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 9557641232 ps |
| CPU time | 14.72 seconds |
| Started | Sep 09 09:52:26 AM UTC 24 |
| Finished | Sep 09 09:52:42 AM UTC 24 |
| Peak memory | 215432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382058553 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_bit_bash.2382058553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/12.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.449402357 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 920705101 ps |
| CPU time | 2.63 seconds |
| Started | Sep 09 09:52:25 AM UTC 24 |
| Finished | Sep 09 09:52:29 AM UTC 24 |
| Peak memory | 215372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449402357 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.449402357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/12.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1296646175 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 148942963 ps |
| CPU time | 1.94 seconds |
| Started | Sep 09 09:52:24 AM UTC 24 |
| Finished | Sep 09 09:52:27 AM UTC 24 |
| Peak memory | 215136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296646175 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.1296646175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/12.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3640996098 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 561284739 ps |
| CPU time | 5.02 seconds |
| Started | Sep 09 09:52:29 AM UTC 24 |
| Finished | Sep 09 09:52:35 AM UTC 24 |
| Peak memory | 215400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640996098 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same_csr_outstanding.3640996098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/12.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_errors.944914927 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 147726404 ps |
| CPU time | 5.27 seconds |
| Started | Sep 09 09:52:26 AM UTC 24 |
| Finished | Sep 09 09:52:33 AM UTC 24 |
| Peak memory | 225720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944914927 -assert nopostproc +UVM_TESTNAME=rv_dm_base _test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.944914927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/12.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_intg_err.480183873 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 15673889167 ps |
| CPU time | 23.74 seconds |
| Started | Sep 09 09:52:26 AM UTC 24 |
| Finished | Sep 09 09:52:52 AM UTC 24 |
| Peak memory | 232628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480183873 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.480183873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/12.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2630170915 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 312390249 ps |
| CPU time | 3.64 seconds |
| Started | Sep 09 09:52:35 AM UTC 24 |
| Finished | Sep 09 09:52:40 AM UTC 24 |
| Peak memory | 232112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2630170915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_ rand_reset.2630170915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/13.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_rw.4268433093 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 654059059 ps |
| CPU time | 3.47 seconds |
| Started | Sep 09 09:52:34 AM UTC 24 |
| Finished | Sep 09 09:52:39 AM UTC 24 |
| Peak memory | 225664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268433093 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.4268433093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/13.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2788503188 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 8588375877 ps |
| CPU time | 15.5 seconds |
| Started | Sep 09 09:52:31 AM UTC 24 |
| Finished | Sep 09 09:52:49 AM UTC 24 |
| Peak memory | 215432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788503188 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_bit_bash.2788503188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/13.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3279861850 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 5852738596 ps |
| CPU time | 10.22 seconds |
| Started | Sep 09 09:52:30 AM UTC 24 |
| Finished | Sep 09 09:52:41 AM UTC 24 |
| Peak memory | 215448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279861850 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.3279861850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/13.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.408797983 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 195383360 ps |
| CPU time | 2.31 seconds |
| Started | Sep 09 09:52:30 AM UTC 24 |
| Finished | Sep 09 09:52:33 AM UTC 24 |
| Peak memory | 215076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408797983 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.408797983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/13.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.997953287 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 966112924 ps |
| CPU time | 6.46 seconds |
| Started | Sep 09 09:52:34 AM UTC 24 |
| Finished | Sep 09 09:52:42 AM UTC 24 |
| Peak memory | 215452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997953287 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_csr_outstanding.997953287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/13.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_errors.2839981685 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 655748934 ps |
| CPU time | 3.83 seconds |
| Started | Sep 09 09:52:32 AM UTC 24 |
| Finished | Sep 09 09:52:37 AM UTC 24 |
| Peak memory | 227776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839981685 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.2839981685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/13.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1001705821 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 5013340638 ps |
| CPU time | 18.86 seconds |
| Started | Sep 09 09:52:34 AM UTC 24 |
| Finished | Sep 09 09:52:54 AM UTC 24 |
| Peak memory | 225692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001705821 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.1001705821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/13.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2564170156 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 126723434 ps |
| CPU time | 2.48 seconds |
| Started | Sep 09 09:52:40 AM UTC 24 |
| Finished | Sep 09 09:52:43 AM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2564170156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_ rand_reset.2564170156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/14.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_rw.1305770410 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 389973261 ps |
| CPU time | 3.03 seconds |
| Started | Sep 09 09:52:39 AM UTC 24 |
| Finished | Sep 09 09:52:43 AM UTC 24 |
| Peak memory | 225528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305770410 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.1305770410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/14.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1855233955 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 12232479866 ps |
| CPU time | 22.89 seconds |
| Started | Sep 09 09:52:36 AM UTC 24 |
| Finished | Sep 09 09:53:01 AM UTC 24 |
| Peak memory | 215368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855233955 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_bit_bash.1855233955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/14.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1811080283 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 2162641046 ps |
| CPU time | 4.78 seconds |
| Started | Sep 09 09:52:36 AM UTC 24 |
| Finished | Sep 09 09:52:42 AM UTC 24 |
| Peak memory | 215424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811080283 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.1811080283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/14.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.313382616 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 1206969570 ps |
| CPU time | 1.99 seconds |
| Started | Sep 09 09:52:35 AM UTC 24 |
| Finished | Sep 09 09:52:38 AM UTC 24 |
| Peak memory | 215084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313382616 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.313382616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/14.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.4180487382 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 321402387 ps |
| CPU time | 6.56 seconds |
| Started | Sep 09 09:52:40 AM UTC 24 |
| Finished | Sep 09 09:52:48 AM UTC 24 |
| Peak memory | 215620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180487382 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same_csr_outstanding.4180487382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/14.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_errors.3961912871 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 81646946 ps |
| CPU time | 5.1 seconds |
| Started | Sep 09 09:52:37 AM UTC 24 |
| Finished | Sep 09 09:52:43 AM UTC 24 |
| Peak memory | 225696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961912871 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.3961912871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/14.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3498014960 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 1571138532 ps |
| CPU time | 10.57 seconds |
| Started | Sep 09 09:52:38 AM UTC 24 |
| Finished | Sep 09 09:52:50 AM UTC 24 |
| Peak memory | 225728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498014960 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.3498014960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/14.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.519446126 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 82149595 ps |
| CPU time | 2.7 seconds |
| Started | Sep 09 09:52:43 AM UTC 24 |
| Finished | Sep 09 09:52:47 AM UTC 24 |
| Peak memory | 227980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=519446126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_r and_reset.519446126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/15.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_rw.4002839868 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 189308741 ps |
| CPU time | 2.87 seconds |
| Started | Sep 09 09:52:43 AM UTC 24 |
| Finished | Sep 09 09:52:47 AM UTC 24 |
| Peak memory | 225724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002839868 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.4002839868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/15.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3896267603 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 23991713453 ps |
| CPU time | 23.83 seconds |
| Started | Sep 09 09:52:42 AM UTC 24 |
| Finished | Sep 09 09:53:07 AM UTC 24 |
| Peak memory | 215292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896267603 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_bit_bash.3896267603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/15.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1006938348 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 1380347807 ps |
| CPU time | 5.3 seconds |
| Started | Sep 09 09:52:41 AM UTC 24 |
| Finished | Sep 09 09:52:48 AM UTC 24 |
| Peak memory | 215224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006938348 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.1006938348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/15.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2073118934 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 169329566 ps |
| CPU time | 1.05 seconds |
| Started | Sep 09 09:52:41 AM UTC 24 |
| Finished | Sep 09 09:52:43 AM UTC 24 |
| Peak memory | 215076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073118934 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.2073118934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/15.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2223186546 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 262186970 ps |
| CPU time | 5.83 seconds |
| Started | Sep 09 09:52:43 AM UTC 24 |
| Finished | Sep 09 09:52:50 AM UTC 24 |
| Peak memory | 215436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223186546 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_csr_outstanding.2223186546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/15.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_errors.468169214 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 1138503841 ps |
| CPU time | 7.99 seconds |
| Started | Sep 09 09:52:42 AM UTC 24 |
| Finished | Sep 09 09:52:51 AM UTC 24 |
| Peak memory | 225700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468169214 -assert nopostproc +UVM_TESTNAME=rv_dm_base _test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.468169214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/15.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_intg_err.4263691788 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 958940054 ps |
| CPU time | 16.56 seconds |
| Started | Sep 09 09:52:42 AM UTC 24 |
| Finished | Sep 09 09:53:00 AM UTC 24 |
| Peak memory | 227712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263691788 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.4263691788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/15.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3948296194 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 89257119 ps |
| CPU time | 3.19 seconds |
| Started | Sep 09 09:52:49 AM UTC 24 |
| Finished | Sep 09 09:52:53 AM UTC 24 |
| Peak memory | 225900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3948296194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_ rand_reset.3948296194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/16.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_rw.298906368 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 300778111 ps |
| CPU time | 2.32 seconds |
| Started | Sep 09 09:52:48 AM UTC 24 |
| Finished | Sep 09 09:52:51 AM UTC 24 |
| Peak memory | 225620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298906368 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.298906368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/16.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.3494490824 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 22805908735 ps |
| CPU time | 37.95 seconds |
| Started | Sep 09 09:52:44 AM UTC 24 |
| Finished | Sep 09 09:53:24 AM UTC 24 |
| Peak memory | 215460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494490824 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_bit_bash.3494490824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/16.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3216231059 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 5355920793 ps |
| CPU time | 17.15 seconds |
| Started | Sep 09 09:52:44 AM UTC 24 |
| Finished | Sep 09 09:53:03 AM UTC 24 |
| Peak memory | 215356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216231059 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.3216231059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/16.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2617547859 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 171801018 ps |
| CPU time | 1.71 seconds |
| Started | Sep 09 09:52:43 AM UTC 24 |
| Finished | Sep 09 09:52:46 AM UTC 24 |
| Peak memory | 215076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617547859 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.2617547859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/16.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3485806958 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 1218026667 ps |
| CPU time | 8.86 seconds |
| Started | Sep 09 09:52:48 AM UTC 24 |
| Finished | Sep 09 09:52:58 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485806958 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_csr_outstanding.3485806958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/16.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_errors.415672171 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 448950007 ps |
| CPU time | 6.62 seconds |
| Started | Sep 09 09:52:45 AM UTC 24 |
| Finished | Sep 09 09:52:52 AM UTC 24 |
| Peak memory | 225796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415672171 -assert nopostproc +UVM_TESTNAME=rv_dm_base _test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.415672171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/16.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3986862996 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 1648811997 ps |
| CPU time | 12.34 seconds |
| Started | Sep 09 09:52:48 AM UTC 24 |
| Finished | Sep 09 09:53:01 AM UTC 24 |
| Peak memory | 232396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986862996 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.3986862996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/16.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3411900332 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 181941943 ps |
| CPU time | 2.97 seconds |
| Started | Sep 09 09:52:52 AM UTC 24 |
| Finished | Sep 09 09:52:56 AM UTC 24 |
| Peak memory | 225808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3411900332 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_ rand_reset.3411900332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/17.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_rw.3788884507 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 93441283 ps |
| CPU time | 2.4 seconds |
| Started | Sep 09 09:52:51 AM UTC 24 |
| Finished | Sep 09 09:52:55 AM UTC 24 |
| Peak memory | 225724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788884507 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.3788884507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/17.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.145335546 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 88517060047 ps |
| CPU time | 124.46 seconds |
| Started | Sep 09 09:52:50 AM UTC 24 |
| Finished | Sep 09 09:54:57 AM UTC 24 |
| Peak memory | 215424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145335546 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_bit_bash.145335546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/17.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3117485276 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 6249310795 ps |
| CPU time | 8.18 seconds |
| Started | Sep 09 09:52:49 AM UTC 24 |
| Finished | Sep 09 09:52:58 AM UTC 24 |
| Peak memory | 215356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117485276 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.3117485276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/17.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1938187156 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 292135984 ps |
| CPU time | 1.27 seconds |
| Started | Sep 09 09:52:49 AM UTC 24 |
| Finished | Sep 09 09:52:51 AM UTC 24 |
| Peak memory | 215136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938187156 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.1938187156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/17.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.539864532 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 1671609356 ps |
| CPU time | 9.35 seconds |
| Started | Sep 09 09:52:52 AM UTC 24 |
| Finished | Sep 09 09:53:03 AM UTC 24 |
| Peak memory | 215492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539864532 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same_csr_outstanding.539864532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/17.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_errors.2674101516 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 140975136 ps |
| CPU time | 2.89 seconds |
| Started | Sep 09 09:52:50 AM UTC 24 |
| Finished | Sep 09 09:52:54 AM UTC 24 |
| Peak memory | 225700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674101516 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.2674101516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/17.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.1923132087 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 1955792483 ps |
| CPU time | 28.97 seconds |
| Started | Sep 09 09:52:50 AM UTC 24 |
| Finished | Sep 09 09:53:20 AM UTC 24 |
| Peak memory | 232496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923132087 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.1923132087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/17.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.557634107 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 170635890 ps |
| CPU time | 2.37 seconds |
| Started | Sep 09 09:52:57 AM UTC 24 |
| Finished | Sep 09 09:53:00 AM UTC 24 |
| Peak memory | 227952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=557634107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_r and_reset.557634107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/18.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_rw.1968341255 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 230134616 ps |
| CPU time | 3.02 seconds |
| Started | Sep 09 09:52:55 AM UTC 24 |
| Finished | Sep 09 09:52:59 AM UTC 24 |
| Peak memory | 231728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968341255 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.1968341255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/18.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.244931840 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 33836126409 ps |
| CPU time | 22.05 seconds |
| Started | Sep 09 09:52:54 AM UTC 24 |
| Finished | Sep 09 09:53:17 AM UTC 24 |
| Peak memory | 215452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244931840 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_bit_bash.244931840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/18.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.139421311 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 3147917895 ps |
| CPU time | 6.87 seconds |
| Started | Sep 09 09:52:52 AM UTC 24 |
| Finished | Sep 09 09:53:00 AM UTC 24 |
| Peak memory | 215460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139421311 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.139421311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/18.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2989742162 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 934477617 ps |
| CPU time | 3.49 seconds |
| Started | Sep 09 09:52:52 AM UTC 24 |
| Finished | Sep 09 09:52:57 AM UTC 24 |
| Peak memory | 215136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989742162 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.2989742162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/18.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1648182418 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 110226353 ps |
| CPU time | 4.92 seconds |
| Started | Sep 09 09:52:56 AM UTC 24 |
| Finished | Sep 09 09:53:02 AM UTC 24 |
| Peak memory | 215360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648182418 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same_csr_outstanding.1648182418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/18.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_errors.940783464 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 153895521 ps |
| CPU time | 3.76 seconds |
| Started | Sep 09 09:52:54 AM UTC 24 |
| Finished | Sep 09 09:52:58 AM UTC 24 |
| Peak memory | 225800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940783464 -assert nopostproc +UVM_TESTNAME=rv_dm_base _test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.940783464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/18.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2293995794 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 229760449 ps |
| CPU time | 2.07 seconds |
| Started | Sep 09 09:53:02 AM UTC 24 |
| Finished | Sep 09 09:53:05 AM UTC 24 |
| Peak memory | 227828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2293995794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_ rand_reset.2293995794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/19.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_rw.1201527410 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 185353862 ps |
| CPU time | 1.73 seconds |
| Started | Sep 09 09:52:59 AM UTC 24 |
| Finished | Sep 09 09:53:02 AM UTC 24 |
| Peak memory | 225224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201527410 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.1201527410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/19.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.4238413047 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 26440510126 ps |
| CPU time | 86.43 seconds |
| Started | Sep 09 09:52:58 AM UTC 24 |
| Finished | Sep 09 09:54:27 AM UTC 24 |
| Peak memory | 214928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238413047 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_bit_bash.4238413047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/19.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.506320387 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 2247785412 ps |
| CPU time | 9.09 seconds |
| Started | Sep 09 09:52:58 AM UTC 24 |
| Finished | Sep 09 09:53:09 AM UTC 24 |
| Peak memory | 215432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506320387 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.506320387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/19.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3693997757 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 373117610 ps |
| CPU time | 1.79 seconds |
| Started | Sep 09 09:52:58 AM UTC 24 |
| Finished | Sep 09 09:53:02 AM UTC 24 |
| Peak memory | 214588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693997757 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.3693997757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/19.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1646702883 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 1076002480 ps |
| CPU time | 9.25 seconds |
| Started | Sep 09 09:53:01 AM UTC 24 |
| Finished | Sep 09 09:53:11 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646702883 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_csr_outstanding.1646702883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/19.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_errors.3439182566 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 247635204 ps |
| CPU time | 5.48 seconds |
| Started | Sep 09 09:52:59 AM UTC 24 |
| Finished | Sep 09 09:53:06 AM UTC 24 |
| Peak memory | 225532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439182566 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.3439182566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/19.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2904697681 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 6503509800 ps |
| CPU time | 22.69 seconds |
| Started | Sep 09 09:52:59 AM UTC 24 |
| Finished | Sep 09 09:53:23 AM UTC 24 |
| Peak memory | 225712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904697681 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.2904697681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/19.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2715393774 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 1226309484 ps |
| CPU time | 77 seconds |
| Started | Sep 09 09:50:22 AM UTC 24 |
| Finished | Sep 09 09:51:41 AM UTC 24 |
| Peak memory | 225728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715393774 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_aliasing.2715393774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/2.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.682361366 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 6205004734 ps |
| CPU time | 45.55 seconds |
| Started | Sep 09 09:50:38 AM UTC 24 |
| Finished | Sep 09 09:51:25 AM UTC 24 |
| Peak memory | 215392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682361366 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.682361366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/2.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.429682805 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 433942516 ps |
| CPU time | 2.38 seconds |
| Started | Sep 09 09:50:38 AM UTC 24 |
| Finished | Sep 09 09:50:41 AM UTC 24 |
| Peak memory | 225276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429682805 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.429682805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/2.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3184373863 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 59150359 ps |
| CPU time | 6.11 seconds |
| Started | Sep 09 09:50:39 AM UTC 24 |
| Finished | Sep 09 09:50:46 AM UTC 24 |
| Peak memory | 232224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3184373863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_r and_reset.3184373863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/2.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_rw.713573382 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 59675585 ps |
| CPU time | 3.02 seconds |
| Started | Sep 09 09:50:38 AM UTC 24 |
| Finished | Sep 09 09:50:42 AM UTC 24 |
| Peak memory | 229560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713573382 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.713573382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/2.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2934408604 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 85667286386 ps |
| CPU time | 45.76 seconds |
| Started | Sep 09 09:50:31 AM UTC 24 |
| Finished | Sep 09 09:51:19 AM UTC 24 |
| Peak memory | 215364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934408604 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_aliasing.2934408604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2045357758 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 57066023 ps |
| CPU time | 1.31 seconds |
| Started | Sep 09 09:50:31 AM UTC 24 |
| Finished | Sep 09 09:50:34 AM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045357758 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_bit_bash.2045357758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.101398777 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 14498731195 ps |
| CPU time | 30.22 seconds |
| Started | Sep 09 09:50:29 AM UTC 24 |
| Finished | Sep 09 09:51:01 AM UTC 24 |
| Peak memory | 215424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101398777 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_hw_reset.101398777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.942203169 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 9038004830 ps |
| CPU time | 15.23 seconds |
| Started | Sep 09 09:50:30 AM UTC 24 |
| Finished | Sep 09 09:50:47 AM UTC 24 |
| Peak memory | 215292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942203169 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.942203169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3665710359 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 1322268866 ps |
| CPU time | 2.69 seconds |
| Started | Sep 09 09:50:28 AM UTC 24 |
| Finished | Sep 09 09:50:32 AM UTC 24 |
| Peak memory | 215216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665710359 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_aliasing.3665710359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3237237150 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 12076094308 ps |
| CPU time | 12.41 seconds |
| Started | Sep 09 09:50:27 AM UTC 24 |
| Finished | Sep 09 09:50:41 AM UTC 24 |
| Peak memory | 215396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237237150 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_bit_bash.3237237150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.4027216602 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 719382769 ps |
| CPU time | 5.2 seconds |
| Started | Sep 09 09:50:24 AM UTC 24 |
| Finished | Sep 09 09:50:30 AM UTC 24 |
| Peak memory | 215148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027216602 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_hw_reset.4027216602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.4047156489 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 397347456 ps |
| CPU time | 2.65 seconds |
| Started | Sep 09 09:50:24 AM UTC 24 |
| Finished | Sep 09 09:50:28 AM UTC 24 |
| Peak memory | 215068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047156489 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.4047156489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1619412503 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 50355525 ps |
| CPU time | 1.27 seconds |
| Started | Sep 09 09:50:36 AM UTC 24 |
| Finished | Sep 09 09:50:38 AM UTC 24 |
| Peak memory | 215140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619412503 -assert nopostproc +UVM _TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_partial_access.1619412503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/2.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_walk.2243482158 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 39727297 ps |
| CPU time | 1.11 seconds |
| Started | Sep 09 09:50:35 AM UTC 24 |
| Finished | Sep 09 09:50:37 AM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243482158 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.2243482158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/2.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2791031018 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 177938741 ps |
| CPU time | 6.83 seconds |
| Started | Sep 09 09:50:38 AM UTC 24 |
| Finished | Sep 09 09:50:46 AM UTC 24 |
| Peak memory | 215488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791031018 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_csr_outstanding.2791031018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/2.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.4006807656 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 4569491232 ps |
| CPU time | 66.18 seconds |
| Started | Sep 09 09:50:33 AM UTC 24 |
| Finished | Sep 09 09:51:40 AM UTC 24 |
| Peak memory | 230048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=4006807656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_re set.4006807656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/2.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_errors.1456722819 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 79272305 ps |
| CPU time | 4.18 seconds |
| Started | Sep 09 09:50:33 AM UTC 24 |
| Finished | Sep 09 09:50:38 AM UTC 24 |
| Peak memory | 225668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456722819 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.1456722819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/2.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1186911853 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 4643096189 ps |
| CPU time | 70.74 seconds |
| Started | Sep 09 09:50:39 AM UTC 24 |
| Finished | Sep 09 09:51:52 AM UTC 24 |
| Peak memory | 225668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186911853 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_aliasing.1186911853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/3.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2969307773 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 1502320827 ps |
| CPU time | 73.45 seconds |
| Started | Sep 09 09:50:57 AM UTC 24 |
| Finished | Sep 09 09:52:13 AM UTC 24 |
| Peak memory | 215340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969307773 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.2969307773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/3.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2597005732 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 653651615 ps |
| CPU time | 4.02 seconds |
| Started | Sep 09 09:50:55 AM UTC 24 |
| Finished | Sep 09 09:51:00 AM UTC 24 |
| Peak memory | 225604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597005732 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.2597005732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/3.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2108966648 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 164579423 ps |
| CPU time | 5.66 seconds |
| Started | Sep 09 09:50:59 AM UTC 24 |
| Finished | Sep 09 09:51:05 AM UTC 24 |
| Peak memory | 229896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2108966648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_r and_reset.2108966648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/3.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1783689918 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 113750124662 ps |
| CPU time | 134.64 seconds |
| Started | Sep 09 09:50:47 AM UTC 24 |
| Finished | Sep 09 09:53:04 AM UTC 24 |
| Peak memory | 215620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783689918 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_aliasing.1783689918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.544936432 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 5373598817 ps |
| CPU time | 8.83 seconds |
| Started | Sep 09 09:50:47 AM UTC 24 |
| Finished | Sep 09 09:50:57 AM UTC 24 |
| Peak memory | 215452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544936432 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_bit_bash.544936432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.4005642152 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 1156747168 ps |
| CPU time | 3.46 seconds |
| Started | Sep 09 09:50:45 AM UTC 24 |
| Finished | Sep 09 09:50:49 AM UTC 24 |
| Peak memory | 215400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005642152 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_hw_reset.4005642152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.392346794 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 7669632329 ps |
| CPU time | 36.54 seconds |
| Started | Sep 09 09:50:46 AM UTC 24 |
| Finished | Sep 09 09:51:24 AM UTC 24 |
| Peak memory | 215292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392346794 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.392346794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1608852805 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 1937157494 ps |
| CPU time | 2.27 seconds |
| Started | Sep 09 09:50:42 AM UTC 24 |
| Finished | Sep 09 09:50:46 AM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608852805 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_aliasing.1608852805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2032905525 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 4785572246 ps |
| CPU time | 19.88 seconds |
| Started | Sep 09 09:50:42 AM UTC 24 |
| Finished | Sep 09 09:51:03 AM UTC 24 |
| Peak memory | 215236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032905525 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_bit_bash.2032905525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1609815437 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 206516778 ps |
| CPU time | 1.57 seconds |
| Started | Sep 09 09:50:41 AM UTC 24 |
| Finished | Sep 09 09:50:44 AM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609815437 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_hw_reset.1609815437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3130293697 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 334575471 ps |
| CPU time | 2.08 seconds |
| Started | Sep 09 09:50:41 AM UTC 24 |
| Finished | Sep 09 09:50:44 AM UTC 24 |
| Peak memory | 215272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130293697 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.3130293697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_partial_access.424338547 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 100527422 ps |
| CPU time | 1.54 seconds |
| Started | Sep 09 09:50:54 AM UTC 24 |
| Finished | Sep 09 09:50:57 AM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424338547 -assert nopostproc +UVM_ TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_partial_access.424338547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/3.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_walk.385210556 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 139875337 ps |
| CPU time | 1.1 seconds |
| Started | Sep 09 09:50:51 AM UTC 24 |
| Finished | Sep 09 09:50:53 AM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385210556 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.385210556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/3.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1824445758 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 1188720411 ps |
| CPU time | 9.78 seconds |
| Started | Sep 09 09:50:57 AM UTC 24 |
| Finished | Sep 09 09:51:09 AM UTC 24 |
| Peak memory | 215552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824445758 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_csr_outstanding.1824445758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/3.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3406566974 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 3027975058 ps |
| CPU time | 60.44 seconds |
| Started | Sep 09 09:50:48 AM UTC 24 |
| Finished | Sep 09 09:51:50 AM UTC 24 |
| Peak memory | 232520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3406566974 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_re set.3406566974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/3.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_errors.2945397421 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 385588178 ps |
| CPU time | 8.44 seconds |
| Started | Sep 09 09:50:48 AM UTC 24 |
| Finished | Sep 09 09:50:57 AM UTC 24 |
| Peak memory | 225824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945397421 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.2945397421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/3.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1737102844 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 5022154520 ps |
| CPU time | 15.4 seconds |
| Started | Sep 09 09:50:50 AM UTC 24 |
| Finished | Sep 09 09:51:07 AM UTC 24 |
| Peak memory | 225800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737102844 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.1737102844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/3.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1047259592 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 958148865 ps |
| CPU time | 37.52 seconds |
| Started | Sep 09 09:51:02 AM UTC 24 |
| Finished | Sep 09 09:51:41 AM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047259592 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_aliasing.1047259592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/4.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3043366251 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 2401060634 ps |
| CPU time | 64.03 seconds |
| Started | Sep 09 09:51:19 AM UTC 24 |
| Finished | Sep 09 09:52:25 AM UTC 24 |
| Peak memory | 215404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043366251 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.3043366251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/4.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3539820459 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 348636375 ps |
| CPU time | 2.58 seconds |
| Started | Sep 09 09:51:16 AM UTC 24 |
| Finished | Sep 09 09:51:19 AM UTC 24 |
| Peak memory | 225668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539820459 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.3539820459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/4.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2022932232 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 263357205 ps |
| CPU time | 4.54 seconds |
| Started | Sep 09 09:51:21 AM UTC 24 |
| Finished | Sep 09 09:51:26 AM UTC 24 |
| Peak memory | 232352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2022932232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_r and_reset.2022932232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/4.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_rw.3599483508 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 772249900 ps |
| CPU time | 3.66 seconds |
| Started | Sep 09 09:51:18 AM UTC 24 |
| Finished | Sep 09 09:51:23 AM UTC 24 |
| Peak memory | 231764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599483508 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.3599483508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/4.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2737581757 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 54949591053 ps |
| CPU time | 69.49 seconds |
| Started | Sep 09 09:51:09 AM UTC 24 |
| Finished | Sep 09 09:52:20 AM UTC 24 |
| Peak memory | 215488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737581757 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_aliasing.2737581757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.1038237244 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 18497064915 ps |
| CPU time | 85.33 seconds |
| Started | Sep 09 09:51:07 AM UTC 24 |
| Finished | Sep 09 09:52:35 AM UTC 24 |
| Peak memory | 215360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038237244 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_bit_bash.1038237244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.394193359 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 2287297081 ps |
| CPU time | 2.9 seconds |
| Started | Sep 09 09:51:06 AM UTC 24 |
| Finished | Sep 09 09:51:10 AM UTC 24 |
| Peak memory | 215524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394193359 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_hw_reset.394193359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.302725953 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 1764098174 ps |
| CPU time | 5.19 seconds |
| Started | Sep 09 09:51:06 AM UTC 24 |
| Finished | Sep 09 09:51:12 AM UTC 24 |
| Peak memory | 215300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302725953 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.302725953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2365260426 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 1365971035 ps |
| CPU time | 7.45 seconds |
| Started | Sep 09 09:51:05 AM UTC 24 |
| Finished | Sep 09 09:51:13 AM UTC 24 |
| Peak memory | 215072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365260426 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_aliasing.2365260426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1213927223 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 2988272839 ps |
| CPU time | 6.31 seconds |
| Started | Sep 09 09:51:04 AM UTC 24 |
| Finished | Sep 09 09:51:11 AM UTC 24 |
| Peak memory | 215324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213927223 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_bit_bash.1213927223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2587505705 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 401281898 ps |
| CPU time | 1.93 seconds |
| Started | Sep 09 09:51:02 AM UTC 24 |
| Finished | Sep 09 09:51:05 AM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587505705 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_hw_reset.2587505705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2114398636 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 86181787 ps |
| CPU time | 1.45 seconds |
| Started | Sep 09 09:51:02 AM UTC 24 |
| Finished | Sep 09 09:51:04 AM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114398636 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.2114398636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3249284870 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 144487118 ps |
| CPU time | 1.13 seconds |
| Started | Sep 09 09:51:14 AM UTC 24 |
| Finished | Sep 09 09:51:17 AM UTC 24 |
| Peak memory | 215140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249284870 -assert nopostproc +UVM _TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_partial_access.3249284870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/4.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_walk.2533932605 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 120964362 ps |
| CPU time | 1.74 seconds |
| Started | Sep 09 09:51:14 AM UTC 24 |
| Finished | Sep 09 09:51:18 AM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533932605 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.2533932605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/4.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1208449533 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 331199501 ps |
| CPU time | 9.64 seconds |
| Started | Sep 09 09:51:20 AM UTC 24 |
| Finished | Sep 09 09:51:31 AM UTC 24 |
| Peak memory | 215504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208449533 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_csr_outstanding.1208449533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/4.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_errors.2355124876 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 665828179 ps |
| CPU time | 10.66 seconds |
| Started | Sep 09 09:51:12 AM UTC 24 |
| Finished | Sep 09 09:51:24 AM UTC 24 |
| Peak memory | 225800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355124876 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2355124876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/4.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1778020903 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 1931560587 ps |
| CPU time | 14.17 seconds |
| Started | Sep 09 09:51:13 AM UTC 24 |
| Finished | Sep 09 09:51:29 AM UTC 24 |
| Peak memory | 227748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778020903 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.1778020903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/4.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1810325778 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 69628521 ps |
| CPU time | 5.13 seconds |
| Started | Sep 09 09:51:30 AM UTC 24 |
| Finished | Sep 09 09:51:36 AM UTC 24 |
| Peak memory | 232024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1810325778 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_r and_reset.1810325778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/5.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_rw.2931898152 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 94091905 ps |
| CPU time | 2.02 seconds |
| Started | Sep 09 09:51:27 AM UTC 24 |
| Finished | Sep 09 09:51:30 AM UTC 24 |
| Peak memory | 225728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931898152 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.2931898152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/5.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.4285174531 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 5256696689 ps |
| CPU time | 25.23 seconds |
| Started | Sep 09 09:51:24 AM UTC 24 |
| Finished | Sep 09 09:51:51 AM UTC 24 |
| Peak memory | 215288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285174531 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_bit_bash.4285174531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/5.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.512339768 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 3247946064 ps |
| CPU time | 14.74 seconds |
| Started | Sep 09 09:51:23 AM UTC 24 |
| Finished | Sep 09 09:51:39 AM UTC 24 |
| Peak memory | 215428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512339768 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.512339768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/5.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.789361396 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 203563100 ps |
| CPU time | 1.67 seconds |
| Started | Sep 09 09:51:22 AM UTC 24 |
| Finished | Sep 09 09:51:25 AM UTC 24 |
| Peak memory | 215084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789361396 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.789361396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/5.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.260940779 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 210902838 ps |
| CPU time | 9.37 seconds |
| Started | Sep 09 09:51:27 AM UTC 24 |
| Finished | Sep 09 09:51:38 AM UTC 24 |
| Peak memory | 215368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260940779 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_csr_outstanding.260940779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/5.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.3957783079 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 2151779220 ps |
| CPU time | 44.75 seconds |
| Started | Sep 09 09:51:25 AM UTC 24 |
| Finished | Sep 09 09:52:12 AM UTC 24 |
| Peak memory | 227976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3957783079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_re set.3957783079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/5.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_errors.684382265 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 140974546 ps |
| CPU time | 5.05 seconds |
| Started | Sep 09 09:51:25 AM UTC 24 |
| Finished | Sep 09 09:51:32 AM UTC 24 |
| Peak memory | 225824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684382265 -assert nopostproc +UVM_TESTNAME=rv_dm_base _test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.684382265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/5.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1497006405 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 72695233 ps |
| CPU time | 3.33 seconds |
| Started | Sep 09 09:51:41 AM UTC 24 |
| Finished | Sep 09 09:51:45 AM UTC 24 |
| Peak memory | 225736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1497006405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_r and_reset.1497006405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/6.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_rw.867044536 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 59172859 ps |
| CPU time | 2.21 seconds |
| Started | Sep 09 09:51:40 AM UTC 24 |
| Finished | Sep 09 09:51:43 AM UTC 24 |
| Peak memory | 229824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867044536 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.867044536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/6.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3467997967 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 7332688118 ps |
| CPU time | 11.63 seconds |
| Started | Sep 09 09:51:33 AM UTC 24 |
| Finished | Sep 09 09:51:46 AM UTC 24 |
| Peak memory | 215452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467997967 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_bit_bash.3467997967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/6.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1269521076 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 5898863487 ps |
| CPU time | 12.57 seconds |
| Started | Sep 09 09:51:32 AM UTC 24 |
| Finished | Sep 09 09:51:45 AM UTC 24 |
| Peak memory | 215404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269521076 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.1269521076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/6.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.568964589 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 305194935 ps |
| CPU time | 2.56 seconds |
| Started | Sep 09 09:51:32 AM UTC 24 |
| Finished | Sep 09 09:51:35 AM UTC 24 |
| Peak memory | 215200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568964589 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.568964589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/6.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.789940918 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 887565281 ps |
| CPU time | 9.14 seconds |
| Started | Sep 09 09:51:41 AM UTC 24 |
| Finished | Sep 09 09:51:51 AM UTC 24 |
| Peak memory | 215488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789940918 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_csr_outstanding.789940918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/6.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.1951052187 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 29003847261 ps |
| CPU time | 87.24 seconds |
| Started | Sep 09 09:51:36 AM UTC 24 |
| Finished | Sep 09 09:53:05 AM UTC 24 |
| Peak memory | 229888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1951052187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_re set.1951052187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/6.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_errors.1397252270 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 108187197 ps |
| CPU time | 4.17 seconds |
| Started | Sep 09 09:51:37 AM UTC 24 |
| Finished | Sep 09 09:51:42 AM UTC 24 |
| Peak memory | 225824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397252270 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.1397252270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/6.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3181504461 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 2712628247 ps |
| CPU time | 12.57 seconds |
| Started | Sep 09 09:51:39 AM UTC 24 |
| Finished | Sep 09 09:51:53 AM UTC 24 |
| Peak memory | 232488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181504461 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.3181504461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/6.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1681725825 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 300990980 ps |
| CPU time | 4.69 seconds |
| Started | Sep 09 09:51:51 AM UTC 24 |
| Finished | Sep 09 09:51:57 AM UTC 24 |
| Peak memory | 229944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1681725825 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_r and_reset.1681725825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/7.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_rw.3389773379 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 253678438 ps |
| CPU time | 2.15 seconds |
| Started | Sep 09 09:51:47 AM UTC 24 |
| Finished | Sep 09 09:51:50 AM UTC 24 |
| Peak memory | 225640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389773379 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.3389773379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/7.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.968273506 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 12690415407 ps |
| CPU time | 55.28 seconds |
| Started | Sep 09 09:51:44 AM UTC 24 |
| Finished | Sep 09 09:52:42 AM UTC 24 |
| Peak memory | 215384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968273506 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_bit_bash.968273506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/7.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3275272818 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 918985316 ps |
| CPU time | 7.04 seconds |
| Started | Sep 09 09:51:43 AM UTC 24 |
| Finished | Sep 09 09:51:52 AM UTC 24 |
| Peak memory | 215300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275272818 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.3275272818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/7.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.69229523 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 225601165 ps |
| CPU time | 1.72 seconds |
| Started | Sep 09 09:51:41 AM UTC 24 |
| Finished | Sep 09 09:51:44 AM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69229523 -assert nopostproc +UVM_TESTNAME=rv_dm_ba se_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.69229523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/7.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.4237705802 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 4557321768 ps |
| CPU time | 14.48 seconds |
| Started | Sep 09 09:51:47 AM UTC 24 |
| Finished | Sep 09 09:52:02 AM UTC 24 |
| Peak memory | 215648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237705802 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_csr_outstanding.4237705802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/7.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.729488518 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 18293558484 ps |
| CPU time | 43.57 seconds |
| Started | Sep 09 09:51:45 AM UTC 24 |
| Finished | Sep 09 09:52:30 AM UTC 24 |
| Peak memory | 227936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=729488518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.729488518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/7.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_errors.3381953470 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 870970663 ps |
| CPU time | 7.02 seconds |
| Started | Sep 09 09:51:45 AM UTC 24 |
| Finished | Sep 09 09:51:53 AM UTC 24 |
| Peak memory | 225888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381953470 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.3381953470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/7.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1524833878 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 3763435777 ps |
| CPU time | 17.75 seconds |
| Started | Sep 09 09:51:47 AM UTC 24 |
| Finished | Sep 09 09:52:06 AM UTC 24 |
| Peak memory | 227840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524833878 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.1524833878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/7.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3604337010 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 95558604 ps |
| CPU time | 3.04 seconds |
| Started | Sep 09 09:51:56 AM UTC 24 |
| Finished | Sep 09 09:52:01 AM UTC 24 |
| Peak memory | 227924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3604337010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_r and_reset.3604337010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/8.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_rw.578222137 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 265879774 ps |
| CPU time | 2.09 seconds |
| Started | Sep 09 09:51:53 AM UTC 24 |
| Finished | Sep 09 09:51:56 AM UTC 24 |
| Peak memory | 229732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578222137 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.578222137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/8.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.4091989698 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 5165462838 ps |
| CPU time | 24.68 seconds |
| Started | Sep 09 09:51:52 AM UTC 24 |
| Finished | Sep 09 09:52:18 AM UTC 24 |
| Peak memory | 215580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091989698 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_bit_bash.4091989698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/8.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1567439694 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 11779419941 ps |
| CPU time | 28.69 seconds |
| Started | Sep 09 09:51:52 AM UTC 24 |
| Finished | Sep 09 09:52:22 AM UTC 24 |
| Peak memory | 215356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567439694 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.1567439694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/8.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2250581929 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 316679713 ps |
| CPU time | 1.81 seconds |
| Started | Sep 09 09:51:51 AM UTC 24 |
| Finished | Sep 09 09:51:54 AM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250581929 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.2250581929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/8.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2947396198 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 177817136 ps |
| CPU time | 9.59 seconds |
| Started | Sep 09 09:51:54 AM UTC 24 |
| Finished | Sep 09 09:52:05 AM UTC 24 |
| Peak memory | 215428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947396198 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_csr_outstanding.2947396198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/8.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1383135216 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 36457305695 ps |
| CPU time | 55.42 seconds |
| Started | Sep 09 09:51:52 AM UTC 24 |
| Finished | Sep 09 09:52:49 AM UTC 24 |
| Peak memory | 229960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1383135216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_re set.1383135216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/8.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_errors.323442822 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 701259054 ps |
| CPU time | 5.27 seconds |
| Started | Sep 09 09:51:53 AM UTC 24 |
| Finished | Sep 09 09:52:00 AM UTC 24 |
| Peak memory | 225800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323442822 -assert nopostproc +UVM_TESTNAME=rv_dm_base _test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.323442822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/8.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3919295296 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 2038379734 ps |
| CPU time | 14.93 seconds |
| Started | Sep 09 09:51:53 AM UTC 24 |
| Finished | Sep 09 09:52:09 AM UTC 24 |
| Peak memory | 232412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919295296 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.3919295296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/8.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2331913950 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 218142538 ps |
| CPU time | 3.22 seconds |
| Started | Sep 09 09:52:08 AM UTC 24 |
| Finished | Sep 09 09:52:12 AM UTC 24 |
| Peak memory | 227868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2331913950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_r and_reset.2331913950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/9.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_rw.3445253277 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 105933845 ps |
| CPU time | 2.36 seconds |
| Started | Sep 09 09:52:06 AM UTC 24 |
| Finished | Sep 09 09:52:09 AM UTC 24 |
| Peak memory | 225608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445253277 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.3445253277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/9.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.389476414 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 11496047346 ps |
| CPU time | 18.84 seconds |
| Started | Sep 09 09:52:01 AM UTC 24 |
| Finished | Sep 09 09:52:21 AM UTC 24 |
| Peak memory | 215188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389476414 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_bit_bash.389476414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/9.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3380921581 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 1492849722 ps |
| CPU time | 8.25 seconds |
| Started | Sep 09 09:51:58 AM UTC 24 |
| Finished | Sep 09 09:52:07 AM UTC 24 |
| Peak memory | 215388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380921581 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.3380921581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/9.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3096065347 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 132658958 ps |
| CPU time | 1.09 seconds |
| Started | Sep 09 09:51:58 AM UTC 24 |
| Finished | Sep 09 09:52:00 AM UTC 24 |
| Peak memory | 215136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096065347 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.3096065347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/9.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3467228015 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 286465198 ps |
| CPU time | 6.59 seconds |
| Started | Sep 09 09:52:07 AM UTC 24 |
| Finished | Sep 09 09:52:15 AM UTC 24 |
| Peak memory | 215488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467228015 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_csr_outstanding.3467228015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/9.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3438530224 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 13394085276 ps |
| CPU time | 92.9 seconds |
| Started | Sep 09 09:52:01 AM UTC 24 |
| Finished | Sep 09 09:53:36 AM UTC 24 |
| Peak memory | 232336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3438530224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_re set.3438530224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/9.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_errors.2292490095 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 261411363 ps |
| CPU time | 7.64 seconds |
| Started | Sep 09 09:52:02 AM UTC 24 |
| Finished | Sep 09 09:52:10 AM UTC 24 |
| Peak memory | 225864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292490095 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.2292490095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/9.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1949255971 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 5207306664 ps |
| CPU time | 19.53 seconds |
| Started | Sep 09 09:52:03 AM UTC 24 |
| Finished | Sep 09 09:52:24 AM UTC 24 |
| Peak memory | 227708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949255971 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.1949255971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/9.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.396693734 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 708542735 ps |
| CPU time | 1.39 seconds |
| Started | Sep 09 09:53:09 AM UTC 24 |
| Finished | Sep 09 09:53:12 AM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396693734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_abstractcmd_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.396693734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_abstractcmd_status/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.3424329065 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 34366823687 ps |
| CPU time | 125.37 seconds |
| Started | Sep 09 09:53:03 AM UTC 24 |
| Finished | Sep 09 09:55:11 AM UTC 24 |
| Peak memory | 226420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424329065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.3424329065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.4009696372 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 139076787 ps |
| CPU time | 1.38 seconds |
| Started | Sep 09 09:53:11 AM UTC 24 |
| Finished | Sep 09 09:53:14 AM UTC 24 |
| Peak memory | 244520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009696372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_buffered_enable.4009696372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_busy.512515212 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 422619555 ps |
| CPU time | 1.77 seconds |
| Started | Sep 09 09:53:03 AM UTC 24 |
| Finished | Sep 09 09:53:06 AM UTC 24 |
| Peak memory | 215944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512515212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.512515212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_cmderr_busy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.2932027473 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 875669603 ps |
| CPU time | 4.44 seconds |
| Started | Sep 09 09:53:03 AM UTC 24 |
| Finished | Sep 09 09:53:09 AM UTC 24 |
| Peak memory | 215812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932027473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.2932027473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_cmderr_exception/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.609715462 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 311921549 ps |
| CPU time | 1.08 seconds |
| Started | Sep 09 09:53:03 AM UTC 24 |
| Finished | Sep 09 09:53:06 AM UTC 24 |
| Peak memory | 215940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609715462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.609715462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_cmderr_not_supported/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_dataaddr_rw_access.3235688149 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 87637302 ps |
| CPU time | 0.98 seconds |
| Started | Sep 09 09:53:06 AM UTC 24 |
| Finished | Sep 09 09:53:08 AM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235688149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.3235688149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_dataaddr_rw_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_debug_disabled.1776735932 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 78786893 ps |
| CPU time | 1.1 seconds |
| Started | Sep 09 09:53:10 AM UTC 24 |
| Finished | Sep 09 09:53:12 AM UTC 24 |
| Peak memory | 237484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776735932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.1776735932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.502771486 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 6725598796 ps |
| CPU time | 7.52 seconds |
| Started | Sep 09 09:53:02 AM UTC 24 |
| Finished | Sep 09 09:53:11 AM UTC 24 |
| Peak memory | 216312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502771486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_tl_access.502771486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_hart_unavail.1712495052 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 211020252 ps |
| CPU time | 0.97 seconds |
| Started | Sep 09 09:53:06 AM UTC 24 |
| Finished | Sep 09 09:53:08 AM UTC 24 |
| Peak memory | 213452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712495052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.1712495052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_hartsel_warl.1697809622 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 72026683 ps |
| CPU time | 1.04 seconds |
| Started | Sep 09 09:53:11 AM UTC 24 |
| Finished | Sep 09 09:53:13 AM UTC 24 |
| Peak memory | 213452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697809622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.1697809622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_hartsel_warl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.757838201 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 629556956 ps |
| CPU time | 3.47 seconds |
| Started | Sep 09 09:53:08 AM UTC 24 |
| Finished | Sep 09 09:53:13 AM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757838201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.757838201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2502001664 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 2033316200 ps |
| CPU time | 5.62 seconds |
| Started | Sep 09 09:53:08 AM UTC 24 |
| Finished | Sep 09 09:53:15 AM UTC 24 |
| Peak memory | 215748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502001664 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.2502001664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_dm_inactive/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2644892529 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 180423152 ps |
| CPU time | 1.67 seconds |
| Started | Sep 09 09:53:09 AM UTC 24 |
| Finished | Sep 09 09:53:12 AM UTC 24 |
| Peak memory | 213452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644892529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.2644892529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_hard_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_idle_hint.3510545354 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 118575039 ps |
| CPU time | 1.64 seconds |
| Started | Sep 09 09:53:08 AM UTC 24 |
| Finished | Sep 09 09:53:11 AM UTC 24 |
| Peak memory | 213396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510545354 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.3510545354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_idle_hint/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_halted.684636401 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 484707695 ps |
| CPU time | 1.33 seconds |
| Started | Sep 09 09:53:03 AM UTC 24 |
| Finished | Sep 09 09:53:06 AM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684636401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.684636401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_halted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.3399680590 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 661579324 ps |
| CPU time | 3.49 seconds |
| Started | Sep 09 09:53:07 AM UTC 24 |
| Finished | Sep 09 09:53:11 AM UTC 24 |
| Peak memory | 226108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399680590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.3399680590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_ndmreset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.450528028 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1285275670 ps |
| CPU time | 3.6 seconds |
| Started | Sep 09 09:53:10 AM UTC 24 |
| Finished | Sep 09 09:53:15 AM UTC 24 |
| Peak memory | 215880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450528028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_progbuf_read_write_execute_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.450528028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_progbuf_read_write_execute/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_tl_access.3023243054 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 536543539 ps |
| CPU time | 4.39 seconds |
| Started | Sep 09 09:53:02 AM UTC 24 |
| Finished | Sep 09 09:53:08 AM UTC 24 |
| Peak memory | 216200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023243054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.3023243054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.2362412394 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 998332598 ps |
| CPU time | 7.56 seconds |
| Started | Sep 09 09:53:13 AM UTC 24 |
| Finished | Sep 09 09:53:22 AM UTC 24 |
| Peak memory | 254812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362412394 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.2362412394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/0.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_abstractcmd_status.2814758781 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 359919407 ps |
| CPU time | 1.49 seconds |
| Started | Sep 09 09:53:19 AM UTC 24 |
| Finished | Sep 09 09:53:21 AM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814758781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_abstractcmd_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.2814758781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_abstractcmd_status/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_alert_test.3228630888 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 84180048 ps |
| CPU time | 1.02 seconds |
| Started | Sep 09 09:53:21 AM UTC 24 |
| Finished | Sep 09 09:53:23 AM UTC 24 |
| Peak memory | 215504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228630888 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.3228630888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_autoincr_sba_tl_access.3209972783 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 22151251042 ps |
| CPU time | 74.43 seconds |
| Started | Sep 09 09:53:14 AM UTC 24 |
| Finished | Sep 09 09:54:30 AM UTC 24 |
| Peak memory | 226624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209972783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.3209972783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_bad_sba_tl_access.1975749970 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 2885525112 ps |
| CPU time | 9.94 seconds |
| Started | Sep 09 09:53:14 AM UTC 24 |
| Finished | Sep 09 09:53:25 AM UTC 24 |
| Peak memory | 216208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975749970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.1975749970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_busy.3049739596 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 711394276 ps |
| CPU time | 2 seconds |
| Started | Sep 09 09:53:14 AM UTC 24 |
| Finished | Sep 09 09:53:17 AM UTC 24 |
| Peak memory | 213460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049739596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.3049739596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_cmderr_busy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.1673927140 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 332056043 ps |
| CPU time | 1.15 seconds |
| Started | Sep 09 09:53:16 AM UTC 24 |
| Finished | Sep 09 09:53:18 AM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673927140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.1673927140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_cmderr_halt_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_not_supported.2721084638 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 182605912 ps |
| CPU time | 1.15 seconds |
| Started | Sep 09 09:53:14 AM UTC 24 |
| Finished | Sep 09 09:53:16 AM UTC 24 |
| Peak memory | 213380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721084638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.2721084638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_cmderr_not_supported/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_dataaddr_rw_access.3349247674 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 67956711 ps |
| CPU time | 1.08 seconds |
| Started | Sep 09 09:53:16 AM UTC 24 |
| Finished | Sep 09 09:53:18 AM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349247674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.3349247674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_dataaddr_rw_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_debug_disabled.3126215954 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 55805745 ps |
| CPU time | 1.15 seconds |
| Started | Sep 09 09:53:19 AM UTC 24 |
| Finished | Sep 09 09:53:21 AM UTC 24 |
| Peak memory | 236048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126215954 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.3126215954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_halt_resume_whereto.1899688937 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 202123359 ps |
| CPU time | 1.19 seconds |
| Started | Sep 09 09:53:17 AM UTC 24 |
| Finished | Sep 09 09:53:20 AM UTC 24 |
| Peak memory | 213452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899688937 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.1899688937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_hart_unavail.3426155652 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 316605755 ps |
| CPU time | 1.02 seconds |
| Started | Sep 09 09:53:15 AM UTC 24 |
| Finished | Sep 09 09:53:17 AM UTC 24 |
| Peak memory | 213452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426155652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.3426155652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.1189768110 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 128706944 ps |
| CPU time | 0.93 seconds |
| Started | Sep 09 09:53:19 AM UTC 24 |
| Finished | Sep 09 09:53:21 AM UTC 24 |
| Peak memory | 213460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189768110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.1189768110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.3469146893 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 294426170 ps |
| CPU time | 1.46 seconds |
| Started | Sep 09 09:53:18 AM UTC 24 |
| Finished | Sep 09 09:53:20 AM UTC 24 |
| Peak memory | 213460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469146893 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.3469146893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_dm_inactive/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_hard_reset.2298703492 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 176166284 ps |
| CPU time | 1.21 seconds |
| Started | Sep 09 09:53:19 AM UTC 24 |
| Finished | Sep 09 09:53:21 AM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298703492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.2298703492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_hard_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1281846161 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 796338901 ps |
| CPU time | 2.22 seconds |
| Started | Sep 09 09:53:18 AM UTC 24 |
| Finished | Sep 09 09:53:21 AM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281846161 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.1281846161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_idle_hint/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_halted.1855990457 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 139404438 ps |
| CPU time | 1.43 seconds |
| Started | Sep 09 09:53:15 AM UTC 24 |
| Finished | Sep 09 09:53:18 AM UTC 24 |
| Peak memory | 213460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855990457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.1855990457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_mem_tl_access_halted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_resuming.651155546 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 350869133 ps |
| CPU time | 1.54 seconds |
| Started | Sep 09 09:53:15 AM UTC 24 |
| Finished | Sep 09 09:53:18 AM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651155546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.651155546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_mem_tl_access_resuming/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_ndmreset_req.2327879148 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 388272612 ps |
| CPU time | 2.18 seconds |
| Started | Sep 09 09:53:18 AM UTC 24 |
| Finished | Sep 09 09:53:21 AM UTC 24 |
| Peak memory | 226108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327879148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.2327879148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_ndmreset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_progbuf_read_write_execute.2200004009 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1082722019 ps |
| CPU time | 1.84 seconds |
| Started | Sep 09 09:53:19 AM UTC 24 |
| Finished | Sep 09 09:53:22 AM UTC 24 |
| Peak memory | 213400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200004009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_progbuf_read_write_execute_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_d m-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.2200004009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_progbuf_read_write_execute/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_rom_read_access.96727411 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 59179341 ps |
| CPU time | 1.44 seconds |
| Started | Sep 09 09:53:19 AM UTC 24 |
| Finished | Sep 09 09:53:21 AM UTC 24 |
| Peak memory | 225860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96727411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv _dm_rom_read_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.96727411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_rom_read_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_debug_disabled.2539043239 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 841242371 ps |
| CPU time | 3.48 seconds |
| Started | Sep 09 09:53:18 AM UTC 24 |
| Finished | Sep 09 09:53:22 AM UTC 24 |
| Peak memory | 216076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539043239 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.2539043239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_sba_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_tl_access.680137360 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 5275083637 ps |
| CPU time | 7.58 seconds |
| Started | Sep 09 09:53:13 AM UTC 24 |
| Finished | Sep 09 09:53:22 AM UTC 24 |
| Peak memory | 216324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680137360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.680137360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_sec_cm.2974069136 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 711723689 ps |
| CPU time | 1.99 seconds |
| Started | Sep 09 09:53:21 AM UTC 24 |
| Finished | Sep 09 09:53:24 AM UTC 24 |
| Peak memory | 252820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974069136 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.2974069136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_smoke.3578352871 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 1957012018 ps |
| CPU time | 5.75 seconds |
| Started | Sep 09 09:53:13 AM UTC 24 |
| Finished | Sep 09 09:53:20 AM UTC 24 |
| Peak memory | 215936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578352871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.3578352871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.3449466549 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 104914670 ps |
| CPU time | 1.22 seconds |
| Started | Sep 09 09:53:21 AM UTC 24 |
| Finished | Sep 09 09:53:23 AM UTC 24 |
| Peak memory | 225616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449466549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sparse_lc_gate_fsm.3449466549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/1.rv_dm_sparse_lc_gate_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/10.rv_dm_alert_test.2173385333 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 55212494 ps |
| CPU time | 1.1 seconds |
| Started | Sep 09 09:54:08 AM UTC 24 |
| Finished | Sep 09 09:54:10 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173385333 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.2173385333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/10.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/10.rv_dm_autoincr_sba_tl_access.70752671 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 6563673423 ps |
| CPU time | 21.35 seconds |
| Started | Sep 09 09:54:06 AM UTC 24 |
| Finished | Sep 09 09:54:28 AM UTC 24 |
| Peak memory | 226504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70752671 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv _dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.70752671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/10.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/10.rv_dm_bad_sba_tl_access.2210672928 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 1213732982 ps |
| CPU time | 4.31 seconds |
| Started | Sep 09 09:54:03 AM UTC 24 |
| Finished | Sep 09 09:54:09 AM UTC 24 |
| Peak memory | 226384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210672928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.2210672928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/10.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.2420405151 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 10030965402 ps |
| CPU time | 13.43 seconds |
| Started | Sep 09 09:54:01 AM UTC 24 |
| Finished | Sep 09 09:54:16 AM UTC 24 |
| Peak memory | 226612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420405151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_tl_access.2420405151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/10.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/10.rv_dm_sba_tl_access.1342685474 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 1223297411 ps |
| CPU time | 3.65 seconds |
| Started | Sep 09 09:54:01 AM UTC 24 |
| Finished | Sep 09 09:54:06 AM UTC 24 |
| Peak memory | 216188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342685474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.1342685474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/10.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/10.rv_dm_stress_all.2986451517 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 1068960024 ps |
| CPU time | 6.15 seconds |
| Started | Sep 09 09:54:07 AM UTC 24 |
| Finished | Sep 09 09:54:14 AM UTC 24 |
| Peak memory | 216020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986451517 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.2986451517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/10.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/11.rv_dm_alert_test.4249148961 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 87493389 ps |
| CPU time | 1.07 seconds |
| Started | Sep 09 09:54:13 AM UTC 24 |
| Finished | Sep 09 09:54:15 AM UTC 24 |
| Peak memory | 215388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249148961 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.4249148961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/11.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/11.rv_dm_autoincr_sba_tl_access.739543106 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 4044063000 ps |
| CPU time | 25.82 seconds |
| Started | Sep 09 09:54:11 AM UTC 24 |
| Finished | Sep 09 09:54:38 AM UTC 24 |
| Peak memory | 226428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739543106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.739543106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/11.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/11.rv_dm_bad_sba_tl_access.29422001 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 2280736744 ps |
| CPU time | 7.43 seconds |
| Started | Sep 09 09:54:11 AM UTC 24 |
| Finished | Sep 09 09:54:19 AM UTC 24 |
| Peak memory | 226560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29422001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv _dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.29422001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/11.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.512010737 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 4970794856 ps |
| CPU time | 10.04 seconds |
| Started | Sep 09 09:54:10 AM UTC 24 |
| Finished | Sep 09 09:54:21 AM UTC 24 |
| Peak memory | 226428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512010737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_tl_access.512010737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/11.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/11.rv_dm_sba_tl_access.1448655098 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 783962859 ps |
| CPU time | 3.57 seconds |
| Started | Sep 09 09:54:08 AM UTC 24 |
| Finished | Sep 09 09:54:12 AM UTC 24 |
| Peak memory | 216132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448655098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.1448655098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/11.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/12.rv_dm_alert_test.3679213479 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 77345223 ps |
| CPU time | 1.12 seconds |
| Started | Sep 09 09:54:17 AM UTC 24 |
| Finished | Sep 09 09:54:20 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679213479 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.3679213479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/12.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/12.rv_dm_autoincr_sba_tl_access.1517446784 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 5718187917 ps |
| CPU time | 23.89 seconds |
| Started | Sep 09 09:54:16 AM UTC 24 |
| Finished | Sep 09 09:54:41 AM UTC 24 |
| Peak memory | 226568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517446784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.1517446784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/12.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/12.rv_dm_bad_sba_tl_access.3214797125 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 4186701009 ps |
| CPU time | 8.72 seconds |
| Started | Sep 09 09:54:15 AM UTC 24 |
| Finished | Sep 09 09:54:25 AM UTC 24 |
| Peak memory | 226512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214797125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.3214797125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/12.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.973382168 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 2867761802 ps |
| CPU time | 4.05 seconds |
| Started | Sep 09 09:54:14 AM UTC 24 |
| Finished | Sep 09 09:54:19 AM UTC 24 |
| Peak memory | 226624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973382168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_tl_access.973382168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/12.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/12.rv_dm_sba_tl_access.3871801126 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 8462257414 ps |
| CPU time | 21.19 seconds |
| Started | Sep 09 09:54:13 AM UTC 24 |
| Finished | Sep 09 09:54:35 AM UTC 24 |
| Peak memory | 216208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871801126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.3871801126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/12.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/12.rv_dm_stress_all.2490755205 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 7609838266 ps |
| CPU time | 14.39 seconds |
| Started | Sep 09 09:54:16 AM UTC 24 |
| Finished | Sep 09 09:54:32 AM UTC 24 |
| Peak memory | 216140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490755205 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.2490755205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/12.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/13.rv_dm_alert_test.2258600390 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 215704726 ps |
| CPU time | 1.23 seconds |
| Started | Sep 09 09:54:26 AM UTC 24 |
| Finished | Sep 09 09:54:28 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258600390 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.2258600390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/13.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/13.rv_dm_bad_sba_tl_access.3612743116 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 5743776108 ps |
| CPU time | 13.77 seconds |
| Started | Sep 09 09:54:21 AM UTC 24 |
| Finished | Sep 09 09:54:36 AM UTC 24 |
| Peak memory | 216320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612743116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.3612743116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/13.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.3468332147 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 8926326799 ps |
| CPU time | 28.77 seconds |
| Started | Sep 09 09:54:21 AM UTC 24 |
| Finished | Sep 09 09:54:51 AM UTC 24 |
| Peak memory | 226624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468332147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_tl_access.3468332147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/13.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/13.rv_dm_sba_tl_access.3235623802 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 4297293655 ps |
| CPU time | 5.86 seconds |
| Started | Sep 09 09:54:20 AM UTC 24 |
| Finished | Sep 09 09:54:26 AM UTC 24 |
| Peak memory | 216324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235623802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.3235623802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/13.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/13.rv_dm_stress_all.1926315834 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 3120289568 ps |
| CPU time | 13.02 seconds |
| Started | Sep 09 09:54:23 AM UTC 24 |
| Finished | Sep 09 09:54:37 AM UTC 24 |
| Peak memory | 216144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926315834 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.1926315834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/13.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/14.rv_dm_alert_test.1950330566 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 34927725 ps |
| CPU time | 0.99 seconds |
| Started | Sep 09 09:54:28 AM UTC 24 |
| Finished | Sep 09 09:54:31 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950330566 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.1950330566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/14.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/14.rv_dm_autoincr_sba_tl_access.2017686790 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 15679125379 ps |
| CPU time | 6.86 seconds |
| Started | Sep 09 09:54:27 AM UTC 24 |
| Finished | Sep 09 09:54:35 AM UTC 24 |
| Peak memory | 226500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017686790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.2017686790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/14.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/14.rv_dm_bad_sba_tl_access.3822309945 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 2483980472 ps |
| CPU time | 6.59 seconds |
| Started | Sep 09 09:54:27 AM UTC 24 |
| Finished | Sep 09 09:54:35 AM UTC 24 |
| Peak memory | 216192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822309945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.3822309945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/14.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.3545188427 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 2569347072 ps |
| CPU time | 9.81 seconds |
| Started | Sep 09 09:54:26 AM UTC 24 |
| Finished | Sep 09 09:54:37 AM UTC 24 |
| Peak memory | 216184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545188427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_tl_access.3545188427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/14.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/14.rv_dm_sba_tl_access.4147979522 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 2124373597 ps |
| CPU time | 5.97 seconds |
| Started | Sep 09 09:54:26 AM UTC 24 |
| Finished | Sep 09 09:54:33 AM UTC 24 |
| Peak memory | 216264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147979522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.4147979522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/14.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/14.rv_dm_stress_all.2721874248 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 1528757366 ps |
| CPU time | 3.65 seconds |
| Started | Sep 09 09:54:28 AM UTC 24 |
| Finished | Sep 09 09:54:33 AM UTC 24 |
| Peak memory | 226112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721874248 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.2721874248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/14.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/15.rv_dm_alert_test.1497667224 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 62471900 ps |
| CPU time | 1.16 seconds |
| Started | Sep 09 09:54:34 AM UTC 24 |
| Finished | Sep 09 09:54:36 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497667224 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.1497667224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/15.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/15.rv_dm_autoincr_sba_tl_access.4093074135 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 5613812404 ps |
| CPU time | 12.55 seconds |
| Started | Sep 09 09:54:32 AM UTC 24 |
| Finished | Sep 09 09:54:45 AM UTC 24 |
| Peak memory | 226500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093074135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.4093074135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/15.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/15.rv_dm_bad_sba_tl_access.4096575595 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 7522113994 ps |
| CPU time | 9.97 seconds |
| Started | Sep 09 09:54:32 AM UTC 24 |
| Finished | Sep 09 09:54:43 AM UTC 24 |
| Peak memory | 226492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096575595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.4096575595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/15.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.4037273301 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 11204619640 ps |
| CPU time | 17.74 seconds |
| Started | Sep 09 09:54:31 AM UTC 24 |
| Finished | Sep 09 09:54:50 AM UTC 24 |
| Peak memory | 226492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037273301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_tl_access.4037273301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/15.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/15.rv_dm_sba_tl_access.1624540392 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 16934502086 ps |
| CPU time | 30.1 seconds |
| Started | Sep 09 09:54:30 AM UTC 24 |
| Finished | Sep 09 09:55:01 AM UTC 24 |
| Peak memory | 226564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624540392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.1624540392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/15.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/15.rv_dm_stress_all.3558985903 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 6323115433 ps |
| CPU time | 9.87 seconds |
| Started | Sep 09 09:54:33 AM UTC 24 |
| Finished | Sep 09 09:54:44 AM UTC 24 |
| Peak memory | 226300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558985903 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.3558985903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/15.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/16.rv_dm_alert_test.895662435 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 79323675 ps |
| CPU time | 1.12 seconds |
| Started | Sep 09 09:54:36 AM UTC 24 |
| Finished | Sep 09 09:54:38 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895662435 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.895662435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/16.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/16.rv_dm_autoincr_sba_tl_access.3530947475 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 6152195118 ps |
| CPU time | 8.61 seconds |
| Started | Sep 09 09:54:36 AM UTC 24 |
| Finished | Sep 09 09:54:46 AM UTC 24 |
| Peak memory | 226568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530947475 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.3530947475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/16.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/16.rv_dm_bad_sba_tl_access.56736423 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 904344764 ps |
| CPU time | 1.61 seconds |
| Started | Sep 09 09:54:34 AM UTC 24 |
| Finished | Sep 09 09:54:37 AM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56736423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv _dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.56736423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/16.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.3770337870 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 769420894 ps |
| CPU time | 5 seconds |
| Started | Sep 09 09:54:34 AM UTC 24 |
| Finished | Sep 09 09:54:40 AM UTC 24 |
| Peak memory | 216200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770337870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_tl_access.3770337870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/16.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/16.rv_dm_sba_tl_access.2381096074 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 969460507 ps |
| CPU time | 2.66 seconds |
| Started | Sep 09 09:54:34 AM UTC 24 |
| Finished | Sep 09 09:54:38 AM UTC 24 |
| Peak memory | 216272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381096074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.2381096074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/16.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/16.rv_dm_stress_all.2810923931 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 5680947892 ps |
| CPU time | 7.26 seconds |
| Started | Sep 09 09:54:36 AM UTC 24 |
| Finished | Sep 09 09:54:45 AM UTC 24 |
| Peak memory | 216136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810923931 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.2810923931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/16.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/17.rv_dm_alert_test.1917256275 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 143997134 ps |
| CPU time | 1.26 seconds |
| Started | Sep 09 09:54:39 AM UTC 24 |
| Finished | Sep 09 09:54:41 AM UTC 24 |
| Peak memory | 215644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917256275 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.1917256275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/17.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/17.rv_dm_bad_sba_tl_access.3032241763 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 5148664390 ps |
| CPU time | 16.76 seconds |
| Started | Sep 09 09:54:37 AM UTC 24 |
| Finished | Sep 09 09:54:55 AM UTC 24 |
| Peak memory | 216260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032241763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.3032241763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/17.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.495553413 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 3976781781 ps |
| CPU time | 6.83 seconds |
| Started | Sep 09 09:54:37 AM UTC 24 |
| Finished | Sep 09 09:54:45 AM UTC 24 |
| Peak memory | 216316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495553413 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_tl_access.495553413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/17.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/17.rv_dm_sba_tl_access.515162816 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 1495578468 ps |
| CPU time | 5.8 seconds |
| Started | Sep 09 09:54:36 AM UTC 24 |
| Finished | Sep 09 09:54:43 AM UTC 24 |
| Peak memory | 216256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515162816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.515162816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/17.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/17.rv_dm_stress_all.2172703443 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 4343074018 ps |
| CPU time | 13.11 seconds |
| Started | Sep 09 09:54:39 AM UTC 24 |
| Finished | Sep 09 09:54:53 AM UTC 24 |
| Peak memory | 215988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172703443 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.2172703443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/17.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/18.rv_dm_alert_test.1642330776 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 54237334 ps |
| CPU time | 1.11 seconds |
| Started | Sep 09 09:54:44 AM UTC 24 |
| Finished | Sep 09 09:54:46 AM UTC 24 |
| Peak memory | 215812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642330776 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.1642330776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/18.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/18.rv_dm_autoincr_sba_tl_access.1450634838 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 14885535340 ps |
| CPU time | 6.58 seconds |
| Started | Sep 09 09:54:42 AM UTC 24 |
| Finished | Sep 09 09:54:50 AM UTC 24 |
| Peak memory | 226500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450634838 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.1450634838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/18.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/18.rv_dm_bad_sba_tl_access.1936915431 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 1369412478 ps |
| CPU time | 2.35 seconds |
| Started | Sep 09 09:54:41 AM UTC 24 |
| Finished | Sep 09 09:54:44 AM UTC 24 |
| Peak memory | 216208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936915431 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.1936915431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/18.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.1437598517 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 8202212486 ps |
| CPU time | 11 seconds |
| Started | Sep 09 09:54:40 AM UTC 24 |
| Finished | Sep 09 09:54:52 AM UTC 24 |
| Peak memory | 226424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437598517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_tl_access.1437598517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/18.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/18.rv_dm_sba_tl_access.1368209971 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 12369080797 ps |
| CPU time | 17.54 seconds |
| Started | Sep 09 09:54:39 AM UTC 24 |
| Finished | Sep 09 09:54:58 AM UTC 24 |
| Peak memory | 226576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368209971 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.1368209971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/18.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/18.rv_dm_stress_all.1964957565 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 3630677044 ps |
| CPU time | 6.87 seconds |
| Started | Sep 09 09:54:42 AM UTC 24 |
| Finished | Sep 09 09:54:50 AM UTC 24 |
| Peak memory | 216076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964957565 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.1964957565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/18.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/19.rv_dm_alert_test.2499649024 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 38788675 ps |
| CPU time | 1.22 seconds |
| Started | Sep 09 09:54:46 AM UTC 24 |
| Finished | Sep 09 09:54:49 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499649024 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.2499649024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/19.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.599932880 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 65160457909 ps |
| CPU time | 121.78 seconds |
| Started | Sep 09 09:54:45 AM UTC 24 |
| Finished | Sep 09 09:56:49 AM UTC 24 |
| Peak memory | 226624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599932880 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.599932880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/19.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/19.rv_dm_bad_sba_tl_access.521903303 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 1849714005 ps |
| CPU time | 4.12 seconds |
| Started | Sep 09 09:54:45 AM UTC 24 |
| Finished | Sep 09 09:54:50 AM UTC 24 |
| Peak memory | 216328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521903303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.521903303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/19.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.3020118091 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 2426974012 ps |
| CPU time | 7.06 seconds |
| Started | Sep 09 09:54:44 AM UTC 24 |
| Finished | Sep 09 09:54:52 AM UTC 24 |
| Peak memory | 226676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020118091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_tl_access.3020118091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/19.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/19.rv_dm_sba_tl_access.1319054946 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 7272014056 ps |
| CPU time | 21.05 seconds |
| Started | Sep 09 09:54:44 AM UTC 24 |
| Finished | Sep 09 09:55:06 AM UTC 24 |
| Peak memory | 216196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319054946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.1319054946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/19.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.3759669354 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 32567990 ps |
| CPU time | 0.96 seconds |
| Started | Sep 09 09:53:24 AM UTC 24 |
| Finished | Sep 09 09:53:26 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759669354 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.3759669354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/2.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.3539028780 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 5215192127 ps |
| CPU time | 8.14 seconds |
| Started | Sep 09 09:53:23 AM UTC 24 |
| Finished | Sep 09 09:53:32 AM UTC 24 |
| Peak memory | 226460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539028780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.3539028780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/2.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.3867773900 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 440165998 ps |
| CPU time | 2.33 seconds |
| Started | Sep 09 09:53:23 AM UTC 24 |
| Finished | Sep 09 09:53:26 AM UTC 24 |
| Peak memory | 252772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867773900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_buffered_enable.3867773900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/2.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.3430822164 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 2915311081 ps |
| CPU time | 16.62 seconds |
| Started | Sep 09 09:53:23 AM UTC 24 |
| Finished | Sep 09 09:53:40 AM UTC 24 |
| Peak memory | 216132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430822164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_tl_access.3430822164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/2.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.2232085352 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 377955172 ps |
| CPU time | 1.59 seconds |
| Started | Sep 09 09:53:23 AM UTC 24 |
| Finished | Sep 09 09:53:25 AM UTC 24 |
| Peak memory | 213392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232085352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_halt_resume_whereto.2232085352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/2.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.1951506539 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 118128516 ps |
| CPU time | 1.09 seconds |
| Started | Sep 09 09:53:23 AM UTC 24 |
| Finished | Sep 09 09:53:25 AM UTC 24 |
| Peak memory | 213436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951506539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.1951506539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/2.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.2674695014 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 2346612034 ps |
| CPU time | 1.91 seconds |
| Started | Sep 09 09:53:22 AM UTC 24 |
| Finished | Sep 09 09:53:25 AM UTC 24 |
| Peak memory | 215444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674695014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.2674695014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/2.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_sparse_lc_gate_fsm.1065824295 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 54155219 ps |
| CPU time | 0.78 seconds |
| Started | Sep 09 09:53:23 AM UTC 24 |
| Finished | Sep 09 09:53:24 AM UTC 24 |
| Peak memory | 225836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065824295 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sparse_lc_gate_fsm.1065824295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/2.rv_dm_sparse_lc_gate_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all.1485189645 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1415871606 ps |
| CPU time | 4.76 seconds |
| Started | Sep 09 09:53:23 AM UTC 24 |
| Finished | Sep 09 09:53:29 AM UTC 24 |
| Peak memory | 216020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485189645 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.1485189645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/2.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.3336172311 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 2683577051 ps |
| CPU time | 59.56 seconds |
| Started | Sep 09 09:53:24 AM UTC 24 |
| Finished | Sep 09 09:54:25 AM UTC 24 |
| Peak memory | 228616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3336172311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stres s_all_with_rand_reset.3336172311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/20.rv_dm_alert_test.1231979259 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 79464455 ps |
| CPU time | 1.24 seconds |
| Started | Sep 09 09:54:48 AM UTC 24 |
| Finished | Sep 09 09:54:50 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231979259 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.1231979259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/20.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/21.rv_dm_alert_test.1289363952 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 35954867 ps |
| CPU time | 1.13 seconds |
| Started | Sep 09 09:54:50 AM UTC 24 |
| Finished | Sep 09 09:54:52 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289363952 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.1289363952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/21.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/21.rv_dm_stress_all.3051229547 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 4376949854 ps |
| CPU time | 8.86 seconds |
| Started | Sep 09 09:54:48 AM UTC 24 |
| Finished | Sep 09 09:54:58 AM UTC 24 |
| Peak memory | 226304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051229547 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.3051229547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/21.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/22.rv_dm_alert_test.1272321024 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 185703999 ps |
| CPU time | 2.16 seconds |
| Started | Sep 09 09:54:51 AM UTC 24 |
| Finished | Sep 09 09:54:54 AM UTC 24 |
| Peak memory | 215876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272321024 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.1272321024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/22.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/23.rv_dm_alert_test.320817848 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 30373111 ps |
| CPU time | 0.88 seconds |
| Started | Sep 09 09:54:51 AM UTC 24 |
| Finished | Sep 09 09:54:53 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320817848 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.320817848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/23.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/24.rv_dm_alert_test.899078523 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 139947624 ps |
| CPU time | 1.11 seconds |
| Started | Sep 09 09:54:51 AM UTC 24 |
| Finished | Sep 09 09:54:53 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899078523 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.899078523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/24.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/24.rv_dm_stress_all.494749331 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 3143182948 ps |
| CPU time | 7.66 seconds |
| Started | Sep 09 09:54:51 AM UTC 24 |
| Finished | Sep 09 09:55:00 AM UTC 24 |
| Peak memory | 216044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494749331 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.494749331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/24.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/25.rv_dm_alert_test.1693712985 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 50916337 ps |
| CPU time | 1.24 seconds |
| Started | Sep 09 09:54:52 AM UTC 24 |
| Finished | Sep 09 09:54:54 AM UTC 24 |
| Peak memory | 215688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693712985 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.1693712985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/25.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.3696809622 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 4303214244 ps |
| CPU time | 12.79 seconds |
| Started | Sep 09 09:54:51 AM UTC 24 |
| Finished | Sep 09 09:55:05 AM UTC 24 |
| Peak memory | 216108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696809622 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.3696809622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/25.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/26.rv_dm_alert_test.2277121085 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 74036780 ps |
| CPU time | 1.04 seconds |
| Started | Sep 09 09:54:53 AM UTC 24 |
| Finished | Sep 09 09:54:55 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277121085 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.2277121085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/26.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/27.rv_dm_alert_test.4238928214 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 83240696 ps |
| CPU time | 1.48 seconds |
| Started | Sep 09 09:54:53 AM UTC 24 |
| Finished | Sep 09 09:54:56 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238928214 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.4238928214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/27.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.3765273258 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1359420851 ps |
| CPU time | 2.26 seconds |
| Started | Sep 09 09:54:53 AM UTC 24 |
| Finished | Sep 09 09:54:57 AM UTC 24 |
| Peak memory | 216012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765273258 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.3765273258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/27.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/28.rv_dm_alert_test.4120944708 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 64739013 ps |
| CPU time | 0.92 seconds |
| Started | Sep 09 09:54:55 AM UTC 24 |
| Finished | Sep 09 09:54:57 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120944708 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.4120944708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/28.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/28.rv_dm_stress_all.623178989 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 8755482044 ps |
| CPU time | 7.24 seconds |
| Started | Sep 09 09:54:53 AM UTC 24 |
| Finished | Sep 09 09:55:02 AM UTC 24 |
| Peak memory | 226392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623178989 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.623178989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/28.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/29.rv_dm_alert_test.1672495227 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 116356444 ps |
| CPU time | 0.85 seconds |
| Started | Sep 09 09:54:55 AM UTC 24 |
| Finished | Sep 09 09:54:57 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672495227 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.1672495227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/29.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/29.rv_dm_stress_all.1556449947 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 2098812335 ps |
| CPU time | 2.09 seconds |
| Started | Sep 09 09:54:55 AM UTC 24 |
| Finished | Sep 09 09:54:58 AM UTC 24 |
| Peak memory | 216076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556449947 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.1556449947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/29.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.3568948834 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 41437443 ps |
| CPU time | 1.09 seconds |
| Started | Sep 09 09:53:27 AM UTC 24 |
| Finished | Sep 09 09:53:29 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568948834 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.3568948834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/3.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.3539005579 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 1173639135 ps |
| CPU time | 5.4 seconds |
| Started | Sep 09 09:53:25 AM UTC 24 |
| Finished | Sep 09 09:53:32 AM UTC 24 |
| Peak memory | 216304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539005579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.3539005579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/3.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.460268906 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 1023963550 ps |
| CPU time | 7.14 seconds |
| Started | Sep 09 09:53:24 AM UTC 24 |
| Finished | Sep 09 09:53:32 AM UTC 24 |
| Peak memory | 216276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460268906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.460268906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/3.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.3577758298 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 462461566 ps |
| CPU time | 3.89 seconds |
| Started | Sep 09 09:53:25 AM UTC 24 |
| Finished | Sep 09 09:53:30 AM UTC 24 |
| Peak memory | 252620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577758298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_buffered_enable.3577758298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/3.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1247197517 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 2589004988 ps |
| CPU time | 2.96 seconds |
| Started | Sep 09 09:53:24 AM UTC 24 |
| Finished | Sep 09 09:53:28 AM UTC 24 |
| Peak memory | 216248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247197517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_tl_access.1247197517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/3.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.2579697562 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 283435766 ps |
| CPU time | 1.27 seconds |
| Started | Sep 09 09:53:25 AM UTC 24 |
| Finished | Sep 09 09:53:28 AM UTC 24 |
| Peak memory | 213452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579697562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_halt_resume_whereto.2579697562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/3.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_hart_unavail.3805838274 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 120227534 ps |
| CPU time | 1.03 seconds |
| Started | Sep 09 09:53:25 AM UTC 24 |
| Finished | Sep 09 09:53:27 AM UTC 24 |
| Peak memory | 213452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805838274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.3805838274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/3.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.1492092812 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 3264201748 ps |
| CPU time | 6.46 seconds |
| Started | Sep 09 09:53:24 AM UTC 24 |
| Finished | Sep 09 09:53:32 AM UTC 24 |
| Peak memory | 216268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492092812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.1492092812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/3.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_sec_cm.3296751920 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 868096019 ps |
| CPU time | 1.66 seconds |
| Started | Sep 09 09:53:27 AM UTC 24 |
| Finished | Sep 09 09:53:29 AM UTC 24 |
| Peak memory | 254380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296751920 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.3296751920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/3.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.3425341586 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 67738486 ps |
| CPU time | 1.32 seconds |
| Started | Sep 09 09:53:26 AM UTC 24 |
| Finished | Sep 09 09:53:29 AM UTC 24 |
| Peak memory | 225856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425341586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sparse_lc_gate_fsm.3425341586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/3.rv_dm_sparse_lc_gate_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.3567977755 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 3519851938 ps |
| CPU time | 7.24 seconds |
| Started | Sep 09 09:53:27 AM UTC 24 |
| Finished | Sep 09 09:53:35 AM UTC 24 |
| Peak memory | 226300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567977755 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.3567977755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/3.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/30.rv_dm_alert_test.148280907 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 139886200 ps |
| CPU time | 1.49 seconds |
| Started | Sep 09 09:54:56 AM UTC 24 |
| Finished | Sep 09 09:54:58 AM UTC 24 |
| Peak memory | 215876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148280907 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.148280907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/30.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.999673183 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 5299071980 ps |
| CPU time | 5.22 seconds |
| Started | Sep 09 09:54:56 AM UTC 24 |
| Finished | Sep 09 09:55:02 AM UTC 24 |
| Peak memory | 226384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999673183 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.999673183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/30.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/31.rv_dm_alert_test.995778772 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 56456133 ps |
| CPU time | 1.08 seconds |
| Started | Sep 09 09:54:57 AM UTC 24 |
| Finished | Sep 09 09:54:59 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995778772 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.995778772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/31.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/31.rv_dm_stress_all.3959294203 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 4586189368 ps |
| CPU time | 9.22 seconds |
| Started | Sep 09 09:54:56 AM UTC 24 |
| Finished | Sep 09 09:55:06 AM UTC 24 |
| Peak memory | 216204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959294203 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.3959294203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/31.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/32.rv_dm_alert_test.3654515698 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 99895975 ps |
| CPU time | 0.89 seconds |
| Started | Sep 09 09:54:57 AM UTC 24 |
| Finished | Sep 09 09:54:59 AM UTC 24 |
| Peak memory | 215792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654515698 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.3654515698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/32.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/32.rv_dm_stress_all.3082160257 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 1627012071 ps |
| CPU time | 3.92 seconds |
| Started | Sep 09 09:54:57 AM UTC 24 |
| Finished | Sep 09 09:55:02 AM UTC 24 |
| Peak memory | 226240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082160257 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.3082160257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/32.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/33.rv_dm_alert_test.1328263703 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 40259960 ps |
| CPU time | 0.84 seconds |
| Started | Sep 09 09:54:57 AM UTC 24 |
| Finished | Sep 09 09:54:59 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328263703 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.1328263703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/33.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.93135933 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 2371174940 ps |
| CPU time | 2.98 seconds |
| Started | Sep 09 09:54:57 AM UTC 24 |
| Finished | Sep 09 09:55:01 AM UTC 24 |
| Peak memory | 216144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93135933 -assert nopostproc +UVM_TESTNAME=rv_ dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.93135933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/33.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/34.rv_dm_alert_test.1590727490 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 139643202 ps |
| CPU time | 1.12 seconds |
| Started | Sep 09 09:54:58 AM UTC 24 |
| Finished | Sep 09 09:55:00 AM UTC 24 |
| Peak memory | 215820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590727490 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.1590727490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/34.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/34.rv_dm_stress_all.3172271553 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 4647206469 ps |
| CPU time | 7.24 seconds |
| Started | Sep 09 09:54:58 AM UTC 24 |
| Finished | Sep 09 09:55:06 AM UTC 24 |
| Peak memory | 226004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172271553 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.3172271553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/34.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/35.rv_dm_alert_test.2565858530 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 36444971 ps |
| CPU time | 1.03 seconds |
| Started | Sep 09 09:54:58 AM UTC 24 |
| Finished | Sep 09 09:55:00 AM UTC 24 |
| Peak memory | 215408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565858530 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.2565858530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/35.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/35.rv_dm_stress_all.2356481341 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 1345773579 ps |
| CPU time | 5.05 seconds |
| Started | Sep 09 09:54:58 AM UTC 24 |
| Finished | Sep 09 09:55:04 AM UTC 24 |
| Peak memory | 226316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356481341 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.2356481341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/35.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/36.rv_dm_alert_test.2030336137 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 114561506 ps |
| CPU time | 1.48 seconds |
| Started | Sep 09 09:54:58 AM UTC 24 |
| Finished | Sep 09 09:55:01 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030336137 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.2030336137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/36.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/36.rv_dm_stress_all.1233650419 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 3026819237 ps |
| CPU time | 2.96 seconds |
| Started | Sep 09 09:54:58 AM UTC 24 |
| Finished | Sep 09 09:55:02 AM UTC 24 |
| Peak memory | 226248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233650419 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.1233650419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/36.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/37.rv_dm_alert_test.3625355583 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 46076453 ps |
| CPU time | 1.17 seconds |
| Started | Sep 09 09:55:00 AM UTC 24 |
| Finished | Sep 09 09:55:02 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625355583 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.3625355583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/37.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/37.rv_dm_stress_all.3280040999 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 9180250961 ps |
| CPU time | 9.69 seconds |
| Started | Sep 09 09:54:59 AM UTC 24 |
| Finished | Sep 09 09:55:10 AM UTC 24 |
| Peak memory | 226316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280040999 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.3280040999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/37.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/38.rv_dm_alert_test.4290478497 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 144754429 ps |
| CPU time | 1.02 seconds |
| Started | Sep 09 09:55:00 AM UTC 24 |
| Finished | Sep 09 09:55:02 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290478497 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.4290478497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/38.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/38.rv_dm_stress_all.2827311544 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4609791458 ps |
| CPU time | 14.4 seconds |
| Started | Sep 09 09:55:00 AM UTC 24 |
| Finished | Sep 09 09:55:15 AM UTC 24 |
| Peak memory | 216140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827311544 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.2827311544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/38.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/39.rv_dm_alert_test.1314953054 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 80897288 ps |
| CPU time | 1.05 seconds |
| Started | Sep 09 09:55:00 AM UTC 24 |
| Finished | Sep 09 09:55:02 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314953054 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.1314953054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/39.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/39.rv_dm_stress_all.3527099915 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 2558137226 ps |
| CPU time | 3.03 seconds |
| Started | Sep 09 09:55:00 AM UTC 24 |
| Finished | Sep 09 09:55:04 AM UTC 24 |
| Peak memory | 216004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527099915 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.3527099915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/39.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_alert_test.1049602682 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 45914892 ps |
| CPU time | 1.09 seconds |
| Started | Sep 09 09:53:32 AM UTC 24 |
| Finished | Sep 09 09:53:35 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049602682 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.1049602682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/4.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_autoincr_sba_tl_access.3217840535 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 32266329453 ps |
| CPU time | 85.02 seconds |
| Started | Sep 09 09:53:29 AM UTC 24 |
| Finished | Sep 09 09:54:56 AM UTC 24 |
| Peak memory | 226624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217840535 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.3217840535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/4.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_bad_sba_tl_access.1293371922 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 6581941847 ps |
| CPU time | 18.29 seconds |
| Started | Sep 09 09:53:28 AM UTC 24 |
| Finished | Sep 09 09:53:47 AM UTC 24 |
| Peak memory | 233324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293371922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.1293371922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/4.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_buffered_enable.2086158359 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 294707393 ps |
| CPU time | 2.23 seconds |
| Started | Sep 09 09:53:30 AM UTC 24 |
| Finished | Sep 09 09:53:33 AM UTC 24 |
| Peak memory | 252680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086158359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_buffered_enable.2086158359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/4.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.2438145275 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 2811679017 ps |
| CPU time | 11.3 seconds |
| Started | Sep 09 09:53:28 AM UTC 24 |
| Finished | Sep 09 09:53:40 AM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438145275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_tl_access.2438145275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/4.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.3660816857 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 269053203 ps |
| CPU time | 1.82 seconds |
| Started | Sep 09 09:53:29 AM UTC 24 |
| Finished | Sep 09 09:53:32 AM UTC 24 |
| Peak memory | 213452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660816857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_halt_resume_whereto.3660816857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/4.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.1605430889 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 129020255 ps |
| CPU time | 1.75 seconds |
| Started | Sep 09 09:53:29 AM UTC 24 |
| Finished | Sep 09 09:53:32 AM UTC 24 |
| Peak memory | 213452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605430889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.1605430889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/4.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_sba_tl_access.446658407 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 1305347619 ps |
| CPU time | 5.89 seconds |
| Started | Sep 09 09:53:28 AM UTC 24 |
| Finished | Sep 09 09:53:35 AM UTC 24 |
| Peak memory | 216200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446658407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.446658407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/4.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_sec_cm.101698155 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 2915093587 ps |
| CPU time | 10.84 seconds |
| Started | Sep 09 09:53:31 AM UTC 24 |
| Finished | Sep 09 09:53:43 AM UTC 24 |
| Peak memory | 254828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101698155 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.101698155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/4.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.3651541189 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9715038625 ps |
| CPU time | 9.1 seconds |
| Started | Sep 09 09:53:30 AM UTC 24 |
| Finished | Sep 09 09:53:40 AM UTC 24 |
| Peak memory | 216068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651541189 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.3651541189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/4.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/40.rv_dm_alert_test.278213641 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 159499917 ps |
| CPU time | 1.14 seconds |
| Started | Sep 09 09:55:01 AM UTC 24 |
| Finished | Sep 09 09:55:03 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278213641 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.278213641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/40.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/40.rv_dm_stress_all.947676079 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 3228774834 ps |
| CPU time | 10.72 seconds |
| Started | Sep 09 09:55:01 AM UTC 24 |
| Finished | Sep 09 09:55:13 AM UTC 24 |
| Peak memory | 215464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947676079 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.947676079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/40.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/41.rv_dm_alert_test.150670413 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 152895218 ps |
| CPU time | 1.38 seconds |
| Started | Sep 09 09:55:01 AM UTC 24 |
| Finished | Sep 09 09:55:03 AM UTC 24 |
| Peak memory | 215936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150670413 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.150670413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/41.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/41.rv_dm_stress_all.3126051422 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 4262079706 ps |
| CPU time | 8.03 seconds |
| Started | Sep 09 09:55:01 AM UTC 24 |
| Finished | Sep 09 09:55:10 AM UTC 24 |
| Peak memory | 216076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126051422 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.3126051422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/41.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/42.rv_dm_alert_test.2736802576 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 40817248 ps |
| CPU time | 0.96 seconds |
| Started | Sep 09 09:55:02 AM UTC 24 |
| Finished | Sep 09 09:55:04 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736802576 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.2736802576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/42.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/42.rv_dm_stress_all.4060287126 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 1327666677 ps |
| CPU time | 5.24 seconds |
| Started | Sep 09 09:55:01 AM UTC 24 |
| Finished | Sep 09 09:55:07 AM UTC 24 |
| Peak memory | 216020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060287126 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.4060287126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/42.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/43.rv_dm_alert_test.3096933860 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 83452903 ps |
| CPU time | 0.97 seconds |
| Started | Sep 09 09:55:02 AM UTC 24 |
| Finished | Sep 09 09:55:04 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096933860 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.3096933860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/43.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/43.rv_dm_stress_all.2018879081 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 4077288185 ps |
| CPU time | 7.12 seconds |
| Started | Sep 09 09:55:02 AM UTC 24 |
| Finished | Sep 09 09:55:10 AM UTC 24 |
| Peak memory | 226328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018879081 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.2018879081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/43.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/44.rv_dm_alert_test.528207947 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 64855177 ps |
| CPU time | 0.91 seconds |
| Started | Sep 09 09:55:02 AM UTC 24 |
| Finished | Sep 09 09:55:04 AM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528207947 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.528207947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/44.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.2522687991 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 5600525981 ps |
| CPU time | 17.62 seconds |
| Started | Sep 09 09:55:02 AM UTC 24 |
| Finished | Sep 09 09:55:21 AM UTC 24 |
| Peak memory | 216096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522687991 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.2522687991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/44.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/45.rv_dm_alert_test.3403795146 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 34597968 ps |
| CPU time | 1.08 seconds |
| Started | Sep 09 09:55:02 AM UTC 24 |
| Finished | Sep 09 09:55:05 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403795146 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.3403795146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/45.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/45.rv_dm_stress_all.518019595 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 995748844 ps |
| CPU time | 1.84 seconds |
| Started | Sep 09 09:55:02 AM UTC 24 |
| Finished | Sep 09 09:55:05 AM UTC 24 |
| Peak memory | 225860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518019595 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.518019595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/45.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/46.rv_dm_alert_test.3528170564 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 70928822 ps |
| CPU time | 0.92 seconds |
| Started | Sep 09 09:55:04 AM UTC 24 |
| Finished | Sep 09 09:55:06 AM UTC 24 |
| Peak memory | 215192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528170564 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3528170564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/46.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/47.rv_dm_alert_test.4049232988 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 198404560 ps |
| CPU time | 0.98 seconds |
| Started | Sep 09 09:55:04 AM UTC 24 |
| Finished | Sep 09 09:55:06 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049232988 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.4049232988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/47.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/47.rv_dm_stress_all.805555273 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 2490708075 ps |
| CPU time | 3.36 seconds |
| Started | Sep 09 09:55:04 AM UTC 24 |
| Finished | Sep 09 09:55:08 AM UTC 24 |
| Peak memory | 216072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805555273 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.805555273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/47.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/48.rv_dm_alert_test.77080537 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 69865104 ps |
| CPU time | 1.14 seconds |
| Started | Sep 09 09:55:05 AM UTC 24 |
| Finished | Sep 09 09:55:07 AM UTC 24 |
| Peak memory | 215932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77080537 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.77080537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/48.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/48.rv_dm_stress_all.1780594912 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 4488615721 ps |
| CPU time | 8.52 seconds |
| Started | Sep 09 09:55:05 AM UTC 24 |
| Finished | Sep 09 09:55:14 AM UTC 24 |
| Peak memory | 226312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780594912 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.1780594912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/48.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/49.rv_dm_alert_test.2324405576 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 177106057 ps |
| CPU time | 0.97 seconds |
| Started | Sep 09 09:55:05 AM UTC 24 |
| Finished | Sep 09 09:55:07 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324405576 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.2324405576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/49.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/49.rv_dm_stress_all.1244356442 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 2978326313 ps |
| CPU time | 5.98 seconds |
| Started | Sep 09 09:55:05 AM UTC 24 |
| Finished | Sep 09 09:55:12 AM UTC 24 |
| Peak memory | 216116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244356442 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.1244356442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/49.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_alert_test.3865550788 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 119312135 ps |
| CPU time | 1.19 seconds |
| Started | Sep 09 09:53:36 AM UTC 24 |
| Finished | Sep 09 09:53:38 AM UTC 24 |
| Peak memory | 215936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865550788 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.3865550788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/5.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.3727594043 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 36432229937 ps |
| CPU time | 134.95 seconds |
| Started | Sep 09 09:53:33 AM UTC 24 |
| Finished | Sep 09 09:55:50 AM UTC 24 |
| Peak memory | 226504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727594043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.3727594043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/5.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.1145279820 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 2070958011 ps |
| CPU time | 11.55 seconds |
| Started | Sep 09 09:53:33 AM UTC 24 |
| Finished | Sep 09 09:53:45 AM UTC 24 |
| Peak memory | 216208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145279820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.1145279820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/5.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_buffered_enable.2929434397 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 159146295 ps |
| CPU time | 2.03 seconds |
| Started | Sep 09 09:53:34 AM UTC 24 |
| Finished | Sep 09 09:53:37 AM UTC 24 |
| Peak memory | 252564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929434397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_buffered_enable.2929434397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/5.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.2646545571 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 986344849 ps |
| CPU time | 4.57 seconds |
| Started | Sep 09 09:53:33 AM UTC 24 |
| Finished | Sep 09 09:53:38 AM UTC 24 |
| Peak memory | 216184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646545571 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl_access.2646545571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/5.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_halt_resume_whereto.3783124368 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 271150996 ps |
| CPU time | 1.46 seconds |
| Started | Sep 09 09:53:34 AM UTC 24 |
| Finished | Sep 09 09:53:36 AM UTC 24 |
| Peak memory | 213108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783124368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_halt_resume_whereto.3783124368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/5.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_sba_tl_access.918921927 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 1706640992 ps |
| CPU time | 4.16 seconds |
| Started | Sep 09 09:53:32 AM UTC 24 |
| Finished | Sep 09 09:53:38 AM UTC 24 |
| Peak memory | 216208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918921927 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.918921927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/5.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.2235625184 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5140643196 ps |
| CPU time | 14.39 seconds |
| Started | Sep 09 09:53:36 AM UTC 24 |
| Finished | Sep 09 09:53:51 AM UTC 24 |
| Peak memory | 216072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235625184 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.2235625184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/5.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.694978199 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 1474079376 ps |
| CPU time | 54.94 seconds |
| Started | Sep 09 09:53:36 AM UTC 24 |
| Finished | Sep 09 09:54:33 AM UTC 24 |
| Peak memory | 233316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=694978199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress _all_with_rand_reset.694978199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_alert_test.2856726414 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 73830217 ps |
| CPU time | 1.17 seconds |
| Started | Sep 09 09:53:42 AM UTC 24 |
| Finished | Sep 09 09:53:44 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856726414 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.2856726414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/6.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_autoincr_sba_tl_access.3576563422 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 24949933070 ps |
| CPU time | 115.09 seconds |
| Started | Sep 09 09:53:38 AM UTC 24 |
| Finished | Sep 09 09:55:36 AM UTC 24 |
| Peak memory | 226624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576563422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.3576563422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/6.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_bad_sba_tl_access.1525299413 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 6933371231 ps |
| CPU time | 17.93 seconds |
| Started | Sep 09 09:53:38 AM UTC 24 |
| Finished | Sep 09 09:53:57 AM UTC 24 |
| Peak memory | 226564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525299413 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.1525299413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/6.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_buffered_enable.2928633391 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 177355231 ps |
| CPU time | 1.31 seconds |
| Started | Sep 09 09:53:39 AM UTC 24 |
| Finished | Sep 09 09:53:42 AM UTC 24 |
| Peak memory | 256888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928633391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_buffered_enable.2928633391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/6.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.2275062060 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 5608418526 ps |
| CPU time | 11.1 seconds |
| Started | Sep 09 09:53:37 AM UTC 24 |
| Finished | Sep 09 09:53:49 AM UTC 24 |
| Peak memory | 216316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275062060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_tl_access.2275062060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/6.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_halt_resume_whereto.1585678190 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 269998126 ps |
| CPU time | 1.99 seconds |
| Started | Sep 09 09:53:39 AM UTC 24 |
| Finished | Sep 09 09:53:42 AM UTC 24 |
| Peak memory | 213068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585678190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_halt_resume_whereto.1585678190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/6.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_sba_tl_access.9340786 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 2807361624 ps |
| CPU time | 12.93 seconds |
| Started | Sep 09 09:53:37 AM UTC 24 |
| Finished | Sep 09 09:53:51 AM UTC 24 |
| Peak memory | 216324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9340786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_ dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.9340786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/6.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all.1143666271 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 3368799596 ps |
| CPU time | 10.92 seconds |
| Started | Sep 09 09:53:39 AM UTC 24 |
| Finished | Sep 09 09:53:51 AM UTC 24 |
| Peak memory | 216020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143666271 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.1143666271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/6.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all_with_rand_reset.2473088230 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 3726336425 ps |
| CPU time | 50.78 seconds |
| Started | Sep 09 09:53:41 AM UTC 24 |
| Finished | Sep 09 09:54:33 AM UTC 24 |
| Peak memory | 243512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2473088230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stres s_all_with_rand_reset.2473088230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_alert_test.3712983938 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 43734887 ps |
| CPU time | 1.09 seconds |
| Started | Sep 09 09:53:48 AM UTC 24 |
| Finished | Sep 09 09:53:50 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712983938 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.3712983938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/7.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.833905824 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 41367419859 ps |
| CPU time | 60.9 seconds |
| Started | Sep 09 09:53:44 AM UTC 24 |
| Finished | Sep 09 09:54:46 AM UTC 24 |
| Peak memory | 226544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833905824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.833905824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/7.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.474598579 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 4481833307 ps |
| CPU time | 6.05 seconds |
| Started | Sep 09 09:53:43 AM UTC 24 |
| Finished | Sep 09 09:53:50 AM UTC 24 |
| Peak memory | 216320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474598579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.474598579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/7.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_buffered_enable.2380839033 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 175032539 ps |
| CPU time | 2.19 seconds |
| Started | Sep 09 09:53:46 AM UTC 24 |
| Finished | Sep 09 09:53:49 AM UTC 24 |
| Peak memory | 252680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380839033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_buffered_enable.2380839033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/7.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3814222218 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 2759620456 ps |
| CPU time | 3.12 seconds |
| Started | Sep 09 09:53:43 AM UTC 24 |
| Finished | Sep 09 09:53:47 AM UTC 24 |
| Peak memory | 226424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814222218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_tl_access.3814222218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/7.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.3016641263 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 192989139 ps |
| CPU time | 1.72 seconds |
| Started | Sep 09 09:53:45 AM UTC 24 |
| Finished | Sep 09 09:53:48 AM UTC 24 |
| Peak memory | 213452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016641263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_halt_resume_whereto.3016641263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/7.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_sba_tl_access.4262167367 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 1421843720 ps |
| CPU time | 10.56 seconds |
| Started | Sep 09 09:53:42 AM UTC 24 |
| Finished | Sep 09 09:53:53 AM UTC 24 |
| Peak memory | 216204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262167367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.4262167367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/7.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all.394292200 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 3366449002 ps |
| CPU time | 17.21 seconds |
| Started | Sep 09 09:53:48 AM UTC 24 |
| Finished | Sep 09 09:54:06 AM UTC 24 |
| Peak memory | 226200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394292200 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.394292200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/7.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.560179193 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 3546289679 ps |
| CPU time | 66.46 seconds |
| Started | Sep 09 09:53:48 AM UTC 24 |
| Finished | Sep 09 09:54:56 AM UTC 24 |
| Peak memory | 233188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=560179193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress _all_with_rand_reset.560179193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_alert_test.1379995545 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 52598541 ps |
| CPU time | 1.06 seconds |
| Started | Sep 09 09:53:53 AM UTC 24 |
| Finished | Sep 09 09:53:55 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379995545 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.1379995545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/8.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.4087508552 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 6019500560 ps |
| CPU time | 35.17 seconds |
| Started | Sep 09 09:53:50 AM UTC 24 |
| Finished | Sep 09 09:54:27 AM UTC 24 |
| Peak memory | 226636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087508552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.4087508552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/8.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_bad_sba_tl_access.4141843132 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 3488812881 ps |
| CPU time | 3.78 seconds |
| Started | Sep 09 09:53:50 AM UTC 24 |
| Finished | Sep 09 09:53:55 AM UTC 24 |
| Peak memory | 226512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141843132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.4141843132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/8.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_buffered_enable.3703033124 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 133151735 ps |
| CPU time | 1.33 seconds |
| Started | Sep 09 09:53:52 AM UTC 24 |
| Finished | Sep 09 09:53:54 AM UTC 24 |
| Peak memory | 251692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703033124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_buffered_enable.3703033124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/8.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.3095282925 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 4411980038 ps |
| CPU time | 9.31 seconds |
| Started | Sep 09 09:53:50 AM UTC 24 |
| Finished | Sep 09 09:54:01 AM UTC 24 |
| Peak memory | 216380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095282925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl_access.3095282925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/8.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_sba_tl_access.2592287530 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 2144199599 ps |
| CPU time | 4.6 seconds |
| Started | Sep 09 09:53:48 AM UTC 24 |
| Finished | Sep 09 09:53:54 AM UTC 24 |
| Peak memory | 216276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592287530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.2592287530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/8.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.3093124966 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 9836504376 ps |
| CPU time | 11.95 seconds |
| Started | Sep 09 09:53:52 AM UTC 24 |
| Finished | Sep 09 09:54:05 AM UTC 24 |
| Peak memory | 216200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093124966 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.3093124966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/8.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.1766676202 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 42631471 ps |
| CPU time | 1.28 seconds |
| Started | Sep 09 09:54:00 AM UTC 24 |
| Finished | Sep 09 09:54:03 AM UTC 24 |
| Peak memory | 215876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766676202 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.1766676202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/9.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_autoincr_sba_tl_access.2662129711 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10925235480 ps |
| CPU time | 13.91 seconds |
| Started | Sep 09 09:53:56 AM UTC 24 |
| Finished | Sep 09 09:54:11 AM UTC 24 |
| Peak memory | 226688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662129711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.2662129711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/9.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.3381049607 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 4309911794 ps |
| CPU time | 16.29 seconds |
| Started | Sep 09 09:53:55 AM UTC 24 |
| Finished | Sep 09 09:54:12 AM UTC 24 |
| Peak memory | 216264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381049607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.3381049607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/9.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_buffered_enable.243522176 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 571253816 ps |
| CPU time | 2.3 seconds |
| Started | Sep 09 09:53:56 AM UTC 24 |
| Finished | Sep 09 09:53:59 AM UTC 24 |
| Peak memory | 249960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243522176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_buffered_enable.243522176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/9.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.2098642582 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 5912504176 ps |
| CPU time | 14.32 seconds |
| Started | Sep 09 09:53:55 AM UTC 24 |
| Finished | Sep 09 09:54:10 AM UTC 24 |
| Peak memory | 226424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098642582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_tl_access.2098642582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/9.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.2742562428 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 2897226797 ps |
| CPU time | 11.61 seconds |
| Started | Sep 09 09:53:54 AM UTC 24 |
| Finished | Sep 09 09:54:07 AM UTC 24 |
| Peak memory | 216324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742562428 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.2742562428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/9.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.3901628967 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1711929106 ps |
| CPU time | 3.63 seconds |
| Started | Sep 09 09:53:56 AM UTC 24 |
| Finished | Sep 09 09:54:01 AM UTC 24 |
| Peak memory | 216060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901628967 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.3901628967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/9.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.3684948728 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 3519943596 ps |
| CPU time | 58.19 seconds |
| Started | Sep 09 09:53:58 AM UTC 24 |
| Finished | Sep 09 09:54:58 AM UTC 24 |
| Peak memory | 233416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3684948728 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stres s_all_with_rand_reset.3684948728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest |
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