Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.06 96.32 90.10 92.10 94.67 90.44 98.63 61.18


Total tests in report: 483
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
53.74 53.74 84.23 84.23 54.17 54.17 33.95 33.95 41.33 41.33 65.36 65.36 92.85 92.85 4.25 4.25 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_resuming.3566593483
63.79 10.06 86.35 2.12 63.79 9.62 37.61 3.66 49.33 8.00 71.67 6.31 93.90 1.05 43.90 39.64 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.1433836236
71.80 8.00 89.82 3.48 70.58 6.79 61.13 23.53 61.33 12.00 77.99 6.31 95.90 2.00 45.82 1.92 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.3674973439
75.98 4.19 90.63 0.81 75.25 4.67 76.97 15.84 68.00 6.67 79.18 1.19 95.90 0.00 45.95 0.14 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_smoke.290819420
78.29 2.31 92.09 1.46 77.65 2.40 78.70 1.72 70.67 2.67 81.23 2.05 96.11 0.21 51.58 5.62 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.989185150
80.35 2.06 93.35 1.26 80.62 2.97 79.33 0.63 77.33 6.67 83.62 2.39 96.21 0.11 51.99 0.41 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.4190776768
81.32 0.97 93.85 0.50 81.19 0.57 83.70 4.37 77.33 0.00 84.98 1.37 96.21 0.00 51.99 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.1828040000
82.13 0.81 93.95 0.10 82.74 1.56 83.78 0.08 77.33 0.00 85.49 0.51 96.21 0.00 55.42 3.43 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.898244510
82.93 0.79 94.16 0.20 83.17 0.42 84.20 0.42 81.33 4.00 86.01 0.51 96.21 0.00 55.42 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.3283134975
83.68 0.76 94.26 0.10 83.45 0.28 84.29 0.08 85.33 4.00 86.69 0.68 96.21 0.00 55.56 0.14 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.3365173570
84.21 0.53 94.26 0.00 83.45 0.00 86.47 2.18 85.33 0.00 86.69 0.00 96.21 0.00 57.06 1.51 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/13.rv_dm_autoincr_sba_tl_access.942722584
84.74 0.52 94.61 0.35 83.88 0.42 87.52 1.05 86.67 1.33 87.20 0.51 96.21 0.00 57.06 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_buffered_enable.4222137501
85.16 0.42 94.61 0.00 84.02 0.14 87.65 0.13 89.33 2.67 87.20 0.00 96.21 0.00 57.06 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.2232180724
85.56 0.40 95.01 0.40 84.58 0.57 87.65 0.00 90.67 1.33 87.71 0.51 96.21 0.00 57.06 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.3159857702
85.90 0.34 95.01 0.00 85.01 0.42 88.82 1.18 90.67 0.00 87.71 0.00 96.32 0.11 57.75 0.69 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.3443519601
86.22 0.32 95.01 0.00 87.27 2.26 88.82 0.00 90.67 0.00 87.71 0.00 96.32 0.00 57.75 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.2502052827
86.53 0.30 95.26 0.25 87.55 0.28 89.62 0.80 90.67 0.00 88.23 0.51 96.32 0.00 58.02 0.27 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.1418616984
86.77 0.24 95.26 0.00 87.55 0.00 89.62 0.00 90.67 0.00 88.23 0.00 98.00 1.68 58.02 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3876010946
87.00 0.24 95.42 0.15 87.84 0.28 90.34 0.71 90.67 0.00 88.74 0.51 98.00 0.00 58.02 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.3367222230
87.23 0.23 95.42 0.00 87.84 0.00 90.59 0.25 92.00 1.33 88.74 0.00 98.00 0.00 58.02 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.413307025
87.44 0.21 95.42 0.00 87.84 0.00 90.59 0.00 93.33 1.33 88.74 0.00 98.00 0.00 58.16 0.14 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.2387741104
87.63 0.19 95.42 0.00 87.84 0.00 90.59 0.00 94.67 1.33 88.74 0.00 98.00 0.00 58.16 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3337973821
87.79 0.16 95.42 0.00 88.40 0.57 91.18 0.59 94.67 0.00 88.74 0.00 98.00 0.00 58.16 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.1540106918
87.95 0.16 95.57 0.15 88.54 0.14 91.26 0.08 94.67 0.00 88.91 0.17 98.00 0.00 58.71 0.55 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.3763707023
88.09 0.14 95.57 0.00 88.54 0.00 91.26 0.00 94.67 0.00 88.91 0.00 98.00 0.00 59.67 0.96 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3433103925
88.21 0.13 95.72 0.15 88.97 0.42 91.26 0.00 94.67 0.00 89.08 0.17 98.00 0.00 59.81 0.14 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/26.rv_dm_stress_all.886511029
88.31 0.10 95.77 0.05 89.11 0.14 91.43 0.17 94.67 0.00 89.42 0.34 98.00 0.00 59.81 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.674822572
88.41 0.09 95.77 0.00 89.11 0.00 91.68 0.25 94.67 0.00 89.42 0.00 98.00 0.00 60.22 0.41 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/17.rv_dm_autoincr_sba_tl_access.918853522
88.50 0.09 95.92 0.15 89.11 0.00 92.02 0.34 94.67 0.00 89.59 0.17 98.00 0.00 60.22 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.1006472624
88.59 0.09 96.07 0.15 89.25 0.14 92.02 0.00 94.67 0.00 89.76 0.17 98.00 0.00 60.36 0.14 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.3547952858
88.66 0.07 96.27 0.20 89.39 0.14 92.02 0.00 94.67 0.00 89.93 0.17 98.00 0.00 60.36 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.3829811424
88.72 0.06 96.27 0.00 89.53 0.14 92.10 0.08 94.67 0.00 90.10 0.17 98.00 0.00 60.36 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.2211221079
88.76 0.04 96.27 0.00 89.67 0.14 92.10 0.00 94.67 0.00 90.27 0.17 98.00 0.00 60.36 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.1939132694
88.80 0.04 96.27 0.00 89.96 0.28 92.10 0.00 94.67 0.00 90.27 0.00 98.00 0.00 60.36 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/11.rv_dm_stress_all.2104491297
88.84 0.04 96.27 0.00 89.96 0.00 92.10 0.00 94.67 0.00 90.27 0.00 98.00 0.00 60.63 0.27 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3007643160
88.88 0.04 96.27 0.00 89.96 0.00 92.10 0.00 94.67 0.00 90.27 0.00 98.00 0.00 60.91 0.27 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.263149654
88.91 0.03 96.32 0.05 89.96 0.00 92.10 0.00 94.67 0.00 90.44 0.17 98.00 0.00 60.91 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2279269768
88.94 0.03 96.32 0.00 89.96 0.00 92.10 0.00 94.67 0.00 90.44 0.00 98.21 0.21 60.91 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.956624563
88.97 0.03 96.32 0.00 89.96 0.00 92.10 0.00 94.67 0.00 90.44 0.00 98.42 0.21 60.91 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2405375246
88.99 0.02 96.32 0.00 90.10 0.14 92.10 0.00 94.67 0.00 90.44 0.00 98.42 0.00 60.91 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.3860634930
89.01 0.02 96.32 0.00 90.10 0.00 92.10 0.00 94.67 0.00 90.44 0.00 98.42 0.00 61.04 0.14 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.554246272
89.03 0.02 96.32 0.00 90.10 0.00 92.10 0.00 94.67 0.00 90.44 0.00 98.42 0.00 61.18 0.14 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/23.rv_dm_stress_all.129651105
89.05 0.02 96.32 0.00 90.10 0.00 92.10 0.00 94.67 0.00 90.44 0.00 98.53 0.11 61.18 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_rw.1760276233
89.06 0.02 96.32 0.00 90.10 0.00 92.10 0.00 94.67 0.00 90.44 0.00 98.63 0.11 61.18 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.693149022

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.4142790488
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2543408937
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3453745962
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.1930469294
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3761925350
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2025952534
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2351597075
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3699353930
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1123499033
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2724108116
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1827437249
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1841992078
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.543313974
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3426398841
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.3075736556
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.850844890
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2496462447
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2169632076
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3960310163
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.4064371581
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.3325429936
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1313527822
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2542706570
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.138957594
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2755075886
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3481076403
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1102526234
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.133776050
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1739523623
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.1810244705
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.530973952
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.814709886
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.863992513
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1806121406
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.1995874282
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.1273983589
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.774162956
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1517058060
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3381248146
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.2225194200
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1510733896
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2185894572
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_rw.3527088611
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.3064706299
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2115902936
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3151933410
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1250563996
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_errors.142549931
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.379743192
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2376264079
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_rw.3789419887
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2382058553
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.449402357
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1296646175
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3640996098
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Total test records in report: 483
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_smoke.290819420 Sep 09 09:53:02 AM UTC 24 Sep 09 09:53:04 AM UTC 24 864721748 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.609715462 Sep 09 09:53:03 AM UTC 24 Sep 09 09:53:06 AM UTC 24 311921549 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_halted.684636401 Sep 09 09:53:03 AM UTC 24 Sep 09 09:53:06 AM UTC 24 484707695 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_busy.512515212 Sep 09 09:53:03 AM UTC 24 Sep 09 09:53:06 AM UTC 24 422619555 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_resuming.3566593483 Sep 09 09:53:05 AM UTC 24 Sep 09 09:53:07 AM UTC 24 186709287 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_tl_access.3023243054 Sep 09 09:53:02 AM UTC 24 Sep 09 09:53:08 AM UTC 24 536543539 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_dataaddr_rw_access.3235688149 Sep 09 09:53:06 AM UTC 24 Sep 09 09:53:08 AM UTC 24 87637302 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_hart_unavail.1712495052 Sep 09 09:53:06 AM UTC 24 Sep 09 09:53:08 AM UTC 24 211020252 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.2932027473 Sep 09 09:53:03 AM UTC 24 Sep 09 09:53:09 AM UTC 24 875669603 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.1418616984 Sep 09 09:53:07 AM UTC 24 Sep 09 09:53:10 AM UTC 24 593567325 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.3860634930 Sep 09 09:53:06 AM UTC 24 Sep 09 09:53:10 AM UTC 24 692048324 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.3674973439 Sep 09 09:53:02 AM UTC 24 Sep 09 09:53:10 AM UTC 24 2752707800 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.502771486 Sep 09 09:53:02 AM UTC 24 Sep 09 09:53:11 AM UTC 24 6725598796 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_idle_hint.3510545354 Sep 09 09:53:08 AM UTC 24 Sep 09 09:53:11 AM UTC 24 118575039 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.674822572 Sep 09 09:53:09 AM UTC 24 Sep 09 09:53:11 AM UTC 24 86751525 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.3399680590 Sep 09 09:53:07 AM UTC 24 Sep 09 09:53:11 AM UTC 24 661579324 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.396693734 Sep 09 09:53:09 AM UTC 24 Sep 09 09:53:12 AM UTC 24 708542735 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2644892529 Sep 09 09:53:09 AM UTC 24 Sep 09 09:53:12 AM UTC 24 180423152 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_debug_disabled.1776735932 Sep 09 09:53:10 AM UTC 24 Sep 09 09:53:12 AM UTC 24 78786893 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.757838201 Sep 09 09:53:08 AM UTC 24 Sep 09 09:53:13 AM UTC 24 629556956 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.2502052827 Sep 09 09:53:11 AM UTC 24 Sep 09 09:53:13 AM UTC 24 93753615 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.3159857702 Sep 09 09:53:11 AM UTC 24 Sep 09 09:53:13 AM UTC 24 120967064 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_hartsel_warl.1697809622 Sep 09 09:53:11 AM UTC 24 Sep 09 09:53:13 AM UTC 24 72026683 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.693149022 Sep 09 09:53:11 AM UTC 24 Sep 09 09:53:14 AM UTC 24 100431323 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.4009696372 Sep 09 09:53:11 AM UTC 24 Sep 09 09:53:14 AM UTC 24 139076787 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.1939132694 Sep 09 09:53:07 AM UTC 24 Sep 09 09:53:14 AM UTC 24 1573707863 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.1540106918 Sep 09 09:53:13 AM UTC 24 Sep 09 09:53:15 AM UTC 24 64134999 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.450528028 Sep 09 09:53:10 AM UTC 24 Sep 09 09:53:15 AM UTC 24 1285275670 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2502001664 Sep 09 09:53:08 AM UTC 24 Sep 09 09:53:15 AM UTC 24 2033316200 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_not_supported.2721084638 Sep 09 09:53:14 AM UTC 24 Sep 09 09:53:16 AM UTC 24 182605912 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.3365173570 Sep 09 09:53:02 AM UTC 24 Sep 09 09:53:16 AM UTC 24 4961528314 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.1828040000 Sep 09 09:53:14 AM UTC 24 Sep 09 09:53:16 AM UTC 24 118226495 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_busy.3049739596 Sep 09 09:53:14 AM UTC 24 Sep 09 09:53:17 AM UTC 24 711394276 ps
T160 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_hart_unavail.3426155652 Sep 09 09:53:15 AM UTC 24 Sep 09 09:53:17 AM UTC 24 316605755 ps
T161 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_halted.1855990457 Sep 09 09:53:15 AM UTC 24 Sep 09 09:53:18 AM UTC 24 139404438 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_resuming.651155546 Sep 09 09:53:15 AM UTC 24 Sep 09 09:53:18 AM UTC 24 350869133 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.1006472624 Sep 09 09:53:13 AM UTC 24 Sep 09 09:53:18 AM UTC 24 1996901088 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_dataaddr_rw_access.3349247674 Sep 09 09:53:16 AM UTC 24 Sep 09 09:53:18 AM UTC 24 67956711 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.1673927140 Sep 09 09:53:16 AM UTC 24 Sep 09 09:53:18 AM UTC 24 332056043 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_halt_resume_whereto.1899688937 Sep 09 09:53:17 AM UTC 24 Sep 09 09:53:20 AM UTC 24 202123359 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_smoke.3578352871 Sep 09 09:53:13 AM UTC 24 Sep 09 09:53:20 AM UTC 24 1957012018 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.3469146893 Sep 09 09:53:18 AM UTC 24 Sep 09 09:53:20 AM UTC 24 294426170 ps
T177 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.1189768110 Sep 09 09:53:19 AM UTC 24 Sep 09 09:53:21 AM UTC 24 128706944 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_ndmreset_req.2327879148 Sep 09 09:53:18 AM UTC 24 Sep 09 09:53:21 AM UTC 24 388272612 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1281846161 Sep 09 09:53:18 AM UTC 24 Sep 09 09:53:21 AM UTC 24 796338901 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_hard_reset.2298703492 Sep 09 09:53:19 AM UTC 24 Sep 09 09:53:21 AM UTC 24 176166284 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_debug_disabled.3126215954 Sep 09 09:53:19 AM UTC 24 Sep 09 09:53:21 AM UTC 24 55805745 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.2211221079 Sep 09 09:53:14 AM UTC 24 Sep 09 09:53:21 AM UTC 24 5318011257 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_abstractcmd_status.2814758781 Sep 09 09:53:19 AM UTC 24 Sep 09 09:53:21 AM UTC 24 359919407 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_rom_read_access.96727411 Sep 09 09:53:19 AM UTC 24 Sep 09 09:53:21 AM UTC 24 59179341 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.2362412394 Sep 09 09:53:13 AM UTC 24 Sep 09 09:53:22 AM UTC 24 998332598 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_tl_access.680137360 Sep 09 09:53:13 AM UTC 24 Sep 09 09:53:22 AM UTC 24 5275083637 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_progbuf_read_write_execute.2200004009 Sep 09 09:53:19 AM UTC 24 Sep 09 09:53:22 AM UTC 24 1082722019 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_debug_disabled.2539043239 Sep 09 09:53:18 AM UTC 24 Sep 09 09:53:22 AM UTC 24 841242371 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_buffered_enable.4222137501 Sep 09 09:53:20 AM UTC 24 Sep 09 09:53:22 AM UTC 24 395537792 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.2387741104 Sep 09 09:53:20 AM UTC 24 Sep 09 09:53:22 AM UTC 24 155594787 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_alert_test.3228630888 Sep 09 09:53:21 AM UTC 24 Sep 09 09:53:23 AM UTC 24 84180048 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.3449466549 Sep 09 09:53:21 AM UTC 24 Sep 09 09:53:23 AM UTC 24 104914670 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_sec_cm.2974069136 Sep 09 09:53:21 AM UTC 24 Sep 09 09:53:24 AM UTC 24 711723689 ps
T84 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_sparse_lc_gate_fsm.1065824295 Sep 09 09:53:23 AM UTC 24 Sep 09 09:53:24 AM UTC 24 54155219 ps
T235 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.1951506539 Sep 09 09:53:23 AM UTC 24 Sep 09 09:53:25 AM UTC 24 118128516 ps
T109 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_bad_sba_tl_access.1975749970 Sep 09 09:53:14 AM UTC 24 Sep 09 09:53:25 AM UTC 24 2885525112 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.2232085352 Sep 09 09:53:23 AM UTC 24 Sep 09 09:53:25 AM UTC 24 377955172 ps
T113 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.2674695014 Sep 09 09:53:22 AM UTC 24 Sep 09 09:53:25 AM UTC 24 2346612034 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.3759669354 Sep 09 09:53:24 AM UTC 24 Sep 09 09:53:26 AM UTC 24 32567990 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.3867773900 Sep 09 09:53:23 AM UTC 24 Sep 09 09:53:26 AM UTC 24 440165998 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.3443519601 Sep 09 09:53:24 AM UTC 24 Sep 09 09:53:27 AM UTC 24 358286622 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.4190776768 Sep 09 09:53:21 AM UTC 24 Sep 09 09:53:27 AM UTC 24 1111567240 ps
T137 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_hart_unavail.3805838274 Sep 09 09:53:25 AM UTC 24 Sep 09 09:53:27 AM UTC 24 120227534 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.2579697562 Sep 09 09:53:25 AM UTC 24 Sep 09 09:53:28 AM UTC 24 283435766 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1247197517 Sep 09 09:53:24 AM UTC 24 Sep 09 09:53:28 AM UTC 24 2589004988 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all.1485189645 Sep 09 09:53:23 AM UTC 24 Sep 09 09:53:29 AM UTC 24 1415871606 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.3568948834 Sep 09 09:53:27 AM UTC 24 Sep 09 09:53:29 AM UTC 24 41437443 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.3425341586 Sep 09 09:53:26 AM UTC 24 Sep 09 09:53:29 AM UTC 24 67738486 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_sec_cm.3296751920 Sep 09 09:53:27 AM UTC 24 Sep 09 09:53:29 AM UTC 24 868096019 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.3577758298 Sep 09 09:53:25 AM UTC 24 Sep 09 09:53:30 AM UTC 24 462461566 ps
T132 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.1492092812 Sep 09 09:53:24 AM UTC 24 Sep 09 09:53:32 AM UTC 24 3264201748 ps
T112 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.3539005579 Sep 09 09:53:25 AM UTC 24 Sep 09 09:53:32 AM UTC 24 1173639135 ps
T224 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.1605430889 Sep 09 09:53:29 AM UTC 24 Sep 09 09:53:32 AM UTC 24 129020255 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.3539028780 Sep 09 09:53:23 AM UTC 24 Sep 09 09:53:32 AM UTC 24 5215192127 ps
T218 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.3660816857 Sep 09 09:53:29 AM UTC 24 Sep 09 09:53:32 AM UTC 24 269053203 ps
T111 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.460268906 Sep 09 09:53:24 AM UTC 24 Sep 09 09:53:32 AM UTC 24 1023963550 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_buffered_enable.2086158359 Sep 09 09:53:30 AM UTC 24 Sep 09 09:53:33 AM UTC 24 294707393 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_alert_test.1049602682 Sep 09 09:53:32 AM UTC 24 Sep 09 09:53:35 AM UTC 24 45914892 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_sba_tl_access.446658407 Sep 09 09:53:28 AM UTC 24 Sep 09 09:53:35 AM UTC 24 1305347619 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.3567977755 Sep 09 09:53:27 AM UTC 24 Sep 09 09:53:35 AM UTC 24 3519851938 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_halt_resume_whereto.3783124368 Sep 09 09:53:34 AM UTC 24 Sep 09 09:53:36 AM UTC 24 271150996 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_buffered_enable.2929434397 Sep 09 09:53:34 AM UTC 24 Sep 09 09:53:37 AM UTC 24 159146295 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_sba_tl_access.918921927 Sep 09 09:53:32 AM UTC 24 Sep 09 09:53:38 AM UTC 24 1706640992 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.2646545571 Sep 09 09:53:33 AM UTC 24 Sep 09 09:53:38 AM UTC 24 986344849 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_alert_test.3865550788 Sep 09 09:53:36 AM UTC 24 Sep 09 09:53:38 AM UTC 24 119312135 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.2438145275 Sep 09 09:53:28 AM UTC 24 Sep 09 09:53:40 AM UTC 24 2811679017 ps
T178 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.3430822164 Sep 09 09:53:23 AM UTC 24 Sep 09 09:53:40 AM UTC 24 2915311081 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.3651541189 Sep 09 09:53:30 AM UTC 24 Sep 09 09:53:40 AM UTC 24 9715038625 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_buffered_enable.2928633391 Sep 09 09:53:39 AM UTC 24 Sep 09 09:53:42 AM UTC 24 177355231 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_halt_resume_whereto.1585678190 Sep 09 09:53:39 AM UTC 24 Sep 09 09:53:42 AM UTC 24 269998126 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_sec_cm.101698155 Sep 09 09:53:31 AM UTC 24 Sep 09 09:53:43 AM UTC 24 2915093587 ps
T164 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_alert_test.2856726414 Sep 09 09:53:42 AM UTC 24 Sep 09 09:53:44 AM UTC 24 73830217 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.1145279820 Sep 09 09:53:33 AM UTC 24 Sep 09 09:53:45 AM UTC 24 2070958011 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3814222218 Sep 09 09:53:43 AM UTC 24 Sep 09 09:53:47 AM UTC 24 2759620456 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_bad_sba_tl_access.1293371922 Sep 09 09:53:28 AM UTC 24 Sep 09 09:53:47 AM UTC 24 6581941847 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.1433836236 Sep 09 09:53:21 AM UTC 24 Sep 09 09:53:47 AM UTC 24 1497021713 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.3016641263 Sep 09 09:53:45 AM UTC 24 Sep 09 09:53:48 AM UTC 24 192989139 ps
T116 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_buffered_enable.2380839033 Sep 09 09:53:46 AM UTC 24 Sep 09 09:53:49 AM UTC 24 175032539 ps
T117 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.2275062060 Sep 09 09:53:37 AM UTC 24 Sep 09 09:53:49 AM UTC 24 5608418526 ps
T118 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.474598579 Sep 09 09:53:43 AM UTC 24 Sep 09 09:53:50 AM UTC 24 4481833307 ps
T119 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_alert_test.3712983938 Sep 09 09:53:48 AM UTC 24 Sep 09 09:53:50 AM UTC 24 43734887 ps
T120 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_sba_tl_access.9340786 Sep 09 09:53:37 AM UTC 24 Sep 09 09:53:51 AM UTC 24 2807361624 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.2235625184 Sep 09 09:53:36 AM UTC 24 Sep 09 09:53:51 AM UTC 24 5140643196 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all.1143666271 Sep 09 09:53:39 AM UTC 24 Sep 09 09:53:51 AM UTC 24 3368799596 ps
T121 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_sba_tl_access.4262167367 Sep 09 09:53:42 AM UTC 24 Sep 09 09:53:53 AM UTC 24 1421843720 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_buffered_enable.3703033124 Sep 09 09:53:52 AM UTC 24 Sep 09 09:53:54 AM UTC 24 133151735 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_sba_tl_access.2592287530 Sep 09 09:53:48 AM UTC 24 Sep 09 09:53:54 AM UTC 24 2144199599 ps
T230 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_alert_test.1379995545 Sep 09 09:53:53 AM UTC 24 Sep 09 09:53:55 AM UTC 24 52598541 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_bad_sba_tl_access.4141843132 Sep 09 09:53:50 AM UTC 24 Sep 09 09:53:55 AM UTC 24 3488812881 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.3283134975 Sep 09 09:53:27 AM UTC 24 Sep 09 09:53:55 AM UTC 24 2989250550 ps
T233 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_bad_sba_tl_access.1525299413 Sep 09 09:53:38 AM UTC 24 Sep 09 09:53:57 AM UTC 24 6933371231 ps
T133 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_buffered_enable.243522176 Sep 09 09:53:56 AM UTC 24 Sep 09 09:53:59 AM UTC 24 571253816 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.3901628967 Sep 09 09:53:56 AM UTC 24 Sep 09 09:54:01 AM UTC 24 1711929106 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.3095282925 Sep 09 09:53:50 AM UTC 24 Sep 09 09:54:01 AM UTC 24 4411980038 ps
T219 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.1766676202 Sep 09 09:54:00 AM UTC 24 Sep 09 09:54:03 AM UTC 24 42631471 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.3093124966 Sep 09 09:53:52 AM UTC 24 Sep 09 09:54:05 AM UTC 24 9836504376 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/10.rv_dm_sba_tl_access.1342685474 Sep 09 09:54:01 AM UTC 24 Sep 09 09:54:06 AM UTC 24 1223297411 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all.394292200 Sep 09 09:53:48 AM UTC 24 Sep 09 09:54:06 AM UTC 24 3366449002 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.2742562428 Sep 09 09:53:54 AM UTC 24 Sep 09 09:54:07 AM UTC 24 2897226797 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/10.rv_dm_bad_sba_tl_access.2210672928 Sep 09 09:54:03 AM UTC 24 Sep 09 09:54:09 AM UTC 24 1213732982 ps
T226 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/10.rv_dm_alert_test.2173385333 Sep 09 09:54:08 AM UTC 24 Sep 09 09:54:10 AM UTC 24 55212494 ps
T227 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.2098642582 Sep 09 09:53:55 AM UTC 24 Sep 09 09:54:10 AM UTC 24 5912504176 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_autoincr_sba_tl_access.2662129711 Sep 09 09:53:56 AM UTC 24 Sep 09 09:54:11 AM UTC 24 10925235480 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/11.rv_dm_sba_tl_access.1448655098 Sep 09 09:54:08 AM UTC 24 Sep 09 09:54:12 AM UTC 24 783962859 ps
T220 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.3381049607 Sep 09 09:53:55 AM UTC 24 Sep 09 09:54:12 AM UTC 24 4309911794 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/10.rv_dm_stress_all.2986451517 Sep 09 09:54:07 AM UTC 24 Sep 09 09:54:14 AM UTC 24 1068960024 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.2232180724 Sep 09 09:53:53 AM UTC 24 Sep 09 09:54:14 AM UTC 24 1391153604 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/11.rv_dm_alert_test.4249148961 Sep 09 09:54:13 AM UTC 24 Sep 09 09:54:15 AM UTC 24 87493389 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.2420405151 Sep 09 09:54:01 AM UTC 24 Sep 09 09:54:16 AM UTC 24 10030965402 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/11.rv_dm_stress_all.2104491297 Sep 09 09:54:12 AM UTC 24 Sep 09 09:54:16 AM UTC 24 2726212171 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.973382168 Sep 09 09:54:14 AM UTC 24 Sep 09 09:54:19 AM UTC 24 2867761802 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/11.rv_dm_bad_sba_tl_access.29422001 Sep 09 09:54:11 AM UTC 24 Sep 09 09:54:19 AM UTC 24 2280736744 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/12.rv_dm_alert_test.3679213479 Sep 09 09:54:17 AM UTC 24 Sep 09 09:54:20 AM UTC 24 77345223 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.512010737 Sep 09 09:54:10 AM UTC 24 Sep 09 09:54:21 AM UTC 24 4970794856 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/12.rv_dm_bad_sba_tl_access.3214797125 Sep 09 09:54:15 AM UTC 24 Sep 09 09:54:25 AM UTC 24 4186701009 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.3336172311 Sep 09 09:53:24 AM UTC 24 Sep 09 09:54:25 AM UTC 24 2683577051 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.3367222230 Sep 09 09:53:23 AM UTC 24 Sep 09 09:54:25 AM UTC 24 19855263359 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/13.rv_dm_sba_tl_access.3235623802 Sep 09 09:54:20 AM UTC 24 Sep 09 09:54:26 AM UTC 24 4297293655 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.4087508552 Sep 09 09:53:50 AM UTC 24 Sep 09 09:54:27 AM UTC 24 6019500560 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/10.rv_dm_autoincr_sba_tl_access.70752671 Sep 09 09:54:06 AM UTC 24 Sep 09 09:54:28 AM UTC 24 6563673423 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/13.rv_dm_alert_test.2258600390 Sep 09 09:54:26 AM UTC 24 Sep 09 09:54:28 AM UTC 24 215704726 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/14.rv_dm_sba_tl_access.4147979522 Sep 09 09:54:26 AM UTC 24 Sep 09 09:54:33 AM UTC 24 2124373597 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_autoincr_sba_tl_access.3209972783 Sep 09 09:53:14 AM UTC 24 Sep 09 09:54:30 AM UTC 24 22151251042 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/14.rv_dm_alert_test.1950330566 Sep 09 09:54:28 AM UTC 24 Sep 09 09:54:31 AM UTC 24 34927725 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.413307025 Sep 09 09:53:13 AM UTC 24 Sep 09 09:54:31 AM UTC 24 6275629553 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/12.rv_dm_stress_all.2490755205 Sep 09 09:54:16 AM UTC 24 Sep 09 09:54:32 AM UTC 24 7609838266 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.694978199 Sep 09 09:53:36 AM UTC 24 Sep 09 09:54:33 AM UTC 24 1474079376 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all_with_rand_reset.2473088230 Sep 09 09:53:41 AM UTC 24 Sep 09 09:54:33 AM UTC 24 3726336425 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/14.rv_dm_stress_all.2721874248 Sep 09 09:54:28 AM UTC 24 Sep 09 09:54:33 AM UTC 24 1528757366 ps
T246 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/14.rv_dm_bad_sba_tl_access.3822309945 Sep 09 09:54:27 AM UTC 24 Sep 09 09:54:35 AM UTC 24 2483980472 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/14.rv_dm_autoincr_sba_tl_access.2017686790 Sep 09 09:54:27 AM UTC 24 Sep 09 09:54:35 AM UTC 24 15679125379 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/12.rv_dm_sba_tl_access.3871801126 Sep 09 09:54:13 AM UTC 24 Sep 09 09:54:35 AM UTC 24 8462257414 ps
T248 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/13.rv_dm_bad_sba_tl_access.3612743116 Sep 09 09:54:21 AM UTC 24 Sep 09 09:54:36 AM UTC 24 5743776108 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/15.rv_dm_alert_test.1497667224 Sep 09 09:54:34 AM UTC 24 Sep 09 09:54:36 AM UTC 24 62471900 ps
T250 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/16.rv_dm_bad_sba_tl_access.56736423 Sep 09 09:54:34 AM UTC 24 Sep 09 09:54:37 AM UTC 24 904344764 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/13.rv_dm_stress_all.1926315834 Sep 09 09:54:23 AM UTC 24 Sep 09 09:54:37 AM UTC 24 3120289568 ps
T251 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.3545188427 Sep 09 09:54:26 AM UTC 24 Sep 09 09:54:37 AM UTC 24 2569347072 ps
T252 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/16.rv_dm_sba_tl_access.2381096074 Sep 09 09:54:34 AM UTC 24 Sep 09 09:54:38 AM UTC 24 969460507 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/11.rv_dm_autoincr_sba_tl_access.739543106 Sep 09 09:54:11 AM UTC 24 Sep 09 09:54:38 AM UTC 24 4044063000 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/16.rv_dm_alert_test.895662435 Sep 09 09:54:36 AM UTC 24 Sep 09 09:54:38 AM UTC 24 79323675 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.3770337870 Sep 09 09:54:34 AM UTC 24 Sep 09 09:54:40 AM UTC 24 769420894 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/17.rv_dm_alert_test.1917256275 Sep 09 09:54:39 AM UTC 24 Sep 09 09:54:41 AM UTC 24 143997134 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/12.rv_dm_autoincr_sba_tl_access.1517446784 Sep 09 09:54:16 AM UTC 24 Sep 09 09:54:41 AM UTC 24 5718187917 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/15.rv_dm_bad_sba_tl_access.4096575595 Sep 09 09:54:32 AM UTC 24 Sep 09 09:54:43 AM UTC 24 7522113994 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/17.rv_dm_sba_tl_access.515162816 Sep 09 09:54:36 AM UTC 24 Sep 09 09:54:43 AM UTC 24 1495578468 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/41.rv_dm_alert_test.150670413 Sep 09 09:55:01 AM UTC 24 Sep 09 09:55:03 AM UTC 24 152895218 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/15.rv_dm_stress_all.3558985903 Sep 09 09:54:33 AM UTC 24 Sep 09 09:54:44 AM UTC 24 6323115433 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/18.rv_dm_bad_sba_tl_access.1936915431 Sep 09 09:54:41 AM UTC 24 Sep 09 09:54:44 AM UTC 24 1369412478 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/16.rv_dm_stress_all.2810923931 Sep 09 09:54:36 AM UTC 24 Sep 09 09:54:45 AM UTC 24 5680947892 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.495553413 Sep 09 09:54:37 AM UTC 24 Sep 09 09:54:45 AM UTC 24 3976781781 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/15.rv_dm_autoincr_sba_tl_access.4093074135 Sep 09 09:54:32 AM UTC 24 Sep 09 09:54:45 AM UTC 24 5613812404 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/39.rv_dm_stress_all.3527099915 Sep 09 09:55:00 AM UTC 24 Sep 09 09:55:04 AM UTC 24 2558137226 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/16.rv_dm_autoincr_sba_tl_access.3530947475 Sep 09 09:54:36 AM UTC 24 Sep 09 09:54:46 AM UTC 24 6152195118 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/18.rv_dm_alert_test.1642330776 Sep 09 09:54:44 AM UTC 24 Sep 09 09:54:46 AM UTC 24 54237334 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.833905824 Sep 09 09:53:44 AM UTC 24 Sep 09 09:54:46 AM UTC 24 41367419859 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/19.rv_dm_alert_test.2499649024 Sep 09 09:54:46 AM UTC 24 Sep 09 09:54:49 AM UTC 24 38788675 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/18.rv_dm_autoincr_sba_tl_access.1450634838 Sep 09 09:54:42 AM UTC 24 Sep 09 09:54:50 AM UTC 24 14885535340 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.4037273301 Sep 09 09:54:31 AM UTC 24 Sep 09 09:54:50 AM UTC 24 11204619640 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/13.rv_dm_autoincr_sba_tl_access.942722584 Sep 09 09:54:22 AM UTC 24 Sep 09 09:54:50 AM UTC 24 22027368961 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/20.rv_dm_alert_test.1231979259 Sep 09 09:54:48 AM UTC 24 Sep 09 09:54:50 AM UTC 24 79464455 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/18.rv_dm_stress_all.1964957565 Sep 09 09:54:42 AM UTC 24 Sep 09 09:54:50 AM UTC 24 3630677044 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.989185150 Sep 09 09:53:30 AM UTC 24 Sep 09 09:54:50 AM UTC 24 31659755399 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/19.rv_dm_bad_sba_tl_access.521903303 Sep 09 09:54:45 AM UTC 24 Sep 09 09:54:50 AM UTC 24 1849714005 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.3468332147 Sep 09 09:54:21 AM UTC 24 Sep 09 09:54:51 AM UTC 24 8926326799 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/21.rv_dm_alert_test.1289363952 Sep 09 09:54:50 AM UTC 24 Sep 09 09:54:52 AM UTC 24 35954867 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.1437598517 Sep 09 09:54:40 AM UTC 24 Sep 09 09:54:52 AM UTC 24 8202212486 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.3020118091 Sep 09 09:54:44 AM UTC 24 Sep 09 09:54:52 AM UTC 24 2426974012 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/23.rv_dm_alert_test.320817848 Sep 09 09:54:51 AM UTC 24 Sep 09 09:54:53 AM UTC 24 30373111 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/17.rv_dm_autoincr_sba_tl_access.918853522 Sep 09 09:54:39 AM UTC 24 Sep 09 09:54:53 AM UTC 24 3409062373 ps
T174 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/24.rv_dm_alert_test.899078523 Sep 09 09:54:51 AM UTC 24 Sep 09 09:54:53 AM UTC 24 139947624 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/17.rv_dm_stress_all.2172703443 Sep 09 09:54:39 AM UTC 24 Sep 09 09:54:53 AM UTC 24 4343074018 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/22.rv_dm_alert_test.1272321024 Sep 09 09:54:51 AM UTC 24 Sep 09 09:54:54 AM UTC 24 185703999 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/25.rv_dm_alert_test.1693712985 Sep 09 09:54:52 AM UTC 24 Sep 09 09:54:54 AM UTC 24 50916337 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/17.rv_dm_bad_sba_tl_access.3032241763 Sep 09 09:54:37 AM UTC 24 Sep 09 09:54:55 AM UTC 24 5148664390 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/26.rv_dm_alert_test.2277121085 Sep 09 09:54:53 AM UTC 24 Sep 09 09:54:55 AM UTC 24 74036780 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_autoincr_sba_tl_access.3217840535 Sep 09 09:53:29 AM UTC 24 Sep 09 09:54:56 AM UTC 24 32266329453 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/27.rv_dm_alert_test.4238928214 Sep 09 09:54:53 AM UTC 24 Sep 09 09:54:56 AM UTC 24 83240696 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.560179193 Sep 09 09:53:48 AM UTC 24 Sep 09 09:54:56 AM UTC 24 3546289679 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/28.rv_dm_alert_test.4120944708 Sep 09 09:54:55 AM UTC 24 Sep 09 09:54:57 AM UTC 24 64739013 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/29.rv_dm_alert_test.1672495227 Sep 09 09:54:55 AM UTC 24 Sep 09 09:54:57 AM UTC 24 116356444 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.3765273258 Sep 09 09:54:53 AM UTC 24 Sep 09 09:54:57 AM UTC 24 1359420851 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.3763707023 Sep 09 09:54:46 AM UTC 24 Sep 09 09:54:57 AM UTC 24 5380308953 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/21.rv_dm_stress_all.3051229547 Sep 09 09:54:48 AM UTC 24 Sep 09 09:54:58 AM UTC 24 4376949854 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/18.rv_dm_sba_tl_access.1368209971 Sep 09 09:54:39 AM UTC 24 Sep 09 09:54:58 AM UTC 24 12369080797 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/29.rv_dm_stress_all.1556449947 Sep 09 09:54:55 AM UTC 24 Sep 09 09:54:58 AM UTC 24 2098812335 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.3684948728 Sep 09 09:53:58 AM UTC 24 Sep 09 09:54:58 AM UTC 24 3519943596 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.263149654 Sep 09 09:54:51 AM UTC 24 Sep 09 09:54:58 AM UTC 24 1920766242 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/30.rv_dm_alert_test.148280907 Sep 09 09:54:56 AM UTC 24 Sep 09 09:54:58 AM UTC 24 139886200 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/33.rv_dm_alert_test.1328263703 Sep 09 09:54:57 AM UTC 24 Sep 09 09:54:59 AM UTC 24 40259960 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/32.rv_dm_alert_test.3654515698 Sep 09 09:54:57 AM UTC 24 Sep 09 09:54:59 AM UTC 24 99895975 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/31.rv_dm_alert_test.995778772 Sep 09 09:54:57 AM UTC 24 Sep 09 09:54:59 AM UTC 24 56456133 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/24.rv_dm_stress_all.494749331 Sep 09 09:54:51 AM UTC 24 Sep 09 09:55:00 AM UTC 24 3143182948 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.3829811424 Sep 09 09:54:47 AM UTC 24 Sep 09 09:55:00 AM UTC 24 3488012849 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/26.rv_dm_stress_all.886511029 Sep 09 09:54:52 AM UTC 24 Sep 09 09:55:00 AM UTC 24 5171188404 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/35.rv_dm_alert_test.2565858530 Sep 09 09:54:58 AM UTC 24 Sep 09 09:55:00 AM UTC 24 36444971 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/34.rv_dm_alert_test.1590727490 Sep 09 09:54:58 AM UTC 24 Sep 09 09:55:00 AM UTC 24 139643202 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/36.rv_dm_alert_test.2030336137 Sep 09 09:54:58 AM UTC 24 Sep 09 09:55:01 AM UTC 24 114561506 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/15.rv_dm_sba_tl_access.1624540392 Sep 09 09:54:30 AM UTC 24 Sep 09 09:55:01 AM UTC 24 16934502086 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.93135933 Sep 09 09:54:57 AM UTC 24 Sep 09 09:55:01 AM UTC 24 2371174940 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/37.rv_dm_alert_test.3625355583 Sep 09 09:55:00 AM UTC 24 Sep 09 09:55:02 AM UTC 24 46076453 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/38.rv_dm_alert_test.4290478497 Sep 09 09:55:00 AM UTC 24 Sep 09 09:55:02 AM UTC 24 144754429 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/39.rv_dm_alert_test.1314953054 Sep 09 09:55:00 AM UTC 24 Sep 09 09:55:02 AM UTC 24 80897288 ps
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T310 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/48.rv_dm_alert_test.77080537 Sep 09 09:55:05 AM UTC 24 Sep 09 09:55:07 AM UTC 24 69865104 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/42.rv_dm_stress_all.4060287126 Sep 09 09:55:01 AM UTC 24 Sep 09 09:55:07 AM UTC 24 1327666677 ps
T312 /workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/coverage/default/47.rv_dm_stress_all.805555273 Sep 09 09:55:04 AM UTC 24 Sep 09 09:55:08 AM UTC 24 2490708075 ps
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