| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 89.06 | 96.32 | 90.10 | 92.10 | 94.67 | 90.44 | 98.63 | 61.18 |
| T83 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.4146338 | Sep 11 08:16:25 AM UTC 24 | Sep 11 08:17:30 AM UTC 24 | 9867428632 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.1458562380 | Sep 11 08:16:14 AM UTC 24 | Sep 11 08:17:31 AM UTC 24 | 10208218868 ps | ||
| T111 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.3075586461 | Sep 11 08:16:34 AM UTC 24 | Sep 11 08:17:34 AM UTC 24 | 3240965960 ps | ||
| T321 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/9.rv_dm_autoincr_sba_tl_access.317560610 | Sep 11 08:16:40 AM UTC 24 | Sep 11 08:17:38 AM UTC 24 | 16653216593 ps | ||
| T322 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2159783771 | Sep 11 08:16:53 AM UTC 24 | Sep 11 08:17:39 AM UTC 24 | 13456487676 ps | ||
| T323 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/12.rv_dm_autoincr_sba_tl_access.3684647433 | Sep 11 08:16:47 AM UTC 24 | Sep 11 08:17:43 AM UTC 24 | 28225306032 ps | ||
| T324 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.1515867896 | Sep 11 08:17:04 AM UTC 24 | Sep 11 08:17:47 AM UTC 24 | 45771302717 ps | ||
| T325 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.1365728103 | Sep 11 08:16:33 AM UTC 24 | Sep 11 08:18:12 AM UTC 24 | 53016020306 ps | ||
| T110 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.2905790272 | Sep 11 08:16:22 AM UTC 24 | Sep 11 08:18:32 AM UTC 24 | 18223540161 ps | ||
| T326 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/16.rv_dm_autoincr_sba_tl_access.3387735239 | Sep 11 08:16:55 AM UTC 24 | Sep 11 08:18:32 AM UTC 24 | 21737286666 ps | ||
| T73 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.2335348151 | Sep 11 08:16:38 AM UTC 24 | Sep 11 08:18:38 AM UTC 24 | 8969138927 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.826249913 | Sep 11 08:16:27 AM UTC 24 | Sep 11 08:18:49 AM UTC 24 | 28216746151 ps | ||
| T327 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.25495752 | Sep 11 08:16:26 AM UTC 24 | Sep 11 08:21:43 AM UTC 24 | 116382329380 ps | ||
| T101 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3606870470 | Sep 11 08:13:55 AM UTC 24 | Sep 11 08:13:57 AM UTC 24 | 251763169 ps | ||
| T102 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.45219012 | Sep 11 08:13:55 AM UTC 24 | Sep 11 08:13:58 AM UTC 24 | 585528100 ps | ||
| T103 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2147604914 | Sep 11 08:13:58 AM UTC 24 | Sep 11 08:14:02 AM UTC 24 | 1004601848 ps | ||
| T328 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3804329235 | Sep 11 08:13:58 AM UTC 24 | Sep 11 08:14:03 AM UTC 24 | 2436228834 ps | ||
| T329 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3968363448 | Sep 11 08:13:58 AM UTC 24 | Sep 11 08:14:05 AM UTC 24 | 1572582091 ps | ||
| T330 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.2895914395 | Sep 11 08:14:03 AM UTC 24 | Sep 11 08:14:05 AM UTC 24 | 34163967 ps | ||
| T331 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1803947014 | Sep 11 08:14:03 AM UTC 24 | Sep 11 08:14:05 AM UTC 24 | 47184635 ps | ||
| T332 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.2368440893 | Sep 11 08:14:02 AM UTC 24 | Sep 11 08:14:07 AM UTC 24 | 140168901 ps | ||
| T130 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2121089261 | Sep 11 08:14:04 AM UTC 24 | Sep 11 08:14:08 AM UTC 24 | 121333839 ps | ||
| T131 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.3970923096 | Sep 11 08:14:04 AM UTC 24 | Sep 11 08:14:08 AM UTC 24 | 58442215 ps | ||
| T333 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3670185110 | Sep 11 08:14:07 AM UTC 24 | Sep 11 08:14:09 AM UTC 24 | 110780504 ps | ||
| T112 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3001623960 | Sep 11 08:14:06 AM UTC 24 | Sep 11 08:14:11 AM UTC 24 | 155232229 ps | ||
| T334 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1734871708 | Sep 11 08:14:07 AM UTC 24 | Sep 11 08:14:11 AM UTC 24 | 683570154 ps | ||
| T335 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.884125751 | Sep 11 08:14:08 AM UTC 24 | Sep 11 08:14:12 AM UTC 24 | 1335199696 ps | ||
| T141 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1498660111 | Sep 11 08:14:10 AM UTC 24 | Sep 11 08:14:16 AM UTC 24 | 2244581176 ps | ||
| T132 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.525290027 | Sep 11 08:14:06 AM UTC 24 | Sep 11 08:14:18 AM UTC 24 | 549932308 ps | ||
| T336 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.983559457 | Sep 11 08:14:17 AM UTC 24 | Sep 11 08:14:20 AM UTC 24 | 66267415 ps | ||
| T337 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.881319728 | Sep 11 08:13:57 AM UTC 24 | Sep 11 08:14:21 AM UTC 24 | 12200927001 ps | ||
| T338 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.1873089576 | Sep 11 08:14:12 AM UTC 24 | Sep 11 08:14:21 AM UTC 24 | 415664224 ps | ||
| T339 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.607858640 | Sep 11 08:14:19 AM UTC 24 | Sep 11 08:14:21 AM UTC 24 | 35309838 ps | ||
| T340 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.832718211 | Sep 11 08:14:00 AM UTC 24 | Sep 11 08:14:23 AM UTC 24 | 19757678905 ps | ||
| T133 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.848839847 | Sep 11 08:14:20 AM UTC 24 | Sep 11 08:14:25 AM UTC 24 | 426381357 ps | ||
| T134 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.1338819440 | Sep 11 08:14:20 AM UTC 24 | Sep 11 08:14:25 AM UTC 24 | 119870449 ps | ||
| T341 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1840104845 | Sep 11 08:14:00 AM UTC 24 | Sep 11 08:14:27 AM UTC 24 | 60001977392 ps | ||
| T135 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3337877437 | Sep 11 08:13:53 AM UTC 24 | Sep 11 08:14:27 AM UTC 24 | 2624554531 ps | ||
| T115 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3754825903 | Sep 11 08:14:22 AM UTC 24 | Sep 11 08:14:27 AM UTC 24 | 261343752 ps | ||
| T342 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.87607416 | Sep 11 08:14:26 AM UTC 24 | Sep 11 08:14:28 AM UTC 24 | 154780422 ps | ||
| T136 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2573267690 | Sep 11 08:14:22 AM UTC 24 | Sep 11 08:14:28 AM UTC 24 | 167386813 ps | ||
| T343 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2106555264 | Sep 11 08:14:26 AM UTC 24 | Sep 11 08:14:29 AM UTC 24 | 459717313 ps | ||
| T344 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2928948988 | Sep 11 08:14:28 AM UTC 24 | Sep 11 08:14:34 AM UTC 24 | 2370328030 ps | ||
| T345 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.959997574 | Sep 11 08:14:28 AM UTC 24 | Sep 11 08:14:34 AM UTC 24 | 1028228840 ps | ||
| T346 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.4278494970 | Sep 11 08:14:10 AM UTC 24 | Sep 11 08:14:35 AM UTC 24 | 18806370147 ps | ||
| T347 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3142094230 | Sep 11 08:14:33 AM UTC 24 | Sep 11 08:14:35 AM UTC 24 | 86208593 ps | ||
| T348 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_walk.2666487214 | Sep 11 08:14:33 AM UTC 24 | Sep 11 08:14:36 AM UTC 24 | 36839245 ps | ||
| T142 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2052360851 | Sep 11 08:14:28 AM UTC 24 | Sep 11 08:14:36 AM UTC 24 | 4505527484 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_errors.3015062615 | Sep 11 08:14:30 AM UTC 24 | Sep 11 08:14:36 AM UTC 24 | 461558855 ps | ||
| T349 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2147414799 | Sep 11 08:14:26 AM UTC 24 | Sep 11 08:14:37 AM UTC 24 | 5357295672 ps | ||
| T137 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.690344728 | Sep 11 08:14:35 AM UTC 24 | Sep 11 08:14:39 AM UTC 24 | 326255934 ps | ||
| T138 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_rw.1737285920 | Sep 11 08:14:36 AM UTC 24 | Sep 11 08:14:39 AM UTC 24 | 112672535 ps | ||
| T350 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.4197744769 | Sep 11 08:14:37 AM UTC 24 | Sep 11 08:14:39 AM UTC 24 | 297466857 ps | ||
| T351 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.372896009 | Sep 11 08:14:39 AM UTC 24 | Sep 11 08:14:42 AM UTC 24 | 400582217 ps | ||
| T139 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2172795396 | Sep 11 08:14:37 AM UTC 24 | Sep 11 08:14:43 AM UTC 24 | 324598436 ps | ||
| T352 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.2104665247 | Sep 11 08:14:37 AM UTC 24 | Sep 11 08:14:44 AM UTC 24 | 226927734 ps | ||
| T185 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2240695391 | Sep 11 08:14:02 AM UTC 24 | Sep 11 08:14:46 AM UTC 24 | 5313920296 ps | ||
| T353 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2678916633 | Sep 11 08:14:37 AM UTC 24 | Sep 11 08:14:46 AM UTC 24 | 1336956452 ps | ||
| T354 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_walk.4284638378 | Sep 11 08:14:46 AM UTC 24 | Sep 11 08:14:49 AM UTC 24 | 76961933 ps | ||
| T355 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_partial_access.537649778 | Sep 11 08:14:47 AM UTC 24 | Sep 11 08:14:50 AM UTC 24 | 136854631 ps | ||
| T143 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1762041441 | Sep 11 08:14:41 AM UTC 24 | Sep 11 08:14:50 AM UTC 24 | 3607702043 ps | ||
| T356 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2887826739 | Sep 11 08:14:08 AM UTC 24 | Sep 11 08:14:52 AM UTC 24 | 8362621683 ps | ||
| T357 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2898645618 | Sep 11 08:14:38 AM UTC 24 | Sep 11 08:14:52 AM UTC 24 | 3257816656 ps | ||
| T358 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.43097489 | Sep 11 08:14:41 AM UTC 24 | Sep 11 08:14:52 AM UTC 24 | 3220000462 ps | ||
| T145 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2639947104 | Sep 11 08:14:49 AM UTC 24 | Sep 11 08:14:53 AM UTC 24 | 127942225 ps | ||
| T359 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1163426456 | Sep 11 08:14:28 AM UTC 24 | Sep 11 08:14:55 AM UTC 24 | 6138526244 ps | ||
| T360 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_errors.1134202776 | Sep 11 08:14:44 AM UTC 24 | Sep 11 08:14:55 AM UTC 24 | 567055572 ps | ||
| T146 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_rw.565652430 | Sep 11 08:14:51 AM UTC 24 | Sep 11 08:14:55 AM UTC 24 | 126046065 ps | ||
| T361 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.4149590776 | Sep 11 08:14:53 AM UTC 24 | Sep 11 08:14:55 AM UTC 24 | 241304526 ps | ||
| T362 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.4093070528 | Sep 11 08:14:54 AM UTC 24 | Sep 11 08:14:57 AM UTC 24 | 171613225 ps | ||
| T363 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3062999400 | Sep 11 08:14:53 AM UTC 24 | Sep 11 08:14:57 AM UTC 24 | 149779524 ps | ||
| T364 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3773535025 | Sep 11 08:15:10 AM UTC 24 | Sep 11 08:15:12 AM UTC 24 | 541086972 ps | ||
| T174 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.718402829 | Sep 11 08:14:13 AM UTC 24 | Sep 11 08:14:57 AM UTC 24 | 6429100544 ps | ||
| T162 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2221176690 | Sep 11 08:14:52 AM UTC 24 | Sep 11 08:14:58 AM UTC 24 | 526661643 ps | ||
| T365 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1940058300 | Sep 11 08:14:55 AM UTC 24 | Sep 11 08:15:00 AM UTC 24 | 521628836 ps | ||
| T366 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_walk.1988372332 | Sep 11 08:15:01 AM UTC 24 | Sep 11 08:15:03 AM UTC 24 | 199487940 ps | ||
| T147 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1068845919 | Sep 11 08:14:24 AM UTC 24 | Sep 11 08:15:03 AM UTC 24 | 9065818636 ps | ||
| T367 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1913181146 | Sep 11 08:15:02 AM UTC 24 | Sep 11 08:15:04 AM UTC 24 | 39900944 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_errors.3484937550 | Sep 11 08:14:58 AM UTC 24 | Sep 11 08:15:05 AM UTC 24 | 206681186 ps | ||
| T368 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.4263896153 | Sep 11 08:14:56 AM UTC 24 | Sep 11 08:15:05 AM UTC 24 | 1137340110 ps | ||
| T176 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.844011139 | Sep 11 08:14:30 AM UTC 24 | Sep 11 08:15:05 AM UTC 24 | 4712114390 ps | ||
| T369 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.586144885 | Sep 11 08:14:55 AM UTC 24 | Sep 11 08:15:07 AM UTC 24 | 12090108253 ps | ||
| T104 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.1048604065 | Sep 11 08:14:12 AM UTC 24 | Sep 11 08:15:07 AM UTC 24 | 9727632155 ps | ||
| T370 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3158422424 | Sep 11 08:15:05 AM UTC 24 | Sep 11 08:15:08 AM UTC 24 | 229853930 ps | ||
| T371 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.4188915883 | Sep 11 08:15:04 AM UTC 24 | Sep 11 08:15:08 AM UTC 24 | 303295315 ps | ||
| T148 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_rw.3522596264 | Sep 11 08:15:04 AM UTC 24 | Sep 11 08:15:08 AM UTC 24 | 124090743 ps | ||
| T372 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1917169292 | Sep 11 08:15:05 AM UTC 24 | Sep 11 08:15:09 AM UTC 24 | 204767729 ps | ||
| T373 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2108881477 | Sep 11 08:14:57 AM UTC 24 | Sep 11 08:15:09 AM UTC 24 | 3592970926 ps | ||
| T163 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2911821882 | Sep 11 08:15:04 AM UTC 24 | Sep 11 08:15:11 AM UTC 24 | 518746052 ps | ||
| T374 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3567257393 | Sep 11 08:14:44 AM UTC 24 | Sep 11 08:15:12 AM UTC 24 | 2996355644 ps | ||
| T198 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2199581279 | Sep 11 08:14:59 AM UTC 24 | Sep 11 08:15:12 AM UTC 24 | 679286679 ps | ||
| T108 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2478321059 | Sep 11 08:14:30 AM UTC 24 | Sep 11 08:15:12 AM UTC 24 | 3002837488 ps | ||
| T149 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_rw.941888998 | Sep 11 08:15:08 AM UTC 24 | Sep 11 08:15:13 AM UTC 24 | 501401995 ps | ||
| T197 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2219633736 | Sep 11 08:14:45 AM UTC 24 | Sep 11 08:15:13 AM UTC 24 | 8464684132 ps | ||
| T375 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2877984501 | Sep 11 08:15:06 AM UTC 24 | Sep 11 08:15:14 AM UTC 24 | 4595646957 ps | ||
| T376 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1434508120 | Sep 11 08:14:10 AM UTC 24 | Sep 11 08:15:14 AM UTC 24 | 14255271689 ps | ||
| T377 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3651303272 | Sep 11 08:15:10 AM UTC 24 | Sep 11 08:15:15 AM UTC 24 | 68617350 ps | ||
| T164 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.193289761 | Sep 11 08:15:08 AM UTC 24 | Sep 11 08:15:15 AM UTC 24 | 265673747 ps | ||
| T378 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_errors.2081210311 | Sep 11 08:15:13 AM UTC 24 | Sep 11 08:15:18 AM UTC 24 | 228864645 ps | ||
| T158 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_rw.2585357199 | Sep 11 08:15:14 AM UTC 24 | Sep 11 08:15:18 AM UTC 24 | 177130619 ps | ||
| T379 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_errors.2920386079 | Sep 11 08:15:08 AM UTC 24 | Sep 11 08:15:18 AM UTC 24 | 534008432 ps | ||
| T380 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2057437916 | Sep 11 08:15:15 AM UTC 24 | Sep 11 08:15:21 AM UTC 24 | 761689787 ps | ||
| T109 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3905707881 | Sep 11 08:15:15 AM UTC 24 | Sep 11 08:15:21 AM UTC 24 | 97286624 ps | ||
| T144 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2521983344 | Sep 11 08:14:56 AM UTC 24 | Sep 11 08:15:22 AM UTC 24 | 5609597441 ps | ||
| T381 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.4030396453 | Sep 11 08:15:13 AM UTC 24 | Sep 11 08:15:23 AM UTC 24 | 8105085004 ps | ||
| T382 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_rw.1050175907 | Sep 11 08:15:20 AM UTC 24 | Sep 11 08:15:23 AM UTC 24 | 158139786 ps | ||
| T165 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1305006662 | Sep 11 08:15:14 AM UTC 24 | Sep 11 08:15:25 AM UTC 24 | 778343538 ps | ||
| T383 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3241526363 | Sep 11 08:15:22 AM UTC 24 | Sep 11 08:15:26 AM UTC 24 | 323393010 ps | ||
| T384 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3215162746 | Sep 11 08:15:22 AM UTC 24 | Sep 11 08:15:26 AM UTC 24 | 77241558 ps | ||
| T385 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_errors.1546374465 | Sep 11 08:15:20 AM UTC 24 | Sep 11 08:15:26 AM UTC 24 | 223078288 ps | ||
| T159 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2696650336 | Sep 11 08:14:22 AM UTC 24 | Sep 11 08:15:28 AM UTC 24 | 5230617733 ps | ||
| T386 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1238985345 | Sep 11 08:15:23 AM UTC 24 | Sep 11 08:15:28 AM UTC 24 | 1680389142 ps | ||
| T160 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2634587163 | Sep 11 08:14:06 AM UTC 24 | Sep 11 08:15:30 AM UTC 24 | 14840393948 ps | ||
| T387 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3081065532 | Sep 11 08:15:06 AM UTC 24 | Sep 11 08:15:30 AM UTC 24 | 7378190433 ps | ||
| T388 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3983979557 | Sep 11 08:15:16 AM UTC 24 | Sep 11 08:15:30 AM UTC 24 | 3224565167 ps | ||
| T166 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1030742810 | Sep 11 08:15:21 AM UTC 24 | Sep 11 08:15:31 AM UTC 24 | 1638293826 ps | ||
| T389 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2269887987 | Sep 11 08:15:27 AM UTC 24 | Sep 11 08:15:31 AM UTC 24 | 747628412 ps | ||
| T161 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_rw.280424674 | Sep 11 08:15:27 AM UTC 24 | Sep 11 08:15:32 AM UTC 24 | 851022294 ps | ||
| T390 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.618977693 | Sep 11 08:15:29 AM UTC 24 | Sep 11 08:15:32 AM UTC 24 | 245561059 ps | ||
| T391 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.1965448266 | Sep 11 08:14:58 AM UTC 24 | Sep 11 08:15:32 AM UTC 24 | 6889856715 ps | ||
| T199 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_intg_err.212694629 | Sep 11 08:15:08 AM UTC 24 | Sep 11 08:15:33 AM UTC 24 | 6119519329 ps | ||
| T201 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_intg_err.90237329 | Sep 11 08:15:13 AM UTC 24 | Sep 11 08:15:33 AM UTC 24 | 15509509097 ps | ||
| T150 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1772835708 | Sep 11 08:14:06 AM UTC 24 | Sep 11 08:15:34 AM UTC 24 | 14240166944 ps | ||
| T392 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_rw.2992903600 | Sep 11 08:15:32 AM UTC 24 | Sep 11 08:15:35 AM UTC 24 | 77662949 ps | ||
| T393 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_errors.1871688205 | Sep 11 08:15:27 AM UTC 24 | Sep 11 08:15:35 AM UTC 24 | 877717633 ps | ||
| T394 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1089252328 | Sep 11 08:14:28 AM UTC 24 | Sep 11 08:15:36 AM UTC 24 | 57838267585 ps | ||
| T395 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.856730527 | Sep 11 08:15:33 AM UTC 24 | Sep 11 08:15:37 AM UTC 24 | 334691461 ps | ||
| T151 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.871685778 | Sep 11 08:15:27 AM UTC 24 | Sep 11 08:15:37 AM UTC 24 | 1679603840 ps | ||
| T396 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2651103377 | Sep 11 08:15:33 AM UTC 24 | Sep 11 08:15:38 AM UTC 24 | 56020290 ps | ||
| T167 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.709160884 | Sep 11 08:15:33 AM UTC 24 | Sep 11 08:15:39 AM UTC 24 | 404112753 ps | ||
| T397 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_errors.1204899972 | Sep 11 08:15:31 AM UTC 24 | Sep 11 08:15:39 AM UTC 24 | 2195936367 ps | ||
| T398 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2196787221 | Sep 11 08:15:34 AM UTC 24 | Sep 11 08:15:40 AM UTC 24 | 5528067406 ps | ||
| T399 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.3291518505 | Sep 11 08:15:36 AM UTC 24 | Sep 11 08:15:41 AM UTC 24 | 409085039 ps | ||
| T400 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3261192217 | Sep 11 08:15:37 AM UTC 24 | Sep 11 08:15:41 AM UTC 24 | 64484640 ps | ||
| T401 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.2376906267 | Sep 11 08:15:36 AM UTC 24 | Sep 11 08:15:41 AM UTC 24 | 969006829 ps | ||
| T113 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3489185124 | Sep 11 08:15:24 AM UTC 24 | Sep 11 08:15:42 AM UTC 24 | 1299578732 ps | ||
| T402 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1926034359 | Sep 11 08:15:37 AM UTC 24 | Sep 11 08:15:42 AM UTC 24 | 487616971 ps | ||
| T200 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_intg_err.4186828542 | Sep 11 08:15:20 AM UTC 24 | Sep 11 08:15:43 AM UTC 24 | 4051205314 ps | ||
| T152 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.999126330 | Sep 11 08:15:36 AM UTC 24 | Sep 11 08:15:44 AM UTC 24 | 522915669 ps | ||
| T403 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_intg_err.4229195041 | Sep 11 08:15:32 AM UTC 24 | Sep 11 08:15:45 AM UTC 24 | 1487622036 ps | ||
| T153 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_rw.739907491 | Sep 11 08:15:41 AM UTC 24 | Sep 11 08:15:45 AM UTC 24 | 361363371 ps | ||
| T404 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1685745829 | Sep 11 08:15:42 AM UTC 24 | Sep 11 08:15:45 AM UTC 24 | 202015755 ps | ||
| T114 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.679622919 | Sep 11 08:15:41 AM UTC 24 | Sep 11 08:15:45 AM UTC 24 | 59178873 ps | ||
| T405 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.4188346194 | Sep 11 08:15:38 AM UTC 24 | Sep 11 08:15:46 AM UTC 24 | 5259498142 ps | ||
| T406 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.3707353616 | Sep 11 08:15:16 AM UTC 24 | Sep 11 08:15:47 AM UTC 24 | 16148734001 ps | ||
| T407 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1555063424 | Sep 11 08:15:50 AM UTC 24 | Sep 11 08:15:55 AM UTC 24 | 2925245732 ps | ||
| T408 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3439687597 | Sep 11 08:15:53 AM UTC 24 | Sep 11 08:15:55 AM UTC 24 | 221540831 ps | ||
| T409 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_rw.61202556 | Sep 11 08:15:44 AM UTC 24 | Sep 11 08:15:48 AM UTC 24 | 353497272 ps | ||
| T410 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_errors.4096203660 | Sep 11 08:15:39 AM UTC 24 | Sep 11 08:15:48 AM UTC 24 | 92739337 ps | ||
| T411 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2069378850 | Sep 11 08:15:29 AM UTC 24 | Sep 11 08:15:48 AM UTC 24 | 4469019051 ps | ||
| T412 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1968616749 | Sep 11 08:15:49 AM UTC 24 | Sep 11 08:15:55 AM UTC 24 | 327470109 ps | ||
| T413 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1941195780 | Sep 11 08:15:46 AM UTC 24 | Sep 11 08:15:48 AM UTC 24 | 193654906 ps | ||
| T414 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2816785656 | Sep 11 08:15:38 AM UTC 24 | Sep 11 08:15:48 AM UTC 24 | 4452244990 ps | ||
| T415 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_errors.597021340 | Sep 11 08:15:43 AM UTC 24 | Sep 11 08:15:49 AM UTC 24 | 421154793 ps | ||
| T154 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3623637196 | Sep 11 08:15:41 AM UTC 24 | Sep 11 08:15:49 AM UTC 24 | 1238636466 ps | ||
| T105 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.10897340 | Sep 11 08:14:02 AM UTC 24 | Sep 11 08:15:49 AM UTC 24 | 22925293588 ps | ||
| T416 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2748068471 | Sep 11 08:15:47 AM UTC 24 | Sep 11 08:15:50 AM UTC 24 | 1219551827 ps | ||
| T417 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.505289594 | Sep 11 08:15:07 AM UTC 24 | Sep 11 08:15:50 AM UTC 24 | 4041971689 ps | ||
| T418 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2478225418 | Sep 11 08:15:34 AM UTC 24 | Sep 11 08:15:51 AM UTC 24 | 5056418337 ps | ||
| T419 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.4282694906 | Sep 11 08:15:49 AM UTC 24 | Sep 11 08:15:52 AM UTC 24 | 125072109 ps | ||
| T420 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_rw.215620783 | Sep 11 08:15:51 AM UTC 24 | Sep 11 08:15:56 AM UTC 24 | 146877488 ps | ||
| T421 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.568116678 | Sep 11 08:15:46 AM UTC 24 | Sep 11 08:15:52 AM UTC 24 | 187589215 ps | ||
| T106 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.984660680 | Sep 11 08:15:13 AM UTC 24 | Sep 11 08:15:52 AM UTC 24 | 7462909937 ps | ||
| T422 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1325065535 | Sep 11 08:14:10 AM UTC 24 | Sep 11 08:15:53 AM UTC 24 | 118468243634 ps | ||
| T423 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.4164029744 | Sep 11 08:15:45 AM UTC 24 | Sep 11 08:15:53 AM UTC 24 | 460725467 ps | ||
| T424 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_errors.4285321764 | Sep 11 08:15:48 AM UTC 24 | Sep 11 08:15:55 AM UTC 24 | 197142956 ps | ||
| T425 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_rw.3537613541 | Sep 11 08:15:49 AM UTC 24 | Sep 11 08:15:53 AM UTC 24 | 63372923 ps | ||
| T426 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.510038035 | Sep 11 08:15:49 AM UTC 24 | Sep 11 08:15:53 AM UTC 24 | 255390421 ps | ||
| T427 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.4207637871 | Sep 11 08:15:42 AM UTC 24 | Sep 11 08:15:53 AM UTC 24 | 13789429283 ps | ||
| T428 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.535881779 | Sep 11 08:15:12 AM UTC 24 | Sep 11 08:15:55 AM UTC 24 | 6561357214 ps | ||
| T429 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1855667742 | Sep 11 08:15:52 AM UTC 24 | Sep 11 08:15:55 AM UTC 24 | 256196605 ps | ||
| T430 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3198791194 | Sep 11 08:15:53 AM UTC 24 | Sep 11 08:15:57 AM UTC 24 | 2589143164 ps | ||
| T431 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_errors.2258927887 | Sep 11 08:15:50 AM UTC 24 | Sep 11 08:15:58 AM UTC 24 | 1049385049 ps | ||
| T432 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_rw.1377769600 | Sep 11 08:15:54 AM UTC 24 | Sep 11 08:15:58 AM UTC 24 | 581039284 ps | ||
| T433 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.145091785 | Sep 11 08:15:55 AM UTC 24 | Sep 11 08:15:58 AM UTC 24 | 217935015 ps | ||
| T434 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1999753800 | Sep 11 08:14:51 AM UTC 24 | Sep 11 08:15:59 AM UTC 24 | 4920186594 ps | ||
| T435 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_rw.2632075808 | Sep 11 08:15:56 AM UTC 24 | Sep 11 08:15:59 AM UTC 24 | 52631303 ps | ||
| T436 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_errors.334653760 | Sep 11 08:15:54 AM UTC 24 | Sep 11 08:15:59 AM UTC 24 | 130939254 ps | ||
| T437 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1875244311 | Sep 11 08:15:58 AM UTC 24 | Sep 11 08:16:00 AM UTC 24 | 140257126 ps | ||
| T438 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.78369167 | Sep 11 08:15:54 AM UTC 24 | Sep 11 08:16:00 AM UTC 24 | 80356981 ps | ||
| T155 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2709202200 | Sep 11 08:14:37 AM UTC 24 | Sep 11 08:16:01 AM UTC 24 | 7039358228 ps | ||
| T439 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2542260962 | Sep 11 08:15:49 AM UTC 24 | Sep 11 08:16:01 AM UTC 24 | 1420912752 ps | ||
| T440 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1684271724 | Sep 11 08:15:57 AM UTC 24 | Sep 11 08:16:02 AM UTC 24 | 143358777 ps | ||
| T441 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2914223360 | Sep 11 08:15:55 AM UTC 24 | Sep 11 08:16:02 AM UTC 24 | 5671596981 ps | ||
| T442 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.5957157 | Sep 11 08:14:43 AM UTC 24 | Sep 11 08:16:03 AM UTC 24 | 84918059827 ps | ||
| T443 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3511492488 | Sep 11 08:15:57 AM UTC 24 | Sep 11 08:16:03 AM UTC 24 | 431594650 ps | ||
| T444 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.2421240546 | Sep 11 08:15:20 AM UTC 24 | Sep 11 08:16:03 AM UTC 24 | 2253421591 ps | ||
| T445 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_rw.3924886537 | Sep 11 08:16:00 AM UTC 24 | Sep 11 08:16:03 AM UTC 24 | 91637402 ps | ||
| T446 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_errors.3343291468 | Sep 11 08:15:56 AM UTC 24 | Sep 11 08:16:04 AM UTC 24 | 394783321 ps | ||
| T447 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.4006038050 | Sep 11 08:16:01 AM UTC 24 | Sep 11 08:16:04 AM UTC 24 | 170333967 ps | ||
| T448 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3738251883 | Sep 11 08:15:31 AM UTC 24 | Sep 11 08:16:04 AM UTC 24 | 29658341527 ps | ||
| T449 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1791498775 | Sep 11 08:15:54 AM UTC 24 | Sep 11 08:16:04 AM UTC 24 | 729177323 ps | ||
| T450 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1904125652 | Sep 11 08:15:04 AM UTC 24 | Sep 11 08:16:04 AM UTC 24 | 1473268089 ps | ||
| T451 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2955172745 | Sep 11 08:16:01 AM UTC 24 | Sep 11 08:16:05 AM UTC 24 | 2149837351 ps | ||
| T452 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3241080238 | Sep 11 08:15:41 AM UTC 24 | Sep 11 08:16:05 AM UTC 24 | 11214126233 ps | ||
| T156 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.113313947 | Sep 11 08:15:52 AM UTC 24 | Sep 11 08:16:05 AM UTC 24 | 4105843627 ps | ||
| T453 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_errors.3490162312 | Sep 11 08:15:59 AM UTC 24 | Sep 11 08:16:06 AM UTC 24 | 261880528 ps | ||
| T454 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2417867915 | Sep 11 08:16:01 AM UTC 24 | Sep 11 08:16:06 AM UTC 24 | 143396689 ps | ||
| T157 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1669883608 | Sep 11 08:14:53 AM UTC 24 | Sep 11 08:16:06 AM UTC 24 | 1190596943 ps | ||
| T202 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1231015373 | Sep 11 08:15:27 AM UTC 24 | Sep 11 08:16:06 AM UTC 24 | 5856839382 ps | ||
| T455 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.610416627 | Sep 11 08:16:00 AM UTC 24 | Sep 11 08:16:06 AM UTC 24 | 825462984 ps | ||
| T456 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_rw.2509751595 | Sep 11 08:16:04 AM UTC 24 | Sep 11 08:16:07 AM UTC 24 | 39058262 ps | ||
| T107 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1160332223 | Sep 11 08:16:04 AM UTC 24 | Sep 11 08:16:07 AM UTC 24 | 187121662 ps | ||
| T457 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.4048929385 | Sep 11 08:14:36 AM UTC 24 | Sep 11 08:16:07 AM UTC 24 | 10210471651 ps | ||
| T458 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.4220242664 | Sep 11 08:16:05 AM UTC 24 | Sep 11 08:16:07 AM UTC 24 | 147357003 ps | ||
| T459 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3523064578 | Sep 11 08:15:43 AM UTC 24 | Sep 11 08:16:07 AM UTC 24 | 2486515173 ps | ||
| T460 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_rw.295656001 | Sep 11 08:16:05 AM UTC 24 | Sep 11 08:16:08 AM UTC 24 | 221976635 ps | ||
| T461 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.4080562389 | Sep 11 08:15:59 AM UTC 24 | Sep 11 08:16:09 AM UTC 24 | 1233624414 ps | ||
| T462 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_errors.142088646 | Sep 11 08:16:03 AM UTC 24 | Sep 11 08:16:10 AM UTC 24 | 404203031 ps | ||
| T463 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.3443400078 | Sep 11 08:16:05 AM UTC 24 | Sep 11 08:16:10 AM UTC 24 | 2189602547 ps | ||
| T464 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_intg_err.4250154162 | Sep 11 08:15:36 AM UTC 24 | Sep 11 08:16:10 AM UTC 24 | 4874603545 ps | ||
| T465 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.596978859 | Sep 11 08:16:06 AM UTC 24 | Sep 11 08:16:10 AM UTC 24 | 220759507 ps | ||
| T466 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_errors.4177670461 | Sep 11 08:16:05 AM UTC 24 | Sep 11 08:16:10 AM UTC 24 | 150569890 ps | ||
| T467 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.920989590 | Sep 11 08:16:04 AM UTC 24 | Sep 11 08:16:11 AM UTC 24 | 369107302 ps | ||
| T468 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2758951914 | Sep 11 08:15:54 AM UTC 24 | Sep 11 08:16:12 AM UTC 24 | 10137347986 ps | ||
| T469 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1579767670 | Sep 11 08:16:06 AM UTC 24 | Sep 11 08:16:12 AM UTC 24 | 101001329 ps | ||
| T203 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3651078244 | Sep 11 08:15:54 AM UTC 24 | Sep 11 08:16:12 AM UTC 24 | 4390339638 ps | ||
| T470 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3119000481 | Sep 11 08:15:51 AM UTC 24 | Sep 11 08:16:13 AM UTC 24 | 6084718415 ps | ||
| T471 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.2791061878 | Sep 11 08:15:50 AM UTC 24 | Sep 11 08:16:14 AM UTC 24 | 44300187686 ps | ||
| T472 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2996796577 | Sep 11 08:15:59 AM UTC 24 | Sep 11 08:16:15 AM UTC 24 | 4591021709 ps | ||
| T204 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3902576307 | Sep 11 08:15:56 AM UTC 24 | Sep 11 08:16:15 AM UTC 24 | 2212817539 ps | ||
| T473 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.816087601 | Sep 11 08:14:41 AM UTC 24 | Sep 11 08:16:15 AM UTC 24 | 27672083746 ps | ||
| T474 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1948293415 | Sep 11 08:15:24 AM UTC 24 | Sep 11 08:16:17 AM UTC 24 | 50630859846 ps | ||
| T475 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.2787888116 | Sep 11 08:15:59 AM UTC 24 | Sep 11 08:16:17 AM UTC 24 | 14701286936 ps | ||
| T476 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.13345547 | Sep 11 08:16:05 AM UTC 24 | Sep 11 08:16:18 AM UTC 24 | 10645062123 ps | ||
| T477 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2865198801 | Sep 11 08:15:43 AM UTC 24 | Sep 11 08:16:21 AM UTC 24 | 24712397155 ps | ||
| T478 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_intg_err.4108207790 | Sep 11 08:16:05 AM UTC 24 | Sep 11 08:16:21 AM UTC 24 | 1644399454 ps | ||
| T479 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_intg_err.208861495 | Sep 11 08:16:04 AM UTC 24 | Sep 11 08:16:22 AM UTC 24 | 2429404398 ps | ||
| T480 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2952859342 | Sep 11 08:14:58 AM UTC 24 | Sep 11 08:16:26 AM UTC 24 | 70805030913 ps | ||
| T481 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2478035336 | Sep 11 08:15:56 AM UTC 24 | Sep 11 08:16:31 AM UTC 24 | 9659298739 ps | ||
| T482 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1991887486 | Sep 11 08:16:03 AM UTC 24 | Sep 11 08:16:32 AM UTC 24 | 29890328770 ps | ||
| T81 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.404651097 | Sep 11 08:15:31 AM UTC 24 | Sep 11 08:16:37 AM UTC 24 | 7510658209 ps | ||
| T483 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2032191149 | Sep 11 08:15:47 AM UTC 24 | Sep 11 08:16:58 AM UTC 24 | 27442153031 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.2252838734 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 292943165 ps |
| CPU time | 1.83 seconds |
| Started | Sep 11 08:16:10 AM UTC 24 |
| Finished | Sep 11 08:16:13 AM UTC 24 |
| Peak memory | 213504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252838734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.2252838734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.4146338 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 9867428632 ps |
| CPU time | 63.68 seconds |
| Started | Sep 11 08:16:25 AM UTC 24 |
| Finished | Sep 11 08:17:30 AM UTC 24 |
| Peak memory | 243500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=4146338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_a ll_with_rand_reset.4146338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.337085340 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 3161181155 ps |
| CPU time | 7.13 seconds |
| Started | Sep 11 08:16:07 AM UTC 24 |
| Finished | Sep 11 08:16:15 AM UTC 24 |
| Peak memory | 216372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337085340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_tl_access.337085340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.3239986495 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 8338981058 ps |
| CPU time | 10.82 seconds |
| Started | Sep 11 08:16:07 AM UTC 24 |
| Finished | Sep 11 08:16:18 AM UTC 24 |
| Peak memory | 216128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239986495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.3239986495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.1310125537 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 5563406118 ps |
| CPU time | 3.52 seconds |
| Started | Sep 11 08:16:22 AM UTC 24 |
| Finished | Sep 11 08:16:26 AM UTC 24 |
| Peak memory | 226380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310125537 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.1310125537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/3.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.231766980 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 5789238556 ps |
| CPU time | 12.22 seconds |
| Started | Sep 11 08:16:20 AM UTC 24 |
| Finished | Sep 11 08:16:33 AM UTC 24 |
| Peak memory | 228528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231766980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.231766980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/2.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.723522271 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 139502116 ps |
| CPU time | 1.32 seconds |
| Started | Sep 11 08:16:13 AM UTC 24 |
| Finished | Sep 11 08:16:15 AM UTC 24 |
| Peak memory | 256808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723522271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_buffered_enable.723522271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2240695391 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 5313920296 ps |
| CPU time | 42.28 seconds |
| Started | Sep 11 08:14:02 AM UTC 24 |
| Finished | Sep 11 08:14:46 AM UTC 24 |
| Peak memory | 227768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240695391 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.2240695391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all_with_rand_reset.3367035117 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 7436258293 ps |
| CPU time | 32.32 seconds |
| Started | Sep 11 08:16:31 AM UTC 24 |
| Finished | Sep 11 08:17:05 AM UTC 24 |
| Peak memory | 233172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3367035117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stres s_all_with_rand_reset.3367035117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_resuming.429667090 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 395424143 ps |
| CPU time | 2.98 seconds |
| Started | Sep 11 08:16:08 AM UTC 24 |
| Finished | Sep 11 08:16:12 AM UTC 24 |
| Peak memory | 215856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429667090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.429667090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_resuming/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.3924966957 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 565872299 ps |
| CPU time | 2.74 seconds |
| Started | Sep 11 08:16:18 AM UTC 24 |
| Finished | Sep 11 08:16:22 AM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924966957 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.3924966957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_dmi_failed_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.2335348151 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 8969138927 ps |
| CPU time | 117.85 seconds |
| Started | Sep 11 08:16:38 AM UTC 24 |
| Finished | Sep 11 08:18:38 AM UTC 24 |
| Peak memory | 232592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2335348151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stres s_all_with_rand_reset.2335348151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.933142803 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 8304862630 ps |
| CPU time | 31.51 seconds |
| Started | Sep 11 08:16:19 AM UTC 24 |
| Finished | Sep 11 08:16:52 AM UTC 24 |
| Peak memory | 233304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=933142803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress _all_with_rand_reset.933142803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.1119772072 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 61993134 ps |
| CPU time | 0.86 seconds |
| Started | Sep 11 08:16:14 AM UTC 24 |
| Finished | Sep 11 08:16:16 AM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119772072 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.1119772072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3001623960 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 155232229 ps |
| CPU time | 3.82 seconds |
| Started | Sep 11 08:14:06 AM UTC 24 |
| Finished | Sep 11 08:14:11 AM UTC 24 |
| Peak memory | 229992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3001623960 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_r and_reset.3001623960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2478321059 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 3002837488 ps |
| CPU time | 41.01 seconds |
| Started | Sep 11 08:14:30 AM UTC 24 |
| Finished | Sep 11 08:15:12 AM UTC 24 |
| Peak memory | 227828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2478321059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_re set.2478321059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/2.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/14.rv_dm_autoincr_sba_tl_access.1463314914 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 21164477378 ps |
| CPU time | 34.01 seconds |
| Started | Sep 11 08:16:51 AM UTC 24 |
| Finished | Sep 11 08:17:27 AM UTC 24 |
| Peak memory | 226560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463314914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.1463314914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/14.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.552855755 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 44344578 ps |
| CPU time | 0.69 seconds |
| Started | Sep 11 08:16:13 AM UTC 24 |
| Finished | Sep 11 08:16:15 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552855755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_scanmode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 0.rv_dm_scanmode.552855755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_scanmode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.3970923096 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 58442215 ps |
| CPU time | 2.67 seconds |
| Started | Sep 11 08:14:04 AM UTC 24 |
| Finished | Sep 11 08:14:08 AM UTC 24 |
| Peak memory | 231804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970923096 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.3970923096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.826249913 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 28216746151 ps |
| CPU time | 138.83 seconds |
| Started | Sep 11 08:16:27 AM UTC 24 |
| Finished | Sep 11 08:18:49 AM UTC 24 |
| Peak memory | 233372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=826249913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress _all_with_rand_reset.826249913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.1515142221 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 227076706 ps |
| CPU time | 1.21 seconds |
| Started | Sep 11 08:16:16 AM UTC 24 |
| Finished | Sep 11 08:16:18 AM UTC 24 |
| Peak memory | 215932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515142221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.1515142221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_cmderr_exception/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.2479717185 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 98550822 ps |
| CPU time | 1.42 seconds |
| Started | Sep 11 08:16:13 AM UTC 24 |
| Finished | Sep 11 08:16:15 AM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479717185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.2479717185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_dmi_failed_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3905707881 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 97286624 ps |
| CPU time | 4.62 seconds |
| Started | Sep 11 08:15:15 AM UTC 24 |
| Finished | Sep 11 08:15:21 AM UTC 24 |
| Peak memory | 229900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3905707881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_r and_reset.3905707881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/6.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.2145091585 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 688137564 ps |
| CPU time | 1.66 seconds |
| Started | Sep 11 08:16:20 AM UTC 24 |
| Finished | Sep 11 08:16:23 AM UTC 24 |
| Peak memory | 253612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145091585 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.2145091585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/2.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.2695557048 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 5439562985 ps |
| CPU time | 6.59 seconds |
| Started | Sep 11 08:16:37 AM UTC 24 |
| Finished | Sep 11 08:16:44 AM UTC 24 |
| Peak memory | 228600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695557048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.2695557048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/8.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.3674718036 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 129930942 ps |
| CPU time | 1 seconds |
| Started | Sep 11 08:16:12 AM UTC 24 |
| Finished | Sep 11 08:16:14 AM UTC 24 |
| Peak memory | 225784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674718036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_rom_read_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.3674718036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_rom_read_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_intg_err.4186828542 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 4051205314 ps |
| CPU time | 21.24 seconds |
| Started | Sep 11 08:15:20 AM UTC 24 |
| Finished | Sep 11 08:15:43 AM UTC 24 |
| Peak memory | 225820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186828542 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.4186828542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/7.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1772835708 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 14240166944 ps |
| CPU time | 86.43 seconds |
| Started | Sep 11 08:14:06 AM UTC 24 |
| Finished | Sep 11 08:15:34 AM UTC 24 |
| Peak memory | 225720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772835708 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_aliasing.1772835708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.1300503797 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 6450343564 ps |
| CPU time | 14.25 seconds |
| Started | Sep 11 08:17:13 AM UTC 24 |
| Finished | Sep 11 08:17:28 AM UTC 24 |
| Peak memory | 216012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300503797 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.1300503797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/33.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.3943775543 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 456151173 ps |
| CPU time | 1.79 seconds |
| Started | Sep 11 08:16:11 AM UTC 24 |
| Finished | Sep 11 08:16:14 AM UTC 24 |
| Peak memory | 225844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943775543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.3943775543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_ndmreset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_buffered_enable.1232414228 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 213210557 ps |
| CPU time | 1.53 seconds |
| Started | Sep 11 08:16:19 AM UTC 24 |
| Finished | Sep 11 08:16:21 AM UTC 24 |
| Peak memory | 257816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232414228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_buffered_enable.1232414228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.4171133371 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 1006218768 ps |
| CPU time | 1.84 seconds |
| Started | Sep 11 08:16:10 AM UTC 24 |
| Finished | Sep 11 08:16:13 AM UTC 24 |
| Peak memory | 215992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171133371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.4171133371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_sba_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.1458562380 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 10208218868 ps |
| CPU time | 75.23 seconds |
| Started | Sep 11 08:16:14 AM UTC 24 |
| Finished | Sep 11 08:17:31 AM UTC 24 |
| Peak memory | 233196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1458562380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stres s_all_with_rand_reset.1458562380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.3075586461 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 3240965960 ps |
| CPU time | 57.84 seconds |
| Started | Sep 11 08:16:34 AM UTC 24 |
| Finished | Sep 11 08:17:34 AM UTC 24 |
| Peak memory | 243508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3075586461 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stres s_all_with_rand_reset.3075586461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.990218420 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 4084517031 ps |
| CPU time | 15.12 seconds |
| Started | Sep 11 08:16:14 AM UTC 24 |
| Finished | Sep 11 08:16:30 AM UTC 24 |
| Peak memory | 216204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990218420 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.990218420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2147604914 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 1004601848 ps |
| CPU time | 2.86 seconds |
| Started | Sep 11 08:13:58 AM UTC 24 |
| Finished | Sep 11 08:14:02 AM UTC 24 |
| Peak memory | 215140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147604914 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_aliasing.2147604914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.525290027 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 549932308 ps |
| CPU time | 10.89 seconds |
| Started | Sep 11 08:14:06 AM UTC 24 |
| Finished | Sep 11 08:14:18 AM UTC 24 |
| Peak memory | 215576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525290027 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_csr_outstanding.525290027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1498660111 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 2244581176 ps |
| CPU time | 5.33 seconds |
| Started | Sep 11 08:14:10 AM UTC 24 |
| Finished | Sep 11 08:14:16 AM UTC 24 |
| Peak memory | 215424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498660111 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_hw_reset.1498660111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.3365678341 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 1400484267 ps |
| CPU time | 2.59 seconds |
| Started | Sep 11 08:16:09 AM UTC 24 |
| Finished | Sep 11 08:16:13 AM UTC 24 |
| Peak memory | 215796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365678341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.3365678341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_cmderr_halt_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.718402829 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 6429100544 ps |
| CPU time | 42.5 seconds |
| Started | Sep 11 08:14:13 AM UTC 24 |
| Finished | Sep 11 08:14:57 AM UTC 24 |
| Peak memory | 232516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718402829 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.718402829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2219633736 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 8464684132 ps |
| CPU time | 26.21 seconds |
| Started | Sep 11 08:14:45 AM UTC 24 |
| Finished | Sep 11 08:15:13 AM UTC 24 |
| Peak memory | 231940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219633736 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.2219633736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/3.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.1439913661 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 584666444 ps |
| CPU time | 3.03 seconds |
| Started | Sep 11 08:16:08 AM UTC 24 |
| Finished | Sep 11 08:16:12 AM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439913661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.1439913661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_cmderr_exception/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_hard_reset.623225312 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 869365392 ps |
| CPU time | 1.43 seconds |
| Started | Sep 11 08:16:17 AM UTC 24 |
| Finished | Sep 11 08:16:20 AM UTC 24 |
| Peak memory | 213504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623225312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.623225312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_hard_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.2657870110 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 7593505675 ps |
| CPU time | 20.89 seconds |
| Started | Sep 11 08:16:19 AM UTC 24 |
| Finished | Sep 11 08:16:41 AM UTC 24 |
| Peak memory | 226368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657870110 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.2657870110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/11.rv_dm_autoincr_sba_tl_access.1884917806 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 5704315796 ps |
| CPU time | 20.58 seconds |
| Started | Sep 11 08:16:45 AM UTC 24 |
| Finished | Sep 11 08:17:07 AM UTC 24 |
| Peak memory | 216320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884917806 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.1884917806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/11.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.845875069 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 67161339 ps |
| CPU time | 0.93 seconds |
| Started | Sep 11 08:16:13 AM UTC 24 |
| Finished | Sep 11 08:16:15 AM UTC 24 |
| Peak memory | 225848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845875069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sparse_lc_gate_fsm.845875069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_sparse_lc_gate_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.3389219673 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 69234478 ps |
| CPU time | 0.96 seconds |
| Started | Sep 11 08:16:19 AM UTC 24 |
| Finished | Sep 11 08:16:21 AM UTC 24 |
| Peak memory | 225848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389219673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sparse_lc_gate_fsm.3389219673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_sparse_lc_gate_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3337877437 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 2624554531 ps |
| CPU time | 32.49 seconds |
| Started | Sep 11 08:13:53 AM UTC 24 |
| Finished | Sep 11 08:14:27 AM UTC 24 |
| Peak memory | 225688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337877437 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_aliasing.3337877437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2634587163 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 14840393948 ps |
| CPU time | 82.14 seconds |
| Started | Sep 11 08:14:06 AM UTC 24 |
| Finished | Sep 11 08:15:30 AM UTC 24 |
| Peak memory | 215384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634587163 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.2634587163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2121089261 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 121333839 ps |
| CPU time | 2.55 seconds |
| Started | Sep 11 08:14:04 AM UTC 24 |
| Finished | Sep 11 08:14:08 AM UTC 24 |
| Peak memory | 225596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121089261 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.2121089261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.832718211 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 19757678905 ps |
| CPU time | 21.9 seconds |
| Started | Sep 11 08:14:00 AM UTC 24 |
| Finished | Sep 11 08:14:23 AM UTC 24 |
| Peak memory | 215352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832718211 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_aliasing.832718211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1840104845 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 60001977392 ps |
| CPU time | 26.08 seconds |
| Started | Sep 11 08:14:00 AM UTC 24 |
| Finished | Sep 11 08:14:27 AM UTC 24 |
| Peak memory | 215452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840104845 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_bit_bash.1840104845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3968363448 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 1572582091 ps |
| CPU time | 5.14 seconds |
| Started | Sep 11 08:13:58 AM UTC 24 |
| Finished | Sep 11 08:14:05 AM UTC 24 |
| Peak memory | 215228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968363448 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_hw_reset.3968363448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3804329235 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 2436228834 ps |
| CPU time | 3.61 seconds |
| Started | Sep 11 08:13:58 AM UTC 24 |
| Finished | Sep 11 08:14:03 AM UTC 24 |
| Peak memory | 215508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804329235 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.3804329235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.881319728 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 12200927001 ps |
| CPU time | 22.6 seconds |
| Started | Sep 11 08:13:57 AM UTC 24 |
| Finished | Sep 11 08:14:21 AM UTC 24 |
| Peak memory | 215352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881319728 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_bit_bash.881319728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.45219012 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 585528100 ps |
| CPU time | 2.39 seconds |
| Started | Sep 11 08:13:55 AM UTC 24 |
| Finished | Sep 11 08:13:58 AM UTC 24 |
| Peak memory | 215260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45219012 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_hw_reset.45219012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3606870470 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 251763169 ps |
| CPU time | 1.45 seconds |
| Started | Sep 11 08:13:55 AM UTC 24 |
| Finished | Sep 11 08:13:57 AM UTC 24 |
| Peak memory | 214416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606870470 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.3606870470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1803947014 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 47184635 ps |
| CPU time | 0.93 seconds |
| Started | Sep 11 08:14:03 AM UTC 24 |
| Finished | Sep 11 08:14:05 AM UTC 24 |
| Peak memory | 215132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803947014 -assert nopostproc +UVM _TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_partial_access.1803947014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.2895914395 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 34163967 ps |
| CPU time | 0.96 seconds |
| Started | Sep 11 08:14:03 AM UTC 24 |
| Finished | Sep 11 08:14:05 AM UTC 24 |
| Peak memory | 215072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895914395 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.2895914395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.10897340 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 22925293588 ps |
| CPU time | 105.46 seconds |
| Started | Sep 11 08:14:02 AM UTC 24 |
| Finished | Sep 11 08:15:49 AM UTC 24 |
| Peak memory | 231864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=10897340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.10897340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.2368440893 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 140168901 ps |
| CPU time | 3.77 seconds |
| Started | Sep 11 08:14:02 AM UTC 24 |
| Finished | Sep 11 08:14:07 AM UTC 24 |
| Peak memory | 225792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368440893 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.2368440893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2696650336 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 5230617733 ps |
| CPU time | 64.71 seconds |
| Started | Sep 11 08:14:22 AM UTC 24 |
| Finished | Sep 11 08:15:28 AM UTC 24 |
| Peak memory | 225692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696650336 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.2696650336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.848839847 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 426381357 ps |
| CPU time | 3.38 seconds |
| Started | Sep 11 08:14:20 AM UTC 24 |
| Finished | Sep 11 08:14:25 AM UTC 24 |
| Peak memory | 225884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848839847 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.848839847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3754825903 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 261343752 ps |
| CPU time | 4.72 seconds |
| Started | Sep 11 08:14:22 AM UTC 24 |
| Finished | Sep 11 08:14:27 AM UTC 24 |
| Peak memory | 232656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3754825903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_r and_reset.3754825903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.1338819440 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 119870449 ps |
| CPU time | 3.81 seconds |
| Started | Sep 11 08:14:20 AM UTC 24 |
| Finished | Sep 11 08:14:25 AM UTC 24 |
| Peak memory | 225588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338819440 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.1338819440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1325065535 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 118468243634 ps |
| CPU time | 100.64 seconds |
| Started | Sep 11 08:14:10 AM UTC 24 |
| Finished | Sep 11 08:15:53 AM UTC 24 |
| Peak memory | 215484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325065535 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_aliasing.1325065535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.4278494970 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 18806370147 ps |
| CPU time | 23.52 seconds |
| Started | Sep 11 08:14:10 AM UTC 24 |
| Finished | Sep 11 08:14:35 AM UTC 24 |
| Peak memory | 215416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278494970 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_bit_bash.4278494970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1434508120 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 14255271689 ps |
| CPU time | 62.88 seconds |
| Started | Sep 11 08:14:10 AM UTC 24 |
| Finished | Sep 11 08:15:14 AM UTC 24 |
| Peak memory | 215352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434508120 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.1434508120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.884125751 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 1335199696 ps |
| CPU time | 2.64 seconds |
| Started | Sep 11 08:14:08 AM UTC 24 |
| Finished | Sep 11 08:14:12 AM UTC 24 |
| Peak memory | 215064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884125751 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_aliasing.884125751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2887826739 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 8362621683 ps |
| CPU time | 41.83 seconds |
| Started | Sep 11 08:14:08 AM UTC 24 |
| Finished | Sep 11 08:14:52 AM UTC 24 |
| Peak memory | 215512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887826739 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_bit_bash.2887826739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3670185110 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 110780504 ps |
| CPU time | 1.24 seconds |
| Started | Sep 11 08:14:07 AM UTC 24 |
| Finished | Sep 11 08:14:09 AM UTC 24 |
| Peak memory | 215136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670185110 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_hw_reset.3670185110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1734871708 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 683570154 ps |
| CPU time | 3.13 seconds |
| Started | Sep 11 08:14:07 AM UTC 24 |
| Finished | Sep 11 08:14:11 AM UTC 24 |
| Peak memory | 215132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734871708 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.1734871708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.607858640 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 35309838 ps |
| CPU time | 0.81 seconds |
| Started | Sep 11 08:14:19 AM UTC 24 |
| Finished | Sep 11 08:14:21 AM UTC 24 |
| Peak memory | 215196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607858640 -assert nopostproc +UVM_ TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_partial_access.607858640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.983559457 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 66267415 ps |
| CPU time | 1.37 seconds |
| Started | Sep 11 08:14:17 AM UTC 24 |
| Finished | Sep 11 08:14:20 AM UTC 24 |
| Peak memory | 215072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983559457 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.983559457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2573267690 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 167386813 ps |
| CPU time | 5.51 seconds |
| Started | Sep 11 08:14:22 AM UTC 24 |
| Finished | Sep 11 08:14:28 AM UTC 24 |
| Peak memory | 215408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573267690 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_csr_outstanding.2573267690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.1048604065 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 9727632155 ps |
| CPU time | 53.84 seconds |
| Started | Sep 11 08:14:12 AM UTC 24 |
| Finished | Sep 11 08:15:07 AM UTC 24 |
| Peak memory | 227916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1048604065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_re set.1048604065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.1873089576 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 415664224 ps |
| CPU time | 7.87 seconds |
| Started | Sep 11 08:14:12 AM UTC 24 |
| Finished | Sep 11 08:14:21 AM UTC 24 |
| Peak memory | 225712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873089576 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.1873089576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3261192217 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 64484640 ps |
| CPU time | 2.76 seconds |
| Started | Sep 11 08:15:37 AM UTC 24 |
| Finished | Sep 11 08:15:41 AM UTC 24 |
| Peak memory | 229836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3261192217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_ rand_reset.3261192217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/10.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.3291518505 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 409085039 ps |
| CPU time | 2.96 seconds |
| Started | Sep 11 08:15:36 AM UTC 24 |
| Finished | Sep 11 08:15:41 AM UTC 24 |
| Peak memory | 225600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291518505 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.3291518505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/10.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2478225418 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 5056418337 ps |
| CPU time | 15.66 seconds |
| Started | Sep 11 08:15:34 AM UTC 24 |
| Finished | Sep 11 08:15:51 AM UTC 24 |
| Peak memory | 215288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478225418 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_bit_bash.2478225418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/10.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2196787221 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 5528067406 ps |
| CPU time | 4.92 seconds |
| Started | Sep 11 08:15:34 AM UTC 24 |
| Finished | Sep 11 08:15:40 AM UTC 24 |
| Peak memory | 215412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196787221 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.2196787221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/10.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.856730527 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 334691461 ps |
| CPU time | 2.09 seconds |
| Started | Sep 11 08:15:33 AM UTC 24 |
| Finished | Sep 11 08:15:37 AM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856730527 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.856730527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/10.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.999126330 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 522915669 ps |
| CPU time | 6.29 seconds |
| Started | Sep 11 08:15:36 AM UTC 24 |
| Finished | Sep 11 08:15:44 AM UTC 24 |
| Peak memory | 215484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999126330 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_csr_outstanding.999126330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/10.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.2376906267 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 969006829 ps |
| CPU time | 3.79 seconds |
| Started | Sep 11 08:15:36 AM UTC 24 |
| Finished | Sep 11 08:15:41 AM UTC 24 |
| Peak memory | 225776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376906267 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.2376906267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/10.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_intg_err.4250154162 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 4874603545 ps |
| CPU time | 32.34 seconds |
| Started | Sep 11 08:15:36 AM UTC 24 |
| Finished | Sep 11 08:16:10 AM UTC 24 |
| Peak memory | 227820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250154162 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.4250154162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/10.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.679622919 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 59178873 ps |
| CPU time | 3.13 seconds |
| Started | Sep 11 08:15:41 AM UTC 24 |
| Finished | Sep 11 08:15:45 AM UTC 24 |
| Peak memory | 229896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=679622919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_r and_reset.679622919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/11.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_rw.739907491 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 361363371 ps |
| CPU time | 2.8 seconds |
| Started | Sep 11 08:15:41 AM UTC 24 |
| Finished | Sep 11 08:15:45 AM UTC 24 |
| Peak memory | 225720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739907491 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.739907491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/11.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.4188346194 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 5259498142 ps |
| CPU time | 6.21 seconds |
| Started | Sep 11 08:15:38 AM UTC 24 |
| Finished | Sep 11 08:15:46 AM UTC 24 |
| Peak memory | 215360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188346194 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_bit_bash.4188346194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/11.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2816785656 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 4452244990 ps |
| CPU time | 8.92 seconds |
| Started | Sep 11 08:15:38 AM UTC 24 |
| Finished | Sep 11 08:15:48 AM UTC 24 |
| Peak memory | 215568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816785656 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.2816785656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/11.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1926034359 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 487616971 ps |
| CPU time | 3.66 seconds |
| Started | Sep 11 08:15:37 AM UTC 24 |
| Finished | Sep 11 08:15:42 AM UTC 24 |
| Peak memory | 215128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926034359 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.1926034359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/11.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3623637196 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 1238636466 ps |
| CPU time | 6.82 seconds |
| Started | Sep 11 08:15:41 AM UTC 24 |
| Finished | Sep 11 08:15:49 AM UTC 24 |
| Peak memory | 215516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623637196 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_csr_outstanding.3623637196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/11.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_errors.4096203660 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 92739337 ps |
| CPU time | 6.8 seconds |
| Started | Sep 11 08:15:39 AM UTC 24 |
| Finished | Sep 11 08:15:48 AM UTC 24 |
| Peak memory | 227836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096203660 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.4096203660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/11.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3241080238 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 11214126233 ps |
| CPU time | 23.09 seconds |
| Started | Sep 11 08:15:41 AM UTC 24 |
| Finished | Sep 11 08:16:05 AM UTC 24 |
| Peak memory | 232516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241080238 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.3241080238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/11.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.568116678 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 187589215 ps |
| CPU time | 5.11 seconds |
| Started | Sep 11 08:15:46 AM UTC 24 |
| Finished | Sep 11 08:15:52 AM UTC 24 |
| Peak memory | 231784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=568116678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_r and_reset.568116678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/12.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_rw.61202556 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 353497272 ps |
| CPU time | 2.03 seconds |
| Started | Sep 11 08:15:44 AM UTC 24 |
| Finished | Sep 11 08:15:48 AM UTC 24 |
| Peak memory | 225724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61202556 -assert nopostproc +UVM_TESTNAME=rv_dm_ba se_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv _dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.61202556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/12.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2865198801 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 24712397155 ps |
| CPU time | 36.68 seconds |
| Started | Sep 11 08:15:43 AM UTC 24 |
| Finished | Sep 11 08:16:21 AM UTC 24 |
| Peak memory | 215452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865198801 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_bit_bash.2865198801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/12.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.4207637871 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 13789429283 ps |
| CPU time | 10.06 seconds |
| Started | Sep 11 08:15:42 AM UTC 24 |
| Finished | Sep 11 08:15:53 AM UTC 24 |
| Peak memory | 215412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207637871 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.4207637871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/12.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1685745829 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 202015755 ps |
| CPU time | 1.93 seconds |
| Started | Sep 11 08:15:42 AM UTC 24 |
| Finished | Sep 11 08:15:45 AM UTC 24 |
| Peak memory | 215128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685745829 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.1685745829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/12.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.4164029744 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 460725467 ps |
| CPU time | 6.18 seconds |
| Started | Sep 11 08:15:45 AM UTC 24 |
| Finished | Sep 11 08:15:53 AM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164029744 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same_csr_outstanding.4164029744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/12.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_errors.597021340 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 421154793 ps |
| CPU time | 4.64 seconds |
| Started | Sep 11 08:15:43 AM UTC 24 |
| Finished | Sep 11 08:15:49 AM UTC 24 |
| Peak memory | 225848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597021340 -assert nopostproc +UVM_TESTNAME=rv_dm_base _test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.597021340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/12.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3523064578 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 2486515173 ps |
| CPU time | 22.79 seconds |
| Started | Sep 11 08:15:43 AM UTC 24 |
| Finished | Sep 11 08:16:07 AM UTC 24 |
| Peak memory | 232520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523064578 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.3523064578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/12.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.510038035 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 255390421 ps |
| CPU time | 3.16 seconds |
| Started | Sep 11 08:15:49 AM UTC 24 |
| Finished | Sep 11 08:15:53 AM UTC 24 |
| Peak memory | 225740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=510038035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_r and_reset.510038035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/13.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_rw.3537613541 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 63372923 ps |
| CPU time | 3.14 seconds |
| Started | Sep 11 08:15:49 AM UTC 24 |
| Finished | Sep 11 08:15:53 AM UTC 24 |
| Peak memory | 225716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537613541 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.3537613541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/13.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2032191149 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 27442153031 ps |
| CPU time | 69.5 seconds |
| Started | Sep 11 08:15:47 AM UTC 24 |
| Finished | Sep 11 08:16:58 AM UTC 24 |
| Peak memory | 215452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032191149 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_bit_bash.2032191149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/13.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2748068471 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 1219551827 ps |
| CPU time | 2.27 seconds |
| Started | Sep 11 08:15:47 AM UTC 24 |
| Finished | Sep 11 08:15:50 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748068471 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.2748068471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/13.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1941195780 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 193654906 ps |
| CPU time | 1.48 seconds |
| Started | Sep 11 08:15:46 AM UTC 24 |
| Finished | Sep 11 08:15:48 AM UTC 24 |
| Peak memory | 214924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941195780 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.1941195780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/13.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1968616749 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 327470109 ps |
| CPU time | 5.18 seconds |
| Started | Sep 11 08:15:49 AM UTC 24 |
| Finished | Sep 11 08:15:55 AM UTC 24 |
| Peak memory | 215408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968616749 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_csr_outstanding.1968616749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/13.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_errors.4285321764 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 197142956 ps |
| CPU time | 5.91 seconds |
| Started | Sep 11 08:15:48 AM UTC 24 |
| Finished | Sep 11 08:15:55 AM UTC 24 |
| Peak memory | 225780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285321764 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.4285321764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/13.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2542260962 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 1420912752 ps |
| CPU time | 11.39 seconds |
| Started | Sep 11 08:15:49 AM UTC 24 |
| Finished | Sep 11 08:16:01 AM UTC 24 |
| Peak memory | 225656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542260962 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.2542260962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/13.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1855667742 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 256196605 ps |
| CPU time | 2.39 seconds |
| Started | Sep 11 08:15:52 AM UTC 24 |
| Finished | Sep 11 08:15:55 AM UTC 24 |
| Peak memory | 227848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1855667742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_ rand_reset.1855667742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/14.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_rw.215620783 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 146877488 ps |
| CPU time | 3.23 seconds |
| Started | Sep 11 08:15:51 AM UTC 24 |
| Finished | Sep 11 08:15:56 AM UTC 24 |
| Peak memory | 225716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215620783 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.215620783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/14.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.2791061878 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 44300187686 ps |
| CPU time | 22.86 seconds |
| Started | Sep 11 08:15:50 AM UTC 24 |
| Finished | Sep 11 08:16:14 AM UTC 24 |
| Peak memory | 215288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791061878 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_bit_bash.2791061878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/14.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1555063424 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 2925245732 ps |
| CPU time | 3.34 seconds |
| Started | Sep 11 08:15:50 AM UTC 24 |
| Finished | Sep 11 08:15:55 AM UTC 24 |
| Peak memory | 215348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555063424 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.1555063424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/14.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.4282694906 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 125072109 ps |
| CPU time | 1.67 seconds |
| Started | Sep 11 08:15:49 AM UTC 24 |
| Finished | Sep 11 08:15:52 AM UTC 24 |
| Peak memory | 215128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282694906 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.4282694906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/14.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.113313947 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 4105843627 ps |
| CPU time | 12.87 seconds |
| Started | Sep 11 08:15:52 AM UTC 24 |
| Finished | Sep 11 08:16:05 AM UTC 24 |
| Peak memory | 215612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113313947 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same_csr_outstanding.113313947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/14.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_errors.2258927887 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 1049385049 ps |
| CPU time | 6.29 seconds |
| Started | Sep 11 08:15:50 AM UTC 24 |
| Finished | Sep 11 08:15:58 AM UTC 24 |
| Peak memory | 225840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258927887 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.2258927887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/14.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3119000481 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 6084718415 ps |
| CPU time | 20.81 seconds |
| Started | Sep 11 08:15:51 AM UTC 24 |
| Finished | Sep 11 08:16:13 AM UTC 24 |
| Peak memory | 225764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119000481 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.3119000481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/14.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.78369167 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 80356981 ps |
| CPU time | 5.04 seconds |
| Started | Sep 11 08:15:54 AM UTC 24 |
| Finished | Sep 11 08:16:00 AM UTC 24 |
| Peak memory | 232208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=78369167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_ra nd_reset.78369167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/15.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_rw.1377769600 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 581039284 ps |
| CPU time | 3.42 seconds |
| Started | Sep 11 08:15:54 AM UTC 24 |
| Finished | Sep 11 08:15:58 AM UTC 24 |
| Peak memory | 225596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377769600 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.1377769600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/15.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2758951914 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 10137347986 ps |
| CPU time | 16.66 seconds |
| Started | Sep 11 08:15:54 AM UTC 24 |
| Finished | Sep 11 08:16:12 AM UTC 24 |
| Peak memory | 215288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758951914 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_bit_bash.2758951914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/15.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3198791194 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 2589143164 ps |
| CPU time | 3.42 seconds |
| Started | Sep 11 08:15:53 AM UTC 24 |
| Finished | Sep 11 08:15:57 AM UTC 24 |
| Peak memory | 215412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198791194 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.3198791194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/15.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3439687597 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 221540831 ps |
| CPU time | 1.02 seconds |
| Started | Sep 11 08:15:53 AM UTC 24 |
| Finished | Sep 11 08:15:55 AM UTC 24 |
| Peak memory | 215068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439687597 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.3439687597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/15.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1791498775 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 729177323 ps |
| CPU time | 9.16 seconds |
| Started | Sep 11 08:15:54 AM UTC 24 |
| Finished | Sep 11 08:16:04 AM UTC 24 |
| Peak memory | 215488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791498775 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_csr_outstanding.1791498775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/15.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_errors.334653760 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 130939254 ps |
| CPU time | 4.41 seconds |
| Started | Sep 11 08:15:54 AM UTC 24 |
| Finished | Sep 11 08:15:59 AM UTC 24 |
| Peak memory | 225660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334653760 -assert nopostproc +UVM_TESTNAME=rv_dm_base _test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.334653760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/15.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3651078244 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 4390339638 ps |
| CPU time | 17.39 seconds |
| Started | Sep 11 08:15:54 AM UTC 24 |
| Finished | Sep 11 08:16:12 AM UTC 24 |
| Peak memory | 225828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651078244 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.3651078244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/15.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1684271724 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 143358777 ps |
| CPU time | 4.19 seconds |
| Started | Sep 11 08:15:57 AM UTC 24 |
| Finished | Sep 11 08:16:02 AM UTC 24 |
| Peak memory | 229856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1684271724 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_ rand_reset.1684271724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/16.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_rw.2632075808 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 52631303 ps |
| CPU time | 2.12 seconds |
| Started | Sep 11 08:15:56 AM UTC 24 |
| Finished | Sep 11 08:15:59 AM UTC 24 |
| Peak memory | 225592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632075808 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.2632075808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/16.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2478035336 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 9659298739 ps |
| CPU time | 33.69 seconds |
| Started | Sep 11 08:15:56 AM UTC 24 |
| Finished | Sep 11 08:16:31 AM UTC 24 |
| Peak memory | 215516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478035336 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_bit_bash.2478035336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/16.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2914223360 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 5671596981 ps |
| CPU time | 5.9 seconds |
| Started | Sep 11 08:15:55 AM UTC 24 |
| Finished | Sep 11 08:16:02 AM UTC 24 |
| Peak memory | 215348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914223360 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.2914223360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/16.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.145091785 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 217935015 ps |
| CPU time | 1.91 seconds |
| Started | Sep 11 08:15:55 AM UTC 24 |
| Finished | Sep 11 08:15:58 AM UTC 24 |
| Peak memory | 215076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145091785 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.145091785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/16.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3511492488 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 431594650 ps |
| CPU time | 5.22 seconds |
| Started | Sep 11 08:15:57 AM UTC 24 |
| Finished | Sep 11 08:16:03 AM UTC 24 |
| Peak memory | 215424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511492488 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_csr_outstanding.3511492488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/16.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_errors.3343291468 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 394783321 ps |
| CPU time | 6.89 seconds |
| Started | Sep 11 08:15:56 AM UTC 24 |
| Finished | Sep 11 08:16:04 AM UTC 24 |
| Peak memory | 225840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343291468 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.3343291468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/16.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3902576307 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 2212817539 ps |
| CPU time | 18.07 seconds |
| Started | Sep 11 08:15:56 AM UTC 24 |
| Finished | Sep 11 08:16:15 AM UTC 24 |
| Peak memory | 227776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902576307 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.3902576307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/16.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2417867915 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 143396689 ps |
| CPU time | 3.36 seconds |
| Started | Sep 11 08:16:01 AM UTC 24 |
| Finished | Sep 11 08:16:06 AM UTC 24 |
| Peak memory | 231800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2417867915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_ rand_reset.2417867915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/17.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_rw.3924886537 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 91637402 ps |
| CPU time | 2.25 seconds |
| Started | Sep 11 08:16:00 AM UTC 24 |
| Finished | Sep 11 08:16:03 AM UTC 24 |
| Peak memory | 225656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924886537 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.3924886537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/17.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.2787888116 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 14701286936 ps |
| CPU time | 17.15 seconds |
| Started | Sep 11 08:15:59 AM UTC 24 |
| Finished | Sep 11 08:16:17 AM UTC 24 |
| Peak memory | 215452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787888116 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_bit_bash.2787888116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/17.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2996796577 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 4591021709 ps |
| CPU time | 14.45 seconds |
| Started | Sep 11 08:15:59 AM UTC 24 |
| Finished | Sep 11 08:16:15 AM UTC 24 |
| Peak memory | 215444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996796577 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.2996796577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/17.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1875244311 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 140257126 ps |
| CPU time | 1.28 seconds |
| Started | Sep 11 08:15:58 AM UTC 24 |
| Finished | Sep 11 08:16:00 AM UTC 24 |
| Peak memory | 215068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875244311 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.1875244311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/17.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.610416627 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 825462984 ps |
| CPU time | 5.18 seconds |
| Started | Sep 11 08:16:00 AM UTC 24 |
| Finished | Sep 11 08:16:06 AM UTC 24 |
| Peak memory | 215616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610416627 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same_csr_outstanding.610416627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/17.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_errors.3490162312 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 261880528 ps |
| CPU time | 5.54 seconds |
| Started | Sep 11 08:15:59 AM UTC 24 |
| Finished | Sep 11 08:16:06 AM UTC 24 |
| Peak memory | 225716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490162312 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.3490162312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/17.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.4080562389 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 1233624414 ps |
| CPU time | 9.07 seconds |
| Started | Sep 11 08:15:59 AM UTC 24 |
| Finished | Sep 11 08:16:09 AM UTC 24 |
| Peak memory | 225700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080562389 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.4080562389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/17.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1160332223 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 187121662 ps |
| CPU time | 1.98 seconds |
| Started | Sep 11 08:16:04 AM UTC 24 |
| Finished | Sep 11 08:16:07 AM UTC 24 |
| Peak memory | 231796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1160332223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_ rand_reset.1160332223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/18.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_rw.2509751595 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 39058262 ps |
| CPU time | 2.02 seconds |
| Started | Sep 11 08:16:04 AM UTC 24 |
| Finished | Sep 11 08:16:07 AM UTC 24 |
| Peak memory | 225780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509751595 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.2509751595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/18.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1991887486 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 29890328770 ps |
| CPU time | 27.76 seconds |
| Started | Sep 11 08:16:03 AM UTC 24 |
| Finished | Sep 11 08:16:32 AM UTC 24 |
| Peak memory | 215396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991887486 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_bit_bash.1991887486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/18.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2955172745 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 2149837351 ps |
| CPU time | 2.39 seconds |
| Started | Sep 11 08:16:01 AM UTC 24 |
| Finished | Sep 11 08:16:05 AM UTC 24 |
| Peak memory | 215440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955172745 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.2955172745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/18.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.4006038050 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 170333967 ps |
| CPU time | 1.28 seconds |
| Started | Sep 11 08:16:01 AM UTC 24 |
| Finished | Sep 11 08:16:04 AM UTC 24 |
| Peak memory | 215068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006038050 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.4006038050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/18.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.920989590 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 369107302 ps |
| CPU time | 6.61 seconds |
| Started | Sep 11 08:16:04 AM UTC 24 |
| Finished | Sep 11 08:16:11 AM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920989590 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same_csr_outstanding.920989590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/18.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_errors.142088646 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 404203031 ps |
| CPU time | 5.93 seconds |
| Started | Sep 11 08:16:03 AM UTC 24 |
| Finished | Sep 11 08:16:10 AM UTC 24 |
| Peak memory | 225820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142088646 -assert nopostproc +UVM_TESTNAME=rv_dm_base _test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.142088646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/18.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_intg_err.208861495 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 2429404398 ps |
| CPU time | 17.44 seconds |
| Started | Sep 11 08:16:04 AM UTC 24 |
| Finished | Sep 11 08:16:22 AM UTC 24 |
| Peak memory | 225788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208861495 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.208861495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/18.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.596978859 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 220759507 ps |
| CPU time | 3.03 seconds |
| Started | Sep 11 08:16:06 AM UTC 24 |
| Finished | Sep 11 08:16:10 AM UTC 24 |
| Peak memory | 225732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=596978859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_r and_reset.596978859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/19.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_rw.295656001 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 221976635 ps |
| CPU time | 1.69 seconds |
| Started | Sep 11 08:16:05 AM UTC 24 |
| Finished | Sep 11 08:16:08 AM UTC 24 |
| Peak memory | 225220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295656001 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.295656001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/19.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.13345547 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 10645062123 ps |
| CPU time | 11.84 seconds |
| Started | Sep 11 08:16:05 AM UTC 24 |
| Finished | Sep 11 08:16:18 AM UTC 24 |
| Peak memory | 215424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13345547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_bit_bash.13345547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/19.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.3443400078 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 2189602547 ps |
| CPU time | 3.89 seconds |
| Started | Sep 11 08:16:05 AM UTC 24 |
| Finished | Sep 11 08:16:10 AM UTC 24 |
| Peak memory | 215428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443400078 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.3443400078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/19.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.4220242664 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 147357003 ps |
| CPU time | 1.25 seconds |
| Started | Sep 11 08:16:05 AM UTC 24 |
| Finished | Sep 11 08:16:07 AM UTC 24 |
| Peak memory | 215064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220242664 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.4220242664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/19.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1579767670 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 101001329 ps |
| CPU time | 4.16 seconds |
| Started | Sep 11 08:16:06 AM UTC 24 |
| Finished | Sep 11 08:16:12 AM UTC 24 |
| Peak memory | 215444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579767670 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_csr_outstanding.1579767670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/19.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_errors.4177670461 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 150569890 ps |
| CPU time | 4.4 seconds |
| Started | Sep 11 08:16:05 AM UTC 24 |
| Finished | Sep 11 08:16:10 AM UTC 24 |
| Peak memory | 225712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177670461 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.4177670461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/19.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_intg_err.4108207790 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 1644399454 ps |
| CPU time | 15.11 seconds |
| Started | Sep 11 08:16:05 AM UTC 24 |
| Finished | Sep 11 08:16:21 AM UTC 24 |
| Peak memory | 225732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108207790 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.4108207790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/19.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1068845919 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 9065818636 ps |
| CPU time | 38.02 seconds |
| Started | Sep 11 08:14:24 AM UTC 24 |
| Finished | Sep 11 08:15:03 AM UTC 24 |
| Peak memory | 225756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068845919 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_aliasing.1068845919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/2.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.4048929385 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 10210471651 ps |
| CPU time | 89.38 seconds |
| Started | Sep 11 08:14:36 AM UTC 24 |
| Finished | Sep 11 08:16:07 AM UTC 24 |
| Peak memory | 225620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048929385 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.4048929385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/2.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.690344728 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 326255934 ps |
| CPU time | 3.23 seconds |
| Started | Sep 11 08:14:35 AM UTC 24 |
| Finished | Sep 11 08:14:39 AM UTC 24 |
| Peak memory | 225756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690344728 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.690344728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/2.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.2104665247 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 226927734 ps |
| CPU time | 6.09 seconds |
| Started | Sep 11 08:14:37 AM UTC 24 |
| Finished | Sep 11 08:14:44 AM UTC 24 |
| Peak memory | 232500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2104665247 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_r and_reset.2104665247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/2.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_rw.1737285920 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 112672535 ps |
| CPU time | 2.66 seconds |
| Started | Sep 11 08:14:36 AM UTC 24 |
| Finished | Sep 11 08:14:39 AM UTC 24 |
| Peak memory | 229820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737285920 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.1737285920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/2.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1089252328 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 57838267585 ps |
| CPU time | 66.37 seconds |
| Started | Sep 11 08:14:28 AM UTC 24 |
| Finished | Sep 11 08:15:36 AM UTC 24 |
| Peak memory | 215416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089252328 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_aliasing.1089252328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1163426456 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 6138526244 ps |
| CPU time | 24.86 seconds |
| Started | Sep 11 08:14:28 AM UTC 24 |
| Finished | Sep 11 08:14:55 AM UTC 24 |
| Peak memory | 215416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163426456 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_bit_bash.1163426456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2052360851 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 4505527484 ps |
| CPU time | 6.61 seconds |
| Started | Sep 11 08:14:28 AM UTC 24 |
| Finished | Sep 11 08:14:36 AM UTC 24 |
| Peak memory | 215384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052360851 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_hw_reset.2052360851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.959997574 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 1028228840 ps |
| CPU time | 5.15 seconds |
| Started | Sep 11 08:14:28 AM UTC 24 |
| Finished | Sep 11 08:14:34 AM UTC 24 |
| Peak memory | 215512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959997574 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.959997574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2928948988 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 2370328030 ps |
| CPU time | 4.6 seconds |
| Started | Sep 11 08:14:28 AM UTC 24 |
| Finished | Sep 11 08:14:34 AM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928948988 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_aliasing.2928948988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2147414799 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 5357295672 ps |
| CPU time | 9.92 seconds |
| Started | Sep 11 08:14:26 AM UTC 24 |
| Finished | Sep 11 08:14:37 AM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147414799 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_bit_bash.2147414799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.87607416 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 154780422 ps |
| CPU time | 1.1 seconds |
| Started | Sep 11 08:14:26 AM UTC 24 |
| Finished | Sep 11 08:14:28 AM UTC 24 |
| Peak memory | 215196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87607416 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_hw_reset.87607416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2106555264 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 459717313 ps |
| CPU time | 2.3 seconds |
| Started | Sep 11 08:14:26 AM UTC 24 |
| Finished | Sep 11 08:14:29 AM UTC 24 |
| Peak memory | 215060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106555264 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.2106555264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3142094230 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 86208593 ps |
| CPU time | 1.03 seconds |
| Started | Sep 11 08:14:33 AM UTC 24 |
| Finished | Sep 11 08:14:35 AM UTC 24 |
| Peak memory | 215132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142094230 -assert nopostproc +UVM _TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_partial_access.3142094230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/2.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_walk.2666487214 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 36839245 ps |
| CPU time | 1.16 seconds |
| Started | Sep 11 08:14:33 AM UTC 24 |
| Finished | Sep 11 08:14:36 AM UTC 24 |
| Peak memory | 215072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666487214 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.2666487214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/2.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2172795396 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 324598436 ps |
| CPU time | 5.55 seconds |
| Started | Sep 11 08:14:37 AM UTC 24 |
| Finished | Sep 11 08:14:43 AM UTC 24 |
| Peak memory | 215480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172795396 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_csr_outstanding.2172795396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/2.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_errors.3015062615 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 461558855 ps |
| CPU time | 5.49 seconds |
| Started | Sep 11 08:14:30 AM UTC 24 |
| Finished | Sep 11 08:14:36 AM UTC 24 |
| Peak memory | 225660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015062615 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.3015062615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/2.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.844011139 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 4712114390 ps |
| CPU time | 34.18 seconds |
| Started | Sep 11 08:14:30 AM UTC 24 |
| Finished | Sep 11 08:15:05 AM UTC 24 |
| Peak memory | 229836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844011139 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.844011139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/2.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2709202200 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 7039358228 ps |
| CPU time | 82.1 seconds |
| Started | Sep 11 08:14:37 AM UTC 24 |
| Finished | Sep 11 08:16:01 AM UTC 24 |
| Peak memory | 225700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709202200 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_aliasing.2709202200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/3.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1999753800 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 4920186594 ps |
| CPU time | 66.22 seconds |
| Started | Sep 11 08:14:51 AM UTC 24 |
| Finished | Sep 11 08:15:59 AM UTC 24 |
| Peak memory | 225692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999753800 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.1999753800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/3.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2639947104 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 127942225 ps |
| CPU time | 2.87 seconds |
| Started | Sep 11 08:14:49 AM UTC 24 |
| Finished | Sep 11 08:14:53 AM UTC 24 |
| Peak memory | 225660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639947104 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.2639947104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/3.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3062999400 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 149779524 ps |
| CPU time | 3.08 seconds |
| Started | Sep 11 08:14:53 AM UTC 24 |
| Finished | Sep 11 08:14:57 AM UTC 24 |
| Peak memory | 229968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3062999400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_r and_reset.3062999400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/3.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_rw.565652430 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 126046065 ps |
| CPU time | 3.54 seconds |
| Started | Sep 11 08:14:51 AM UTC 24 |
| Finished | Sep 11 08:14:55 AM UTC 24 |
| Peak memory | 225592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565652430 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.565652430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/3.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.5957157 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 84918059827 ps |
| CPU time | 78.17 seconds |
| Started | Sep 11 08:14:43 AM UTC 24 |
| Finished | Sep 11 08:16:03 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5957157 -assert nopostproc +UVM_TESTNAME=rv_ dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_aliasing.5957157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.816087601 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 27672083746 ps |
| CPU time | 92.41 seconds |
| Started | Sep 11 08:14:41 AM UTC 24 |
| Finished | Sep 11 08:16:15 AM UTC 24 |
| Peak memory | 215352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816087601 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_bit_bash.816087601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1762041441 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 3607702043 ps |
| CPU time | 8.72 seconds |
| Started | Sep 11 08:14:41 AM UTC 24 |
| Finished | Sep 11 08:14:50 AM UTC 24 |
| Peak memory | 215352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762041441 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_hw_reset.1762041441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.43097489 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 3220000462 ps |
| CPU time | 10.29 seconds |
| Started | Sep 11 08:14:41 AM UTC 24 |
| Finished | Sep 11 08:14:52 AM UTC 24 |
| Peak memory | 215504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43097489 -assert nopostproc +UVM_TESTNAME=rv_dm_ba se_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.43097489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.372896009 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 400582217 ps |
| CPU time | 1.52 seconds |
| Started | Sep 11 08:14:39 AM UTC 24 |
| Finished | Sep 11 08:14:42 AM UTC 24 |
| Peak memory | 215136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372896009 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_aliasing.372896009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2898645618 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 3257816656 ps |
| CPU time | 12.56 seconds |
| Started | Sep 11 08:14:38 AM UTC 24 |
| Finished | Sep 11 08:14:52 AM UTC 24 |
| Peak memory | 215420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898645618 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_bit_bash.2898645618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2678916633 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 1336956452 ps |
| CPU time | 8.14 seconds |
| Started | Sep 11 08:14:37 AM UTC 24 |
| Finished | Sep 11 08:14:46 AM UTC 24 |
| Peak memory | 215200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678916633 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_hw_reset.2678916633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.4197744769 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 297466857 ps |
| CPU time | 1.27 seconds |
| Started | Sep 11 08:14:37 AM UTC 24 |
| Finished | Sep 11 08:14:39 AM UTC 24 |
| Peak memory | 215132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197744769 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.4197744769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_partial_access.537649778 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 136854631 ps |
| CPU time | 1.18 seconds |
| Started | Sep 11 08:14:47 AM UTC 24 |
| Finished | Sep 11 08:14:50 AM UTC 24 |
| Peak memory | 215196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537649778 -assert nopostproc +UVM_ TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_partial_access.537649778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/3.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_walk.4284638378 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 76961933 ps |
| CPU time | 1.4 seconds |
| Started | Sep 11 08:14:46 AM UTC 24 |
| Finished | Sep 11 08:14:49 AM UTC 24 |
| Peak memory | 215072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284638378 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.4284638378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/3.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2221176690 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 526661643 ps |
| CPU time | 5.18 seconds |
| Started | Sep 11 08:14:52 AM UTC 24 |
| Finished | Sep 11 08:14:58 AM UTC 24 |
| Peak memory | 215428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221176690 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_csr_outstanding.2221176690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/3.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3567257393 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 2996355644 ps |
| CPU time | 26.21 seconds |
| Started | Sep 11 08:14:44 AM UTC 24 |
| Finished | Sep 11 08:15:12 AM UTC 24 |
| Peak memory | 225948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3567257393 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_re set.3567257393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/3.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_errors.1134202776 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 567055572 ps |
| CPU time | 9.76 seconds |
| Started | Sep 11 08:14:44 AM UTC 24 |
| Finished | Sep 11 08:14:55 AM UTC 24 |
| Peak memory | 225792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134202776 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.1134202776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/3.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1669883608 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 1190596943 ps |
| CPU time | 71.28 seconds |
| Started | Sep 11 08:14:53 AM UTC 24 |
| Finished | Sep 11 08:16:06 AM UTC 24 |
| Peak memory | 215388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669883608 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_aliasing.1669883608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/4.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1904125652 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 1473268089 ps |
| CPU time | 59 seconds |
| Started | Sep 11 08:15:04 AM UTC 24 |
| Finished | Sep 11 08:16:04 AM UTC 24 |
| Peak memory | 215260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904125652 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.1904125652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/4.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.4188915883 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 303295315 ps |
| CPU time | 2.93 seconds |
| Started | Sep 11 08:15:04 AM UTC 24 |
| Finished | Sep 11 08:15:08 AM UTC 24 |
| Peak memory | 225596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188915883 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.4188915883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/4.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1917169292 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 204767729 ps |
| CPU time | 3.21 seconds |
| Started | Sep 11 08:15:05 AM UTC 24 |
| Finished | Sep 11 08:15:09 AM UTC 24 |
| Peak memory | 231876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1917169292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_r and_reset.1917169292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/4.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_rw.3522596264 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 124090743 ps |
| CPU time | 2.9 seconds |
| Started | Sep 11 08:15:04 AM UTC 24 |
| Finished | Sep 11 08:15:08 AM UTC 24 |
| Peak memory | 225724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522596264 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.3522596264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/4.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2952859342 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 70805030913 ps |
| CPU time | 86.01 seconds |
| Started | Sep 11 08:14:58 AM UTC 24 |
| Finished | Sep 11 08:16:26 AM UTC 24 |
| Peak memory | 215392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952859342 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_aliasing.2952859342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2108881477 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 3592970926 ps |
| CPU time | 11.62 seconds |
| Started | Sep 11 08:14:57 AM UTC 24 |
| Finished | Sep 11 08:15:09 AM UTC 24 |
| Peak memory | 215416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108881477 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_bit_bash.2108881477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2521983344 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 5609597441 ps |
| CPU time | 24.16 seconds |
| Started | Sep 11 08:14:56 AM UTC 24 |
| Finished | Sep 11 08:15:22 AM UTC 24 |
| Peak memory | 215488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521983344 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_hw_reset.2521983344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.4263896153 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 1137340110 ps |
| CPU time | 7.73 seconds |
| Started | Sep 11 08:14:56 AM UTC 24 |
| Finished | Sep 11 08:15:05 AM UTC 24 |
| Peak memory | 215352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263896153 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.4263896153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1940058300 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 521628836 ps |
| CPU time | 3.73 seconds |
| Started | Sep 11 08:14:55 AM UTC 24 |
| Finished | Sep 11 08:15:00 AM UTC 24 |
| Peak memory | 215064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940058300 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_aliasing.1940058300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.586144885 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 12090108253 ps |
| CPU time | 10.32 seconds |
| Started | Sep 11 08:14:55 AM UTC 24 |
| Finished | Sep 11 08:15:07 AM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586144885 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_bit_bash.586144885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.4149590776 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 241304526 ps |
| CPU time | 1.38 seconds |
| Started | Sep 11 08:14:53 AM UTC 24 |
| Finished | Sep 11 08:14:55 AM UTC 24 |
| Peak memory | 215136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149590776 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_hw_reset.4149590776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.4093070528 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 171613225 ps |
| CPU time | 1.54 seconds |
| Started | Sep 11 08:14:54 AM UTC 24 |
| Finished | Sep 11 08:14:57 AM UTC 24 |
| Peak memory | 215072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093070528 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.4093070528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1913181146 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 39900944 ps |
| CPU time | 1.01 seconds |
| Started | Sep 11 08:15:02 AM UTC 24 |
| Finished | Sep 11 08:15:04 AM UTC 24 |
| Peak memory | 215132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913181146 -assert nopostproc +UVM _TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_partial_access.1913181146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/4.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_walk.1988372332 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 199487940 ps |
| CPU time | 1.21 seconds |
| Started | Sep 11 08:15:01 AM UTC 24 |
| Finished | Sep 11 08:15:03 AM UTC 24 |
| Peak memory | 215072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988372332 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.1988372332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/4.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2911821882 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 518746052 ps |
| CPU time | 6.37 seconds |
| Started | Sep 11 08:15:04 AM UTC 24 |
| Finished | Sep 11 08:15:11 AM UTC 24 |
| Peak memory | 215480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911821882 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_csr_outstanding.2911821882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/4.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.1965448266 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 6889856715 ps |
| CPU time | 33.15 seconds |
| Started | Sep 11 08:14:58 AM UTC 24 |
| Finished | Sep 11 08:15:32 AM UTC 24 |
| Peak memory | 227844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1965448266 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_re set.1965448266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/4.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_errors.3484937550 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 206681186 ps |
| CPU time | 5.74 seconds |
| Started | Sep 11 08:14:58 AM UTC 24 |
| Finished | Sep 11 08:15:05 AM UTC 24 |
| Peak memory | 225916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484937550 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.3484937550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/4.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2199581279 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 679286679 ps |
| CPU time | 11.73 seconds |
| Started | Sep 11 08:14:59 AM UTC 24 |
| Finished | Sep 11 08:15:12 AM UTC 24 |
| Peak memory | 232360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199581279 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.2199581279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/4.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3651303272 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 68617350 ps |
| CPU time | 4.54 seconds |
| Started | Sep 11 08:15:10 AM UTC 24 |
| Finished | Sep 11 08:15:15 AM UTC 24 |
| Peak memory | 229928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3651303272 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_r and_reset.3651303272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/5.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_rw.941888998 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 501401995 ps |
| CPU time | 3.32 seconds |
| Started | Sep 11 08:15:08 AM UTC 24 |
| Finished | Sep 11 08:15:13 AM UTC 24 |
| Peak memory | 225784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941888998 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.941888998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/5.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3081065532 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 7378190433 ps |
| CPU time | 22.81 seconds |
| Started | Sep 11 08:15:06 AM UTC 24 |
| Finished | Sep 11 08:15:30 AM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081065532 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_bit_bash.3081065532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/5.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2877984501 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 4595646957 ps |
| CPU time | 6.68 seconds |
| Started | Sep 11 08:15:06 AM UTC 24 |
| Finished | Sep 11 08:15:14 AM UTC 24 |
| Peak memory | 215444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877984501 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.2877984501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/5.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3158422424 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 229853930 ps |
| CPU time | 1.54 seconds |
| Started | Sep 11 08:15:05 AM UTC 24 |
| Finished | Sep 11 08:15:08 AM UTC 24 |
| Peak memory | 215072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158422424 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.3158422424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/5.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.193289761 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 265673747 ps |
| CPU time | 5.95 seconds |
| Started | Sep 11 08:15:08 AM UTC 24 |
| Finished | Sep 11 08:15:15 AM UTC 24 |
| Peak memory | 215356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193289761 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_csr_outstanding.193289761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/5.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.505289594 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 4041971689 ps |
| CPU time | 41.46 seconds |
| Started | Sep 11 08:15:07 AM UTC 24 |
| Finished | Sep 11 08:15:50 AM UTC 24 |
| Peak memory | 229872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=505289594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.505289594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/5.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_errors.2920386079 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 534008432 ps |
| CPU time | 9.09 seconds |
| Started | Sep 11 08:15:08 AM UTC 24 |
| Finished | Sep 11 08:15:18 AM UTC 24 |
| Peak memory | 225692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920386079 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.2920386079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/5.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_intg_err.212694629 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 6119519329 ps |
| CPU time | 22.93 seconds |
| Started | Sep 11 08:15:08 AM UTC 24 |
| Finished | Sep 11 08:15:33 AM UTC 24 |
| Peak memory | 227744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212694629 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.212694629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/5.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_rw.2585357199 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 177130619 ps |
| CPU time | 3.23 seconds |
| Started | Sep 11 08:15:14 AM UTC 24 |
| Finished | Sep 11 08:15:18 AM UTC 24 |
| Peak memory | 225696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585357199 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.2585357199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/6.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.4030396453 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 8105085004 ps |
| CPU time | 9.19 seconds |
| Started | Sep 11 08:15:13 AM UTC 24 |
| Finished | Sep 11 08:15:23 AM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030396453 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_bit_bash.4030396453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/6.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.535881779 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 6561357214 ps |
| CPU time | 41.4 seconds |
| Started | Sep 11 08:15:12 AM UTC 24 |
| Finished | Sep 11 08:15:55 AM UTC 24 |
| Peak memory | 215448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535881779 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.535881779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/6.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3773535025 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 541086972 ps |
| CPU time | 1.5 seconds |
| Started | Sep 11 08:15:10 AM UTC 24 |
| Finished | Sep 11 08:15:12 AM UTC 24 |
| Peak memory | 215072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773535025 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.3773535025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/6.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1305006662 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 778343538 ps |
| CPU time | 10.17 seconds |
| Started | Sep 11 08:15:14 AM UTC 24 |
| Finished | Sep 11 08:15:25 AM UTC 24 |
| Peak memory | 215480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305006662 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_csr_outstanding.1305006662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/6.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.984660680 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 7462909937 ps |
| CPU time | 38.14 seconds |
| Started | Sep 11 08:15:13 AM UTC 24 |
| Finished | Sep 11 08:15:52 AM UTC 24 |
| Peak memory | 232536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=984660680 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.984660680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/6.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_errors.2081210311 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 228864645 ps |
| CPU time | 4.27 seconds |
| Started | Sep 11 08:15:13 AM UTC 24 |
| Finished | Sep 11 08:15:18 AM UTC 24 |
| Peak memory | 225660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081210311 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.2081210311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/6.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_intg_err.90237329 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 15509509097 ps |
| CPU time | 18.71 seconds |
| Started | Sep 11 08:15:13 AM UTC 24 |
| Finished | Sep 11 08:15:33 AM UTC 24 |
| Peak memory | 232512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90237329 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.90237329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/6.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3215162746 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 77241558 ps |
| CPU time | 2.37 seconds |
| Started | Sep 11 08:15:22 AM UTC 24 |
| Finished | Sep 11 08:15:26 AM UTC 24 |
| Peak memory | 227912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3215162746 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_r and_reset.3215162746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/7.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_rw.1050175907 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 158139786 ps |
| CPU time | 2.25 seconds |
| Started | Sep 11 08:15:20 AM UTC 24 |
| Finished | Sep 11 08:15:23 AM UTC 24 |
| Peak memory | 225620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050175907 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.1050175907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/7.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.3707353616 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 16148734001 ps |
| CPU time | 29.13 seconds |
| Started | Sep 11 08:15:16 AM UTC 24 |
| Finished | Sep 11 08:15:47 AM UTC 24 |
| Peak memory | 215360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707353616 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_bit_bash.3707353616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/7.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3983979557 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 3224565167 ps |
| CPU time | 12.81 seconds |
| Started | Sep 11 08:15:16 AM UTC 24 |
| Finished | Sep 11 08:15:30 AM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983979557 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.3983979557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/7.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2057437916 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 761689787 ps |
| CPU time | 4.5 seconds |
| Started | Sep 11 08:15:15 AM UTC 24 |
| Finished | Sep 11 08:15:21 AM UTC 24 |
| Peak memory | 215136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057437916 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.2057437916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/7.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1030742810 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 1638293826 ps |
| CPU time | 8.42 seconds |
| Started | Sep 11 08:15:21 AM UTC 24 |
| Finished | Sep 11 08:15:31 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030742810 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_csr_outstanding.1030742810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/7.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.2421240546 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 2253421591 ps |
| CPU time | 41.71 seconds |
| Started | Sep 11 08:15:20 AM UTC 24 |
| Finished | Sep 11 08:16:03 AM UTC 24 |
| Peak memory | 227896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2421240546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_re set.2421240546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/7.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_errors.1546374465 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 223078288 ps |
| CPU time | 4.66 seconds |
| Started | Sep 11 08:15:20 AM UTC 24 |
| Finished | Sep 11 08:15:26 AM UTC 24 |
| Peak memory | 225724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546374465 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.1546374465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/7.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2269887987 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 747628412 ps |
| CPU time | 3.22 seconds |
| Started | Sep 11 08:15:27 AM UTC 24 |
| Finished | Sep 11 08:15:31 AM UTC 24 |
| Peak memory | 229872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2269887987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_r and_reset.2269887987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/8.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_rw.280424674 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 851022294 ps |
| CPU time | 4.11 seconds |
| Started | Sep 11 08:15:27 AM UTC 24 |
| Finished | Sep 11 08:15:32 AM UTC 24 |
| Peak memory | 229868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280424674 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.280424674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/8.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1948293415 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 50630859846 ps |
| CPU time | 51.39 seconds |
| Started | Sep 11 08:15:24 AM UTC 24 |
| Finished | Sep 11 08:16:17 AM UTC 24 |
| Peak memory | 215384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948293415 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_bit_bash.1948293415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/8.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1238985345 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 1680389142 ps |
| CPU time | 3.67 seconds |
| Started | Sep 11 08:15:23 AM UTC 24 |
| Finished | Sep 11 08:15:28 AM UTC 24 |
| Peak memory | 215288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238985345 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.1238985345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/8.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3241526363 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 323393010 ps |
| CPU time | 2.22 seconds |
| Started | Sep 11 08:15:22 AM UTC 24 |
| Finished | Sep 11 08:15:26 AM UTC 24 |
| Peak memory | 215060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241526363 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.3241526363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/8.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.871685778 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 1679603840 ps |
| CPU time | 9.08 seconds |
| Started | Sep 11 08:15:27 AM UTC 24 |
| Finished | Sep 11 08:15:37 AM UTC 24 |
| Peak memory | 215420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871685778 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_csr_outstanding.871685778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/8.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3489185124 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 1299578732 ps |
| CPU time | 16.38 seconds |
| Started | Sep 11 08:15:24 AM UTC 24 |
| Finished | Sep 11 08:15:42 AM UTC 24 |
| Peak memory | 232492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3489185124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_re set.3489185124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/8.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_errors.1871688205 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 877717633 ps |
| CPU time | 7.5 seconds |
| Started | Sep 11 08:15:27 AM UTC 24 |
| Finished | Sep 11 08:15:35 AM UTC 24 |
| Peak memory | 225724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871688205 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.1871688205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/8.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1231015373 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 5856839382 ps |
| CPU time | 38.08 seconds |
| Started | Sep 11 08:15:27 AM UTC 24 |
| Finished | Sep 11 08:16:06 AM UTC 24 |
| Peak memory | 225852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231015373 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.1231015373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/8.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2651103377 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 56020290 ps |
| CPU time | 2.8 seconds |
| Started | Sep 11 08:15:33 AM UTC 24 |
| Finished | Sep 11 08:15:38 AM UTC 24 |
| Peak memory | 227716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2651103377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_r and_reset.2651103377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/9.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_rw.2992903600 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 77662949 ps |
| CPU time | 1.6 seconds |
| Started | Sep 11 08:15:32 AM UTC 24 |
| Finished | Sep 11 08:15:35 AM UTC 24 |
| Peak memory | 229196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992903600 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.2992903600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/9.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3738251883 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 29658341527 ps |
| CPU time | 31.25 seconds |
| Started | Sep 11 08:15:31 AM UTC 24 |
| Finished | Sep 11 08:16:04 AM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738251883 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_bit_bash.3738251883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/9.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2069378850 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 4469019051 ps |
| CPU time | 18.14 seconds |
| Started | Sep 11 08:15:29 AM UTC 24 |
| Finished | Sep 11 08:15:48 AM UTC 24 |
| Peak memory | 215388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069378850 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.2069378850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/9.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.618977693 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 245561059 ps |
| CPU time | 1.96 seconds |
| Started | Sep 11 08:15:29 AM UTC 24 |
| Finished | Sep 11 08:15:32 AM UTC 24 |
| Peak memory | 215076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618977693 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.618977693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/9.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.709160884 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 404112753 ps |
| CPU time | 4.09 seconds |
| Started | Sep 11 08:15:33 AM UTC 24 |
| Finished | Sep 11 08:15:39 AM UTC 24 |
| Peak memory | 215556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709160884 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_csr_outstanding.709160884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/9.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.404651097 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 7510658209 ps |
| CPU time | 64.38 seconds |
| Started | Sep 11 08:15:31 AM UTC 24 |
| Finished | Sep 11 08:16:37 AM UTC 24 |
| Peak memory | 232472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=404651097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.404651097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/9.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_errors.1204899972 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 2195936367 ps |
| CPU time | 6.76 seconds |
| Started | Sep 11 08:15:31 AM UTC 24 |
| Finished | Sep 11 08:15:39 AM UTC 24 |
| Peak memory | 225880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204899972 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.1204899972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/9.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_intg_err.4229195041 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 1487622036 ps |
| CPU time | 11.11 seconds |
| Started | Sep 11 08:15:32 AM UTC 24 |
| Finished | Sep 11 08:15:45 AM UTC 24 |
| Peak memory | 225744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229195041 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.4229195041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/9.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.725211682 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 145730082 ps |
| CPU time | 1.76 seconds |
| Started | Sep 11 08:16:12 AM UTC 24 |
| Finished | Sep 11 08:16:14 AM UTC 24 |
| Peak memory | 213508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725211682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_abstractcmd_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.725211682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_abstractcmd_status/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.854746425 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 46112618393 ps |
| CPU time | 37.29 seconds |
| Started | Sep 11 08:16:08 AM UTC 24 |
| Finished | Sep 11 08:16:46 AM UTC 24 |
| Peak memory | 226548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854746425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.854746425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.792011827 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 7359126769 ps |
| CPU time | 11.59 seconds |
| Started | Sep 11 08:16:07 AM UTC 24 |
| Finished | Sep 11 08:16:19 AM UTC 24 |
| Peak memory | 226440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792011827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.792011827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_busy.3028857384 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1133804651 ps |
| CPU time | 4.75 seconds |
| Started | Sep 11 08:16:08 AM UTC 24 |
| Finished | Sep 11 08:16:14 AM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028857384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.3028857384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_cmderr_busy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.362287415 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 398170085 ps |
| CPU time | 1.54 seconds |
| Started | Sep 11 08:16:08 AM UTC 24 |
| Finished | Sep 11 08:16:10 AM UTC 24 |
| Peak memory | 213448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362287415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.362287415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_cmderr_not_supported/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_dataaddr_rw_access.551026652 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 333372143 ps |
| CPU time | 1.38 seconds |
| Started | Sep 11 08:16:10 AM UTC 24 |
| Finished | Sep 11 08:16:13 AM UTC 24 |
| Peak memory | 213508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551026652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_dataaddr_rw_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.551026652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_dataaddr_rw_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_debug_disabled.3881616068 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 82711392 ps |
| CPU time | 1.33 seconds |
| Started | Sep 11 08:16:13 AM UTC 24 |
| Finished | Sep 11 08:16:15 AM UTC 24 |
| Peak memory | 237476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881616068 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.3881616068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_hart_unavail.1517808866 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 157332715 ps |
| CPU time | 1.47 seconds |
| Started | Sep 11 08:16:08 AM UTC 24 |
| Finished | Sep 11 08:16:11 AM UTC 24 |
| Peak memory | 213444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517808866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.1517808866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_hartsel_warl.355547412 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 268767459 ps |
| CPU time | 1.58 seconds |
| Started | Sep 11 08:16:13 AM UTC 24 |
| Finished | Sep 11 08:16:16 AM UTC 24 |
| Peak memory | 213508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355547412 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_hartsel_warl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.355547412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_hartsel_warl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.153712485 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 321530905 ps |
| CPU time | 0.83 seconds |
| Started | Sep 11 08:16:12 AM UTC 24 |
| Finished | Sep 11 08:16:13 AM UTC 24 |
| Peak memory | 213444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153712485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.153712485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2612241550 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 720283110 ps |
| CPU time | 3.21 seconds |
| Started | Sep 11 08:16:12 AM UTC 24 |
| Finished | Sep 11 08:16:16 AM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612241550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.2612241550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_dm_inactive/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_hard_reset.1866008871 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 214671276 ps |
| CPU time | 1.67 seconds |
| Started | Sep 11 08:16:12 AM UTC 24 |
| Finished | Sep 11 08:16:14 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866008871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.1866008871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_hard_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_idle_hint.3126828668 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 637643233 ps |
| CPU time | 1.42 seconds |
| Started | Sep 11 08:16:11 AM UTC 24 |
| Finished | Sep 11 08:16:14 AM UTC 24 |
| Peak memory | 213448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126828668 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.3126828668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_idle_hint/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_halted.92819288 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 558048300 ps |
| CPU time | 1.26 seconds |
| Started | Sep 11 08:16:08 AM UTC 24 |
| Finished | Sep 11 08:16:10 AM UTC 24 |
| Peak memory | 213512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92819288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv _dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.92819288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_halted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.889607999 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 424043429 ps |
| CPU time | 1.49 seconds |
| Started | Sep 11 08:16:13 AM UTC 24 |
| Finished | Sep 11 08:16:15 AM UTC 24 |
| Peak memory | 215936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889607999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_progbuf_read_write_execute_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.889607999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_progbuf_read_write_execute/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_tl_access.1915880307 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 796223874 ps |
| CPU time | 2.59 seconds |
| Started | Sep 11 08:16:07 AM UTC 24 |
| Finished | Sep 11 08:16:10 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915880307 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.1915880307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.1871716201 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1438189685 ps |
| CPU time | 3.1 seconds |
| Started | Sep 11 08:16:14 AM UTC 24 |
| Finished | Sep 11 08:16:18 AM UTC 24 |
| Peak memory | 256864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871716201 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.1871716201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_smoke.147363242 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 1476607864 ps |
| CPU time | 4.79 seconds |
| Started | Sep 11 08:16:07 AM UTC 24 |
| Finished | Sep 11 08:16:12 AM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147363242 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.147363242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/0.rv_dm_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_abstractcmd_status.2413392956 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 282524496 ps |
| CPU time | 1.01 seconds |
| Started | Sep 11 08:16:17 AM UTC 24 |
| Finished | Sep 11 08:16:19 AM UTC 24 |
| Peak memory | 213508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413392956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_abstractcmd_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.2413392956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_abstractcmd_status/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_alert_test.1413847421 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 92538567 ps |
| CPU time | 1.05 seconds |
| Started | Sep 11 08:16:19 AM UTC 24 |
| Finished | Sep 11 08:16:21 AM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413847421 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.1413847421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_autoincr_sba_tl_access.4002701746 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 16315070066 ps |
| CPU time | 27.22 seconds |
| Started | Sep 11 08:16:15 AM UTC 24 |
| Finished | Sep 11 08:16:44 AM UTC 24 |
| Peak memory | 226508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002701746 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.4002701746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_bad_sba_tl_access.1885128072 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 4346573935 ps |
| CPU time | 4.18 seconds |
| Started | Sep 11 08:16:14 AM UTC 24 |
| Finished | Sep 11 08:16:20 AM UTC 24 |
| Peak memory | 226492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885128072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.1885128072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_busy.1389118340 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 255186643 ps |
| CPU time | 1.88 seconds |
| Started | Sep 11 08:16:16 AM UTC 24 |
| Finished | Sep 11 08:16:18 AM UTC 24 |
| Peak memory | 213428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389118340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.1389118340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_cmderr_busy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.2456136337 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 211253559 ps |
| CPU time | 1.08 seconds |
| Started | Sep 11 08:16:16 AM UTC 24 |
| Finished | Sep 11 08:16:18 AM UTC 24 |
| Peak memory | 213508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456136337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.2456136337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_cmderr_halt_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_not_supported.2544857789 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 547780312 ps |
| CPU time | 2.86 seconds |
| Started | Sep 11 08:16:16 AM UTC 24 |
| Finished | Sep 11 08:16:19 AM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544857789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.2544857789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_cmderr_not_supported/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_dataaddr_rw_access.2267932421 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 115301047 ps |
| CPU time | 1.19 seconds |
| Started | Sep 11 08:16:16 AM UTC 24 |
| Finished | Sep 11 08:16:18 AM UTC 24 |
| Peak memory | 213508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267932421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.2267932421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_dataaddr_rw_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_debug_disabled.820421504 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 44457764 ps |
| CPU time | 1.07 seconds |
| Started | Sep 11 08:16:18 AM UTC 24 |
| Finished | Sep 11 08:16:20 AM UTC 24 |
| Peak memory | 236044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820421504 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.820421504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.1669633555 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 1425849379 ps |
| CPU time | 3.44 seconds |
| Started | Sep 11 08:16:14 AM UTC 24 |
| Finished | Sep 11 08:16:19 AM UTC 24 |
| Peak memory | 216188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669633555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_tl_access.1669633555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_halt_resume_whereto.677705603 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 793190621 ps |
| CPU time | 1.22 seconds |
| Started | Sep 11 08:16:16 AM UTC 24 |
| Finished | Sep 11 08:16:18 AM UTC 24 |
| Peak memory | 213504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677705603 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.677705603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_hart_unavail.341449570 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 75092370 ps |
| CPU time | 1.05 seconds |
| Started | Sep 11 08:16:16 AM UTC 24 |
| Finished | Sep 11 08:16:18 AM UTC 24 |
| Peak memory | 213508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341449570 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.341449570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.3702643224 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 302251623 ps |
| CPU time | 1.98 seconds |
| Started | Sep 11 08:16:17 AM UTC 24 |
| Finished | Sep 11 08:16:20 AM UTC 24 |
| Peak memory | 213452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702643224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.3702643224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1425595455 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 429443124 ps |
| CPU time | 1.67 seconds |
| Started | Sep 11 08:16:17 AM UTC 24 |
| Finished | Sep 11 08:16:20 AM UTC 24 |
| Peak memory | 213452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425595455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.1425595455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_dm_inactive/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1660368561 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 802812470 ps |
| CPU time | 1.34 seconds |
| Started | Sep 11 08:16:17 AM UTC 24 |
| Finished | Sep 11 08:16:19 AM UTC 24 |
| Peak memory | 213508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660368561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.1660368561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_idle_hint/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_halted.2917045648 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 92064242 ps |
| CPU time | 1.1 seconds |
| Started | Sep 11 08:16:16 AM UTC 24 |
| Finished | Sep 11 08:16:18 AM UTC 24 |
| Peak memory | 213452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917045648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.2917045648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_mem_tl_access_halted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_resuming.2995433326 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 145534096 ps |
| CPU time | 0.9 seconds |
| Started | Sep 11 08:16:16 AM UTC 24 |
| Finished | Sep 11 08:16:18 AM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995433326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.2995433326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_mem_tl_access_resuming/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_ndmreset_req.193793093 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 148173775 ps |
| CPU time | 0.85 seconds |
| Started | Sep 11 08:16:16 AM UTC 24 |
| Finished | Sep 11 08:16:18 AM UTC 24 |
| Peak memory | 225848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193793093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.193793093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_ndmreset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_progbuf_read_write_execute.648563502 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 905246433 ps |
| CPU time | 2.32 seconds |
| Started | Sep 11 08:16:18 AM UTC 24 |
| Finished | Sep 11 08:16:22 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648563502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_progbuf_read_write_execute_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.648563502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_progbuf_read_write_execute/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_rom_read_access.2082278868 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 67662595 ps |
| CPU time | 1 seconds |
| Started | Sep 11 08:16:17 AM UTC 24 |
| Finished | Sep 11 08:16:19 AM UTC 24 |
| Peak memory | 225784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082278868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_rom_read_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.2082278868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_rom_read_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_debug_disabled.997374069 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 3792166439 ps |
| CPU time | 6.65 seconds |
| Started | Sep 11 08:16:16 AM UTC 24 |
| Finished | Sep 11 08:16:24 AM UTC 24 |
| Peak memory | 216064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997374069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sba_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.997374069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_sba_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_tl_access.2918312555 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 8563254010 ps |
| CPU time | 7.35 seconds |
| Started | Sep 11 08:16:14 AM UTC 24 |
| Finished | Sep 11 08:16:23 AM UTC 24 |
| Peak memory | 216328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918312555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.2918312555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_sec_cm.1022958667 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 520485215 ps |
| CPU time | 1.28 seconds |
| Started | Sep 11 08:16:19 AM UTC 24 |
| Finished | Sep 11 08:16:21 AM UTC 24 |
| Peak memory | 251564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022958667 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.1022958667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_smoke.1357762703 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 606713700 ps |
| CPU time | 2.65 seconds |
| Started | Sep 11 08:16:14 AM UTC 24 |
| Finished | Sep 11 08:16:18 AM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357762703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.1357762703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/1.rv_dm_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/10.rv_dm_alert_test.301601735 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 122985268 ps |
| CPU time | 1.16 seconds |
| Started | Sep 11 08:16:44 AM UTC 24 |
| Finished | Sep 11 08:16:46 AM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301601735 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.301601735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/10.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/10.rv_dm_autoincr_sba_tl_access.2980383546 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 2189350058 ps |
| CPU time | 3.18 seconds |
| Started | Sep 11 08:16:42 AM UTC 24 |
| Finished | Sep 11 08:16:46 AM UTC 24 |
| Peak memory | 216384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980383546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.2980383546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/10.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/10.rv_dm_bad_sba_tl_access.2937590642 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 1035108090 ps |
| CPU time | 3.49 seconds |
| Started | Sep 11 08:16:42 AM UTC 24 |
| Finished | Sep 11 08:16:46 AM UTC 24 |
| Peak memory | 216256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937590642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.2937590642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/10.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.3540767504 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 1644311079 ps |
| CPU time | 5.38 seconds |
| Started | Sep 11 08:16:41 AM UTC 24 |
| Finished | Sep 11 08:16:47 AM UTC 24 |
| Peak memory | 216128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540767504 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_tl_access.3540767504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/10.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/10.rv_dm_sba_tl_access.2376865289 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 1532385902 ps |
| CPU time | 4.09 seconds |
| Started | Sep 11 08:16:41 AM UTC 24 |
| Finished | Sep 11 08:16:46 AM UTC 24 |
| Peak memory | 216308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376865289 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.2376865289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/10.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/10.rv_dm_stress_all.4074303989 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 2847502685 ps |
| CPU time | 6.51 seconds |
| Started | Sep 11 08:16:42 AM UTC 24 |
| Finished | Sep 11 08:16:50 AM UTC 24 |
| Peak memory | 216048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074303989 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.4074303989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/10.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/11.rv_dm_alert_test.3923387736 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 117108828 ps |
| CPU time | 1.16 seconds |
| Started | Sep 11 08:16:46 AM UTC 24 |
| Finished | Sep 11 08:16:48 AM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923387736 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.3923387736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/11.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/11.rv_dm_bad_sba_tl_access.848580032 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 3007692559 ps |
| CPU time | 4.71 seconds |
| Started | Sep 11 08:16:45 AM UTC 24 |
| Finished | Sep 11 08:16:51 AM UTC 24 |
| Peak memory | 226620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848580032 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.848580032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/11.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.2550612032 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 1185922745 ps |
| CPU time | 3.01 seconds |
| Started | Sep 11 08:16:44 AM UTC 24 |
| Finished | Sep 11 08:16:48 AM UTC 24 |
| Peak memory | 216252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550612032 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_tl_access.2550612032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/11.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/11.rv_dm_sba_tl_access.1216336140 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 981180264 ps |
| CPU time | 1.9 seconds |
| Started | Sep 11 08:16:44 AM UTC 24 |
| Finished | Sep 11 08:16:47 AM UTC 24 |
| Peak memory | 215492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216336140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.1216336140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/11.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/11.rv_dm_stress_all.3402941724 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 7511574744 ps |
| CPU time | 25.14 seconds |
| Started | Sep 11 08:16:46 AM UTC 24 |
| Finished | Sep 11 08:17:12 AM UTC 24 |
| Peak memory | 226304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402941724 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.3402941724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/11.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/12.rv_dm_alert_test.3867951581 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 130013245 ps |
| CPU time | 1.07 seconds |
| Started | Sep 11 08:16:47 AM UTC 24 |
| Finished | Sep 11 08:16:49 AM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867951581 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.3867951581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/12.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/12.rv_dm_autoincr_sba_tl_access.3684647433 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 28225306032 ps |
| CPU time | 54.23 seconds |
| Started | Sep 11 08:16:47 AM UTC 24 |
| Finished | Sep 11 08:17:43 AM UTC 24 |
| Peak memory | 226612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684647433 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.3684647433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/12.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/12.rv_dm_bad_sba_tl_access.1479910527 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 5816352111 ps |
| CPU time | 18.34 seconds |
| Started | Sep 11 08:16:47 AM UTC 24 |
| Finished | Sep 11 08:17:06 AM UTC 24 |
| Peak memory | 216312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479910527 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.1479910527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/12.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.3444156244 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 8194413569 ps |
| CPU time | 6.52 seconds |
| Started | Sep 11 08:16:46 AM UTC 24 |
| Finished | Sep 11 08:16:53 AM UTC 24 |
| Peak memory | 226680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444156244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_tl_access.3444156244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/12.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/12.rv_dm_sba_tl_access.3682821892 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 1771367648 ps |
| CPU time | 3.27 seconds |
| Started | Sep 11 08:16:46 AM UTC 24 |
| Finished | Sep 11 08:16:50 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682821892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.3682821892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/12.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/12.rv_dm_stress_all.2970292537 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 1762355045 ps |
| CPU time | 2.84 seconds |
| Started | Sep 11 08:16:47 AM UTC 24 |
| Finished | Sep 11 08:16:51 AM UTC 24 |
| Peak memory | 226244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970292537 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.2970292537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/12.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/13.rv_dm_alert_test.3234367903 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 138997438 ps |
| CPU time | 0.85 seconds |
| Started | Sep 11 08:16:49 AM UTC 24 |
| Finished | Sep 11 08:16:51 AM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234367903 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.3234367903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/13.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/13.rv_dm_autoincr_sba_tl_access.3260763410 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 8937904865 ps |
| CPU time | 26.71 seconds |
| Started | Sep 11 08:16:48 AM UTC 24 |
| Finished | Sep 11 08:17:16 AM UTC 24 |
| Peak memory | 216308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260763410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.3260763410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/13.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/13.rv_dm_bad_sba_tl_access.927578918 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 2485072462 ps |
| CPU time | 4.65 seconds |
| Started | Sep 11 08:16:48 AM UTC 24 |
| Finished | Sep 11 08:16:54 AM UTC 24 |
| Peak memory | 226548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927578918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.927578918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/13.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.4129995776 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 3267296494 ps |
| CPU time | 1.8 seconds |
| Started | Sep 11 08:16:48 AM UTC 24 |
| Finished | Sep 11 08:16:51 AM UTC 24 |
| Peak memory | 225644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129995776 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_tl_access.4129995776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/13.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/13.rv_dm_sba_tl_access.3366031351 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 5753345758 ps |
| CPU time | 15.81 seconds |
| Started | Sep 11 08:16:47 AM UTC 24 |
| Finished | Sep 11 08:17:04 AM UTC 24 |
| Peak memory | 226628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366031351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.3366031351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/13.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/13.rv_dm_stress_all.4223345972 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 3858442197 ps |
| CPU time | 14.17 seconds |
| Started | Sep 11 08:16:49 AM UTC 24 |
| Finished | Sep 11 08:17:05 AM UTC 24 |
| Peak memory | 216120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223345972 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.4223345972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/13.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/14.rv_dm_alert_test.2463336528 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 103760823 ps |
| CPU time | 1.23 seconds |
| Started | Sep 11 08:16:51 AM UTC 24 |
| Finished | Sep 11 08:16:53 AM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463336528 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.2463336528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/14.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/14.rv_dm_bad_sba_tl_access.790134695 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 3597649790 ps |
| CPU time | 6.36 seconds |
| Started | Sep 11 08:16:50 AM UTC 24 |
| Finished | Sep 11 08:16:57 AM UTC 24 |
| Peak memory | 226428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790134695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.790134695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/14.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.3426951909 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 3196339964 ps |
| CPU time | 8.27 seconds |
| Started | Sep 11 08:16:50 AM UTC 24 |
| Finished | Sep 11 08:16:59 AM UTC 24 |
| Peak memory | 216176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426951909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_tl_access.3426951909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/14.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/14.rv_dm_sba_tl_access.2496996329 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 2084526815 ps |
| CPU time | 7.7 seconds |
| Started | Sep 11 08:16:50 AM UTC 24 |
| Finished | Sep 11 08:16:58 AM UTC 24 |
| Peak memory | 216188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496996329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.2496996329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/14.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/14.rv_dm_stress_all.692471193 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 3248091828 ps |
| CPU time | 9.73 seconds |
| Started | Sep 11 08:16:51 AM UTC 24 |
| Finished | Sep 11 08:17:02 AM UTC 24 |
| Peak memory | 226244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692471193 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.692471193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/14.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/15.rv_dm_alert_test.1126312529 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 46622367 ps |
| CPU time | 1.15 seconds |
| Started | Sep 11 08:16:53 AM UTC 24 |
| Finished | Sep 11 08:16:56 AM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126312529 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.1126312529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/15.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/15.rv_dm_autoincr_sba_tl_access.3503981967 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 13667916105 ps |
| CPU time | 19.99 seconds |
| Started | Sep 11 08:16:53 AM UTC 24 |
| Finished | Sep 11 08:17:15 AM UTC 24 |
| Peak memory | 226492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503981967 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.3503981967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/15.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/15.rv_dm_bad_sba_tl_access.2712166071 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 1398947989 ps |
| CPU time | 2.01 seconds |
| Started | Sep 11 08:16:53 AM UTC 24 |
| Finished | Sep 11 08:16:57 AM UTC 24 |
| Peak memory | 216200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712166071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.2712166071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/15.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2159783771 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 13456487676 ps |
| CPU time | 43.82 seconds |
| Started | Sep 11 08:16:53 AM UTC 24 |
| Finished | Sep 11 08:17:39 AM UTC 24 |
| Peak memory | 226604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159783771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_tl_access.2159783771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/15.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/15.rv_dm_sba_tl_access.1922088673 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 2422309105 ps |
| CPU time | 4.27 seconds |
| Started | Sep 11 08:16:53 AM UTC 24 |
| Finished | Sep 11 08:16:59 AM UTC 24 |
| Peak memory | 226484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922088673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.1922088673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/15.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/15.rv_dm_stress_all.1341694698 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 1791722795 ps |
| CPU time | 4 seconds |
| Started | Sep 11 08:16:53 AM UTC 24 |
| Finished | Sep 11 08:16:59 AM UTC 24 |
| Peak memory | 215988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341694698 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.1341694698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/15.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/16.rv_dm_alert_test.1657443153 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 35188595 ps |
| CPU time | 1.09 seconds |
| Started | Sep 11 08:16:55 AM UTC 24 |
| Finished | Sep 11 08:16:57 AM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657443153 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.1657443153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/16.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/16.rv_dm_autoincr_sba_tl_access.3387735239 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 21737286666 ps |
| CPU time | 95.21 seconds |
| Started | Sep 11 08:16:55 AM UTC 24 |
| Finished | Sep 11 08:18:32 AM UTC 24 |
| Peak memory | 226428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387735239 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.3387735239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/16.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/16.rv_dm_bad_sba_tl_access.2781450641 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 1328372700 ps |
| CPU time | 8.33 seconds |
| Started | Sep 11 08:16:55 AM UTC 24 |
| Finished | Sep 11 08:17:05 AM UTC 24 |
| Peak memory | 226548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781450641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.2781450641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/16.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.1598084674 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 9409026283 ps |
| CPU time | 11.01 seconds |
| Started | Sep 11 08:16:53 AM UTC 24 |
| Finished | Sep 11 08:17:06 AM UTC 24 |
| Peak memory | 226476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598084674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_tl_access.1598084674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/16.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/16.rv_dm_sba_tl_access.751300315 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 2172717513 ps |
| CPU time | 2.31 seconds |
| Started | Sep 11 08:16:53 AM UTC 24 |
| Finished | Sep 11 08:16:57 AM UTC 24 |
| Peak memory | 216220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751300315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.751300315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/16.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/16.rv_dm_stress_all.1677177210 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 3784885731 ps |
| CPU time | 5.97 seconds |
| Started | Sep 11 08:16:55 AM UTC 24 |
| Finished | Sep 11 08:17:02 AM UTC 24 |
| Peak memory | 216192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677177210 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.1677177210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/16.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/17.rv_dm_alert_test.1272980533 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 88923434 ps |
| CPU time | 1.21 seconds |
| Started | Sep 11 08:16:58 AM UTC 24 |
| Finished | Sep 11 08:17:00 AM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272980533 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.1272980533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/17.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/17.rv_dm_autoincr_sba_tl_access.2387789585 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 3589589062 ps |
| CPU time | 13 seconds |
| Started | Sep 11 08:16:58 AM UTC 24 |
| Finished | Sep 11 08:17:12 AM UTC 24 |
| Peak memory | 226424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387789585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.2387789585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/17.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/17.rv_dm_bad_sba_tl_access.1299995075 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 4181119364 ps |
| CPU time | 4.94 seconds |
| Started | Sep 11 08:16:58 AM UTC 24 |
| Finished | Sep 11 08:17:04 AM UTC 24 |
| Peak memory | 216308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299995075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.1299995075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/17.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.4097753422 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 2319303990 ps |
| CPU time | 8.06 seconds |
| Started | Sep 11 08:16:57 AM UTC 24 |
| Finished | Sep 11 08:17:06 AM UTC 24 |
| Peak memory | 216256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097753422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_tl_access.4097753422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/17.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/17.rv_dm_sba_tl_access.2340740987 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 2394098314 ps |
| CPU time | 12.63 seconds |
| Started | Sep 11 08:16:56 AM UTC 24 |
| Finished | Sep 11 08:17:10 AM UTC 24 |
| Peak memory | 216072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340740987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.2340740987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/17.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/17.rv_dm_stress_all.925074724 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 8635644541 ps |
| CPU time | 27.39 seconds |
| Started | Sep 11 08:16:58 AM UTC 24 |
| Finished | Sep 11 08:17:27 AM UTC 24 |
| Peak memory | 226312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925074724 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.925074724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/17.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/18.rv_dm_alert_test.4218518599 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 99499186 ps |
| CPU time | 1.32 seconds |
| Started | Sep 11 08:17:00 AM UTC 24 |
| Finished | Sep 11 08:17:03 AM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218518599 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.4218518599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/18.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/18.rv_dm_autoincr_sba_tl_access.3489142955 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 1141767642 ps |
| CPU time | 2.06 seconds |
| Started | Sep 11 08:16:59 AM UTC 24 |
| Finished | Sep 11 08:17:03 AM UTC 24 |
| Peak memory | 216256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489142955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.3489142955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/18.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/18.rv_dm_bad_sba_tl_access.1145704948 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 1815022539 ps |
| CPU time | 3.87 seconds |
| Started | Sep 11 08:16:59 AM UTC 24 |
| Finished | Sep 11 08:17:04 AM UTC 24 |
| Peak memory | 216264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145704948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.1145704948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/18.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.2920307857 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 2668437518 ps |
| CPU time | 7.71 seconds |
| Started | Sep 11 08:16:59 AM UTC 24 |
| Finished | Sep 11 08:17:08 AM UTC 24 |
| Peak memory | 216320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920307857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_tl_access.2920307857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/18.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/18.rv_dm_sba_tl_access.2027740309 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 3127191782 ps |
| CPU time | 11.27 seconds |
| Started | Sep 11 08:16:58 AM UTC 24 |
| Finished | Sep 11 08:17:11 AM UTC 24 |
| Peak memory | 216372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027740309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.2027740309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/18.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/18.rv_dm_stress_all.1695762780 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 2909838971 ps |
| CPU time | 11.87 seconds |
| Started | Sep 11 08:16:59 AM UTC 24 |
| Finished | Sep 11 08:17:12 AM UTC 24 |
| Peak memory | 216080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695762780 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.1695762780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/18.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/19.rv_dm_alert_test.1276139532 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 40194474 ps |
| CPU time | 1.21 seconds |
| Started | Sep 11 08:17:04 AM UTC 24 |
| Finished | Sep 11 08:17:06 AM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276139532 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.1276139532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/19.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.1515867896 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 45771302717 ps |
| CPU time | 41.46 seconds |
| Started | Sep 11 08:17:04 AM UTC 24 |
| Finished | Sep 11 08:17:47 AM UTC 24 |
| Peak memory | 226484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515867896 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.1515867896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/19.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/19.rv_dm_bad_sba_tl_access.2366552368 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 4911446191 ps |
| CPU time | 8.73 seconds |
| Started | Sep 11 08:17:02 AM UTC 24 |
| Finished | Sep 11 08:17:12 AM UTC 24 |
| Peak memory | 226436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366552368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.2366552368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/19.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2425204835 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 13177124165 ps |
| CPU time | 22.18 seconds |
| Started | Sep 11 08:17:01 AM UTC 24 |
| Finished | Sep 11 08:17:25 AM UTC 24 |
| Peak memory | 226420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425204835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_tl_access.2425204835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/19.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/19.rv_dm_sba_tl_access.1286577519 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 13244711402 ps |
| CPU time | 22.45 seconds |
| Started | Sep 11 08:17:00 AM UTC 24 |
| Finished | Sep 11 08:17:24 AM UTC 24 |
| Peak memory | 216384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286577519 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.1286577519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/19.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.141730666 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 2602183318 ps |
| CPU time | 2.81 seconds |
| Started | Sep 11 08:17:04 AM UTC 24 |
| Finished | Sep 11 08:17:08 AM UTC 24 |
| Peak memory | 216068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141730666 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.141730666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/19.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.1928008544 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 64863119 ps |
| CPU time | 0.92 seconds |
| Started | Sep 11 08:16:20 AM UTC 24 |
| Finished | Sep 11 08:16:22 AM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928008544 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.1928008544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/2.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.1089398649 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 11373458630 ps |
| CPU time | 27.65 seconds |
| Started | Sep 11 08:16:20 AM UTC 24 |
| Finished | Sep 11 08:16:49 AM UTC 24 |
| Peak memory | 226484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089398649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.1089398649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/2.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.719326809 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 156464162 ps |
| CPU time | 1.31 seconds |
| Started | Sep 11 08:16:20 AM UTC 24 |
| Finished | Sep 11 08:16:23 AM UTC 24 |
| Peak memory | 258160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719326809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_buffered_enable.719326809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/2.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.3790103708 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 1697094452 ps |
| CPU time | 3.69 seconds |
| Started | Sep 11 08:16:19 AM UTC 24 |
| Finished | Sep 11 08:16:24 AM UTC 24 |
| Peak memory | 216436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790103708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_tl_access.3790103708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/2.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.1069368224 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 399735351 ps |
| CPU time | 2.06 seconds |
| Started | Sep 11 08:16:20 AM UTC 24 |
| Finished | Sep 11 08:16:23 AM UTC 24 |
| Peak memory | 215924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069368224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_halt_resume_whereto.1069368224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/2.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.3838996531 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 117390019 ps |
| CPU time | 1.01 seconds |
| Started | Sep 11 08:16:20 AM UTC 24 |
| Finished | Sep 11 08:16:22 AM UTC 24 |
| Peak memory | 213444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838996531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.3838996531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/2.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.1197099218 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 7569547755 ps |
| CPU time | 28.18 seconds |
| Started | Sep 11 08:16:19 AM UTC 24 |
| Finished | Sep 11 08:16:48 AM UTC 24 |
| Peak memory | 226624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197099218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.1197099218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/2.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/2.rv_dm_sparse_lc_gate_fsm.55146202 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 152438946 ps |
| CPU time | 1.21 seconds |
| Started | Sep 11 08:16:20 AM UTC 24 |
| Finished | Sep 11 08:16:22 AM UTC 24 |
| Peak memory | 225848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55146202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv _dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sparse_lc_gate_fsm.55146202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/2.rv_dm_sparse_lc_gate_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all.530316595 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5675473912 ps |
| CPU time | 5.59 seconds |
| Started | Sep 11 08:16:20 AM UTC 24 |
| Finished | Sep 11 08:16:27 AM UTC 24 |
| Peak memory | 216072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530316595 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.530316595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/2.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.4028215172 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 4633960847 ps |
| CPU time | 34.21 seconds |
| Started | Sep 11 08:16:20 AM UTC 24 |
| Finished | Sep 11 08:16:56 AM UTC 24 |
| Peak memory | 243484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=4028215172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stres s_all_with_rand_reset.4028215172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/20.rv_dm_alert_test.77370280 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 41161552 ps |
| CPU time | 1.06 seconds |
| Started | Sep 11 08:17:05 AM UTC 24 |
| Finished | Sep 11 08:17:07 AM UTC 24 |
| Peak memory | 215924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77370280 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.77370280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/20.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.765898708 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 8385309040 ps |
| CPU time | 3.82 seconds |
| Started | Sep 11 08:17:05 AM UTC 24 |
| Finished | Sep 11 08:17:10 AM UTC 24 |
| Peak memory | 216000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765898708 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.765898708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/20.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/21.rv_dm_alert_test.1939010966 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 111951162 ps |
| CPU time | 1.34 seconds |
| Started | Sep 11 08:17:06 AM UTC 24 |
| Finished | Sep 11 08:17:08 AM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939010966 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.1939010966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/21.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/21.rv_dm_stress_all.3464963481 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 3469232062 ps |
| CPU time | 13.6 seconds |
| Started | Sep 11 08:17:05 AM UTC 24 |
| Finished | Sep 11 08:17:20 AM UTC 24 |
| Peak memory | 216184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464963481 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.3464963481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/21.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/22.rv_dm_alert_test.629734142 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 79868521 ps |
| CPU time | 1.29 seconds |
| Started | Sep 11 08:17:06 AM UTC 24 |
| Finished | Sep 11 08:17:09 AM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629734142 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.629734142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/22.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.3786961356 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 3738430956 ps |
| CPU time | 3.76 seconds |
| Started | Sep 11 08:17:06 AM UTC 24 |
| Finished | Sep 11 08:17:11 AM UTC 24 |
| Peak memory | 226284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786961356 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.3786961356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/22.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/23.rv_dm_alert_test.4075665915 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 84165037 ps |
| CPU time | 1.58 seconds |
| Started | Sep 11 08:17:07 AM UTC 24 |
| Finished | Sep 11 08:17:10 AM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075665915 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.4075665915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/23.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/23.rv_dm_stress_all.116339039 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 1671366633 ps |
| CPU time | 6.88 seconds |
| Started | Sep 11 08:17:06 AM UTC 24 |
| Finished | Sep 11 08:17:14 AM UTC 24 |
| Peak memory | 216120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116339039 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.116339039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/23.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/24.rv_dm_alert_test.2472052998 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 236777364 ps |
| CPU time | 1.09 seconds |
| Started | Sep 11 08:17:07 AM UTC 24 |
| Finished | Sep 11 08:17:10 AM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472052998 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.2472052998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/24.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/24.rv_dm_stress_all.2219466755 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 2353068431 ps |
| CPU time | 6.85 seconds |
| Started | Sep 11 08:17:07 AM UTC 24 |
| Finished | Sep 11 08:17:15 AM UTC 24 |
| Peak memory | 226304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219466755 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.2219466755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/24.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/25.rv_dm_alert_test.3491720000 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 88303230 ps |
| CPU time | 1.04 seconds |
| Started | Sep 11 08:17:09 AM UTC 24 |
| Finished | Sep 11 08:17:11 AM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491720000 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.3491720000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/25.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.376368138 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 2781945101 ps |
| CPU time | 3.15 seconds |
| Started | Sep 11 08:17:09 AM UTC 24 |
| Finished | Sep 11 08:17:13 AM UTC 24 |
| Peak memory | 216128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376368138 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.376368138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/25.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/26.rv_dm_alert_test.2237308119 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 39368076 ps |
| CPU time | 1.19 seconds |
| Started | Sep 11 08:17:09 AM UTC 24 |
| Finished | Sep 11 08:17:11 AM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237308119 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.2237308119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/26.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/26.rv_dm_stress_all.283361552 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 6930688374 ps |
| CPU time | 8.1 seconds |
| Started | Sep 11 08:17:09 AM UTC 24 |
| Finished | Sep 11 08:17:18 AM UTC 24 |
| Peak memory | 216064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283361552 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.283361552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/26.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/27.rv_dm_alert_test.3026360465 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 69992910 ps |
| CPU time | 1.05 seconds |
| Started | Sep 11 08:17:10 AM UTC 24 |
| Finished | Sep 11 08:17:12 AM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026360465 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.3026360465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/27.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.4260119053 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 3872734995 ps |
| CPU time | 11.12 seconds |
| Started | Sep 11 08:17:10 AM UTC 24 |
| Finished | Sep 11 08:17:22 AM UTC 24 |
| Peak memory | 226428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260119053 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.4260119053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/27.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/28.rv_dm_alert_test.677848560 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 55179758 ps |
| CPU time | 0.86 seconds |
| Started | Sep 11 08:17:11 AM UTC 24 |
| Finished | Sep 11 08:17:13 AM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677848560 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.677848560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/28.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/28.rv_dm_stress_all.4198999207 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 820350615 ps |
| CPU time | 2.57 seconds |
| Started | Sep 11 08:17:11 AM UTC 24 |
| Finished | Sep 11 08:17:15 AM UTC 24 |
| Peak memory | 215924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198999207 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.4198999207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/28.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/29.rv_dm_alert_test.912004544 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 42003093 ps |
| CPU time | 1.05 seconds |
| Started | Sep 11 08:17:11 AM UTC 24 |
| Finished | Sep 11 08:17:13 AM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912004544 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.912004544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/29.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/29.rv_dm_stress_all.3897734925 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 3817873112 ps |
| CPU time | 8.97 seconds |
| Started | Sep 11 08:17:11 AM UTC 24 |
| Finished | Sep 11 08:17:21 AM UTC 24 |
| Peak memory | 226492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897734925 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.3897734925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/29.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.4045252551 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 125689332 ps |
| CPU time | 1.04 seconds |
| Started | Sep 11 08:16:23 AM UTC 24 |
| Finished | Sep 11 08:16:25 AM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045252551 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.4045252551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/3.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.4169253008 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 4675611842 ps |
| CPU time | 17.91 seconds |
| Started | Sep 11 08:16:22 AM UTC 24 |
| Finished | Sep 11 08:16:41 AM UTC 24 |
| Peak memory | 226488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169253008 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.4169253008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/3.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.1524278706 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 1099236420 ps |
| CPU time | 3.03 seconds |
| Started | Sep 11 08:16:21 AM UTC 24 |
| Finished | Sep 11 08:16:25 AM UTC 24 |
| Peak memory | 216124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524278706 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.1524278706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/3.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.2390754757 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 271930832 ps |
| CPU time | 1.68 seconds |
| Started | Sep 11 08:16:22 AM UTC 24 |
| Finished | Sep 11 08:16:24 AM UTC 24 |
| Peak memory | 244248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390754757 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_buffered_enable.2390754757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/3.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.637906569 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 5738415199 ps |
| CPU time | 19.16 seconds |
| Started | Sep 11 08:16:20 AM UTC 24 |
| Finished | Sep 11 08:16:41 AM UTC 24 |
| Peak memory | 226484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637906569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_tl_access.637906569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/3.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.125084880 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 217829726 ps |
| CPU time | 1.19 seconds |
| Started | Sep 11 08:16:22 AM UTC 24 |
| Finished | Sep 11 08:16:24 AM UTC 24 |
| Peak memory | 213508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125084880 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_halt_resume_whereto.125084880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/3.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/3.rv_dm_hart_unavail.2240539997 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 56986887 ps |
| CPU time | 1.21 seconds |
| Started | Sep 11 08:16:22 AM UTC 24 |
| Finished | Sep 11 08:16:24 AM UTC 24 |
| Peak memory | 213444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240539997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.2240539997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/3.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.1992762082 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 746250856 ps |
| CPU time | 1.37 seconds |
| Started | Sep 11 08:16:20 AM UTC 24 |
| Finished | Sep 11 08:16:23 AM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992762082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.1992762082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/3.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/3.rv_dm_sec_cm.3103673804 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 1016067923 ps |
| CPU time | 6.5 seconds |
| Started | Sep 11 08:16:23 AM UTC 24 |
| Finished | Sep 11 08:16:31 AM UTC 24 |
| Peak memory | 256932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103673804 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.3103673804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/3.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.1664749421 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 112757850 ps |
| CPU time | 1.46 seconds |
| Started | Sep 11 08:16:22 AM UTC 24 |
| Finished | Sep 11 08:16:24 AM UTC 24 |
| Peak memory | 225424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664749421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sparse_lc_gate_fsm.1664749421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/3.rv_dm_sparse_lc_gate_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.2905790272 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 18223540161 ps |
| CPU time | 127.97 seconds |
| Started | Sep 11 08:16:22 AM UTC 24 |
| Finished | Sep 11 08:18:32 AM UTC 24 |
| Peak memory | 245528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2905790272 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stres s_all_with_rand_reset.2905790272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/30.rv_dm_alert_test.2460096658 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 94045771 ps |
| CPU time | 0.95 seconds |
| Started | Sep 11 08:17:11 AM UTC 24 |
| Finished | Sep 11 08:17:13 AM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460096658 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.2460096658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/30.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.4073818478 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 5505222703 ps |
| CPU time | 8 seconds |
| Started | Sep 11 08:17:11 AM UTC 24 |
| Finished | Sep 11 08:17:20 AM UTC 24 |
| Peak memory | 216056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073818478 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.4073818478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/30.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/31.rv_dm_alert_test.2607450635 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 109497644 ps |
| CPU time | 1.07 seconds |
| Started | Sep 11 08:17:13 AM UTC 24 |
| Finished | Sep 11 08:17:15 AM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607450635 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.2607450635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/31.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/31.rv_dm_stress_all.2289163264 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 2775448889 ps |
| CPU time | 9.7 seconds |
| Started | Sep 11 08:17:13 AM UTC 24 |
| Finished | Sep 11 08:17:23 AM UTC 24 |
| Peak memory | 216076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289163264 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.2289163264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/31.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/32.rv_dm_alert_test.2295193699 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 178025294 ps |
| CPU time | 1.1 seconds |
| Started | Sep 11 08:17:13 AM UTC 24 |
| Finished | Sep 11 08:17:15 AM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295193699 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.2295193699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/32.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/32.rv_dm_stress_all.169560142 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 2604396686 ps |
| CPU time | 3.9 seconds |
| Started | Sep 11 08:17:13 AM UTC 24 |
| Finished | Sep 11 08:17:18 AM UTC 24 |
| Peak memory | 216084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169560142 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.169560142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/32.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/33.rv_dm_alert_test.4062121818 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 40237698 ps |
| CPU time | 0.81 seconds |
| Started | Sep 11 08:17:13 AM UTC 24 |
| Finished | Sep 11 08:17:15 AM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062121818 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.4062121818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/33.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/34.rv_dm_alert_test.2461291697 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 91758734 ps |
| CPU time | 1.18 seconds |
| Started | Sep 11 08:17:14 AM UTC 24 |
| Finished | Sep 11 08:17:16 AM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461291697 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.2461291697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/34.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/34.rv_dm_stress_all.2044152821 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 2602998003 ps |
| CPU time | 9.63 seconds |
| Started | Sep 11 08:17:14 AM UTC 24 |
| Finished | Sep 11 08:17:25 AM UTC 24 |
| Peak memory | 216120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044152821 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.2044152821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/34.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/35.rv_dm_alert_test.1450230613 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 55142963 ps |
| CPU time | 1.07 seconds |
| Started | Sep 11 08:17:14 AM UTC 24 |
| Finished | Sep 11 08:17:16 AM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450230613 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.1450230613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/35.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/35.rv_dm_stress_all.3102582252 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 1609423033 ps |
| CPU time | 5.32 seconds |
| Started | Sep 11 08:17:14 AM UTC 24 |
| Finished | Sep 11 08:17:20 AM UTC 24 |
| Peak memory | 226200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102582252 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.3102582252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/35.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/36.rv_dm_alert_test.1245990509 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 56248228 ps |
| CPU time | 1.09 seconds |
| Started | Sep 11 08:17:14 AM UTC 24 |
| Finished | Sep 11 08:17:16 AM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245990509 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.1245990509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/36.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/36.rv_dm_stress_all.2035457760 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 3429808863 ps |
| CPU time | 6.97 seconds |
| Started | Sep 11 08:17:14 AM UTC 24 |
| Finished | Sep 11 08:17:22 AM UTC 24 |
| Peak memory | 216076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035457760 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.2035457760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/36.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/37.rv_dm_alert_test.1091034887 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 54634148 ps |
| CPU time | 1.11 seconds |
| Started | Sep 11 08:17:16 AM UTC 24 |
| Finished | Sep 11 08:17:18 AM UTC 24 |
| Peak memory | 215844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091034887 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.1091034887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/37.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/37.rv_dm_stress_all.3121829907 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 2713556514 ps |
| CPU time | 11.28 seconds |
| Started | Sep 11 08:17:16 AM UTC 24 |
| Finished | Sep 11 08:17:28 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121829907 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.3121829907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/37.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/38.rv_dm_alert_test.3171773238 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 44172096 ps |
| CPU time | 1.07 seconds |
| Started | Sep 11 08:17:16 AM UTC 24 |
| Finished | Sep 11 08:17:18 AM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171773238 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.3171773238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/38.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/38.rv_dm_stress_all.1013042726 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 2250161103 ps |
| CPU time | 3.36 seconds |
| Started | Sep 11 08:17:16 AM UTC 24 |
| Finished | Sep 11 08:17:20 AM UTC 24 |
| Peak memory | 215988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013042726 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.1013042726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/38.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/39.rv_dm_alert_test.1416602544 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 149268939 ps |
| CPU time | 1.09 seconds |
| Started | Sep 11 08:17:16 AM UTC 24 |
| Finished | Sep 11 08:17:18 AM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416602544 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.1416602544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/39.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/39.rv_dm_stress_all.3452328339 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 1478837461 ps |
| CPU time | 7.33 seconds |
| Started | Sep 11 08:17:16 AM UTC 24 |
| Finished | Sep 11 08:17:24 AM UTC 24 |
| Peak memory | 216068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452328339 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.3452328339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/39.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/4.rv_dm_alert_test.2795248787 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 85097052 ps |
| CPU time | 1.09 seconds |
| Started | Sep 11 08:16:25 AM UTC 24 |
| Finished | Sep 11 08:16:27 AM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795248787 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.2795248787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/4.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/4.rv_dm_autoincr_sba_tl_access.353803007 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 92171362280 ps |
| CPU time | 64.26 seconds |
| Started | Sep 11 08:16:23 AM UTC 24 |
| Finished | Sep 11 08:17:29 AM UTC 24 |
| Peak memory | 226472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353803007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.353803007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/4.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/4.rv_dm_bad_sba_tl_access.1557295165 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 4005284337 ps |
| CPU time | 13.9 seconds |
| Started | Sep 11 08:16:23 AM UTC 24 |
| Finished | Sep 11 08:16:38 AM UTC 24 |
| Peak memory | 226552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557295165 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.1557295165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/4.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/4.rv_dm_buffered_enable.3855234865 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 171722254 ps |
| CPU time | 1.69 seconds |
| Started | Sep 11 08:16:25 AM UTC 24 |
| Finished | Sep 11 08:16:28 AM UTC 24 |
| Peak memory | 257700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855234865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_buffered_enable.3855234865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/4.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.4022997690 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 6290048150 ps |
| CPU time | 8.44 seconds |
| Started | Sep 11 08:16:23 AM UTC 24 |
| Finished | Sep 11 08:16:33 AM UTC 24 |
| Peak memory | 226548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022997690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_tl_access.4022997690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/4.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.4186379024 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1133867894 ps |
| CPU time | 4.4 seconds |
| Started | Sep 11 08:16:23 AM UTC 24 |
| Finished | Sep 11 08:16:29 AM UTC 24 |
| Peak memory | 215924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186379024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_halt_resume_whereto.4186379024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/4.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.2773638727 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 117286204 ps |
| CPU time | 1.66 seconds |
| Started | Sep 11 08:16:23 AM UTC 24 |
| Finished | Sep 11 08:16:26 AM UTC 24 |
| Peak memory | 213444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773638727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.2773638727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/4.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/4.rv_dm_sba_tl_access.2157103257 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 2083042033 ps |
| CPU time | 8.73 seconds |
| Started | Sep 11 08:16:23 AM UTC 24 |
| Finished | Sep 11 08:16:33 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157103257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.2157103257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/4.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/4.rv_dm_sec_cm.958780334 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 2471134110 ps |
| CPU time | 9.82 seconds |
| Started | Sep 11 08:16:25 AM UTC 24 |
| Finished | Sep 11 08:16:36 AM UTC 24 |
| Peak memory | 254812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958780334 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.958780334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/4.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.3602711794 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1953529459 ps |
| CPU time | 5.54 seconds |
| Started | Sep 11 08:16:25 AM UTC 24 |
| Finished | Sep 11 08:16:31 AM UTC 24 |
| Peak memory | 215932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602711794 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.3602711794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/4.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/40.rv_dm_alert_test.2268619713 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 53376783 ps |
| CPU time | 1.13 seconds |
| Started | Sep 11 08:17:17 AM UTC 24 |
| Finished | Sep 11 08:17:20 AM UTC 24 |
| Peak memory | 215760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268619713 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.2268619713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/40.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/40.rv_dm_stress_all.2655719992 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 3898183848 ps |
| CPU time | 10.71 seconds |
| Started | Sep 11 08:17:16 AM UTC 24 |
| Finished | Sep 11 08:17:28 AM UTC 24 |
| Peak memory | 216076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655719992 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.2655719992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/40.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/41.rv_dm_alert_test.2993865533 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 112538904 ps |
| CPU time | 1.63 seconds |
| Started | Sep 11 08:17:17 AM UTC 24 |
| Finished | Sep 11 08:17:20 AM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993865533 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.2993865533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/41.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/41.rv_dm_stress_all.556683835 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 5914895976 ps |
| CPU time | 11.08 seconds |
| Started | Sep 11 08:17:17 AM UTC 24 |
| Finished | Sep 11 08:17:30 AM UTC 24 |
| Peak memory | 215956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556683835 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.556683835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/41.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/42.rv_dm_alert_test.658585689 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 147199674 ps |
| CPU time | 1.16 seconds |
| Started | Sep 11 08:17:17 AM UTC 24 |
| Finished | Sep 11 08:17:20 AM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658585689 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.658585689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/42.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/42.rv_dm_stress_all.395992707 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 6290812949 ps |
| CPU time | 11.43 seconds |
| Started | Sep 11 08:17:17 AM UTC 24 |
| Finished | Sep 11 08:17:30 AM UTC 24 |
| Peak memory | 216132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395992707 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.395992707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/42.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/43.rv_dm_alert_test.4160654304 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 32193974 ps |
| CPU time | 0.95 seconds |
| Started | Sep 11 08:17:19 AM UTC 24 |
| Finished | Sep 11 08:17:21 AM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160654304 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.4160654304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/43.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/43.rv_dm_stress_all.332679470 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 2186969183 ps |
| CPU time | 7.89 seconds |
| Started | Sep 11 08:17:18 AM UTC 24 |
| Finished | Sep 11 08:17:28 AM UTC 24 |
| Peak memory | 216144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332679470 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.332679470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/43.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/44.rv_dm_alert_test.2585429685 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 66853129 ps |
| CPU time | 1.1 seconds |
| Started | Sep 11 08:17:19 AM UTC 24 |
| Finished | Sep 11 08:17:21 AM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585429685 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.2585429685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/44.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.1894956864 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 1624332829 ps |
| CPU time | 3.4 seconds |
| Started | Sep 11 08:17:19 AM UTC 24 |
| Finished | Sep 11 08:17:23 AM UTC 24 |
| Peak memory | 216000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894956864 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.1894956864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/44.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/45.rv_dm_alert_test.270947432 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 78064753 ps |
| CPU time | 1.22 seconds |
| Started | Sep 11 08:17:21 AM UTC 24 |
| Finished | Sep 11 08:17:23 AM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270947432 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.270947432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/45.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/45.rv_dm_stress_all.1949476285 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 2482702651 ps |
| CPU time | 4.47 seconds |
| Started | Sep 11 08:17:19 AM UTC 24 |
| Finished | Sep 11 08:17:24 AM UTC 24 |
| Peak memory | 216260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949476285 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.1949476285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/45.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/46.rv_dm_alert_test.4208215305 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 29628425 ps |
| CPU time | 1.14 seconds |
| Started | Sep 11 08:17:21 AM UTC 24 |
| Finished | Sep 11 08:17:23 AM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208215305 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.4208215305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/46.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.3149120799 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 2337553039 ps |
| CPU time | 3.45 seconds |
| Started | Sep 11 08:17:21 AM UTC 24 |
| Finished | Sep 11 08:17:26 AM UTC 24 |
| Peak memory | 216000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149120799 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.3149120799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/46.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/47.rv_dm_alert_test.2970087931 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 109648794 ps |
| CPU time | 0.92 seconds |
| Started | Sep 11 08:17:21 AM UTC 24 |
| Finished | Sep 11 08:17:23 AM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970087931 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.2970087931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/47.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/47.rv_dm_stress_all.726564830 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 5055511191 ps |
| CPU time | 5.02 seconds |
| Started | Sep 11 08:17:21 AM UTC 24 |
| Finished | Sep 11 08:17:27 AM UTC 24 |
| Peak memory | 216000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726564830 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.726564830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/47.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/48.rv_dm_alert_test.1182777622 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 41136118 ps |
| CPU time | 0.88 seconds |
| Started | Sep 11 08:17:22 AM UTC 24 |
| Finished | Sep 11 08:17:24 AM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182777622 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.1182777622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/48.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/48.rv_dm_stress_all.528406974 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 6427077162 ps |
| CPU time | 3.97 seconds |
| Started | Sep 11 08:17:21 AM UTC 24 |
| Finished | Sep 11 08:17:26 AM UTC 24 |
| Peak memory | 216204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528406974 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.528406974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/48.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/49.rv_dm_alert_test.2397138177 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 198047412 ps |
| CPU time | 1.11 seconds |
| Started | Sep 11 08:17:22 AM UTC 24 |
| Finished | Sep 11 08:17:24 AM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397138177 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.2397138177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/49.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/49.rv_dm_stress_all.347197557 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 2997951030 ps |
| CPU time | 3.53 seconds |
| Started | Sep 11 08:17:22 AM UTC 24 |
| Finished | Sep 11 08:17:27 AM UTC 24 |
| Peak memory | 226428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347197557 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.347197557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/49.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/5.rv_dm_alert_test.4120428807 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 63890945 ps |
| CPU time | 1.17 seconds |
| Started | Sep 11 08:16:27 AM UTC 24 |
| Finished | Sep 11 08:16:29 AM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120428807 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.4120428807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/5.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.25495752 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 116382329380 ps |
| CPU time | 312.67 seconds |
| Started | Sep 11 08:16:26 AM UTC 24 |
| Finished | Sep 11 08:21:43 AM UTC 24 |
| Peak memory | 226484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25495752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv _dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.25495752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/5.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.1507551229 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 9658885841 ps |
| CPU time | 7.38 seconds |
| Started | Sep 11 08:16:25 AM UTC 24 |
| Finished | Sep 11 08:16:34 AM UTC 24 |
| Peak memory | 216308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507551229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.1507551229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/5.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/5.rv_dm_buffered_enable.3041253552 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 288443299 ps |
| CPU time | 1.73 seconds |
| Started | Sep 11 08:16:26 AM UTC 24 |
| Finished | Sep 11 08:16:29 AM UTC 24 |
| Peak memory | 258652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041253552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_buffered_enable.3041253552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/5.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.3157427197 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 14804008820 ps |
| CPU time | 44.32 seconds |
| Started | Sep 11 08:16:25 AM UTC 24 |
| Finished | Sep 11 08:17:11 AM UTC 24 |
| Peak memory | 226416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157427197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl_access.3157427197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/5.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/5.rv_dm_halt_resume_whereto.3869658982 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 295557235 ps |
| CPU time | 1.24 seconds |
| Started | Sep 11 08:16:26 AM UTC 24 |
| Finished | Sep 11 08:16:28 AM UTC 24 |
| Peak memory | 213324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869658982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_halt_resume_whereto.3869658982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/5.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/5.rv_dm_sba_tl_access.1905483274 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 2791523070 ps |
| CPU time | 10.85 seconds |
| Started | Sep 11 08:16:25 AM UTC 24 |
| Finished | Sep 11 08:16:37 AM UTC 24 |
| Peak memory | 216248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905483274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.1905483274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/5.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.3044841112 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 3608162851 ps |
| CPU time | 17.47 seconds |
| Started | Sep 11 08:16:26 AM UTC 24 |
| Finished | Sep 11 08:16:45 AM UTC 24 |
| Peak memory | 226440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044841112 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.3044841112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/5.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/6.rv_dm_alert_test.2844612763 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 59865720 ps |
| CPU time | 1.3 seconds |
| Started | Sep 11 08:16:31 AM UTC 24 |
| Finished | Sep 11 08:16:33 AM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844612763 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.2844612763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/6.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/6.rv_dm_autoincr_sba_tl_access.2183777990 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 6325776167 ps |
| CPU time | 15.19 seconds |
| Started | Sep 11 08:16:29 AM UTC 24 |
| Finished | Sep 11 08:16:45 AM UTC 24 |
| Peak memory | 216256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183777990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.2183777990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/6.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/6.rv_dm_bad_sba_tl_access.1704261689 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 3371278624 ps |
| CPU time | 9.4 seconds |
| Started | Sep 11 08:16:28 AM UTC 24 |
| Finished | Sep 11 08:16:39 AM UTC 24 |
| Peak memory | 226624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704261689 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.1704261689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/6.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/6.rv_dm_buffered_enable.4231871138 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 222314556 ps |
| CPU time | 1.35 seconds |
| Started | Sep 11 08:16:30 AM UTC 24 |
| Finished | Sep 11 08:16:32 AM UTC 24 |
| Peak memory | 251660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231871138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_buffered_enable.4231871138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/6.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.3460376895 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 5378054940 ps |
| CPU time | 9.62 seconds |
| Started | Sep 11 08:16:28 AM UTC 24 |
| Finished | Sep 11 08:16:39 AM UTC 24 |
| Peak memory | 216240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460376895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_tl_access.3460376895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/6.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/6.rv_dm_halt_resume_whereto.830953775 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 547336497 ps |
| CPU time | 3.07 seconds |
| Started | Sep 11 08:16:30 AM UTC 24 |
| Finished | Sep 11 08:16:34 AM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830953775 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_halt_resume_whereto.830953775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/6.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/6.rv_dm_sba_tl_access.3900350414 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 1433957419 ps |
| CPU time | 10.29 seconds |
| Started | Sep 11 08:16:27 AM UTC 24 |
| Finished | Sep 11 08:16:39 AM UTC 24 |
| Peak memory | 216320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900350414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.3900350414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/6.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all.4240966146 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 1529864927 ps |
| CPU time | 4.64 seconds |
| Started | Sep 11 08:16:30 AM UTC 24 |
| Finished | Sep 11 08:16:35 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240966146 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.4240966146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/6.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/7.rv_dm_alert_test.1311079642 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 56312442 ps |
| CPU time | 1.1 seconds |
| Started | Sep 11 08:16:35 AM UTC 24 |
| Finished | Sep 11 08:16:37 AM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311079642 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.1311079642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/7.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.1365728103 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 53016020306 ps |
| CPU time | 96.49 seconds |
| Started | Sep 11 08:16:33 AM UTC 24 |
| Finished | Sep 11 08:18:12 AM UTC 24 |
| Peak memory | 226496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365728103 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.1365728103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/7.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.3573669194 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 1046345326 ps |
| CPU time | 3.28 seconds |
| Started | Sep 11 08:16:32 AM UTC 24 |
| Finished | Sep 11 08:16:36 AM UTC 24 |
| Peak memory | 216308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573669194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.3573669194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/7.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/7.rv_dm_buffered_enable.3238745012 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 646406419 ps |
| CPU time | 1.84 seconds |
| Started | Sep 11 08:16:33 AM UTC 24 |
| Finished | Sep 11 08:16:36 AM UTC 24 |
| Peak memory | 252284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238745012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_buffered_enable.3238745012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/7.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3720219814 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 6022365684 ps |
| CPU time | 11.95 seconds |
| Started | Sep 11 08:16:32 AM UTC 24 |
| Finished | Sep 11 08:16:45 AM UTC 24 |
| Peak memory | 226600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720219814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_tl_access.3720219814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/7.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.916069856 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 206637537 ps |
| CPU time | 1.6 seconds |
| Started | Sep 11 08:16:33 AM UTC 24 |
| Finished | Sep 11 08:16:36 AM UTC 24 |
| Peak memory | 213508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916069856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_halt_resume_whereto.916069856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/7.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/7.rv_dm_sba_tl_access.1232322710 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 3521102453 ps |
| CPU time | 4.73 seconds |
| Started | Sep 11 08:16:32 AM UTC 24 |
| Finished | Sep 11 08:16:38 AM UTC 24 |
| Peak memory | 216324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232322710 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.1232322710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/7.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all.3918245765 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 3690707844 ps |
| CPU time | 8.2 seconds |
| Started | Sep 11 08:16:34 AM UTC 24 |
| Finished | Sep 11 08:16:44 AM UTC 24 |
| Peak memory | 226240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918245765 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.3918245765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/7.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/8.rv_dm_alert_test.1367618544 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 147677235 ps |
| CPU time | 1.29 seconds |
| Started | Sep 11 08:16:38 AM UTC 24 |
| Finished | Sep 11 08:16:40 AM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367618544 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.1367618544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/8.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/8.rv_dm_bad_sba_tl_access.3285846037 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 6985344604 ps |
| CPU time | 18.78 seconds |
| Started | Sep 11 08:16:37 AM UTC 24 |
| Finished | Sep 11 08:16:57 AM UTC 24 |
| Peak memory | 226556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285846037 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.3285846037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/8.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/8.rv_dm_buffered_enable.2130911430 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 565551064 ps |
| CPU time | 2.38 seconds |
| Started | Sep 11 08:16:37 AM UTC 24 |
| Finished | Sep 11 08:16:40 AM UTC 24 |
| Peak memory | 258740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130911430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_buffered_enable.2130911430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/8.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.2260437058 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 6706981161 ps |
| CPU time | 8.54 seconds |
| Started | Sep 11 08:16:35 AM UTC 24 |
| Finished | Sep 11 08:16:44 AM UTC 24 |
| Peak memory | 226416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260437058 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl_access.2260437058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/8.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/8.rv_dm_sba_tl_access.1186852206 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 2152930513 ps |
| CPU time | 10.61 seconds |
| Started | Sep 11 08:16:35 AM UTC 24 |
| Finished | Sep 11 08:16:46 AM UTC 24 |
| Peak memory | 216240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186852206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.1186852206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/8.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.3311790193 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 3666685008 ps |
| CPU time | 16.39 seconds |
| Started | Sep 11 08:16:37 AM UTC 24 |
| Finished | Sep 11 08:16:54 AM UTC 24 |
| Peak memory | 216128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311790193 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.3311790193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/8.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.3238511112 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 39463048 ps |
| CPU time | 1.25 seconds |
| Started | Sep 11 08:16:41 AM UTC 24 |
| Finished | Sep 11 08:16:43 AM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238511112 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.3238511112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/9.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/9.rv_dm_autoincr_sba_tl_access.317560610 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 16653216593 ps |
| CPU time | 56.94 seconds |
| Started | Sep 11 08:16:40 AM UTC 24 |
| Finished | Sep 11 08:17:38 AM UTC 24 |
| Peak memory | 226324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317560610 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.317560610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/9.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.2591211018 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 3217300999 ps |
| CPU time | 15.73 seconds |
| Started | Sep 11 08:16:39 AM UTC 24 |
| Finished | Sep 11 08:16:56 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591211018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.2591211018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/9.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/9.rv_dm_buffered_enable.142736605 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 356133603 ps |
| CPU time | 2.38 seconds |
| Started | Sep 11 08:16:40 AM UTC 24 |
| Finished | Sep 11 08:16:43 AM UTC 24 |
| Peak memory | 246476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142736605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_buffered_enable.142736605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/9.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.1463520992 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 13603313217 ps |
| CPU time | 41.03 seconds |
| Started | Sep 11 08:16:38 AM UTC 24 |
| Finished | Sep 11 08:17:21 AM UTC 24 |
| Peak memory | 226492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463520992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_tl_access.1463520992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/9.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.1925955291 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 3877365076 ps |
| CPU time | 12.37 seconds |
| Started | Sep 11 08:16:38 AM UTC 24 |
| Finished | Sep 11 08:16:52 AM UTC 24 |
| Peak memory | 216332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925955291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.1925955291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/9.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.1865529178 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 3805857138 ps |
| CPU time | 10.54 seconds |
| Started | Sep 11 08:16:40 AM UTC 24 |
| Finished | Sep 11 08:16:51 AM UTC 24 |
| Peak memory | 216136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865529178 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.1865529178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/9.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.4110364194 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 6990066574 ps |
| CPU time | 44.36 seconds |
| Started | Sep 11 08:16:40 AM UTC 24 |
| Finished | Sep 11 08:17:26 AM UTC 24 |
| Peak memory | 233332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=4110364194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stres s_all_with_rand_reset.4110364194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |