| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 89.06 | 96.32 | 90.10 | 92.10 | 94.67 | 90.44 | 98.63 | 61.18 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 53.83 | 53.83 | 85.34 | 85.34 | 54.31 | 54.31 | 26.22 | 26.22 | 46.67 | 46.67 | 66.89 | 66.89 | 92.95 | 92.95 | 4.39 | 4.39 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.2252838734 |
| 63.01 | 9.19 | 86.60 | 1.26 | 61.53 | 7.21 | 29.87 | 3.66 | 48.00 | 1.33 | 71.16 | 4.27 | 94.01 | 1.05 | 49.93 | 45.54 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.4146338 |
| 70.98 | 7.97 | 89.22 | 2.62 | 68.74 | 7.21 | 60.59 | 30.71 | 56.00 | 8.00 | 75.94 | 4.78 | 95.48 | 1.47 | 50.89 | 0.96 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.337085340 |
| 76.03 | 5.05 | 90.08 | 0.86 | 72.14 | 3.39 | 77.82 | 17.23 | 66.67 | 10.67 | 78.16 | 2.22 | 95.90 | 0.42 | 51.44 | 0.55 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.3239986495 |
| 78.92 | 2.89 | 91.74 | 1.66 | 76.38 | 4.24 | 81.55 | 3.74 | 73.33 | 6.67 | 81.57 | 3.41 | 96.00 | 0.11 | 51.85 | 0.41 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.1310125537 |
| 80.17 | 1.25 | 92.70 | 0.96 | 77.65 | 1.27 | 82.31 | 0.76 | 76.00 | 2.67 | 83.45 | 1.88 | 96.00 | 0.00 | 53.09 | 1.23 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.231766980 |
| 81.09 | 0.92 | 93.35 | 0.65 | 78.50 | 0.85 | 84.87 | 2.56 | 77.33 | 1.33 | 84.47 | 1.02 | 96.00 | 0.00 | 53.09 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.723522271 |
| 81.99 | 0.90 | 93.40 | 0.05 | 79.49 | 0.99 | 86.13 | 1.26 | 77.33 | 0.00 | 84.64 | 0.17 | 96.00 | 0.00 | 56.93 | 3.84 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2240695391 |
| 82.79 | 0.80 | 94.16 | 0.76 | 81.19 | 1.70 | 86.39 | 0.25 | 78.67 | 1.33 | 86.01 | 1.37 | 96.21 | 0.21 | 56.93 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all_with_rand_reset.3367035117 |
| 83.34 | 0.55 | 94.26 | 0.10 | 82.32 | 1.13 | 87.23 | 0.84 | 80.00 | 1.33 | 86.18 | 0.17 | 96.21 | 0.00 | 57.20 | 0.27 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_resuming.429667090 |
| 83.86 | 0.52 | 94.66 | 0.40 | 83.17 | 0.85 | 87.27 | 0.04 | 81.33 | 1.33 | 87.03 | 0.85 | 96.21 | 0.00 | 57.34 | 0.14 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.3924966957 |
| 84.35 | 0.49 | 94.81 | 0.15 | 83.59 | 0.42 | 87.27 | 0.00 | 84.00 | 2.67 | 87.20 | 0.17 | 96.21 | 0.00 | 57.34 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.2335348151 |
| 84.82 | 0.48 | 95.21 | 0.40 | 84.30 | 0.71 | 87.65 | 0.38 | 85.33 | 1.33 | 87.71 | 0.51 | 96.21 | 0.00 | 57.34 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.933142803 |
| 85.24 | 0.41 | 95.67 | 0.45 | 85.15 | 0.85 | 88.32 | 0.67 | 85.33 | 0.00 | 88.23 | 0.51 | 96.21 | 0.00 | 57.75 | 0.41 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.1119772072 |
| 85.62 | 0.38 | 95.67 | 0.00 | 85.15 | 0.00 | 88.32 | 0.00 | 88.00 | 2.67 | 88.23 | 0.00 | 96.21 | 0.00 | 57.75 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3001623960 |
| 86.00 | 0.38 | 95.67 | 0.00 | 85.15 | 0.00 | 88.32 | 0.00 | 90.67 | 2.67 | 88.23 | 0.00 | 96.21 | 0.00 | 57.75 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2478321059 |
| 86.37 | 0.37 | 95.67 | 0.00 | 85.15 | 0.00 | 90.80 | 2.48 | 90.67 | 0.00 | 88.23 | 0.00 | 96.21 | 0.00 | 57.89 | 0.14 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/14.rv_dm_autoincr_sba_tl_access.1463314914 |
| 86.70 | 0.32 | 95.67 | 0.00 | 87.41 | 2.26 | 90.80 | 0.00 | 90.67 | 0.00 | 88.23 | 0.00 | 96.21 | 0.00 | 57.89 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.552855755 |
| 86.98 | 0.29 | 95.72 | 0.05 | 87.98 | 0.57 | 90.80 | 0.00 | 90.67 | 0.00 | 88.57 | 0.34 | 97.27 | 1.05 | 57.89 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.3970923096 |
| 87.21 | 0.23 | 95.77 | 0.05 | 87.98 | 0.00 | 90.84 | 0.04 | 92.00 | 1.33 | 88.74 | 0.17 | 97.27 | 0.00 | 57.89 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.826249913 |
| 87.42 | 0.21 | 95.92 | 0.15 | 88.26 | 0.28 | 91.22 | 0.38 | 92.00 | 0.00 | 89.42 | 0.68 | 97.27 | 0.00 | 57.89 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.1515142221 |
| 87.63 | 0.20 | 96.02 | 0.10 | 88.26 | 0.00 | 91.22 | 0.00 | 93.33 | 1.33 | 89.42 | 0.00 | 97.27 | 0.00 | 57.89 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.2479717185 |
| 87.82 | 0.19 | 96.02 | 0.00 | 88.26 | 0.00 | 91.22 | 0.00 | 94.67 | 1.33 | 89.42 | 0.00 | 97.27 | 0.00 | 57.89 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3905707881 |
| 87.99 | 0.17 | 96.02 | 0.00 | 88.68 | 0.42 | 91.64 | 0.42 | 94.67 | 0.00 | 89.42 | 0.00 | 97.37 | 0.11 | 58.16 | 0.27 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.2145091585 |
| 88.14 | 0.15 | 96.02 | 0.00 | 88.83 | 0.14 | 91.72 | 0.08 | 94.67 | 0.00 | 89.42 | 0.00 | 97.37 | 0.00 | 58.98 | 0.82 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.2695557048 |
| 88.24 | 0.10 | 96.07 | 0.05 | 88.97 | 0.14 | 91.89 | 0.17 | 94.67 | 0.00 | 89.76 | 0.34 | 97.37 | 0.00 | 58.98 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.3674718036 |
| 88.34 | 0.10 | 96.07 | 0.00 | 88.97 | 0.00 | 91.89 | 0.00 | 94.67 | 0.00 | 89.76 | 0.00 | 97.37 | 0.00 | 59.67 | 0.69 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_intg_err.4186828542 |
| 88.43 | 0.09 | 96.07 | 0.00 | 88.97 | 0.00 | 91.89 | 0.00 | 94.67 | 0.00 | 89.76 | 0.00 | 98.00 | 0.63 | 59.67 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1772835708 |
| 88.51 | 0.08 | 96.07 | 0.00 | 88.97 | 0.00 | 91.89 | 0.00 | 94.67 | 0.00 | 89.76 | 0.00 | 98.00 | 0.00 | 60.22 | 0.55 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.1300503797 |
| 88.58 | 0.07 | 96.22 | 0.15 | 88.97 | 0.00 | 92.06 | 0.17 | 94.67 | 0.00 | 89.93 | 0.17 | 98.00 | 0.00 | 60.22 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.3943775543 |
| 88.64 | 0.06 | 96.27 | 0.05 | 89.11 | 0.14 | 92.10 | 0.04 | 94.67 | 0.00 | 90.10 | 0.17 | 98.00 | 0.00 | 60.22 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_buffered_enable.1232414228 |
| 88.68 | 0.04 | 96.27 | 0.00 | 89.25 | 0.14 | 92.10 | 0.00 | 94.67 | 0.00 | 90.27 | 0.17 | 98.00 | 0.00 | 60.22 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.4171133371 |
| 88.72 | 0.04 | 96.27 | 0.00 | 89.53 | 0.28 | 92.10 | 0.00 | 94.67 | 0.00 | 90.27 | 0.00 | 98.00 | 0.00 | 60.22 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.1458562380 |
| 88.76 | 0.04 | 96.27 | 0.00 | 89.82 | 0.28 | 92.10 | 0.00 | 94.67 | 0.00 | 90.27 | 0.00 | 98.00 | 0.00 | 60.22 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.3075586461 |
| 88.80 | 0.04 | 96.27 | 0.00 | 89.96 | 0.14 | 92.10 | 0.00 | 94.67 | 0.00 | 90.27 | 0.00 | 98.00 | 0.00 | 60.36 | 0.14 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.990218420 |
| 88.84 | 0.03 | 96.32 | 0.05 | 89.96 | 0.00 | 92.10 | 0.00 | 94.67 | 0.00 | 90.44 | 0.17 | 98.00 | 0.00 | 60.36 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2147604914 |
| 88.87 | 0.03 | 96.32 | 0.00 | 89.96 | 0.00 | 92.10 | 0.00 | 94.67 | 0.00 | 90.44 | 0.00 | 98.21 | 0.21 | 60.36 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.525290027 |
| 88.90 | 0.03 | 96.32 | 0.00 | 89.96 | 0.00 | 92.10 | 0.00 | 94.67 | 0.00 | 90.44 | 0.00 | 98.42 | 0.21 | 60.36 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1498660111 |
| 88.92 | 0.02 | 96.32 | 0.00 | 90.10 | 0.14 | 92.10 | 0.00 | 94.67 | 0.00 | 90.44 | 0.00 | 98.42 | 0.00 | 60.36 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.3365678341 |
| 88.94 | 0.02 | 96.32 | 0.00 | 90.10 | 0.00 | 92.10 | 0.00 | 94.67 | 0.00 | 90.44 | 0.00 | 98.42 | 0.00 | 60.49 | 0.14 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.718402829 |
| 88.96 | 0.02 | 96.32 | 0.00 | 90.10 | 0.00 | 92.10 | 0.00 | 94.67 | 0.00 | 90.44 | 0.00 | 98.42 | 0.00 | 60.63 | 0.14 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2219633736 |
| 88.97 | 0.02 | 96.32 | 0.00 | 90.10 | 0.00 | 92.10 | 0.00 | 94.67 | 0.00 | 90.44 | 0.00 | 98.42 | 0.00 | 60.77 | 0.14 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.1439913661 |
| 88.99 | 0.02 | 96.32 | 0.00 | 90.10 | 0.00 | 92.10 | 0.00 | 94.67 | 0.00 | 90.44 | 0.00 | 98.42 | 0.00 | 60.91 | 0.14 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_hard_reset.623225312 |
| 89.01 | 0.02 | 96.32 | 0.00 | 90.10 | 0.00 | 92.10 | 0.00 | 94.67 | 0.00 | 90.44 | 0.00 | 98.42 | 0.00 | 61.04 | 0.14 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.2657870110 |
| 89.03 | 0.02 | 96.32 | 0.00 | 90.10 | 0.00 | 92.10 | 0.00 | 94.67 | 0.00 | 90.44 | 0.00 | 98.42 | 0.00 | 61.18 | 0.14 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/11.rv_dm_autoincr_sba_tl_access.1884917806 |
| 89.05 | 0.02 | 96.32 | 0.00 | 90.10 | 0.00 | 92.10 | 0.00 | 94.67 | 0.00 | 90.44 | 0.00 | 98.53 | 0.11 | 61.18 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.845875069 |
| 89.06 | 0.02 | 96.32 | 0.00 | 90.10 | 0.00 | 92.10 | 0.00 | 94.67 | 0.00 | 90.44 | 0.00 | 98.63 | 0.11 | 61.18 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.3389219673 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3337877437 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2634587163 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2121089261 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.832718211 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1840104845 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3968363448 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3804329235 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.881319728 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.45219012 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3606870470 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1803947014 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.2895914395 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.10897340 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.2368440893 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2696650336 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.848839847 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3754825903 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.1338819440 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1325065535 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.4278494970 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1434508120 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.884125751 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2887826739 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3670185110 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1734871708 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.607858640 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.983559457 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2573267690 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.1048604065 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.1873089576 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3261192217 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.3291518505 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2478225418 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2196787221 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.856730527 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.999126330 |
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| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/19.rv_dm_alert_test.1276139532 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.1515867896 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/19.rv_dm_bad_sba_tl_access.2366552368 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2425204835 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/19.rv_dm_sba_tl_access.1286577519 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.141730666 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.1928008544 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.1089398649 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.719326809 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.3790103708 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.1069368224 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.3838996531 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.1197099218 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/2.rv_dm_sparse_lc_gate_fsm.55146202 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all.530316595 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.4028215172 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/20.rv_dm_alert_test.77370280 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.765898708 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/21.rv_dm_alert_test.1939010966 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/21.rv_dm_stress_all.3464963481 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/22.rv_dm_alert_test.629734142 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.3786961356 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/23.rv_dm_alert_test.4075665915 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/23.rv_dm_stress_all.116339039 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/24.rv_dm_alert_test.2472052998 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/24.rv_dm_stress_all.2219466755 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/25.rv_dm_alert_test.3491720000 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.376368138 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/26.rv_dm_alert_test.2237308119 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/26.rv_dm_stress_all.283361552 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/27.rv_dm_alert_test.3026360465 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.4260119053 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/28.rv_dm_alert_test.677848560 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/28.rv_dm_stress_all.4198999207 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/29.rv_dm_alert_test.912004544 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/29.rv_dm_stress_all.3897734925 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.4045252551 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.4169253008 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.1524278706 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.2390754757 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.637906569 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.125084880 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/3.rv_dm_hart_unavail.2240539997 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.1992762082 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/3.rv_dm_sec_cm.3103673804 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.1664749421 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.2905790272 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/30.rv_dm_alert_test.2460096658 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.4073818478 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/31.rv_dm_alert_test.2607450635 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/31.rv_dm_stress_all.2289163264 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/32.rv_dm_alert_test.2295193699 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/32.rv_dm_stress_all.169560142 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/33.rv_dm_alert_test.4062121818 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/34.rv_dm_alert_test.2461291697 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/34.rv_dm_stress_all.2044152821 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/35.rv_dm_alert_test.1450230613 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/35.rv_dm_stress_all.3102582252 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/36.rv_dm_alert_test.1245990509 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/36.rv_dm_stress_all.2035457760 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/37.rv_dm_alert_test.1091034887 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/37.rv_dm_stress_all.3121829907 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/38.rv_dm_alert_test.3171773238 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/38.rv_dm_stress_all.1013042726 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/39.rv_dm_alert_test.1416602544 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/39.rv_dm_stress_all.3452328339 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/4.rv_dm_alert_test.2795248787 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/4.rv_dm_autoincr_sba_tl_access.353803007 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/4.rv_dm_bad_sba_tl_access.1557295165 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/4.rv_dm_buffered_enable.3855234865 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.4022997690 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.4186379024 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.2773638727 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/4.rv_dm_sba_tl_access.2157103257 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/4.rv_dm_sec_cm.958780334 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.3602711794 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/40.rv_dm_alert_test.2268619713 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/40.rv_dm_stress_all.2655719992 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/41.rv_dm_alert_test.2993865533 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/41.rv_dm_stress_all.556683835 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/42.rv_dm_alert_test.658585689 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/42.rv_dm_stress_all.395992707 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/43.rv_dm_alert_test.4160654304 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/43.rv_dm_stress_all.332679470 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/44.rv_dm_alert_test.2585429685 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.1894956864 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/45.rv_dm_alert_test.270947432 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/45.rv_dm_stress_all.1949476285 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/46.rv_dm_alert_test.4208215305 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.3149120799 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/47.rv_dm_alert_test.2970087931 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/47.rv_dm_stress_all.726564830 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/48.rv_dm_alert_test.1182777622 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/48.rv_dm_stress_all.528406974 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/49.rv_dm_alert_test.2397138177 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/49.rv_dm_stress_all.347197557 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/5.rv_dm_alert_test.4120428807 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.25495752 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.1507551229 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/5.rv_dm_buffered_enable.3041253552 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.3157427197 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/5.rv_dm_halt_resume_whereto.3869658982 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/5.rv_dm_sba_tl_access.1905483274 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.3044841112 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/6.rv_dm_alert_test.2844612763 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/6.rv_dm_autoincr_sba_tl_access.2183777990 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/6.rv_dm_bad_sba_tl_access.1704261689 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/6.rv_dm_buffered_enable.4231871138 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.3460376895 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/6.rv_dm_halt_resume_whereto.830953775 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/6.rv_dm_sba_tl_access.3900350414 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all.4240966146 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/7.rv_dm_alert_test.1311079642 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.1365728103 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.3573669194 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/7.rv_dm_buffered_enable.3238745012 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3720219814 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.916069856 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/7.rv_dm_sba_tl_access.1232322710 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all.3918245765 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/8.rv_dm_alert_test.1367618544 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/8.rv_dm_bad_sba_tl_access.3285846037 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/8.rv_dm_buffered_enable.2130911430 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.2260437058 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/8.rv_dm_sba_tl_access.1186852206 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.3311790193 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.3238511112 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/9.rv_dm_autoincr_sba_tl_access.317560610 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.2591211018 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/9.rv_dm_buffered_enable.142736605 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.1463520992 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.1925955291 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.1865529178 |
| /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.4110364194 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_tl_access.1915880307 | Sep 11 08:16:07 AM UTC 24 | Sep 11 08:16:10 AM UTC 24 | 796223874 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_halted.92819288 | Sep 11 08:16:08 AM UTC 24 | Sep 11 08:16:10 AM UTC 24 | 558048300 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.362287415 | Sep 11 08:16:08 AM UTC 24 | Sep 11 08:16:10 AM UTC 24 | 398170085 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_hart_unavail.1517808866 | Sep 11 08:16:08 AM UTC 24 | Sep 11 08:16:11 AM UTC 24 | 157332715 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_resuming.429667090 | Sep 11 08:16:08 AM UTC 24 | Sep 11 08:16:12 AM UTC 24 | 395424143 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.1439913661 | Sep 11 08:16:08 AM UTC 24 | Sep 11 08:16:12 AM UTC 24 | 584666444 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_smoke.147363242 | Sep 11 08:16:07 AM UTC 24 | Sep 11 08:16:12 AM UTC 24 | 1476607864 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_dataaddr_rw_access.551026652 | Sep 11 08:16:10 AM UTC 24 | Sep 11 08:16:13 AM UTC 24 | 333372143 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.3365678341 | Sep 11 08:16:09 AM UTC 24 | Sep 11 08:16:13 AM UTC 24 | 1400484267 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.2252838734 | Sep 11 08:16:10 AM UTC 24 | Sep 11 08:16:13 AM UTC 24 | 292943165 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.4171133371 | Sep 11 08:16:10 AM UTC 24 | Sep 11 08:16:13 AM UTC 24 | 1006218768 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_debug_disabled.997374069 | Sep 11 08:16:16 AM UTC 24 | Sep 11 08:16:24 AM UTC 24 | 3792166439 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.153712485 | Sep 11 08:16:12 AM UTC 24 | Sep 11 08:16:13 AM UTC 24 | 321530905 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_busy.3028857384 | Sep 11 08:16:08 AM UTC 24 | Sep 11 08:16:14 AM UTC 24 | 1133804651 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.3674718036 | Sep 11 08:16:12 AM UTC 24 | Sep 11 08:16:14 AM UTC 24 | 129930942 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_idle_hint.3126828668 | Sep 11 08:16:11 AM UTC 24 | Sep 11 08:16:14 AM UTC 24 | 637643233 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.3943775543 | Sep 11 08:16:11 AM UTC 24 | Sep 11 08:16:14 AM UTC 24 | 456151173 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_hard_reset.1866008871 | Sep 11 08:16:12 AM UTC 24 | Sep 11 08:16:14 AM UTC 24 | 214671276 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.725211682 | Sep 11 08:16:12 AM UTC 24 | Sep 11 08:16:14 AM UTC 24 | 145730082 ps | ||
| T79 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.552855755 | Sep 11 08:16:13 AM UTC 24 | Sep 11 08:16:15 AM UTC 24 | 44344578 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.337085340 | Sep 11 08:16:07 AM UTC 24 | Sep 11 08:16:15 AM UTC 24 | 3161181155 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.845875069 | Sep 11 08:16:13 AM UTC 24 | Sep 11 08:16:15 AM UTC 24 | 67161339 ps | ||
| T91 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_debug_disabled.3881616068 | Sep 11 08:16:13 AM UTC 24 | Sep 11 08:16:15 AM UTC 24 | 82711392 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.889607999 | Sep 11 08:16:13 AM UTC 24 | Sep 11 08:16:15 AM UTC 24 | 424043429 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.2479717185 | Sep 11 08:16:13 AM UTC 24 | Sep 11 08:16:15 AM UTC 24 | 98550822 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.723522271 | Sep 11 08:16:13 AM UTC 24 | Sep 11 08:16:15 AM UTC 24 | 139502116 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_hartsel_warl.355547412 | Sep 11 08:16:13 AM UTC 24 | Sep 11 08:16:16 AM UTC 24 | 268767459 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2612241550 | Sep 11 08:16:12 AM UTC 24 | Sep 11 08:16:16 AM UTC 24 | 720283110 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.1119772072 | Sep 11 08:16:14 AM UTC 24 | Sep 11 08:16:16 AM UTC 24 | 61993134 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_resuming.2995433326 | Sep 11 08:16:16 AM UTC 24 | Sep 11 08:16:18 AM UTC 24 | 145534096 ps | ||
| T100 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_hart_unavail.341449570 | Sep 11 08:16:16 AM UTC 24 | Sep 11 08:16:18 AM UTC 24 | 75092370 ps | ||
| T168 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_halted.2917045648 | Sep 11 08:16:16 AM UTC 24 | Sep 11 08:16:18 AM UTC 24 | 92064242 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.1515142221 | Sep 11 08:16:16 AM UTC 24 | Sep 11 08:16:18 AM UTC 24 | 227076706 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_smoke.1357762703 | Sep 11 08:16:14 AM UTC 24 | Sep 11 08:16:18 AM UTC 24 | 606713700 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_ndmreset_req.193793093 | Sep 11 08:16:16 AM UTC 24 | Sep 11 08:16:18 AM UTC 24 | 148173775 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.2456136337 | Sep 11 08:16:16 AM UTC 24 | Sep 11 08:16:18 AM UTC 24 | 211253559 ps | ||
| T169 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_dataaddr_rw_access.2267932421 | Sep 11 08:16:16 AM UTC 24 | Sep 11 08:16:18 AM UTC 24 | 115301047 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_halt_resume_whereto.677705603 | Sep 11 08:16:16 AM UTC 24 | Sep 11 08:16:18 AM UTC 24 | 793190621 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.1871716201 | Sep 11 08:16:14 AM UTC 24 | Sep 11 08:16:18 AM UTC 24 | 1438189685 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_busy.1389118340 | Sep 11 08:16:16 AM UTC 24 | Sep 11 08:16:18 AM UTC 24 | 255186643 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.3239986495 | Sep 11 08:16:07 AM UTC 24 | Sep 11 08:16:18 AM UTC 24 | 8338981058 ps | ||
| T85 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.1669633555 | Sep 11 08:16:14 AM UTC 24 | Sep 11 08:16:19 AM UTC 24 | 1425849379 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_abstractcmd_status.2413392956 | Sep 11 08:16:17 AM UTC 24 | Sep 11 08:16:19 AM UTC 24 | 282524496 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_rom_read_access.2082278868 | Sep 11 08:16:17 AM UTC 24 | Sep 11 08:16:19 AM UTC 24 | 67662595 ps | ||
| T80 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1660368561 | Sep 11 08:16:17 AM UTC 24 | Sep 11 08:16:19 AM UTC 24 | 802812470 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_not_supported.2544857789 | Sep 11 08:16:16 AM UTC 24 | Sep 11 08:16:19 AM UTC 24 | 547780312 ps | ||
| T88 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.792011827 | Sep 11 08:16:07 AM UTC 24 | Sep 11 08:16:19 AM UTC 24 | 7359126769 ps | ||
| T89 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_bad_sba_tl_access.1885128072 | Sep 11 08:16:14 AM UTC 24 | Sep 11 08:16:20 AM UTC 24 | 4346573935 ps | ||
| T78 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_hard_reset.623225312 | Sep 11 08:16:17 AM UTC 24 | Sep 11 08:16:20 AM UTC 24 | 869365392 ps | ||
| T184 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1425595455 | Sep 11 08:16:17 AM UTC 24 | Sep 11 08:16:20 AM UTC 24 | 429443124 ps | ||
| T183 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.3702643224 | Sep 11 08:16:17 AM UTC 24 | Sep 11 08:16:20 AM UTC 24 | 302251623 ps | ||
| T94 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_debug_disabled.820421504 | Sep 11 08:16:18 AM UTC 24 | Sep 11 08:16:20 AM UTC 24 | 44457764 ps | ||
| T52 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.3389219673 | Sep 11 08:16:19 AM UTC 24 | Sep 11 08:16:21 AM UTC 24 | 69234478 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_alert_test.1413847421 | Sep 11 08:16:19 AM UTC 24 | Sep 11 08:16:21 AM UTC 24 | 92538567 ps | ||
| T92 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_sec_cm.1022958667 | Sep 11 08:16:19 AM UTC 24 | Sep 11 08:16:21 AM UTC 24 | 520485215 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_buffered_enable.1232414228 | Sep 11 08:16:19 AM UTC 24 | Sep 11 08:16:21 AM UTC 24 | 213210557 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_progbuf_read_write_execute.648563502 | Sep 11 08:16:18 AM UTC 24 | Sep 11 08:16:22 AM UTC 24 | 905246433 ps | ||
| T99 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.3838996531 | Sep 11 08:16:20 AM UTC 24 | Sep 11 08:16:22 AM UTC 24 | 117390019 ps | ||
| T76 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.3924966957 | Sep 11 08:16:18 AM UTC 24 | Sep 11 08:16:22 AM UTC 24 | 565872299 ps | ||
| T93 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.1928008544 | Sep 11 08:16:20 AM UTC 24 | Sep 11 08:16:22 AM UTC 24 | 64863119 ps | ||
| T84 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/2.rv_dm_sparse_lc_gate_fsm.55146202 | Sep 11 08:16:20 AM UTC 24 | Sep 11 08:16:22 AM UTC 24 | 152438946 ps | ||
| T87 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.719326809 | Sep 11 08:16:20 AM UTC 24 | Sep 11 08:16:23 AM UTC 24 | 156464162 ps | ||
| T120 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_tl_access.2918312555 | Sep 11 08:16:14 AM UTC 24 | Sep 11 08:16:23 AM UTC 24 | 8563254010 ps | ||
| T121 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.1992762082 | Sep 11 08:16:20 AM UTC 24 | Sep 11 08:16:23 AM UTC 24 | 746250856 ps | ||
| T90 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.2145091585 | Sep 11 08:16:20 AM UTC 24 | Sep 11 08:16:23 AM UTC 24 | 688137564 ps | ||
| T59 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.1069368224 | Sep 11 08:16:20 AM UTC 24 | Sep 11 08:16:23 AM UTC 24 | 399735351 ps | ||
| T122 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.3790103708 | Sep 11 08:16:19 AM UTC 24 | Sep 11 08:16:24 AM UTC 24 | 1697094452 ps | ||
| T259 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/3.rv_dm_hart_unavail.2240539997 | Sep 11 08:16:22 AM UTC 24 | Sep 11 08:16:24 AM UTC 24 | 56986887 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.125084880 | Sep 11 08:16:22 AM UTC 24 | Sep 11 08:16:24 AM UTC 24 | 217829726 ps | ||
| T86 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.1664749421 | Sep 11 08:16:22 AM UTC 24 | Sep 11 08:16:24 AM UTC 24 | 112757850 ps | ||
| T116 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.2390754757 | Sep 11 08:16:22 AM UTC 24 | Sep 11 08:16:24 AM UTC 24 | 271930832 ps | ||
| T117 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.1524278706 | Sep 11 08:16:21 AM UTC 24 | Sep 11 08:16:25 AM UTC 24 | 1099236420 ps | ||
| T51 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.4045252551 | Sep 11 08:16:23 AM UTC 24 | Sep 11 08:16:25 AM UTC 24 | 125689332 ps | ||
| T248 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.2773638727 | Sep 11 08:16:23 AM UTC 24 | Sep 11 08:16:26 AM UTC 24 | 117286204 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.1310125537 | Sep 11 08:16:22 AM UTC 24 | Sep 11 08:16:26 AM UTC 24 | 5563406118 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all.530316595 | Sep 11 08:16:20 AM UTC 24 | Sep 11 08:16:27 AM UTC 24 | 5675473912 ps | ||
| T170 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/4.rv_dm_alert_test.2795248787 | Sep 11 08:16:25 AM UTC 24 | Sep 11 08:16:27 AM UTC 24 | 85097052 ps | ||
| T253 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/4.rv_dm_buffered_enable.3855234865 | Sep 11 08:16:25 AM UTC 24 | Sep 11 08:16:28 AM UTC 24 | 171722254 ps | ||
| T61 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/5.rv_dm_halt_resume_whereto.3869658982 | Sep 11 08:16:26 AM UTC 24 | Sep 11 08:16:28 AM UTC 24 | 295557235 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.4186379024 | Sep 11 08:16:23 AM UTC 24 | Sep 11 08:16:29 AM UTC 24 | 1133867894 ps | ||
| T207 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/5.rv_dm_buffered_enable.3041253552 | Sep 11 08:16:26 AM UTC 24 | Sep 11 08:16:29 AM UTC 24 | 288443299 ps | ||
| T171 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/5.rv_dm_alert_test.4120428807 | Sep 11 08:16:27 AM UTC 24 | Sep 11 08:16:29 AM UTC 24 | 63890945 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.990218420 | Sep 11 08:16:14 AM UTC 24 | Sep 11 08:16:30 AM UTC 24 | 4084517031 ps | ||
| T97 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/3.rv_dm_sec_cm.3103673804 | Sep 11 08:16:23 AM UTC 24 | Sep 11 08:16:31 AM UTC 24 | 1016067923 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.3602711794 | Sep 11 08:16:25 AM UTC 24 | Sep 11 08:16:31 AM UTC 24 | 1953529459 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/6.rv_dm_buffered_enable.4231871138 | Sep 11 08:16:30 AM UTC 24 | Sep 11 08:16:32 AM UTC 24 | 222314556 ps | ||
| T140 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.4022997690 | Sep 11 08:16:23 AM UTC 24 | Sep 11 08:16:33 AM UTC 24 | 6290048150 ps | ||
| T195 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/4.rv_dm_sba_tl_access.2157103257 | Sep 11 08:16:23 AM UTC 24 | Sep 11 08:16:33 AM UTC 24 | 2083042033 ps | ||
| T172 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/6.rv_dm_alert_test.2844612763 | Sep 11 08:16:31 AM UTC 24 | Sep 11 08:16:33 AM UTC 24 | 59865720 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.231766980 | Sep 11 08:16:20 AM UTC 24 | Sep 11 08:16:33 AM UTC 24 | 5789238556 ps | ||
| T118 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.1507551229 | Sep 11 08:16:25 AM UTC 24 | Sep 11 08:16:34 AM UTC 24 | 9658885841 ps | ||
| T95 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/14.rv_dm_stress_all.692471193 | Sep 11 08:16:51 AM UTC 24 | Sep 11 08:17:02 AM UTC 24 | 3248091828 ps | ||
| T206 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/6.rv_dm_halt_resume_whereto.830953775 | Sep 11 08:16:30 AM UTC 24 | Sep 11 08:16:34 AM UTC 24 | 547336497 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all.4240966146 | Sep 11 08:16:30 AM UTC 24 | Sep 11 08:16:35 AM UTC 24 | 1529864927 ps | ||
| T98 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/4.rv_dm_sec_cm.958780334 | Sep 11 08:16:25 AM UTC 24 | Sep 11 08:16:36 AM UTC 24 | 2471134110 ps | ||
| T192 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.916069856 | Sep 11 08:16:33 AM UTC 24 | Sep 11 08:16:36 AM UTC 24 | 206637537 ps | ||
| T262 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/7.rv_dm_buffered_enable.3238745012 | Sep 11 08:16:33 AM UTC 24 | Sep 11 08:16:36 AM UTC 24 | 646406419 ps | ||
| T119 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.3573669194 | Sep 11 08:16:32 AM UTC 24 | Sep 11 08:16:36 AM UTC 24 | 1046345326 ps | ||
| T233 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/7.rv_dm_alert_test.1311079642 | Sep 11 08:16:35 AM UTC 24 | Sep 11 08:16:37 AM UTC 24 | 56312442 ps | ||
| T238 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/5.rv_dm_sba_tl_access.1905483274 | Sep 11 08:16:25 AM UTC 24 | Sep 11 08:16:37 AM UTC 24 | 2791523070 ps | ||
| T263 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/7.rv_dm_sba_tl_access.1232322710 | Sep 11 08:16:32 AM UTC 24 | Sep 11 08:16:38 AM UTC 24 | 3521102453 ps | ||
| T264 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/4.rv_dm_bad_sba_tl_access.1557295165 | Sep 11 08:16:23 AM UTC 24 | Sep 11 08:16:38 AM UTC 24 | 4005284337 ps | ||
| T265 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/6.rv_dm_sba_tl_access.3900350414 | Sep 11 08:16:27 AM UTC 24 | Sep 11 08:16:39 AM UTC 24 | 1433957419 ps | ||
| T239 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/6.rv_dm_bad_sba_tl_access.1704261689 | Sep 11 08:16:28 AM UTC 24 | Sep 11 08:16:39 AM UTC 24 | 3371278624 ps | ||
| T266 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.3460376895 | Sep 11 08:16:28 AM UTC 24 | Sep 11 08:16:39 AM UTC 24 | 5378054940 ps | ||
| T186 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/8.rv_dm_buffered_enable.2130911430 | Sep 11 08:16:37 AM UTC 24 | Sep 11 08:16:40 AM UTC 24 | 565551064 ps | ||
| T267 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/8.rv_dm_alert_test.1367618544 | Sep 11 08:16:38 AM UTC 24 | Sep 11 08:16:40 AM UTC 24 | 147677235 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.4169253008 | Sep 11 08:16:22 AM UTC 24 | Sep 11 08:16:41 AM UTC 24 | 4675611842 ps | ||
| T96 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.2657870110 | Sep 11 08:16:19 AM UTC 24 | Sep 11 08:16:41 AM UTC 24 | 7593505675 ps | ||
| T268 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.637906569 | Sep 11 08:16:20 AM UTC 24 | Sep 11 08:16:41 AM UTC 24 | 5738415199 ps | ||
| T187 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/9.rv_dm_buffered_enable.142736605 | Sep 11 08:16:40 AM UTC 24 | Sep 11 08:16:43 AM UTC 24 | 356133603 ps | ||
| T245 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.3238511112 | Sep 11 08:16:41 AM UTC 24 | Sep 11 08:16:43 AM UTC 24 | 39463048 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all.3918245765 | Sep 11 08:16:34 AM UTC 24 | Sep 11 08:16:44 AM UTC 24 | 3690707844 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_autoincr_sba_tl_access.4002701746 | Sep 11 08:16:15 AM UTC 24 | Sep 11 08:16:44 AM UTC 24 | 16315070066 ps | ||
| T269 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.2260437058 | Sep 11 08:16:35 AM UTC 24 | Sep 11 08:16:44 AM UTC 24 | 6706981161 ps | ||
| T188 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.2695557048 | Sep 11 08:16:37 AM UTC 24 | Sep 11 08:16:44 AM UTC 24 | 5439562985 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.3044841112 | Sep 11 08:16:26 AM UTC 24 | Sep 11 08:16:45 AM UTC 24 | 3608162851 ps | ||
| T190 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/6.rv_dm_autoincr_sba_tl_access.2183777990 | Sep 11 08:16:29 AM UTC 24 | Sep 11 08:16:45 AM UTC 24 | 6325776167 ps | ||
| T196 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3720219814 | Sep 11 08:16:32 AM UTC 24 | Sep 11 08:16:45 AM UTC 24 | 6022365684 ps | ||
| T270 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/10.rv_dm_sba_tl_access.2376865289 | Sep 11 08:16:41 AM UTC 24 | Sep 11 08:16:46 AM UTC 24 | 1532385902 ps | ||
| T224 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/10.rv_dm_autoincr_sba_tl_access.2980383546 | Sep 11 08:16:42 AM UTC 24 | Sep 11 08:16:46 AM UTC 24 | 2189350058 ps | ||
| T271 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/8.rv_dm_sba_tl_access.1186852206 | Sep 11 08:16:35 AM UTC 24 | Sep 11 08:16:46 AM UTC 24 | 2152930513 ps | ||
| T225 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/10.rv_dm_alert_test.301601735 | Sep 11 08:16:44 AM UTC 24 | Sep 11 08:16:46 AM UTC 24 | 122985268 ps | ||
| T272 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.854746425 | Sep 11 08:16:08 AM UTC 24 | Sep 11 08:16:46 AM UTC 24 | 46112618393 ps | ||
| T273 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/10.rv_dm_bad_sba_tl_access.2937590642 | Sep 11 08:16:42 AM UTC 24 | Sep 11 08:16:46 AM UTC 24 | 1035108090 ps | ||
| T274 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/11.rv_dm_sba_tl_access.1216336140 | Sep 11 08:16:44 AM UTC 24 | Sep 11 08:16:47 AM UTC 24 | 981180264 ps | ||
| T275 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.3540767504 | Sep 11 08:16:41 AM UTC 24 | Sep 11 08:16:47 AM UTC 24 | 1644311079 ps | ||
| T222 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/11.rv_dm_alert_test.3923387736 | Sep 11 08:16:46 AM UTC 24 | Sep 11 08:16:48 AM UTC 24 | 117108828 ps | ||
| T252 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.2550612032 | Sep 11 08:16:44 AM UTC 24 | Sep 11 08:16:48 AM UTC 24 | 1185922745 ps | ||
| T227 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.1197099218 | Sep 11 08:16:19 AM UTC 24 | Sep 11 08:16:48 AM UTC 24 | 7569547755 ps | ||
| T276 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.1089398649 | Sep 11 08:16:20 AM UTC 24 | Sep 11 08:16:49 AM UTC 24 | 11373458630 ps | ||
| T260 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/12.rv_dm_alert_test.3867951581 | Sep 11 08:16:47 AM UTC 24 | Sep 11 08:16:49 AM UTC 24 | 130013245 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/10.rv_dm_stress_all.4074303989 | Sep 11 08:16:42 AM UTC 24 | Sep 11 08:16:50 AM UTC 24 | 2847502685 ps | ||
| T277 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/12.rv_dm_sba_tl_access.3682821892 | Sep 11 08:16:46 AM UTC 24 | Sep 11 08:16:50 AM UTC 24 | 1771367648 ps | ||
| T191 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/12.rv_dm_stress_all.2970292537 | Sep 11 08:16:47 AM UTC 24 | Sep 11 08:16:51 AM UTC 24 | 1762355045 ps | ||
| T278 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.4129995776 | Sep 11 08:16:48 AM UTC 24 | Sep 11 08:16:51 AM UTC 24 | 3267296494 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.1865529178 | Sep 11 08:16:40 AM UTC 24 | Sep 11 08:16:51 AM UTC 24 | 3805857138 ps | ||
| T279 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/13.rv_dm_alert_test.3234367903 | Sep 11 08:16:49 AM UTC 24 | Sep 11 08:16:51 AM UTC 24 | 138997438 ps | ||
| T247 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/11.rv_dm_bad_sba_tl_access.848580032 | Sep 11 08:16:45 AM UTC 24 | Sep 11 08:16:51 AM UTC 24 | 3007692559 ps | ||
| T280 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.1925955291 | Sep 11 08:16:38 AM UTC 24 | Sep 11 08:16:52 AM UTC 24 | 3877365076 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.933142803 | Sep 11 08:16:19 AM UTC 24 | Sep 11 08:16:52 AM UTC 24 | 8304862630 ps | ||
| T123 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/14.rv_dm_alert_test.2463336528 | Sep 11 08:16:51 AM UTC 24 | Sep 11 08:16:53 AM UTC 24 | 103760823 ps | ||
| T124 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.3444156244 | Sep 11 08:16:46 AM UTC 24 | Sep 11 08:16:53 AM UTC 24 | 8194413569 ps | ||
| T125 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/13.rv_dm_bad_sba_tl_access.927578918 | Sep 11 08:16:48 AM UTC 24 | Sep 11 08:16:54 AM UTC 24 | 2485072462 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.3311790193 | Sep 11 08:16:37 AM UTC 24 | Sep 11 08:16:54 AM UTC 24 | 3666685008 ps | ||
| T126 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/15.rv_dm_alert_test.1126312529 | Sep 11 08:16:53 AM UTC 24 | Sep 11 08:16:56 AM UTC 24 | 46622367 ps | ||
| T70 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.4028215172 | Sep 11 08:16:20 AM UTC 24 | Sep 11 08:16:56 AM UTC 24 | 4633960847 ps | ||
| T127 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.2591211018 | Sep 11 08:16:39 AM UTC 24 | Sep 11 08:16:56 AM UTC 24 | 3217300999 ps | ||
| T128 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/15.rv_dm_bad_sba_tl_access.2712166071 | Sep 11 08:16:53 AM UTC 24 | Sep 11 08:16:57 AM UTC 24 | 1398947989 ps | ||
| T129 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/8.rv_dm_bad_sba_tl_access.3285846037 | Sep 11 08:16:37 AM UTC 24 | Sep 11 08:16:57 AM UTC 24 | 6985344604 ps | ||
| T177 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/17.rv_dm_alert_test.1272980533 | Sep 11 08:16:58 AM UTC 24 | Sep 11 08:17:00 AM UTC 24 | 88923434 ps | ||
| T178 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/16.rv_dm_sba_tl_access.751300315 | Sep 11 08:16:53 AM UTC 24 | Sep 11 08:16:57 AM UTC 24 | 2172717513 ps | ||
| T179 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/14.rv_dm_bad_sba_tl_access.790134695 | Sep 11 08:16:50 AM UTC 24 | Sep 11 08:16:57 AM UTC 24 | 3597649790 ps | ||
| T180 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/16.rv_dm_alert_test.1657443153 | Sep 11 08:16:55 AM UTC 24 | Sep 11 08:16:57 AM UTC 24 | 35188595 ps | ||
| T181 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/15.rv_dm_sba_tl_access.1922088673 | Sep 11 08:16:53 AM UTC 24 | Sep 11 08:16:59 AM UTC 24 | 2422309105 ps | ||
| T182 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/14.rv_dm_sba_tl_access.2496996329 | Sep 11 08:16:50 AM UTC 24 | Sep 11 08:16:58 AM UTC 24 | 2084526815 ps | ||
| T230 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/15.rv_dm_stress_all.1341694698 | Sep 11 08:16:53 AM UTC 24 | Sep 11 08:16:59 AM UTC 24 | 1791722795 ps | ||
| T235 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/20.rv_dm_alert_test.77370280 | Sep 11 08:17:05 AM UTC 24 | Sep 11 08:17:07 AM UTC 24 | 41161552 ps | ||
| T281 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.3426951909 | Sep 11 08:16:50 AM UTC 24 | Sep 11 08:16:59 AM UTC 24 | 3196339964 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/16.rv_dm_stress_all.1677177210 | Sep 11 08:16:55 AM UTC 24 | Sep 11 08:17:02 AM UTC 24 | 3784885731 ps | ||
| T246 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/18.rv_dm_autoincr_sba_tl_access.3489142955 | Sep 11 08:16:59 AM UTC 24 | Sep 11 08:17:03 AM UTC 24 | 1141767642 ps | ||
| T282 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/18.rv_dm_alert_test.4218518599 | Sep 11 08:17:00 AM UTC 24 | Sep 11 08:17:03 AM UTC 24 | 99499186 ps | ||
| T283 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/17.rv_dm_bad_sba_tl_access.1299995075 | Sep 11 08:16:58 AM UTC 24 | Sep 11 08:17:04 AM UTC 24 | 4181119364 ps | ||
| T284 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/13.rv_dm_sba_tl_access.3366031351 | Sep 11 08:16:47 AM UTC 24 | Sep 11 08:17:04 AM UTC 24 | 5753345758 ps | ||
| T193 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/18.rv_dm_bad_sba_tl_access.1145704948 | Sep 11 08:16:59 AM UTC 24 | Sep 11 08:17:04 AM UTC 24 | 1815022539 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all_with_rand_reset.3367035117 | Sep 11 08:16:31 AM UTC 24 | Sep 11 08:17:05 AM UTC 24 | 7436258293 ps | ||
| T285 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/16.rv_dm_bad_sba_tl_access.2781450641 | Sep 11 08:16:55 AM UTC 24 | Sep 11 08:17:05 AM UTC 24 | 1328372700 ps | ||
| T221 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/13.rv_dm_stress_all.4223345972 | Sep 11 08:16:49 AM UTC 24 | Sep 11 08:17:05 AM UTC 24 | 3858442197 ps | ||
| T218 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.4097753422 | Sep 11 08:16:57 AM UTC 24 | Sep 11 08:17:06 AM UTC 24 | 2319303990 ps | ||
| T286 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.1598084674 | Sep 11 08:16:53 AM UTC 24 | Sep 11 08:17:06 AM UTC 24 | 9409026283 ps | ||
| T229 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/19.rv_dm_alert_test.1276139532 | Sep 11 08:17:04 AM UTC 24 | Sep 11 08:17:06 AM UTC 24 | 40194474 ps | ||
| T287 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/12.rv_dm_bad_sba_tl_access.1479910527 | Sep 11 08:16:47 AM UTC 24 | Sep 11 08:17:06 AM UTC 24 | 5816352111 ps | ||
| T194 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/11.rv_dm_autoincr_sba_tl_access.1884917806 | Sep 11 08:16:45 AM UTC 24 | Sep 11 08:17:07 AM UTC 24 | 5704315796 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.141730666 | Sep 11 08:17:04 AM UTC 24 | Sep 11 08:17:08 AM UTC 24 | 2602183318 ps | ||
| T255 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.2920307857 | Sep 11 08:16:59 AM UTC 24 | Sep 11 08:17:08 AM UTC 24 | 2668437518 ps | ||
| T234 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/21.rv_dm_alert_test.1939010966 | Sep 11 08:17:06 AM UTC 24 | Sep 11 08:17:08 AM UTC 24 | 111951162 ps | ||
| T236 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/22.rv_dm_alert_test.629734142 | Sep 11 08:17:06 AM UTC 24 | Sep 11 08:17:09 AM UTC 24 | 79868521 ps | ||
| T288 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/24.rv_dm_alert_test.2472052998 | Sep 11 08:17:07 AM UTC 24 | Sep 11 08:17:10 AM UTC 24 | 236777364 ps | ||
| T289 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.765898708 | Sep 11 08:17:05 AM UTC 24 | Sep 11 08:17:10 AM UTC 24 | 8385309040 ps | ||
| T226 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/23.rv_dm_alert_test.4075665915 | Sep 11 08:17:07 AM UTC 24 | Sep 11 08:17:10 AM UTC 24 | 84165037 ps | ||
| T290 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/17.rv_dm_sba_tl_access.2340740987 | Sep 11 08:16:56 AM UTC 24 | Sep 11 08:17:10 AM UTC 24 | 2394098314 ps | ||
| T291 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/18.rv_dm_sba_tl_access.2027740309 | Sep 11 08:16:58 AM UTC 24 | Sep 11 08:17:11 AM UTC 24 | 3127191782 ps | ||
| T232 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/25.rv_dm_alert_test.3491720000 | Sep 11 08:17:09 AM UTC 24 | Sep 11 08:17:11 AM UTC 24 | 88303230 ps | ||
| T292 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.3157427197 | Sep 11 08:16:25 AM UTC 24 | Sep 11 08:17:11 AM UTC 24 | 14804008820 ps | ||
| T293 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/26.rv_dm_alert_test.2237308119 | Sep 11 08:17:09 AM UTC 24 | Sep 11 08:17:11 AM UTC 24 | 39368076 ps | ||
| T209 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.3786961356 | Sep 11 08:17:06 AM UTC 24 | Sep 11 08:17:11 AM UTC 24 | 3738430956 ps | ||
| T242 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/17.rv_dm_autoincr_sba_tl_access.2387789585 | Sep 11 08:16:58 AM UTC 24 | Sep 11 08:17:12 AM UTC 24 | 3589589062 ps | ||
| T189 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/11.rv_dm_stress_all.3402941724 | Sep 11 08:16:46 AM UTC 24 | Sep 11 08:17:12 AM UTC 24 | 7511574744 ps | ||
| T220 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/27.rv_dm_alert_test.3026360465 | Sep 11 08:17:10 AM UTC 24 | Sep 11 08:17:12 AM UTC 24 | 69992910 ps | ||
| T256 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/19.rv_dm_bad_sba_tl_access.2366552368 | Sep 11 08:17:02 AM UTC 24 | Sep 11 08:17:12 AM UTC 24 | 4911446191 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/18.rv_dm_stress_all.1695762780 | Sep 11 08:16:59 AM UTC 24 | Sep 11 08:17:12 AM UTC 24 | 2909838971 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.376368138 | Sep 11 08:17:09 AM UTC 24 | Sep 11 08:17:13 AM UTC 24 | 2781945101 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.3149120799 | Sep 11 08:17:21 AM UTC 24 | Sep 11 08:17:26 AM UTC 24 | 2337553039 ps | ||
| T219 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/28.rv_dm_alert_test.677848560 | Sep 11 08:17:11 AM UTC 24 | Sep 11 08:17:13 AM UTC 24 | 55179758 ps | ||
| T249 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/30.rv_dm_alert_test.2460096658 | Sep 11 08:17:11 AM UTC 24 | Sep 11 08:17:13 AM UTC 24 | 94045771 ps | ||
| T294 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/29.rv_dm_alert_test.912004544 | Sep 11 08:17:11 AM UTC 24 | Sep 11 08:17:13 AM UTC 24 | 42003093 ps | ||
| T213 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/23.rv_dm_stress_all.116339039 | Sep 11 08:17:06 AM UTC 24 | Sep 11 08:17:14 AM UTC 24 | 1671366633 ps | ||
| T211 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/28.rv_dm_stress_all.4198999207 | Sep 11 08:17:11 AM UTC 24 | Sep 11 08:17:15 AM UTC 24 | 820350615 ps | ||
| T295 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/31.rv_dm_alert_test.2607450635 | Sep 11 08:17:13 AM UTC 24 | Sep 11 08:17:15 AM UTC 24 | 109497644 ps | ||
| T296 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/32.rv_dm_alert_test.2295193699 | Sep 11 08:17:13 AM UTC 24 | Sep 11 08:17:15 AM UTC 24 | 178025294 ps | ||
| T297 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/15.rv_dm_autoincr_sba_tl_access.3503981967 | Sep 11 08:16:53 AM UTC 24 | Sep 11 08:17:15 AM UTC 24 | 13667916105 ps | ||
| T237 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/33.rv_dm_alert_test.4062121818 | Sep 11 08:17:13 AM UTC 24 | Sep 11 08:17:15 AM UTC 24 | 40237698 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/24.rv_dm_stress_all.2219466755 | Sep 11 08:17:07 AM UTC 24 | Sep 11 08:17:15 AM UTC 24 | 2353068431 ps | ||
| T298 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/13.rv_dm_autoincr_sba_tl_access.3260763410 | Sep 11 08:16:48 AM UTC 24 | Sep 11 08:17:16 AM UTC 24 | 8937904865 ps | ||
| T299 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/35.rv_dm_alert_test.1450230613 | Sep 11 08:17:14 AM UTC 24 | Sep 11 08:17:16 AM UTC 24 | 55142963 ps | ||
| T300 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/34.rv_dm_alert_test.2461291697 | Sep 11 08:17:14 AM UTC 24 | Sep 11 08:17:16 AM UTC 24 | 91758734 ps | ||
| T301 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/36.rv_dm_alert_test.1245990509 | Sep 11 08:17:14 AM UTC 24 | Sep 11 08:17:16 AM UTC 24 | 56248228 ps | ||
| T216 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/32.rv_dm_stress_all.169560142 | Sep 11 08:17:13 AM UTC 24 | Sep 11 08:17:18 AM UTC 24 | 2604396686 ps | ||
| T302 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/26.rv_dm_stress_all.283361552 | Sep 11 08:17:09 AM UTC 24 | Sep 11 08:17:18 AM UTC 24 | 6930688374 ps | ||
| T303 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/37.rv_dm_alert_test.1091034887 | Sep 11 08:17:16 AM UTC 24 | Sep 11 08:17:18 AM UTC 24 | 54634148 ps | ||
| T304 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/38.rv_dm_alert_test.3171773238 | Sep 11 08:17:16 AM UTC 24 | Sep 11 08:17:18 AM UTC 24 | 44172096 ps | ||
| T305 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/39.rv_dm_alert_test.1416602544 | Sep 11 08:17:16 AM UTC 24 | Sep 11 08:17:18 AM UTC 24 | 149268939 ps | ||
| T306 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/40.rv_dm_alert_test.2268619713 | Sep 11 08:17:17 AM UTC 24 | Sep 11 08:17:20 AM UTC 24 | 53376783 ps | ||
| T244 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/42.rv_dm_alert_test.658585689 | Sep 11 08:17:17 AM UTC 24 | Sep 11 08:17:20 AM UTC 24 | 147199674 ps | ||
| T241 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/21.rv_dm_stress_all.3464963481 | Sep 11 08:17:05 AM UTC 24 | Sep 11 08:17:20 AM UTC 24 | 3469232062 ps | ||
| T258 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/41.rv_dm_alert_test.2993865533 | Sep 11 08:17:17 AM UTC 24 | Sep 11 08:17:20 AM UTC 24 | 112538904 ps | ||
| T254 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/38.rv_dm_stress_all.1013042726 | Sep 11 08:17:16 AM UTC 24 | Sep 11 08:17:20 AM UTC 24 | 2250161103 ps | ||
| T208 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.4073818478 | Sep 11 08:17:11 AM UTC 24 | Sep 11 08:17:20 AM UTC 24 | 5505222703 ps | ||
| T217 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/35.rv_dm_stress_all.3102582252 | Sep 11 08:17:14 AM UTC 24 | Sep 11 08:17:20 AM UTC 24 | 1609423033 ps | ||
| T307 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.1463520992 | Sep 11 08:16:38 AM UTC 24 | Sep 11 08:17:21 AM UTC 24 | 13603313217 ps | ||
| T308 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/43.rv_dm_alert_test.4160654304 | Sep 11 08:17:19 AM UTC 24 | Sep 11 08:17:21 AM UTC 24 | 32193974 ps | ||
| T309 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/44.rv_dm_alert_test.2585429685 | Sep 11 08:17:19 AM UTC 24 | Sep 11 08:17:21 AM UTC 24 | 66853129 ps | ||
| T231 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/29.rv_dm_stress_all.3897734925 | Sep 11 08:17:11 AM UTC 24 | Sep 11 08:17:21 AM UTC 24 | 3817873112 ps | ||
| T205 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.4260119053 | Sep 11 08:17:10 AM UTC 24 | Sep 11 08:17:22 AM UTC 24 | 3872734995 ps | ||
| T212 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/36.rv_dm_stress_all.2035457760 | Sep 11 08:17:14 AM UTC 24 | Sep 11 08:17:22 AM UTC 24 | 3429808863 ps | ||
| T310 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/47.rv_dm_alert_test.2970087931 | Sep 11 08:17:21 AM UTC 24 | Sep 11 08:17:23 AM UTC 24 | 109648794 ps | ||
| T250 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/46.rv_dm_alert_test.4208215305 | Sep 11 08:17:21 AM UTC 24 | Sep 11 08:17:23 AM UTC 24 | 29628425 ps | ||
| T311 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/45.rv_dm_alert_test.270947432 | Sep 11 08:17:21 AM UTC 24 | Sep 11 08:17:23 AM UTC 24 | 78064753 ps | ||
| T312 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.1894956864 | Sep 11 08:17:19 AM UTC 24 | Sep 11 08:17:23 AM UTC 24 | 1624332829 ps | ||
| T313 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/31.rv_dm_stress_all.2289163264 | Sep 11 08:17:13 AM UTC 24 | Sep 11 08:17:23 AM UTC 24 | 2775448889 ps | ||
| T314 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/48.rv_dm_alert_test.1182777622 | Sep 11 08:17:22 AM UTC 24 | Sep 11 08:17:24 AM UTC 24 | 41136118 ps | ||
| T315 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/19.rv_dm_sba_tl_access.1286577519 | Sep 11 08:17:00 AM UTC 24 | Sep 11 08:17:24 AM UTC 24 | 13244711402 ps | ||
| T210 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/39.rv_dm_stress_all.3452328339 | Sep 11 08:17:16 AM UTC 24 | Sep 11 08:17:24 AM UTC 24 | 1478837461 ps | ||
| T251 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/49.rv_dm_alert_test.2397138177 | Sep 11 08:17:22 AM UTC 24 | Sep 11 08:17:24 AM UTC 24 | 198047412 ps | ||
| T223 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/45.rv_dm_stress_all.1949476285 | Sep 11 08:17:19 AM UTC 24 | Sep 11 08:17:24 AM UTC 24 | 2482702651 ps | ||
| T240 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/34.rv_dm_stress_all.2044152821 | Sep 11 08:17:14 AM UTC 24 | Sep 11 08:17:25 AM UTC 24 | 2602998003 ps | ||
| T316 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2425204835 | Sep 11 08:17:01 AM UTC 24 | Sep 11 08:17:25 AM UTC 24 | 13177124165 ps | ||
| T82 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.4110364194 | Sep 11 08:16:40 AM UTC 24 | Sep 11 08:17:26 AM UTC 24 | 6990066574 ps | ||
| T77 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/48.rv_dm_stress_all.528406974 | Sep 11 08:17:21 AM UTC 24 | Sep 11 08:17:26 AM UTC 24 | 6427077162 ps | ||
| T317 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/14.rv_dm_autoincr_sba_tl_access.1463314914 | Sep 11 08:16:51 AM UTC 24 | Sep 11 08:17:27 AM UTC 24 | 21164477378 ps | ||
| T257 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/17.rv_dm_stress_all.925074724 | Sep 11 08:16:58 AM UTC 24 | Sep 11 08:17:27 AM UTC 24 | 8635644541 ps | ||
| T228 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/49.rv_dm_stress_all.347197557 | Sep 11 08:17:22 AM UTC 24 | Sep 11 08:17:27 AM UTC 24 | 2997951030 ps | ||
| T261 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/47.rv_dm_stress_all.726564830 | Sep 11 08:17:21 AM UTC 24 | Sep 11 08:17:27 AM UTC 24 | 5055511191 ps | ||
| T72 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/43.rv_dm_stress_all.332679470 | Sep 11 08:17:18 AM UTC 24 | Sep 11 08:17:28 AM UTC 24 | 2186969183 ps | ||
| T215 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/40.rv_dm_stress_all.2655719992 | Sep 11 08:17:16 AM UTC 24 | Sep 11 08:17:28 AM UTC 24 | 3898183848 ps | ||
| T318 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/37.rv_dm_stress_all.3121829907 | Sep 11 08:17:16 AM UTC 24 | Sep 11 08:17:28 AM UTC 24 | 2713556514 ps | ||
| T243 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.1300503797 | Sep 11 08:17:13 AM UTC 24 | Sep 11 08:17:28 AM UTC 24 | 6450343564 ps | ||
| T319 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/4.rv_dm_autoincr_sba_tl_access.353803007 | Sep 11 08:16:23 AM UTC 24 | Sep 11 08:17:29 AM UTC 24 | 92171362280 ps | ||
| T214 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/41.rv_dm_stress_all.556683835 | Sep 11 08:17:17 AM UTC 24 | Sep 11 08:17:30 AM UTC 24 | 5914895976 ps | ||
| T320 | /workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/coverage/default/42.rv_dm_stress_all.395992707 | Sep 11 08:17:17 AM UTC 24 | Sep 11 08:17:30 AM UTC 24 | 6290812949 ps |
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