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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.33 96.34 89.82 92.10 93.33 90.27 98.74 57.72


Total test records in report: 483
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T221 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/49.rv_dm_stress_all.368917079 Sep 18 08:23:41 AM UTC 24 Sep 18 08:23:48 AM UTC 24 2756618303 ps
T326 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/41.rv_dm_stress_all.276761587 Sep 18 08:23:39 AM UTC 24 Sep 18 08:23:49 AM UTC 24 3840387245 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/15.rv_dm_autoincr_sba_tl_access.1856202000 Sep 18 08:23:14 AM UTC 24 Sep 18 08:23:52 AM UTC 24 10221262625 ps
T327 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/18.rv_dm_autoincr_sba_tl_access.50634184 Sep 18 08:23:21 AM UTC 24 Sep 18 08:23:53 AM UTC 24 13741726147 ps
T328 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/11.rv_dm_autoincr_sba_tl_access.1572168505 Sep 18 08:23:06 AM UTC 24 Sep 18 08:23:54 AM UTC 24 20777304512 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/36.rv_dm_stress_all.845830983 Sep 18 08:23:36 AM UTC 24 Sep 18 08:23:56 AM UTC 24 4858851471 ps
T329 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.299364166 Sep 18 08:22:51 AM UTC 24 Sep 18 08:23:58 AM UTC 24 35521494807 ps
T330 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/42.rv_dm_stress_all.1835418958 Sep 18 08:23:39 AM UTC 24 Sep 18 08:23:59 AM UTC 24 5554371220 ps
T331 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.3846732252 Sep 18 08:23:41 AM UTC 24 Sep 18 08:24:00 AM UTC 24 8498414296 ps
T332 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.3862929740 Sep 18 08:23:25 AM UTC 24 Sep 18 08:24:01 AM UTC 24 8472815293 ps
T333 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_autoincr_sba_tl_access.3338849758 Sep 18 08:22:12 AM UTC 24 Sep 18 08:24:09 AM UTC 24 58195109083 ps
T334 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/12.rv_dm_autoincr_sba_tl_access.1364197906 Sep 18 08:23:07 AM UTC 24 Sep 18 08:24:18 AM UTC 24 55005796140 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.4073093933 Sep 18 08:22:23 AM UTC 24 Sep 18 08:27:09 AM UTC 24 69920951271 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1232625563 Sep 18 07:53:00 AM UTC 24 Sep 18 07:53:02 AM UTC 24 279042869 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.582229115 Sep 18 07:53:02 AM UTC 24 Sep 18 07:53:05 AM UTC 24 369793493 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1599074262 Sep 18 07:53:03 AM UTC 24 Sep 18 07:53:08 AM UTC 24 2797309949 ps
T335 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1172891071 Sep 18 07:53:04 AM UTC 24 Sep 18 07:53:08 AM UTC 24 1210206076 ps
T336 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.2851792944 Sep 18 07:53:06 AM UTC 24 Sep 18 07:53:08 AM UTC 24 55206984 ps
T337 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1525359650 Sep 18 07:53:06 AM UTC 24 Sep 18 07:53:08 AM UTC 24 87236493 ps
T126 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.4017691054 Sep 18 07:53:06 AM UTC 24 Sep 18 07:53:09 AM UTC 24 235034019 ps
T127 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.574876246 Sep 18 07:53:08 AM UTC 24 Sep 18 07:53:11 AM UTC 24 180300701 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.3902253775 Sep 18 07:53:05 AM UTC 24 Sep 18 07:53:11 AM UTC 24 318899564 ps
T338 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1830691228 Sep 18 07:53:09 AM UTC 24 Sep 18 07:53:11 AM UTC 24 294319029 ps
T339 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3649967917 Sep 18 07:53:04 AM UTC 24 Sep 18 07:53:12 AM UTC 24 3171408047 ps
T340 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.4013754931 Sep 18 07:53:10 AM UTC 24 Sep 18 07:53:13 AM UTC 24 149633299 ps
T341 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.698187673 Sep 18 07:53:42 AM UTC 24 Sep 18 07:53:45 AM UTC 24 401811251 ps
T235 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3738098754 Sep 18 07:53:09 AM UTC 24 Sep 18 07:53:13 AM UTC 24 130763442 ps
T342 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2838447596 Sep 18 07:53:10 AM UTC 24 Sep 18 07:53:15 AM UTC 24 2413792493 ps
T343 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.179402206 Sep 18 07:53:14 AM UTC 24 Sep 18 07:53:16 AM UTC 24 86025482 ps
T344 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.1479587561 Sep 18 07:53:14 AM UTC 24 Sep 18 07:53:16 AM UTC 24 138185363 ps
T128 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3316154252 Sep 18 07:53:09 AM UTC 24 Sep 18 07:53:16 AM UTC 24 1075018810 ps
T139 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3936714070 Sep 18 07:53:04 AM UTC 24 Sep 18 07:53:17 AM UTC 24 9844744112 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2536686328 Sep 18 07:53:15 AM UTC 24 Sep 18 07:53:18 AM UTC 24 193466050 ps
T130 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.701779013 Sep 18 07:53:16 AM UTC 24 Sep 18 07:53:19 AM UTC 24 541749748 ps
T345 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.2216509647 Sep 18 07:53:13 AM UTC 24 Sep 18 07:53:20 AM UTC 24 681073890 ps
T346 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3057569365 Sep 18 07:53:18 AM UTC 24 Sep 18 07:53:21 AM UTC 24 572214651 ps
T347 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.276399061 Sep 18 07:53:19 AM UTC 24 Sep 18 07:53:22 AM UTC 24 243026635 ps
T348 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1266462620 Sep 18 07:53:11 AM UTC 24 Sep 18 07:53:22 AM UTC 24 2891732688 ps
T349 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.447517804 Sep 18 07:53:11 AM UTC 24 Sep 18 07:53:22 AM UTC 24 2948601731 ps
T350 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.4293524810 Sep 18 07:53:17 AM UTC 24 Sep 18 07:53:22 AM UTC 24 264270831 ps
T351 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3259869686 Sep 18 07:53:20 AM UTC 24 Sep 18 07:53:23 AM UTC 24 182401482 ps
T352 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_walk.2167632105 Sep 18 07:53:23 AM UTC 24 Sep 18 07:53:25 AM UTC 24 35207346 ps
T353 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_partial_access.899768309 Sep 18 07:53:23 AM UTC 24 Sep 18 07:53:25 AM UTC 24 72588948 ps
T131 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_rw.448144479 Sep 18 07:53:23 AM UTC 24 Sep 18 07:53:26 AM UTC 24 92367002 ps
T132 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.665869683 Sep 18 07:53:23 AM UTC 24 Sep 18 07:53:26 AM UTC 24 378728403 ps
T133 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3883786184 Sep 18 07:53:17 AM UTC 24 Sep 18 07:53:27 AM UTC 24 475065407 ps
T354 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.890877963 Sep 18 07:53:25 AM UTC 24 Sep 18 07:53:28 AM UTC 24 216017817 ps
T355 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3941087169 Sep 18 07:53:23 AM UTC 24 Sep 18 07:53:29 AM UTC 24 366941196 ps
T356 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1578817845 Sep 18 07:53:26 AM UTC 24 Sep 18 07:53:29 AM UTC 24 226112635 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_errors.4097433436 Sep 18 07:53:22 AM UTC 24 Sep 18 07:53:30 AM UTC 24 223694942 ps
T357 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2926813269 Sep 18 07:53:28 AM UTC 24 Sep 18 07:53:32 AM UTC 24 1395411073 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.291661202 Sep 18 07:53:00 AM UTC 24 Sep 18 07:53:32 AM UTC 24 4470249309 ps
T358 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_walk.1678659172 Sep 18 07:53:30 AM UTC 24 Sep 18 07:53:32 AM UTC 24 76296337 ps
T359 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1559746002 Sep 18 07:53:28 AM UTC 24 Sep 18 07:53:32 AM UTC 24 1269923413 ps
T360 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_partial_access.4094639618 Sep 18 07:53:30 AM UTC 24 Sep 18 07:53:32 AM UTC 24 96655807 ps
T134 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3296274206 Sep 18 07:53:23 AM UTC 24 Sep 18 07:53:33 AM UTC 24 2062230746 ps
T361 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1136697352 Sep 18 07:53:22 AM UTC 24 Sep 18 07:53:33 AM UTC 24 2915224450 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.354005198 Sep 18 07:53:06 AM UTC 24 Sep 18 07:53:34 AM UTC 24 7434037476 ps
T177 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_errors.2771733591 Sep 18 07:53:30 AM UTC 24 Sep 18 07:53:34 AM UTC 24 202893140 ps
T135 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3619911341 Sep 18 07:53:32 AM UTC 24 Sep 18 07:53:35 AM UTC 24 367677539 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.429542584 Sep 18 07:53:09 AM UTC 24 Sep 18 07:53:35 AM UTC 24 2164522313 ps
T362 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1634112315 Sep 18 07:53:32 AM UTC 24 Sep 18 07:53:36 AM UTC 24 111645066 ps
T363 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2651551498 Sep 18 07:53:34 AM UTC 24 Sep 18 07:53:36 AM UTC 24 617631208 ps
T364 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.300450032 Sep 18 07:53:34 AM UTC 24 Sep 18 07:53:37 AM UTC 24 715094119 ps
T365 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3798727296 Sep 18 07:53:34 AM UTC 24 Sep 18 07:53:45 AM UTC 24 11536306963 ps
T149 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_rw.3929389515 Sep 18 07:53:32 AM UTC 24 Sep 18 07:53:37 AM UTC 24 127933730 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3900017940 Sep 18 07:53:14 AM UTC 24 Sep 18 07:53:37 AM UTC 24 2694899588 ps
T366 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3846148082 Sep 18 07:53:34 AM UTC 24 Sep 18 07:53:37 AM UTC 24 494708428 ps
T367 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_walk.1485586699 Sep 18 07:53:36 AM UTC 24 Sep 18 07:53:38 AM UTC 24 71517549 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2605132632 Sep 18 07:53:22 AM UTC 24 Sep 18 07:53:39 AM UTC 24 2373866465 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2505550594 Sep 18 07:53:34 AM UTC 24 Sep 18 07:53:39 AM UTC 24 15606372717 ps
T368 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_partial_access.824924788 Sep 18 07:53:37 AM UTC 24 Sep 18 07:53:39 AM UTC 24 39680618 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1097994325 Sep 18 07:53:32 AM UTC 24 Sep 18 07:53:40 AM UTC 24 548904691 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_rw.3168808517 Sep 18 07:53:38 AM UTC 24 Sep 18 07:53:41 AM UTC 24 102047886 ps
T369 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3857471771 Sep 18 07:53:39 AM UTC 24 Sep 18 07:53:41 AM UTC 24 454365882 ps
T174 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.786444924 Sep 18 07:53:37 AM UTC 24 Sep 18 07:53:41 AM UTC 24 151191708 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2079336346 Sep 18 07:53:20 AM UTC 24 Sep 18 07:53:42 AM UTC 24 4876842138 ps
T370 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_errors.1959463032 Sep 18 07:53:36 AM UTC 24 Sep 18 07:53:42 AM UTC 24 164360180 ps
T371 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3938606813 Sep 18 07:53:39 AM UTC 24 Sep 18 07:53:42 AM UTC 24 108949970 ps
T227 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2113539969 Sep 18 07:53:30 AM UTC 24 Sep 18 07:53:43 AM UTC 24 2020275679 ps
T372 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2211821293 Sep 18 07:53:40 AM UTC 24 Sep 18 07:53:44 AM UTC 24 2267199235 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2363604866 Sep 18 07:53:39 AM UTC 24 Sep 18 07:53:45 AM UTC 24 189662292 ps
T373 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_rw.875115172 Sep 18 07:53:41 AM UTC 24 Sep 18 07:53:45 AM UTC 24 689135267 ps
T113 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2373297597 Sep 18 07:53:42 AM UTC 24 Sep 18 07:53:47 AM UTC 24 84676119 ps
T374 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_errors.2516789568 Sep 18 07:53:44 AM UTC 24 Sep 18 07:53:47 AM UTC 24 130249378 ps
T159 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_rw.3555946505 Sep 18 07:53:45 AM UTC 24 Sep 18 07:53:48 AM UTC 24 156016367 ps
T375 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_errors.1232983635 Sep 18 07:53:41 AM UTC 24 Sep 18 07:53:48 AM UTC 24 270172469 ps
T376 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1703113780 Sep 18 07:53:22 AM UTC 24 Sep 18 07:53:49 AM UTC 24 25332646662 ps
T377 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2802198986 Sep 18 07:53:46 AM UTC 24 Sep 18 07:53:49 AM UTC 24 547751137 ps
T378 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3115263663 Sep 18 07:53:46 AM UTC 24 Sep 18 07:53:50 AM UTC 24 164734051 ps
T379 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2111170944 Sep 18 07:53:35 AM UTC 24 Sep 18 07:53:51 AM UTC 24 3334594410 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3778432629 Sep 18 07:53:42 AM UTC 24 Sep 18 07:53:51 AM UTC 24 243152147 ps
T380 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_errors.196115098 Sep 18 07:53:48 AM UTC 24 Sep 18 07:53:52 AM UTC 24 117888172 ps
T381 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.981120613 Sep 18 07:53:20 AM UTC 24 Sep 18 07:53:52 AM UTC 24 31781283941 ps
T160 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_rw.3033480578 Sep 18 07:53:49 AM UTC 24 Sep 18 07:53:53 AM UTC 24 77189204 ps
T161 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_rw.3233533837 Sep 18 07:54:16 AM UTC 24 Sep 18 07:54:19 AM UTC 24 81638224 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2684397137 Sep 18 07:54:09 AM UTC 24 Sep 18 07:54:19 AM UTC 24 1546814765 ps
T150 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1031047080 Sep 18 07:53:17 AM UTC 24 Sep 18 07:53:53 AM UTC 24 9593479107 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2224946124 Sep 18 07:53:45 AM UTC 24 Sep 18 07:53:54 AM UTC 24 402193554 ps
T382 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2028422208 Sep 18 07:53:42 AM UTC 24 Sep 18 07:53:54 AM UTC 24 12773334526 ps
T383 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.593069406 Sep 18 07:53:40 AM UTC 24 Sep 18 07:53:55 AM UTC 24 4477026233 ps
T384 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3860177425 Sep 18 07:53:52 AM UTC 24 Sep 18 07:53:55 AM UTC 24 688508172 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3180940785 Sep 18 07:53:50 AM UTC 24 Sep 18 07:53:56 AM UTC 24 236145166 ps
T226 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2623912614 Sep 18 07:53:36 AM UTC 24 Sep 18 07:53:56 AM UTC 24 2975813282 ps
T385 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3412324398 Sep 18 07:53:29 AM UTC 24 Sep 18 07:53:56 AM UTC 24 34945759198 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.909283199 Sep 18 07:53:50 AM UTC 24 Sep 18 07:53:57 AM UTC 24 351424774 ps
T386 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_errors.547569001 Sep 18 07:53:53 AM UTC 24 Sep 18 07:53:57 AM UTC 24 124371431 ps
T387 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2147613213 Sep 18 07:53:55 AM UTC 24 Sep 18 07:53:58 AM UTC 24 1125663892 ps
T233 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_intg_err.89401463 Sep 18 07:53:41 AM UTC 24 Sep 18 07:53:58 AM UTC 24 1623304787 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_rw.1413106143 Sep 18 07:53:54 AM UTC 24 Sep 18 07:53:58 AM UTC 24 247586184 ps
T388 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1370556333 Sep 18 07:53:46 AM UTC 24 Sep 18 07:53:59 AM UTC 24 5944569548 ps
T389 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2065187539 Sep 18 07:53:55 AM UTC 24 Sep 18 07:53:59 AM UTC 24 81024659 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2289846949 Sep 18 07:53:55 AM UTC 24 Sep 18 07:54:01 AM UTC 24 181781920 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_rw.2852205725 Sep 18 07:53:58 AM UTC 24 Sep 18 07:54:01 AM UTC 24 107188986 ps
T390 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.841558901 Sep 18 07:53:59 AM UTC 24 Sep 18 07:54:01 AM UTC 24 192756643 ps
T391 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.4248672197 Sep 18 07:53:09 AM UTC 24 Sep 18 07:54:02 AM UTC 24 5857272780 ps
T392 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1745313026 Sep 18 07:53:46 AM UTC 24 Sep 18 07:54:02 AM UTC 24 10267295641 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2024668641 Sep 18 07:53:35 AM UTC 24 Sep 18 07:54:02 AM UTC 24 4577772265 ps
T393 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.4224518307 Sep 18 07:53:23 AM UTC 24 Sep 18 07:54:02 AM UTC 24 4761181447 ps
T394 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.834643644 Sep 18 07:53:55 AM UTC 24 Sep 18 07:54:02 AM UTC 24 5243295460 ps
T395 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_errors.4242173745 Sep 18 07:53:56 AM UTC 24 Sep 18 07:54:02 AM UTC 24 772621678 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3386992776 Sep 18 07:53:58 AM UTC 24 Sep 18 07:54:03 AM UTC 24 484858344 ps
T396 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2752971925 Sep 18 07:53:17 AM UTC 24 Sep 18 07:54:19 AM UTC 24 5107063377 ps
T164 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2389828744 Sep 18 07:53:34 AM UTC 24 Sep 18 07:54:04 AM UTC 24 6940537415 ps
T397 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.4186626389 Sep 18 07:53:59 AM UTC 24 Sep 18 07:54:04 AM UTC 24 116981630 ps
T398 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.543661143 Sep 18 07:54:00 AM UTC 24 Sep 18 07:54:04 AM UTC 24 274778895 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.980685544 Sep 18 07:53:28 AM UTC 24 Sep 18 07:54:04 AM UTC 24 13706918042 ps
T399 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3445336914 Sep 18 07:53:44 AM UTC 24 Sep 18 07:54:05 AM UTC 24 2770714464 ps
T400 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2297444860 Sep 18 07:54:02 AM UTC 24 Sep 18 07:54:05 AM UTC 24 43767360 ps
T401 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3595296833 Sep 18 07:53:10 AM UTC 24 Sep 18 07:54:05 AM UTC 24 18226622235 ps
T402 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.323798407 Sep 18 07:54:03 AM UTC 24 Sep 18 07:54:05 AM UTC 24 237557489 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.774844863 Sep 18 07:54:02 AM UTC 24 Sep 18 07:54:06 AM UTC 24 370641539 ps
T403 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_rw.1389398288 Sep 18 07:54:03 AM UTC 24 Sep 18 07:54:07 AM UTC 24 79410547 ps
T404 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.4272058232 Sep 18 07:53:59 AM UTC 24 Sep 18 07:54:07 AM UTC 24 2409956405 ps
T405 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.183638604 Sep 18 07:54:03 AM UTC 24 Sep 18 07:54:07 AM UTC 24 3778532342 ps
T406 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_errors.397081039 Sep 18 07:54:03 AM UTC 24 Sep 18 07:54:08 AM UTC 24 490846966 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.4238235720 Sep 18 07:53:40 AM UTC 24 Sep 18 07:54:08 AM UTC 24 1677102067 ps
T407 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3258712962 Sep 18 07:54:06 AM UTC 24 Sep 18 07:54:08 AM UTC 24 394249166 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.540543261 Sep 18 07:53:13 AM UTC 24 Sep 18 07:54:08 AM UTC 24 3429895412 ps
T165 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_rw.1712366839 Sep 18 07:54:07 AM UTC 24 Sep 18 07:54:09 AM UTC 24 399065804 ps
T408 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.1553476339 Sep 18 07:54:02 AM UTC 24 Sep 18 07:54:10 AM UTC 24 1177172032 ps
T409 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.1436409230 Sep 18 07:53:56 AM UTC 24 Sep 18 07:54:10 AM UTC 24 11422375889 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3867749373 Sep 18 07:53:54 AM UTC 24 Sep 18 07:54:10 AM UTC 24 6230950491 ps
T410 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3235924854 Sep 18 07:53:35 AM UTC 24 Sep 18 07:54:10 AM UTC 24 25601071468 ps
T411 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2374270043 Sep 18 07:54:08 AM UTC 24 Sep 18 07:54:10 AM UTC 24 144683180 ps
T412 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1546219857 Sep 18 07:54:05 AM UTC 24 Sep 18 07:54:10 AM UTC 24 197297956 ps
T413 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_errors.2131993306 Sep 18 07:54:06 AM UTC 24 Sep 18 07:54:10 AM UTC 24 64277293 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3828177184 Sep 18 07:53:48 AM UTC 24 Sep 18 07:54:11 AM UTC 24 2395190816 ps
T414 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3745264332 Sep 18 07:53:43 AM UTC 24 Sep 18 07:54:12 AM UTC 24 15448223786 ps
T415 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_rw.1797322857 Sep 18 07:54:09 AM UTC 24 Sep 18 07:54:13 AM UTC 24 187977196 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2719203320 Sep 18 07:54:08 AM UTC 24 Sep 18 07:54:13 AM UTC 24 133212347 ps
T416 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.3552466149 Sep 18 07:54:11 AM UTC 24 Sep 18 07:54:13 AM UTC 24 205165859 ps
T417 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_errors.1020569344 Sep 18 07:54:09 AM UTC 24 Sep 18 07:54:13 AM UTC 24 134476299 ps
T418 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2426424702 Sep 18 07:54:08 AM UTC 24 Sep 18 07:54:14 AM UTC 24 2563198484 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_rw.3043990893 Sep 18 07:54:11 AM UTC 24 Sep 18 07:54:14 AM UTC 24 118071619 ps
T419 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1755417502 Sep 18 07:54:11 AM UTC 24 Sep 18 07:54:14 AM UTC 24 105080565 ps
T420 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3478861545 Sep 18 07:54:01 AM UTC 24 Sep 18 07:54:15 AM UTC 24 1893853226 ps
T421 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.815572862 Sep 18 07:54:09 AM UTC 24 Sep 18 07:54:15 AM UTC 24 3896980559 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2170031394 Sep 18 07:54:05 AM UTC 24 Sep 18 07:54:15 AM UTC 24 520062069 ps
T422 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1503681499 Sep 18 07:54:12 AM UTC 24 Sep 18 07:54:15 AM UTC 24 101650930 ps
T423 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.4081443737 Sep 18 07:54:09 AM UTC 24 Sep 18 07:54:15 AM UTC 24 404563667 ps
T424 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3900134093 Sep 18 07:54:13 AM UTC 24 Sep 18 07:54:15 AM UTC 24 99255404 ps
T425 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_errors.1267058871 Sep 18 07:54:11 AM UTC 24 Sep 18 07:54:15 AM UTC 24 377741349 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.2903122274 Sep 18 07:53:44 AM UTC 24 Sep 18 07:54:16 AM UTC 24 7325402478 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2554188408 Sep 18 07:54:07 AM UTC 24 Sep 18 07:54:17 AM UTC 24 1868344295 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3579964331 Sep 18 07:54:12 AM UTC 24 Sep 18 07:54:17 AM UTC 24 162864915 ps
T426 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_rw.1996847710 Sep 18 07:54:14 AM UTC 24 Sep 18 07:54:17 AM UTC 24 1105713362 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3105298100 Sep 18 07:53:57 AM UTC 24 Sep 18 07:54:17 AM UTC 24 3078365123 ps
T427 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1041286597 Sep 18 07:54:11 AM UTC 24 Sep 18 07:54:18 AM UTC 24 1624499263 ps
T428 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2645762347 Sep 18 07:54:06 AM UTC 24 Sep 18 07:54:18 AM UTC 24 4630390547 ps
T429 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.392191755 Sep 18 07:54:16 AM UTC 24 Sep 18 07:54:18 AM UTC 24 473399681 ps
T430 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1679213247 Sep 18 07:53:29 AM UTC 24 Sep 18 07:54:19 AM UTC 24 23516533688 ps
T431 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3146607373 Sep 18 07:54:17 AM UTC 24 Sep 18 07:54:19 AM UTC 24 498166555 ps
T432 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3896831076 Sep 18 07:54:16 AM UTC 24 Sep 18 07:54:20 AM UTC 24 97651139 ps
T433 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_errors.2149466374 Sep 18 07:54:14 AM UTC 24 Sep 18 07:54:21 AM UTC 24 517190465 ps
T434 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_rw.2780022818 Sep 18 07:54:18 AM UTC 24 Sep 18 07:54:21 AM UTC 24 284048722 ps
T435 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3276268635 Sep 18 07:54:16 AM UTC 24 Sep 18 07:54:21 AM UTC 24 92118311 ps
T436 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3516767307 Sep 18 07:54:06 AM UTC 24 Sep 18 07:54:21 AM UTC 24 2331585344 ps
T437 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_errors.3712876802 Sep 18 07:54:16 AM UTC 24 Sep 18 07:54:21 AM UTC 24 135311774 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.750990353 Sep 18 07:54:15 AM UTC 24 Sep 18 07:54:21 AM UTC 24 334469081 ps
T438 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.779239227 Sep 18 07:54:17 AM UTC 24 Sep 18 07:54:22 AM UTC 24 254501190 ps
T439 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1386725148 Sep 18 07:53:52 AM UTC 24 Sep 18 07:54:22 AM UTC 24 7717678784 ps
T440 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3249475516 Sep 18 07:53:27 AM UTC 24 Sep 18 07:54:22 AM UTC 24 15554785435 ps
T441 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.53423632 Sep 18 07:54:19 AM UTC 24 Sep 18 07:54:23 AM UTC 24 826782057 ps
T442 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3735041256 Sep 18 07:54:14 AM UTC 24 Sep 18 07:54:24 AM UTC 24 7332896213 ps
T443 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1074415271 Sep 18 07:54:03 AM UTC 24 Sep 18 07:54:24 AM UTC 24 5872789754 ps
T444 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.550838189 Sep 18 07:54:22 AM UTC 24 Sep 18 07:54:24 AM UTC 24 157407224 ps
T445 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_errors.747503436 Sep 18 07:54:18 AM UTC 24 Sep 18 07:54:24 AM UTC 24 363150460 ps
T446 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.28650792 Sep 18 07:53:52 AM UTC 24 Sep 18 07:54:25 AM UTC 24 8480451798 ps
T447 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_rw.3925098334 Sep 18 07:54:21 AM UTC 24 Sep 18 07:54:25 AM UTC 24 112470511 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3912177852 Sep 18 07:54:16 AM UTC 24 Sep 18 07:54:25 AM UTC 24 1291924500 ps
T448 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3496046550 Sep 18 07:54:19 AM UTC 24 Sep 18 07:54:25 AM UTC 24 160545723 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.4051126531 Sep 18 07:54:22 AM UTC 24 Sep 18 07:54:25 AM UTC 24 136659804 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_rw.3045200829 Sep 18 07:54:23 AM UTC 24 Sep 18 07:54:26 AM UTC 24 170625563 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.216165157 Sep 18 07:53:30 AM UTC 24 Sep 18 07:54:26 AM UTC 24 15935020795 ps
T449 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.43996215 Sep 18 07:54:19 AM UTC 24 Sep 18 07:54:26 AM UTC 24 165056643 ps
T450 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.426120252 Sep 18 07:54:23 AM UTC 24 Sep 18 07:54:27 AM UTC 24 207327209 ps
T230 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1739580438 Sep 18 07:54:03 AM UTC 24 Sep 18 07:54:27 AM UTC 24 4675953397 ps
T451 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.754151928 Sep 18 07:54:18 AM UTC 24 Sep 18 07:54:27 AM UTC 24 4714834884 ps
T452 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_errors.3152059842 Sep 18 07:54:20 AM UTC 24 Sep 18 07:54:27 AM UTC 24 273424859 ps
T453 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3328618954 Sep 18 07:54:19 AM UTC 24 Sep 18 07:54:29 AM UTC 24 5934963250 ps
T454 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3168122381 Sep 18 07:53:35 AM UTC 24 Sep 18 07:54:29 AM UTC 24 17695617756 ps
T455 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.432863293 Sep 18 07:53:11 AM UTC 24 Sep 18 07:54:29 AM UTC 24 58509152935 ps
T456 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1104612512 Sep 18 07:54:22 AM UTC 24 Sep 18 07:54:29 AM UTC 24 1273552545 ps
T457 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2409350036 Sep 18 07:54:22 AM UTC 24 Sep 18 07:54:30 AM UTC 24 6028986748 ps
T458 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_errors.3999205835 Sep 18 07:54:23 AM UTC 24 Sep 18 07:54:30 AM UTC 24 1095723461 ps
T459 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2886481872 Sep 18 07:54:18 AM UTC 24 Sep 18 07:54:30 AM UTC 24 815045884 ps
T460 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.334745868 Sep 18 07:53:38 AM UTC 24 Sep 18 07:54:31 AM UTC 24 7046133412 ps
T461 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.2184610506 Sep 18 07:53:53 AM UTC 24 Sep 18 07:54:31 AM UTC 24 1917268779 ps
T462 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3755343309 Sep 18 07:54:11 AM UTC 24 Sep 18 07:54:31 AM UTC 24 4297359477 ps
T463 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1409064633 Sep 18 07:54:16 AM UTC 24 Sep 18 07:54:32 AM UTC 24 16064726760 ps
T464 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3142460272 Sep 18 07:54:14 AM UTC 24 Sep 18 07:54:32 AM UTC 24 2968533904 ps
T465 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3159583106 Sep 18 07:54:20 AM UTC 24 Sep 18 07:54:33 AM UTC 24 847839897 ps
T466 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2441563470 Sep 18 07:54:23 AM UTC 24 Sep 18 07:54:33 AM UTC 24 379271858 ps
T467 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2607360509 Sep 18 07:54:06 AM UTC 24 Sep 18 07:54:37 AM UTC 24 9935886459 ps
T468 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3786238004 Sep 18 07:53:22 AM UTC 24 Sep 18 07:54:39 AM UTC 24 27312622394 ps
T109 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.694563370 Sep 18 07:53:22 AM UTC 24 Sep 18 07:54:39 AM UTC 24 8146765985 ps
T469 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1302720761 Sep 18 07:53:05 AM UTC 24 Sep 18 07:54:40 AM UTC 24 21881554173 ps
T470 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3046928274 Sep 18 07:53:23 AM UTC 24 Sep 18 07:54:41 AM UTC 24 8591651740 ps
T471 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_intg_err.191699593 Sep 18 07:54:23 AM UTC 24 Sep 18 07:54:44 AM UTC 24 1085511733 ps
T472 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.476368599 Sep 18 07:53:32 AM UTC 24 Sep 18 07:54:45 AM UTC 24 6745324875 ps
T473 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.2038324847 Sep 18 07:54:11 AM UTC 24 Sep 18 07:54:47 AM UTC 24 26847746419 ps
T474 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.4082820329 Sep 18 07:53:56 AM UTC 24 Sep 18 07:54:47 AM UTC 24 13813029395 ps
T475 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2324927083 Sep 18 07:53:11 AM UTC 24 Sep 18 07:54:59 AM UTC 24 27342302612 ps
T476 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1592014276 Sep 18 07:54:18 AM UTC 24 Sep 18 07:55:06 AM UTC 24 53252487876 ps
T477 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.294254968 Sep 18 07:54:16 AM UTC 24 Sep 18 07:55:10 AM UTC 24 11925675592 ps
T478 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1910911291 Sep 18 07:53:04 AM UTC 24 Sep 18 07:55:11 AM UTC 24 48168858954 ps
T479 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3516600190 Sep 18 07:54:00 AM UTC 24 Sep 18 07:55:35 AM UTC 24 33060079601 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.3054276689 Sep 18 07:53:47 AM UTC 24 Sep 18 07:55:45 AM UTC 24 45026684607 ps
T480 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1005448279 Sep 18 07:53:05 AM UTC 24 Sep 18 07:55:51 AM UTC 24 114637055588 ps
T481 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.4068717844 Sep 18 07:54:23 AM UTC 24 Sep 18 07:55:55 AM UTC 24 56236734087 ps
T482 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.3433511388 Sep 18 07:54:20 AM UTC 24 Sep 18 07:57:39 AM UTC 24 83229776531 ps
T483 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.303711838 Sep 18 07:54:14 AM UTC 24 Sep 18 07:59:11 AM UTC 24 100023362417 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.1125163472
Short name T2
Test name
Test status
Simulation time 272222489 ps
CPU time 1.31 seconds
Started Sep 18 08:21:59 AM UTC 24
Finished Sep 18 08:22:02 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125163472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.1125163472
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_cmderr_exception/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.3212527864
Short name T33
Test name
Test status
Simulation time 10532101697 ps
CPU time 38.56 seconds
Started Sep 18 08:22:20 AM UTC 24
Finished Sep 18 08:23:00 AM UTC 24
Peak memory 232892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=3212527864 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stres
s_all_with_rand_reset.3212527864
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_bad_sba_tl_access.4252615307
Short name T80
Test name
Test status
Simulation time 3291607274 ps
CPU time 5.32 seconds
Started Sep 18 08:22:12 AM UTC 24
Finished Sep 18 08:22:19 AM UTC 24
Peak memory 216096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252615307 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.4252615307
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.3317683512
Short name T9
Test name
Test status
Simulation time 3651908012 ps
CPU time 3.19 seconds
Started Sep 18 08:22:10 AM UTC 24
Finished Sep 18 08:22:15 AM UTC 24
Peak memory 215992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317683512 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.3317683512
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.3604027458
Short name T19
Test name
Test status
Simulation time 239282429 ps
CPU time 1.8 seconds
Started Sep 18 08:22:24 AM UTC 24
Finished Sep 18 08:22:28 AM UTC 24
Peak memory 250744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604027458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_buffered_enable.3604027458
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/2.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.3054276689
Short name T110
Test name
Test status
Simulation time 45026684607 ps
CPU time 115.95 seconds
Started Sep 18 07:53:47 AM UTC 24
Finished Sep 18 07:55:45 AM UTC 24
Peak memory 232376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3054276689 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_re
set.3054276689
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.354005198
Short name T181
Test name
Test status
Simulation time 7434037476 ps
CPU time 26.53 seconds
Started Sep 18 07:53:06 AM UTC 24
Finished Sep 18 07:53:34 AM UTC 24
Peak memory 232792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354005198 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.354005198
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.183037516
Short name T20
Test name
Test status
Simulation time 6589933026 ps
CPU time 8.43 seconds
Started Sep 18 08:21:59 AM UTC 24
Finished Sep 18 08:22:09 AM UTC 24
Peak memory 232916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183037516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.183037516
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2024668641
Short name T106
Test name
Test status
Simulation time 4577772265 ps
CPU time 25.64 seconds
Started Sep 18 07:53:35 AM UTC 24
Finished Sep 18 07:54:02 AM UTC 24
Peak memory 228076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2024668641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_re
set.2024668641
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.2684006022
Short name T42
Test name
Test status
Simulation time 693781013 ps
CPU time 2.28 seconds
Started Sep 18 08:22:07 AM UTC 24
Finished Sep 18 08:22:11 AM UTC 24
Peak memory 215792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684006022 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_progbuf_read_write_execute_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_d
m-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.2684006022
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3316154252
Short name T128
Test name
Test status
Simulation time 1075018810 ps
CPU time 6.5 seconds
Started Sep 18 07:53:09 AM UTC 24
Finished Sep 18 07:53:16 AM UTC 24
Peak memory 215540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316154252 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_csr_outstanding.3316154252
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all_with_rand_reset.2422153887
Short name T18
Test name
Test status
Simulation time 30872543323 ps
CPU time 51.84 seconds
Started Sep 18 08:22:43 AM UTC 24
Finished Sep 18 08:23:37 AM UTC 24
Peak memory 232928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=2422153887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stres
s_all_with_rand_reset.2422153887
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.3344127123
Short name T99
Test name
Test status
Simulation time 117507644 ps
CPU time 0.95 seconds
Started Sep 18 08:22:10 AM UTC 24
Finished Sep 18 08:22:12 AM UTC 24
Peak memory 215392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344127123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_scanmode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_scanmode.3344127123
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_scanmode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/14.rv_dm_autoincr_sba_tl_access.3915638472
Short name T186
Test name
Test status
Simulation time 5167786933 ps
CPU time 4.17 seconds
Started Sep 18 08:23:11 AM UTC 24
Finished Sep 18 08:23:16 AM UTC 24
Peak memory 226460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915638472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.3915638472
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.1695343093
Short name T90
Test name
Test status
Simulation time 983157201 ps
CPU time 4.39 seconds
Started Sep 18 08:22:25 AM UTC 24
Finished Sep 18 08:22:30 AM UTC 24
Peak memory 256192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695343093 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.1695343093
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/2.rv_dm_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/34.rv_dm_stress_all.3813655582
Short name T225
Test name
Test status
Simulation time 4826137269 ps
CPU time 4.9 seconds
Started Sep 18 08:23:35 AM UTC 24
Finished Sep 18 08:23:40 AM UTC 24
Peak memory 226180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813655582 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.3813655582
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/34.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.1265998099
Short name T69
Test name
Test status
Simulation time 3556803336 ps
CPU time 38.5 seconds
Started Sep 18 08:22:28 AM UTC 24
Finished Sep 18 08:23:08 AM UTC 24
Peak memory 232936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=1265998099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stres
s_all_with_rand_reset.1265998099
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.975669932
Short name T73
Test name
Test status
Simulation time 379992159 ps
CPU time 1.93 seconds
Started Sep 18 08:22:08 AM UTC 24
Finished Sep 18 08:22:11 AM UTC 24
Peak memory 215048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975669932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_dmi_failed_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.975669932
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_dmi_failed_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.1801367338
Short name T83
Test name
Test status
Simulation time 10195162086 ps
CPU time 24.45 seconds
Started Sep 18 08:21:56 AM UTC 24
Finished Sep 18 08:22:22 AM UTC 24
Peak memory 215928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801367338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.1801367338
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.4238235720
Short name T107
Test name
Test status
Simulation time 1677102067 ps
CPU time 26.94 seconds
Started Sep 18 07:53:40 AM UTC 24
Finished Sep 18 07:54:08 AM UTC 24
Peak memory 228148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=4238235720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_re
set.4238235720
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.2903122274
Short name T103
Test name
Test status
Simulation time 7325402478 ps
CPU time 30.75 seconds
Started Sep 18 07:53:44 AM UTC 24
Finished Sep 18 07:54:16 AM UTC 24
Peak memory 228012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2903122274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_re
set.2903122274
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.1330573241
Short name T108
Test name
Test status
Simulation time 2796916430 ps
CPU time 41.92 seconds
Started Sep 18 08:22:52 AM UTC 24
Finished Sep 18 08:23:35 AM UTC 24
Peak memory 230388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=1330573241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stres
s_all_with_rand_reset.1330573241
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/15.rv_dm_autoincr_sba_tl_access.1856202000
Short name T187
Test name
Test status
Simulation time 10221262625 ps
CPU time 37.05 seconds
Started Sep 18 08:23:14 AM UTC 24
Finished Sep 18 08:23:52 AM UTC 24
Peak memory 226316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856202000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.1856202000
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.286696430
Short name T45
Test name
Test status
Simulation time 40657562 ps
CPU time 1.03 seconds
Started Sep 18 08:22:11 AM UTC 24
Finished Sep 18 08:22:13 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286696430 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.286696430
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.3787564271
Short name T28
Test name
Test status
Simulation time 1721350992 ps
CPU time 3.76 seconds
Started Sep 18 08:23:34 AM UTC 24
Finished Sep 18 08:23:39 AM UTC 24
Peak memory 215792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787564271 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.3787564271
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/33.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/6.rv_dm_autoincr_sba_tl_access.205063797
Short name T256
Test name
Test status
Simulation time 12886928425 ps
CPU time 25.33 seconds
Started Sep 18 08:22:43 AM UTC 24
Finished Sep 18 08:23:09 AM UTC 24
Peak memory 225924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205063797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.205063797
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_rw.2852205725
Short name T152
Test name
Test status
Simulation time 107188986 ps
CPU time 2.43 seconds
Started Sep 18 07:53:58 AM UTC 24
Finished Sep 18 07:54:01 AM UTC 24
Peak memory 225840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852205725 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.2852205725
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/9.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/43.rv_dm_stress_all.2101260076
Short name T204
Test name
Test status
Simulation time 2764440257 ps
CPU time 3.1 seconds
Started Sep 18 08:23:39 AM UTC 24
Finished Sep 18 08:23:43 AM UTC 24
Peak memory 215852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101260076 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.2101260076
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/43.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.1632367456
Short name T61
Test name
Test status
Simulation time 129496316 ps
CPU time 1.06 seconds
Started Sep 18 08:22:07 AM UTC 24
Finished Sep 18 08:22:09 AM UTC 24
Peak memory 225136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632367456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_rom_read_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.1632367456
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_rom_read_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.1469661520
Short name T70
Test name
Test status
Simulation time 420103197 ps
CPU time 1.87 seconds
Started Sep 18 08:22:46 AM UTC 24
Finished Sep 18 08:22:48 AM UTC 24
Peak memory 215332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469661520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_halt_resume_whereto.1469661520
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/7.rv_dm_halt_resume_whereto/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.291661202
Short name T148
Test name
Test status
Simulation time 4470249309 ps
CPU time 29.85 seconds
Started Sep 18 07:53:00 AM UTC 24
Finished Sep 18 07:53:32 AM UTC 24
Peak memory 215756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291661202 -asse
rt nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_aliasing.291661202
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/31.rv_dm_stress_all.2835066801
Short name T208
Test name
Test status
Simulation time 3010591749 ps
CPU time 6.55 seconds
Started Sep 18 08:23:33 AM UTC 24
Finished Sep 18 08:23:41 AM UTC 24
Peak memory 226244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835066801 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.2835066801
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/31.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.1616741191
Short name T59
Test name
Test status
Simulation time 263517604 ps
CPU time 3.01 seconds
Started Sep 18 08:22:10 AM UTC 24
Finished Sep 18 08:22:14 AM UTC 24
Peak memory 252128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616741191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_buffered_enable.1616741191
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2605132632
Short name T183
Test name
Test status
Simulation time 2373866465 ps
CPU time 15.55 seconds
Started Sep 18 07:53:22 AM UTC 24
Finished Sep 18 07:53:39 AM UTC 24
Peak memory 228040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605132632 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.2605132632
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/2.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.2288676505
Short name T29
Test name
Test status
Simulation time 5897743266 ps
CPU time 19.72 seconds
Started Sep 18 08:23:25 AM UTC 24
Finished Sep 18 08:23:46 AM UTC 24
Peak memory 215928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288676505 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.2288676505
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/19.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.3638609250
Short name T179
Test name
Test status
Simulation time 2640939316 ps
CPU time 9.61 seconds
Started Sep 18 08:22:55 AM UTC 24
Finished Sep 18 08:23:05 AM UTC 24
Peak memory 226528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638609250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.3638609250
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/9.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.3794272388
Short name T21
Test name
Test status
Simulation time 768695562 ps
CPU time 4.92 seconds
Started Sep 18 08:22:04 AM UTC 24
Finished Sep 18 08:22:10 AM UTC 24
Peak memory 216000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794272388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.3794272388
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_sba_debug_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3105298100
Short name T229
Test name
Test status
Simulation time 3078365123 ps
CPU time 19.85 seconds
Started Sep 18 07:53:57 AM UTC 24
Finished Sep 18 07:54:17 AM UTC 24
Peak memory 228024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105298100 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.3105298100
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/9.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/32.rv_dm_stress_all.3492892616
Short name T214
Test name
Test status
Simulation time 1971398024 ps
CPU time 7.51 seconds
Started Sep 18 08:23:33 AM UTC 24
Finished Sep 18 08:23:42 AM UTC 24
Peak memory 215984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492892616 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.3492892616
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/32.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.2792875464
Short name T75
Test name
Test status
Simulation time 2085739243 ps
CPU time 2.97 seconds
Started Sep 18 08:22:40 AM UTC 24
Finished Sep 18 08:22:44 AM UTC 24
Peak memory 226040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792875464 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.2792875464
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/5.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1172891071
Short name T335
Test name
Test status
Simulation time 1210206076 ps
CPU time 3.02 seconds
Started Sep 18 07:53:04 AM UTC 24
Finished Sep 18 07:53:08 AM UTC 24
Peak memory 215384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172891071 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_aliasing.1172891071
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.2325959464
Short name T52
Test name
Test status
Simulation time 8579417503 ps
CPU time 9.75 seconds
Started Sep 18 08:23:31 AM UTC 24
Finished Sep 18 08:23:42 AM UTC 24
Peak memory 216188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325959464 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.2325959464
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/27.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3936714070
Short name T139
Test name
Test status
Simulation time 9844744112 ps
CPU time 12.26 seconds
Started Sep 18 07:53:04 AM UTC 24
Finished Sep 18 07:53:17 AM UTC 24
Peak memory 215760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936714070 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_hw_reset.3936714070
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.2707821672
Short name T5
Test name
Test status
Simulation time 213377724 ps
CPU time 1.66 seconds
Started Sep 18 08:22:03 AM UTC 24
Finished Sep 18 08:22:07 AM UTC 24
Peak memory 215276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707821672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.2707821672
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_cmderr_halt_resume/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_ndmreset_req.2804438647
Short name T39
Test name
Test status
Simulation time 308163931 ps
CPU time 1.6 seconds
Started Sep 18 08:22:16 AM UTC 24
Finished Sep 18 08:22:19 AM UTC 24
Peak memory 225136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804438647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.2804438647
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_ndmreset_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/10.rv_dm_stress_all.3432972060
Short name T30
Test name
Test status
Simulation time 3933592210 ps
CPU time 14.18 seconds
Started Sep 18 08:23:02 AM UTC 24
Finished Sep 18 08:23:17 AM UTC 24
Peak memory 226360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432972060 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.3432972060
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/10.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/12.rv_dm_stress_all.1706868326
Short name T31
Test name
Test status
Simulation time 2303768164 ps
CPU time 2.65 seconds
Started Sep 18 08:23:07 AM UTC 24
Finished Sep 18 08:23:11 AM UTC 24
Peak memory 215912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706868326 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.1706868326
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/12.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/14.rv_dm_bad_sba_tl_access.3953601729
Short name T190
Test name
Test status
Simulation time 5665768190 ps
CPU time 24.59 seconds
Started Sep 18 08:23:11 AM UTC 24
Finished Sep 18 08:23:37 AM UTC 24
Peak memory 226600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953601729 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.3953601729
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/14.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.2196047051
Short name T63
Test name
Test status
Simulation time 2754358418 ps
CPU time 5.16 seconds
Started Sep 18 08:22:33 AM UTC 24
Finished Sep 18 08:22:40 AM UTC 24
Peak memory 216172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196047051 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.2196047051
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/4.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.758381901
Short name T192
Test name
Test status
Simulation time 3578305646 ps
CPU time 12.3 seconds
Started Sep 18 08:22:46 AM UTC 24
Finished Sep 18 08:22:59 AM UTC 24
Peak memory 216216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758381901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.758381901
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/7.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_rw.3045200829
Short name T157
Test name
Test status
Simulation time 170625563 ps
CPU time 2.38 seconds
Started Sep 18 07:54:23 AM UTC 24
Finished Sep 18 07:54:26 AM UTC 24
Peak memory 232516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045200829 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.3045200829
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/19.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.467793502
Short name T44
Test name
Test status
Simulation time 69482875 ps
CPU time 1.27 seconds
Started Sep 18 08:22:10 AM UTC 24
Finished Sep 18 08:22:12 AM UTC 24
Peak memory 225252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467793502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sparse_lc_gate_fsm.467793502
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_sparse_lc_gate_fsm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.1165409235
Short name T49
Test name
Test status
Simulation time 45605434 ps
CPU time 1.15 seconds
Started Sep 18 08:22:20 AM UTC 24
Finished Sep 18 08:22:22 AM UTC 24
Peak memory 225136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165409235 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sparse_lc_gate_fsm.1165409235
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_sparse_lc_gate_fsm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3142460272
Short name T464
Test name
Test status
Simulation time 2968533904 ps
CPU time 16.95 seconds
Started Sep 18 07:54:14 AM UTC 24
Finished Sep 18 07:54:32 AM UTC 24
Peak memory 226072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142460272 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.3142460272
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/15.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.4248672197
Short name T391
Test name
Test status
Simulation time 5857272780 ps
CPU time 51.44 seconds
Started Sep 18 07:53:09 AM UTC 24
Finished Sep 18 07:54:02 AM UTC 24
Peak memory 225952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248672197 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.4248672197
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.4017691054
Short name T126
Test name
Test status
Simulation time 235034019 ps
CPU time 1.85 seconds
Started Sep 18 07:53:06 AM UTC 24
Finished Sep 18 07:53:09 AM UTC 24
Peak memory 225208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017691054 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.4017691054
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3738098754
Short name T235
Test name
Test status
Simulation time 130763442 ps
CPU time 3.24 seconds
Started Sep 18 07:53:09 AM UTC 24
Finished Sep 18 07:53:13 AM UTC 24
Peak memory 232468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=3738098754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_r
and_reset.3738098754
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.574876246
Short name T127
Test name
Test status
Simulation time 180300701 ps
CPU time 2.03 seconds
Started Sep 18 07:53:08 AM UTC 24
Finished Sep 18 07:53:11 AM UTC 24
Peak memory 225932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574876246 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/r
v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.574876246
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1005448279
Short name T480
Test name
Test status
Simulation time 114637055588 ps
CPU time 163.07 seconds
Started Sep 18 07:53:05 AM UTC 24
Finished Sep 18 07:55:51 AM UTC 24
Peak memory 215584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005448279 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_aliasing.1005448279
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1910911291
Short name T478
Test name
Test status
Simulation time 48168858954 ps
CPU time 125.18 seconds
Started Sep 18 07:53:04 AM UTC 24
Finished Sep 18 07:55:11 AM UTC 24
Peak memory 215692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910911291 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_bit_bash.1910911291
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3649967917
Short name T339
Test name
Test status
Simulation time 3171408047 ps
CPU time 6.51 seconds
Started Sep 18 07:53:04 AM UTC 24
Finished Sep 18 07:53:12 AM UTC 24
Peak memory 215596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649967917 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.3649967917
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1599074262
Short name T102
Test name
Test status
Simulation time 2797309949 ps
CPU time 4.18 seconds
Started Sep 18 07:53:03 AM UTC 24
Finished Sep 18 07:53:08 AM UTC 24
Peak memory 215556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599074262 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_bit_bash.1599074262
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1232625563
Short name T100
Test name
Test status
Simulation time 279042869 ps
CPU time 0.95 seconds
Started Sep 18 07:53:00 AM UTC 24
Finished Sep 18 07:53:02 AM UTC 24
Peak memory 214792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232625563 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_hw_reset.1232625563
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.582229115
Short name T101
Test name
Test status
Simulation time 369793493 ps
CPU time 2.51 seconds
Started Sep 18 07:53:02 AM UTC 24
Finished Sep 18 07:53:05 AM UTC 24
Peak memory 215456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582229115 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.582229115
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1525359650
Short name T337
Test name
Test status
Simulation time 87236493 ps
CPU time 1.09 seconds
Started Sep 18 07:53:06 AM UTC 24
Finished Sep 18 07:53:08 AM UTC 24
Peak memory 215312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525359650 -assert nopostproc +UVM
_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_partial_access.1525359650
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.2851792944
Short name T336
Test name
Test status
Simulation time 55206984 ps
CPU time 0.88 seconds
Started Sep 18 07:53:06 AM UTC 24
Finished Sep 18 07:53:08 AM UTC 24
Peak memory 215308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851792944 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.2851792944
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1302720761
Short name T469
Test name
Test status
Simulation time 21881554173 ps
CPU time 93.35 seconds
Started Sep 18 07:53:05 AM UTC 24
Finished Sep 18 07:54:40 AM UTC 24
Peak memory 232788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=1302720761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_re
set.1302720761
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.3902253775
Short name T175
Test name
Test status
Simulation time 318899564 ps
CPU time 4.58 seconds
Started Sep 18 07:53:05 AM UTC 24
Finished Sep 18 07:53:11 AM UTC 24
Peak memory 225832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902253775 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.3902253775
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.429542584
Short name T173
Test name
Test status
Simulation time 2164522313 ps
CPU time 25.02 seconds
Started Sep 18 07:53:09 AM UTC 24
Finished Sep 18 07:53:35 AM UTC 24
Peak memory 215684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429542584 -asse
rt nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_aliasing.429542584
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2752971925
Short name T396
Test name
Test status
Simulation time 5107063377 ps
CPU time 60.67 seconds
Started Sep 18 07:53:17 AM UTC 24
Finished Sep 18 07:54:19 AM UTC 24
Peak memory 215700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752971925 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.2752971925
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2536686328
Short name T129
Test name
Test status
Simulation time 193466050 ps
CPU time 2.29 seconds
Started Sep 18 07:53:15 AM UTC 24
Finished Sep 18 07:53:18 AM UTC 24
Peak memory 225872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536686328 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2536686328
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.4293524810
Short name T350
Test name
Test status
Simulation time 264270831 ps
CPU time 4.1 seconds
Started Sep 18 07:53:17 AM UTC 24
Finished Sep 18 07:53:22 AM UTC 24
Peak memory 230072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=4293524810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_r
and_reset.4293524810
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.701779013
Short name T130
Test name
Test status
Simulation time 541749748 ps
CPU time 2.31 seconds
Started Sep 18 07:53:16 AM UTC 24
Finished Sep 18 07:53:19 AM UTC 24
Peak memory 225864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701779013 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/r
v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.701779013
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2324927083
Short name T475
Test name
Test status
Simulation time 27342302612 ps
CPU time 105.85 seconds
Started Sep 18 07:53:11 AM UTC 24
Finished Sep 18 07:54:59 AM UTC 24
Peak memory 215664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324927083 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_aliasing.2324927083
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.432863293
Short name T455
Test name
Test status
Simulation time 58509152935 ps
CPU time 76.11 seconds
Started Sep 18 07:53:11 AM UTC 24
Finished Sep 18 07:54:29 AM UTC 24
Peak memory 215604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432863293 -assert nopostpro
c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_bit_bash.432863293
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1266462620
Short name T348
Test name
Test status
Simulation time 2891732688 ps
CPU time 9.4 seconds
Started Sep 18 07:53:11 AM UTC 24
Finished Sep 18 07:53:22 AM UTC 24
Peak memory 215664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266462620 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_hw_reset.1266462620
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.447517804
Short name T349
Test name
Test status
Simulation time 2948601731 ps
CPU time 9.6 seconds
Started Sep 18 07:53:11 AM UTC 24
Finished Sep 18 07:53:22 AM UTC 24
Peak memory 215608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447517804 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.447517804
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2838447596
Short name T342
Test name
Test status
Simulation time 2413792493 ps
CPU time 4.08 seconds
Started Sep 18 07:53:10 AM UTC 24
Finished Sep 18 07:53:15 AM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838447596 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_aliasing.2838447596
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3595296833
Short name T401
Test name
Test status
Simulation time 18226622235 ps
CPU time 53.9 seconds
Started Sep 18 07:53:10 AM UTC 24
Finished Sep 18 07:54:05 AM UTC 24
Peak memory 215516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595296833 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_bit_bash.3595296833
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1830691228
Short name T338
Test name
Test status
Simulation time 294319029 ps
CPU time 1.1 seconds
Started Sep 18 07:53:09 AM UTC 24
Finished Sep 18 07:53:11 AM UTC 24
Peak memory 215312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830691228 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_hw_reset.1830691228
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.4013754931
Short name T340
Test name
Test status
Simulation time 149633299 ps
CPU time 1.68 seconds
Started Sep 18 07:53:10 AM UTC 24
Finished Sep 18 07:53:13 AM UTC 24
Peak memory 215308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013754931 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.4013754931
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.179402206
Short name T343
Test name
Test status
Simulation time 86025482 ps
CPU time 1.06 seconds
Started Sep 18 07:53:14 AM UTC 24
Finished Sep 18 07:53:16 AM UTC 24
Peak memory 215312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179402206 -assert nopostproc +UVM_
TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_partial_access.179402206
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.1479587561
Short name T344
Test name
Test status
Simulation time 138185363 ps
CPU time 1.14 seconds
Started Sep 18 07:53:14 AM UTC 24
Finished Sep 18 07:53:16 AM UTC 24
Peak memory 215308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479587561 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.1479587561
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3883786184
Short name T133
Test name
Test status
Simulation time 475065407 ps
CPU time 8.69 seconds
Started Sep 18 07:53:17 AM UTC 24
Finished Sep 18 07:53:27 AM UTC 24
Peak memory 215544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883786184 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_csr_outstanding.3883786184
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.540543261
Short name T114
Test name
Test status
Simulation time 3429895412 ps
CPU time 54.31 seconds
Started Sep 18 07:53:13 AM UTC 24
Finished Sep 18 07:54:08 AM UTC 24
Peak memory 226132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=540543261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.540543261
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.2216509647
Short name T345
Test name
Test status
Simulation time 681073890 ps
CPU time 6.05 seconds
Started Sep 18 07:53:13 AM UTC 24
Finished Sep 18 07:53:20 AM UTC 24
Peak memory 225920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216509647 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.2216509647
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3900017940
Short name T182
Test name
Test status
Simulation time 2694899588 ps
CPU time 22.26 seconds
Started Sep 18 07:53:14 AM UTC 24
Finished Sep 18 07:53:37 AM UTC 24
Peak memory 232824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900017940 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.3900017940
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2297444860
Short name T400
Test name
Test status
Simulation time 43767360 ps
CPU time 1.99 seconds
Started Sep 18 07:54:02 AM UTC 24
Finished Sep 18 07:54:05 AM UTC 24
Peak memory 229324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=2297444860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_
rand_reset.2297444860
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.774844863
Short name T166
Test name
Test status
Simulation time 370641539 ps
CPU time 3.02 seconds
Started Sep 18 07:54:02 AM UTC 24
Finished Sep 18 07:54:06 AM UTC 24
Peak memory 232012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774844863 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/r
v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.774844863
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/10.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3516600190
Short name T479
Test name
Test status
Simulation time 33060079601 ps
CPU time 92.95 seconds
Started Sep 18 07:54:00 AM UTC 24
Finished Sep 18 07:55:35 AM UTC 24
Peak memory 215532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516600190 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_bit_bash.3516600190
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.4272058232
Short name T404
Test name
Test status
Simulation time 2409956405 ps
CPU time 7 seconds
Started Sep 18 07:53:59 AM UTC 24
Finished Sep 18 07:54:07 AM UTC 24
Peak memory 215528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272058232 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.4272058232
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.841558901
Short name T390
Test name
Test status
Simulation time 192756643 ps
CPU time 1.49 seconds
Started Sep 18 07:53:59 AM UTC 24
Finished Sep 18 07:54:01 AM UTC 24
Peak memory 215308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841558901 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.841558901
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.1553476339
Short name T408
Test name
Test status
Simulation time 1177172032 ps
CPU time 6.5 seconds
Started Sep 18 07:54:02 AM UTC 24
Finished Sep 18 07:54:10 AM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553476339 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_csr_outstanding.1553476339
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/10.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.543661143
Short name T398
Test name
Test status
Simulation time 274778895 ps
CPU time 3.46 seconds
Started Sep 18 07:54:00 AM UTC 24
Finished Sep 18 07:54:04 AM UTC 24
Peak memory 225872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543661143 -assert nopostproc +UVM_TESTNAME=rv_dm_base
_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_d
m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.543661143
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/10.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3478861545
Short name T420
Test name
Test status
Simulation time 1893853226 ps
CPU time 12.56 seconds
Started Sep 18 07:54:01 AM UTC 24
Finished Sep 18 07:54:15 AM UTC 24
Peak memory 232584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478861545 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.3478861545
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/10.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1546219857
Short name T412
Test name
Test status
Simulation time 197297956 ps
CPU time 4.69 seconds
Started Sep 18 07:54:05 AM UTC 24
Finished Sep 18 07:54:10 AM UTC 24
Peak memory 232256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=1546219857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_
rand_reset.1546219857
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_rw.1389398288
Short name T403
Test name
Test status
Simulation time 79410547 ps
CPU time 2.25 seconds
Started Sep 18 07:54:03 AM UTC 24
Finished Sep 18 07:54:07 AM UTC 24
Peak memory 225800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389398288 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.1389398288
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/11.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1074415271
Short name T443
Test name
Test status
Simulation time 5872789754 ps
CPU time 19.25 seconds
Started Sep 18 07:54:03 AM UTC 24
Finished Sep 18 07:54:24 AM UTC 24
Peak memory 215660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074415271 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_bit_bash.1074415271
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.183638604
Short name T405
Test name
Test status
Simulation time 3778532342 ps
CPU time 3.08 seconds
Started Sep 18 07:54:03 AM UTC 24
Finished Sep 18 07:54:07 AM UTC 24
Peak memory 215764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183638604 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.183638604
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.323798407
Short name T402
Test name
Test status
Simulation time 237557489 ps
CPU time 1.25 seconds
Started Sep 18 07:54:03 AM UTC 24
Finished Sep 18 07:54:05 AM UTC 24
Peak memory 215308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323798407 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.323798407
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2170031394
Short name T153
Test name
Test status
Simulation time 520062069 ps
CPU time 9.4 seconds
Started Sep 18 07:54:05 AM UTC 24
Finished Sep 18 07:54:15 AM UTC 24
Peak memory 215508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170031394 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_csr_outstanding.2170031394
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/11.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_errors.397081039
Short name T406
Test name
Test status
Simulation time 490846966 ps
CPU time 3.59 seconds
Started Sep 18 07:54:03 AM UTC 24
Finished Sep 18 07:54:08 AM UTC 24
Peak memory 225840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397081039 -assert nopostproc +UVM_TESTNAME=rv_dm_base
_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_d
m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.397081039
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/11.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1739580438
Short name T230
Test name
Test status
Simulation time 4675953397 ps
CPU time 22.47 seconds
Started Sep 18 07:54:03 AM UTC 24
Finished Sep 18 07:54:27 AM UTC 24
Peak memory 226104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739580438 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.1739580438
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/11.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2719203320
Short name T115
Test name
Test status
Simulation time 133212347 ps
CPU time 3.9 seconds
Started Sep 18 07:54:08 AM UTC 24
Finished Sep 18 07:54:13 AM UTC 24
Peak memory 229952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=2719203320 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_
rand_reset.2719203320
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_rw.1712366839
Short name T165
Test name
Test status
Simulation time 399065804 ps
CPU time 1.6 seconds
Started Sep 18 07:54:07 AM UTC 24
Finished Sep 18 07:54:09 AM UTC 24
Peak memory 225360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712366839 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.1712366839
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/12.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2607360509
Short name T467
Test name
Test status
Simulation time 9935886459 ps
CPU time 30.25 seconds
Started Sep 18 07:54:06 AM UTC 24
Finished Sep 18 07:54:37 AM UTC 24
Peak memory 215684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607360509 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_bit_bash.2607360509
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2645762347
Short name T428
Test name
Test status
Simulation time 4630390547 ps
CPU time 11.24 seconds
Started Sep 18 07:54:06 AM UTC 24
Finished Sep 18 07:54:18 AM UTC 24
Peak memory 215600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645762347 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.2645762347
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3258712962
Short name T407
Test name
Test status
Simulation time 394249166 ps
CPU time 1.72 seconds
Started Sep 18 07:54:06 AM UTC 24
Finished Sep 18 07:54:08 AM UTC 24
Peak memory 215308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258712962 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.3258712962
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2554188408
Short name T154
Test name
Test status
Simulation time 1868344295 ps
CPU time 8.62 seconds
Started Sep 18 07:54:07 AM UTC 24
Finished Sep 18 07:54:17 AM UTC 24
Peak memory 215604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554188408 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same_csr_outstanding.2554188408
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/12.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_errors.2131993306
Short name T413
Test name
Test status
Simulation time 64277293 ps
CPU time 3.74 seconds
Started Sep 18 07:54:06 AM UTC 24
Finished Sep 18 07:54:10 AM UTC 24
Peak memory 226036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131993306 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.2131993306
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/12.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3516767307
Short name T436
Test name
Test status
Simulation time 2331585344 ps
CPU time 14.46 seconds
Started Sep 18 07:54:06 AM UTC 24
Finished Sep 18 07:54:21 AM UTC 24
Peak memory 232924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516767307 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.3516767307
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/12.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1755417502
Short name T419
Test name
Test status
Simulation time 105080565 ps
CPU time 3.01 seconds
Started Sep 18 07:54:11 AM UTC 24
Finished Sep 18 07:54:14 AM UTC 24
Peak memory 230016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=1755417502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_
rand_reset.1755417502
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_rw.1797322857
Short name T415
Test name
Test status
Simulation time 187977196 ps
CPU time 2.42 seconds
Started Sep 18 07:54:09 AM UTC 24
Finished Sep 18 07:54:13 AM UTC 24
Peak memory 225960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797322857 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.1797322857
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/13.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.815572862
Short name T421
Test name
Test status
Simulation time 3896980559 ps
CPU time 4.52 seconds
Started Sep 18 07:54:09 AM UTC 24
Finished Sep 18 07:54:15 AM UTC 24
Peak memory 215620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815572862 -assert nopostpro
c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_bit_bash.815572862
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2426424702
Short name T418
Test name
Test status
Simulation time 2563198484 ps
CPU time 4.75 seconds
Started Sep 18 07:54:08 AM UTC 24
Finished Sep 18 07:54:14 AM UTC 24
Peak memory 215600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426424702 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.2426424702
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2374270043
Short name T411
Test name
Test status
Simulation time 144683180 ps
CPU time 1.22 seconds
Started Sep 18 07:54:08 AM UTC 24
Finished Sep 18 07:54:10 AM UTC 24
Peak memory 215308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374270043 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.2374270043
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.4081443737
Short name T423
Test name
Test status
Simulation time 404563667 ps
CPU time 4.69 seconds
Started Sep 18 07:54:09 AM UTC 24
Finished Sep 18 07:54:15 AM UTC 24
Peak memory 215548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081443737 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_csr_outstanding.4081443737
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/13.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_errors.1020569344
Short name T417
Test name
Test status
Simulation time 134476299 ps
CPU time 2.99 seconds
Started Sep 18 07:54:09 AM UTC 24
Finished Sep 18 07:54:13 AM UTC 24
Peak memory 226156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020569344 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.1020569344
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/13.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2684397137
Short name T231
Test name
Test status
Simulation time 1546814765 ps
CPU time 8.76 seconds
Started Sep 18 07:54:09 AM UTC 24
Finished Sep 18 07:54:19 AM UTC 24
Peak memory 232692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684397137 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.2684397137
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/13.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1503681499
Short name T422
Test name
Test status
Simulation time 101650930 ps
CPU time 1.99 seconds
Started Sep 18 07:54:12 AM UTC 24
Finished Sep 18 07:54:15 AM UTC 24
Peak memory 227324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=1503681499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_
rand_reset.1503681499
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_rw.3043990893
Short name T163
Test name
Test status
Simulation time 118071619 ps
CPU time 2.48 seconds
Started Sep 18 07:54:11 AM UTC 24
Finished Sep 18 07:54:14 AM UTC 24
Peak memory 229920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043990893 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.3043990893
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/14.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.2038324847
Short name T473
Test name
Test status
Simulation time 26847746419 ps
CPU time 34.88 seconds
Started Sep 18 07:54:11 AM UTC 24
Finished Sep 18 07:54:47 AM UTC 24
Peak memory 215248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038324847 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_bit_bash.2038324847
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1041286597
Short name T427
Test name
Test status
Simulation time 1624499263 ps
CPU time 6.3 seconds
Started Sep 18 07:54:11 AM UTC 24
Finished Sep 18 07:54:18 AM UTC 24
Peak memory 215600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041286597 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.1041286597
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.3552466149
Short name T416
Test name
Test status
Simulation time 205165859 ps
CPU time 1.42 seconds
Started Sep 18 07:54:11 AM UTC 24
Finished Sep 18 07:54:13 AM UTC 24
Peak memory 215308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552466149 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.3552466149
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3579964331
Short name T155
Test name
Test status
Simulation time 162864915 ps
CPU time 4.12 seconds
Started Sep 18 07:54:12 AM UTC 24
Finished Sep 18 07:54:17 AM UTC 24
Peak memory 215476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579964331 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same_csr_outstanding.3579964331
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/14.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_errors.1267058871
Short name T425
Test name
Test status
Simulation time 377741349 ps
CPU time 3.69 seconds
Started Sep 18 07:54:11 AM UTC 24
Finished Sep 18 07:54:15 AM UTC 24
Peak memory 225536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267058871 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.1267058871
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/14.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3755343309
Short name T462
Test name
Test status
Simulation time 4297359477 ps
CPU time 19.21 seconds
Started Sep 18 07:54:11 AM UTC 24
Finished Sep 18 07:54:31 AM UTC 24
Peak memory 225992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755343309 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.3755343309
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/14.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3896831076
Short name T432
Test name
Test status
Simulation time 97651139 ps
CPU time 3.94 seconds
Started Sep 18 07:54:16 AM UTC 24
Finished Sep 18 07:54:20 AM UTC 24
Peak memory 232508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=3896831076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_
rand_reset.3896831076
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_rw.1996847710
Short name T426
Test name
Test status
Simulation time 1105713362 ps
CPU time 2.27 seconds
Started Sep 18 07:54:14 AM UTC 24
Finished Sep 18 07:54:17 AM UTC 24
Peak memory 225896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996847710 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.1996847710
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/15.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.303711838
Short name T483
Test name
Test status
Simulation time 100023362417 ps
CPU time 292.88 seconds
Started Sep 18 07:54:14 AM UTC 24
Finished Sep 18 07:59:11 AM UTC 24
Peak memory 215636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303711838 -assert nopostpro
c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_bit_bash.303711838
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3735041256
Short name T442
Test name
Test status
Simulation time 7332896213 ps
CPU time 8.5 seconds
Started Sep 18 07:54:14 AM UTC 24
Finished Sep 18 07:54:24 AM UTC 24
Peak memory 215600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735041256 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.3735041256
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3900134093
Short name T424
Test name
Test status
Simulation time 99255404 ps
CPU time 1.22 seconds
Started Sep 18 07:54:13 AM UTC 24
Finished Sep 18 07:54:15 AM UTC 24
Peak memory 215308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900134093 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.3900134093
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.750990353
Short name T156
Test name
Test status
Simulation time 334469081 ps
CPU time 4.9 seconds
Started Sep 18 07:54:15 AM UTC 24
Finished Sep 18 07:54:21 AM UTC 24
Peak memory 215552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750990353 -assert nopostproc +UV
M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_csr_outstanding.750990353
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/15.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_errors.2149466374
Short name T433
Test name
Test status
Simulation time 517190465 ps
CPU time 5.53 seconds
Started Sep 18 07:54:14 AM UTC 24
Finished Sep 18 07:54:21 AM UTC 24
Peak memory 225968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149466374 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.2149466374
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/15.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.779239227
Short name T438
Test name
Test status
Simulation time 254501190 ps
CPU time 3.95 seconds
Started Sep 18 07:54:17 AM UTC 24
Finished Sep 18 07:54:22 AM UTC 24
Peak memory 229944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=779239227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_r
and_reset.779239227
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_rw.3233533837
Short name T161
Test name
Test status
Simulation time 81638224 ps
CPU time 2.18 seconds
Started Sep 18 07:54:16 AM UTC 24
Finished Sep 18 07:54:19 AM UTC 24
Peak memory 229936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233533837 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.3233533837
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/16.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1409064633
Short name T463
Test name
Test status
Simulation time 16064726760 ps
CPU time 14.99 seconds
Started Sep 18 07:54:16 AM UTC 24
Finished Sep 18 07:54:32 AM UTC 24
Peak memory 215596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409064633 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_bit_bash.1409064633
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.294254968
Short name T477
Test name
Test status
Simulation time 11925675592 ps
CPU time 53.08 seconds
Started Sep 18 07:54:16 AM UTC 24
Finished Sep 18 07:55:10 AM UTC 24
Peak memory 215524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294254968 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.294254968
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.392191755
Short name T429
Test name
Test status
Simulation time 473399681 ps
CPU time 1.52 seconds
Started Sep 18 07:54:16 AM UTC 24
Finished Sep 18 07:54:18 AM UTC 24
Peak memory 215308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392191755 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.392191755
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3276268635
Short name T435
Test name
Test status
Simulation time 92118311 ps
CPU time 4.42 seconds
Started Sep 18 07:54:16 AM UTC 24
Finished Sep 18 07:54:21 AM UTC 24
Peak memory 215580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276268635 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_csr_outstanding.3276268635
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/16.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_errors.3712876802
Short name T437
Test name
Test status
Simulation time 135311774 ps
CPU time 4.73 seconds
Started Sep 18 07:54:16 AM UTC 24
Finished Sep 18 07:54:21 AM UTC 24
Peak memory 226028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712876802 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.3712876802
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/16.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3912177852
Short name T232
Test name
Test status
Simulation time 1291924500 ps
CPU time 8.02 seconds
Started Sep 18 07:54:16 AM UTC 24
Finished Sep 18 07:54:25 AM UTC 24
Peak memory 225912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912177852 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.3912177852
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/16.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3496046550
Short name T448
Test name
Test status
Simulation time 160545723 ps
CPU time 4.68 seconds
Started Sep 18 07:54:19 AM UTC 24
Finished Sep 18 07:54:25 AM UTC 24
Peak memory 225944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=3496046550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_
rand_reset.3496046550
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_rw.2780022818
Short name T434
Test name
Test status
Simulation time 284048722 ps
CPU time 2.16 seconds
Started Sep 18 07:54:18 AM UTC 24
Finished Sep 18 07:54:21 AM UTC 24
Peak memory 225832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780022818 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.2780022818
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/17.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1592014276
Short name T476
Test name
Test status
Simulation time 53252487876 ps
CPU time 46.64 seconds
Started Sep 18 07:54:18 AM UTC 24
Finished Sep 18 07:55:06 AM UTC 24
Peak memory 215596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592014276 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_bit_bash.1592014276
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.754151928
Short name T451
Test name
Test status
Simulation time 4714834884 ps
CPU time 8.29 seconds
Started Sep 18 07:54:18 AM UTC 24
Finished Sep 18 07:54:27 AM UTC 24
Peak memory 215596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754151928 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.754151928
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3146607373
Short name T431
Test name
Test status
Simulation time 498166555 ps
CPU time 1.57 seconds
Started Sep 18 07:54:17 AM UTC 24
Finished Sep 18 07:54:19 AM UTC 24
Peak memory 215308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146607373 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.3146607373
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.43996215
Short name T449
Test name
Test status
Simulation time 165056643 ps
CPU time 6.23 seconds
Started Sep 18 07:54:19 AM UTC 24
Finished Sep 18 07:54:26 AM UTC 24
Peak memory 215544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43996215 -assert nopostproc +UVM
_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same_csr_outstanding.43996215
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/17.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_errors.747503436
Short name T445
Test name
Test status
Simulation time 363150460 ps
CPU time 5.28 seconds
Started Sep 18 07:54:18 AM UTC 24
Finished Sep 18 07:54:24 AM UTC 24
Peak memory 226160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747503436 -assert nopostproc +UVM_TESTNAME=rv_dm_base
_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_d
m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.747503436
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/17.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2886481872
Short name T459
Test name
Test status
Simulation time 815045884 ps
CPU time 11.11 seconds
Started Sep 18 07:54:18 AM UTC 24
Finished Sep 18 07:54:30 AM UTC 24
Peak memory 232596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886481872 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.2886481872
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/17.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.4051126531
Short name T77
Test name
Test status
Simulation time 136659804 ps
CPU time 2.51 seconds
Started Sep 18 07:54:22 AM UTC 24
Finished Sep 18 07:54:25 AM UTC 24
Peak memory 225840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=4051126531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_
rand_reset.4051126531
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_rw.3925098334
Short name T447
Test name
Test status
Simulation time 112470511 ps
CPU time 3.29 seconds
Started Sep 18 07:54:21 AM UTC 24
Finished Sep 18 07:54:25 AM UTC 24
Peak memory 225772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925098334 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.3925098334
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/18.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.3433511388
Short name T482
Test name
Test status
Simulation time 83229776531 ps
CPU time 195.76 seconds
Started Sep 18 07:54:20 AM UTC 24
Finished Sep 18 07:57:39 AM UTC 24
Peak memory 215724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433511388 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_bit_bash.3433511388
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3328618954
Short name T453
Test name
Test status
Simulation time 5934963250 ps
CPU time 8.3 seconds
Started Sep 18 07:54:19 AM UTC 24
Finished Sep 18 07:54:29 AM UTC 24
Peak memory 215544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328618954 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.3328618954
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.53423632
Short name T441
Test name
Test status
Simulation time 826782057 ps
CPU time 2.44 seconds
Started Sep 18 07:54:19 AM UTC 24
Finished Sep 18 07:54:23 AM UTC 24
Peak memory 215384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53423632 -assert nopostproc +UVM_TESTNAME=rv_dm_ba
se_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.53423632
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1104612512
Short name T456
Test name
Test status
Simulation time 1273552545 ps
CPU time 6.7 seconds
Started Sep 18 07:54:22 AM UTC 24
Finished Sep 18 07:54:29 AM UTC 24
Peak memory 215392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104612512 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same_csr_outstanding.1104612512
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/18.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_errors.3152059842
Short name T452
Test name
Test status
Simulation time 273424859 ps
CPU time 6.03 seconds
Started Sep 18 07:54:20 AM UTC 24
Finished Sep 18 07:54:27 AM UTC 24
Peak memory 225896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152059842 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.3152059842
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/18.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3159583106
Short name T465
Test name
Test status
Simulation time 847839897 ps
CPU time 11.69 seconds
Started Sep 18 07:54:20 AM UTC 24
Finished Sep 18 07:54:33 AM UTC 24
Peak memory 225972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159583106 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3159583106
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/18.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.426120252
Short name T450
Test name
Test status
Simulation time 207327209 ps
CPU time 2.65 seconds
Started Sep 18 07:54:23 AM UTC 24
Finished Sep 18 07:54:27 AM UTC 24
Peak memory 225916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=426120252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_r
and_reset.426120252
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.4068717844
Short name T481
Test name
Test status
Simulation time 56236734087 ps
CPU time 90.43 seconds
Started Sep 18 07:54:23 AM UTC 24
Finished Sep 18 07:55:55 AM UTC 24
Peak memory 215596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068717844 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_bit_bash.4068717844
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2409350036
Short name T457
Test name
Test status
Simulation time 6028986748 ps
CPU time 6.89 seconds
Started Sep 18 07:54:22 AM UTC 24
Finished Sep 18 07:54:30 AM UTC 24
Peak memory 215688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409350036 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.2409350036
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.550838189
Short name T444
Test name
Test status
Simulation time 157407224 ps
CPU time 1.29 seconds
Started Sep 18 07:54:22 AM UTC 24
Finished Sep 18 07:54:24 AM UTC 24
Peak memory 215244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550838189 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.550838189
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2441563470
Short name T466
Test name
Test status
Simulation time 379271858 ps
CPU time 9.11 seconds
Started Sep 18 07:54:23 AM UTC 24
Finished Sep 18 07:54:33 AM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441563470 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_csr_outstanding.2441563470
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/19.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_errors.3999205835
Short name T458
Test name
Test status
Simulation time 1095723461 ps
CPU time 6.27 seconds
Started Sep 18 07:54:23 AM UTC 24
Finished Sep 18 07:54:30 AM UTC 24
Peak memory 226056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999205835 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.3999205835
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/19.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_intg_err.191699593
Short name T471
Test name
Test status
Simulation time 1085511733 ps
CPU time 20.28 seconds
Started Sep 18 07:54:23 AM UTC 24
Finished Sep 18 07:54:44 AM UTC 24
Peak memory 228032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191699593 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.191699593
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/19.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1031047080
Short name T150
Test name
Test status
Simulation time 9593479107 ps
CPU time 34.87 seconds
Started Sep 18 07:53:17 AM UTC 24
Finished Sep 18 07:53:53 AM UTC 24
Peak memory 215736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031047080 -ass
ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_aliasing.1031047080
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/2.rv_dm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.4224518307
Short name T393
Test name
Test status
Simulation time 4761181447 ps
CPU time 37.53 seconds
Started Sep 18 07:53:23 AM UTC 24
Finished Sep 18 07:54:02 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224518307 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.4224518307
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/2.rv_dm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.665869683
Short name T132
Test name
Test status
Simulation time 378728403 ps
CPU time 2.19 seconds
Started Sep 18 07:53:23 AM UTC 24
Finished Sep 18 07:53:26 AM UTC 24
Peak memory 225872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665869683 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.665869683
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/2.rv_dm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3941087169
Short name T355
Test name
Test status
Simulation time 366941196 ps
CPU time 5 seconds
Started Sep 18 07:53:23 AM UTC 24
Finished Sep 18 07:53:29 AM UTC 24
Peak memory 232060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=3941087169 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_r
and_reset.3941087169
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_rw.448144479
Short name T131
Test name
Test status
Simulation time 92367002 ps
CPU time 2.16 seconds
Started Sep 18 07:53:23 AM UTC 24
Finished Sep 18 07:53:26 AM UTC 24
Peak memory 232072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448144479 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/r
v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.448144479
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/2.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3786238004
Short name T468
Test name
Test status
Simulation time 27312622394 ps
CPU time 75.56 seconds
Started Sep 18 07:53:22 AM UTC 24
Finished Sep 18 07:54:39 AM UTC 24
Peak memory 215664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786238004 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_aliasing.3786238004
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1703113780
Short name T376
Test name
Test status
Simulation time 25332646662 ps
CPU time 25.57 seconds
Started Sep 18 07:53:22 AM UTC 24
Finished Sep 18 07:53:49 AM UTC 24
Peak memory 215632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703113780 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_bit_bash.1703113780
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2079336346
Short name T141
Test name
Test status
Simulation time 4876842138 ps
CPU time 20.28 seconds
Started Sep 18 07:53:20 AM UTC 24
Finished Sep 18 07:53:42 AM UTC 24
Peak memory 215696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079336346 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_hw_reset.2079336346
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1136697352
Short name T361
Test name
Test status
Simulation time 2915224450 ps
CPU time 10.29 seconds
Started Sep 18 07:53:22 AM UTC 24
Finished Sep 18 07:53:33 AM UTC 24
Peak memory 215524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136697352 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1136697352
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3259869686
Short name T351
Test name
Test status
Simulation time 182401482 ps
CPU time 1.22 seconds
Started Sep 18 07:53:20 AM UTC 24
Finished Sep 18 07:53:23 AM UTC 24
Peak memory 215312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259869686 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_aliasing.3259869686
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.981120613
Short name T381
Test name
Test status
Simulation time 31781283941 ps
CPU time 30.25 seconds
Started Sep 18 07:53:20 AM UTC 24
Finished Sep 18 07:53:52 AM UTC 24
Peak memory 215596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981120613 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_bit_bash.981120613
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3057569365
Short name T346
Test name
Test status
Simulation time 572214651 ps
CPU time 1.77 seconds
Started Sep 18 07:53:18 AM UTC 24
Finished Sep 18 07:53:21 AM UTC 24
Peak memory 215312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057569365 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_hw_reset.3057569365
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.276399061
Short name T347
Test name
Test status
Simulation time 243026635 ps
CPU time 1.34 seconds
Started Sep 18 07:53:19 AM UTC 24
Finished Sep 18 07:53:22 AM UTC 24
Peak memory 215252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276399061 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.276399061
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_partial_access.899768309
Short name T353
Test name
Test status
Simulation time 72588948 ps
CPU time 1.12 seconds
Started Sep 18 07:53:23 AM UTC 24
Finished Sep 18 07:53:25 AM UTC 24
Peak memory 215212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899768309 -assert nopostproc +UVM_
TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_partial_access.899768309
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/2.rv_dm_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_walk.2167632105
Short name T352
Test name
Test status
Simulation time 35207346 ps
CPU time 1.05 seconds
Started Sep 18 07:53:23 AM UTC 24
Finished Sep 18 07:53:25 AM UTC 24
Peak memory 215308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167632105 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.2167632105
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/2.rv_dm_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3296274206
Short name T134
Test name
Test status
Simulation time 2062230746 ps
CPU time 8.47 seconds
Started Sep 18 07:53:23 AM UTC 24
Finished Sep 18 07:53:33 AM UTC 24
Peak memory 215604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296274206 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_csr_outstanding.3296274206
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/2.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.694563370
Short name T109
Test name
Test status
Simulation time 8146765985 ps
CPU time 75.63 seconds
Started Sep 18 07:53:22 AM UTC 24
Finished Sep 18 07:54:39 AM UTC 24
Peak memory 230360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=694563370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.694563370
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_errors.4097433436
Short name T176
Test name
Test status
Simulation time 223694942 ps
CPU time 6.75 seconds
Started Sep 18 07:53:22 AM UTC 24
Finished Sep 18 07:53:30 AM UTC 24
Peak memory 226032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097433436 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.4097433436
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/2.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3046928274
Short name T470
Test name
Test status
Simulation time 8591651740 ps
CPU time 75.53 seconds
Started Sep 18 07:53:23 AM UTC 24
Finished Sep 18 07:54:41 AM UTC 24
Peak memory 215632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046928274 -ass
ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_aliasing.3046928274
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/3.rv_dm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.476368599
Short name T472
Test name
Test status
Simulation time 6745324875 ps
CPU time 70.52 seconds
Started Sep 18 07:53:32 AM UTC 24
Finished Sep 18 07:54:45 AM UTC 24
Peak memory 225940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476368599 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.476368599
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/3.rv_dm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3619911341
Short name T135
Test name
Test status
Simulation time 367677539 ps
CPU time 1.81 seconds
Started Sep 18 07:53:32 AM UTC 24
Finished Sep 18 07:53:35 AM UTC 24
Peak memory 225248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619911341 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.3619911341
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/3.rv_dm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1634112315
Short name T362
Test name
Test status
Simulation time 111645066 ps
CPU time 2.6 seconds
Started Sep 18 07:53:32 AM UTC 24
Finished Sep 18 07:53:36 AM UTC 24
Peak memory 226128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=1634112315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_r
and_reset.1634112315
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_rw.3929389515
Short name T149
Test name
Test status
Simulation time 127933730 ps
CPU time 3.38 seconds
Started Sep 18 07:53:32 AM UTC 24
Finished Sep 18 07:53:37 AM UTC 24
Peak memory 225812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929389515 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.3929389515
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/3.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3412324398
Short name T385
Test name
Test status
Simulation time 34945759198 ps
CPU time 25.93 seconds
Started Sep 18 07:53:29 AM UTC 24
Finished Sep 18 07:53:56 AM UTC 24
Peak memory 215600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412324398 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_aliasing.3412324398
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1679213247
Short name T430
Test name
Test status
Simulation time 23516533688 ps
CPU time 48.73 seconds
Started Sep 18 07:53:29 AM UTC 24
Finished Sep 18 07:54:19 AM UTC 24
Peak memory 215532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679213247 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_bit_bash.1679213247
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.980685544
Short name T142
Test name
Test status
Simulation time 13706918042 ps
CPU time 35.47 seconds
Started Sep 18 07:53:28 AM UTC 24
Finished Sep 18 07:54:04 AM UTC 24
Peak memory 215728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980685544 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_hw_reset.980685544
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2926813269
Short name T357
Test name
Test status
Simulation time 1395411073 ps
CPU time 2.92 seconds
Started Sep 18 07:53:28 AM UTC 24
Finished Sep 18 07:53:32 AM UTC 24
Peak memory 215596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926813269 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.2926813269
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1559746002
Short name T359
Test name
Test status
Simulation time 1269923413 ps
CPU time 3.53 seconds
Started Sep 18 07:53:28 AM UTC 24
Finished Sep 18 07:53:32 AM UTC 24
Peak memory 215384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559746002 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_aliasing.1559746002
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3249475516
Short name T440
Test name
Test status
Simulation time 15554785435 ps
CPU time 53.23 seconds
Started Sep 18 07:53:27 AM UTC 24
Finished Sep 18 07:54:22 AM UTC 24
Peak memory 215664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249475516 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_bit_bash.3249475516
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.890877963
Short name T354
Test name
Test status
Simulation time 216017817 ps
CPU time 1.53 seconds
Started Sep 18 07:53:25 AM UTC 24
Finished Sep 18 07:53:28 AM UTC 24
Peak memory 215308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890877963 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_hw_reset.890877963
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1578817845
Short name T356
Test name
Test status
Simulation time 226112635 ps
CPU time 2.09 seconds
Started Sep 18 07:53:26 AM UTC 24
Finished Sep 18 07:53:29 AM UTC 24
Peak memory 215380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578817845 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.1578817845
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_partial_access.4094639618
Short name T360
Test name
Test status
Simulation time 96655807 ps
CPU time 1.39 seconds
Started Sep 18 07:53:30 AM UTC 24
Finished Sep 18 07:53:32 AM UTC 24
Peak memory 215312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094639618 -assert nopostproc +UVM
_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_partial_access.4094639618
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/3.rv_dm_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_walk.1678659172
Short name T358
Test name
Test status
Simulation time 76296337 ps
CPU time 1.08 seconds
Started Sep 18 07:53:30 AM UTC 24
Finished Sep 18 07:53:32 AM UTC 24
Peak memory 215308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678659172 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.1678659172
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/3.rv_dm_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1097994325
Short name T167
Test name
Test status
Simulation time 548904691 ps
CPU time 6.47 seconds
Started Sep 18 07:53:32 AM UTC 24
Finished Sep 18 07:53:40 AM UTC 24
Peak memory 215476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097994325 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_csr_outstanding.1097994325
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/3.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.216165157
Short name T104
Test name
Test status
Simulation time 15935020795 ps
CPU time 54.92 seconds
Started Sep 18 07:53:30 AM UTC 24
Finished Sep 18 07:54:26 AM UTC 24
Peak memory 230232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=216165157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.216165157
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_errors.2771733591
Short name T177
Test name
Test status
Simulation time 202893140 ps
CPU time 3.48 seconds
Started Sep 18 07:53:30 AM UTC 24
Finished Sep 18 07:53:34 AM UTC 24
Peak memory 225964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771733591 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.2771733591
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/3.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2113539969
Short name T227
Test name
Test status
Simulation time 2020275679 ps
CPU time 12.08 seconds
Started Sep 18 07:53:30 AM UTC 24
Finished Sep 18 07:53:43 AM UTC 24
Peak memory 227984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113539969 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.2113539969
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/3.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2389828744
Short name T164
Test name
Test status
Simulation time 6940537415 ps
CPU time 28.77 seconds
Started Sep 18 07:53:34 AM UTC 24
Finished Sep 18 07:54:04 AM UTC 24
Peak memory 215704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389828744 -ass
ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_aliasing.2389828744
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/4.rv_dm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.334745868
Short name T460
Test name
Test status
Simulation time 7046133412 ps
CPU time 51.55 seconds
Started Sep 18 07:53:38 AM UTC 24
Finished Sep 18 07:54:31 AM UTC 24
Peak memory 225888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334745868 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.334745868
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/4.rv_dm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.786444924
Short name T174
Test name
Test status
Simulation time 151191708 ps
CPU time 2.81 seconds
Started Sep 18 07:53:37 AM UTC 24
Finished Sep 18 07:53:41 AM UTC 24
Peak memory 225872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786444924 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.786444924
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/4.rv_dm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3938606813
Short name T371
Test name
Test status
Simulation time 108949970 ps
CPU time 2.72 seconds
Started Sep 18 07:53:39 AM UTC 24
Finished Sep 18 07:53:42 AM UTC 24
Peak memory 227964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=3938606813 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_r
and_reset.3938606813
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_rw.3168808517
Short name T158
Test name
Test status
Simulation time 102047886 ps
CPU time 2.08 seconds
Started Sep 18 07:53:38 AM UTC 24
Finished Sep 18 07:53:41 AM UTC 24
Peak memory 225928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168808517 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.3168808517
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/4.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3168122381
Short name T454
Test name
Test status
Simulation time 17695617756 ps
CPU time 52.6 seconds
Started Sep 18 07:53:35 AM UTC 24
Finished Sep 18 07:54:29 AM UTC 24
Peak memory 215660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168122381 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_aliasing.3168122381
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3235924854
Short name T410
Test name
Test status
Simulation time 25601071468 ps
CPU time 33.69 seconds
Started Sep 18 07:53:35 AM UTC 24
Finished Sep 18 07:54:10 AM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235924854 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_bit_bash.3235924854
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2505550594
Short name T140
Test name
Test status
Simulation time 15606372717 ps
CPU time 4.23 seconds
Started Sep 18 07:53:34 AM UTC 24
Finished Sep 18 07:53:39 AM UTC 24
Peak memory 215596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505550594 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_hw_reset.2505550594
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2111170944
Short name T379
Test name
Test status
Simulation time 3334594410 ps
CPU time 14.64 seconds
Started Sep 18 07:53:35 AM UTC 24
Finished Sep 18 07:53:51 AM UTC 24
Peak memory 215596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111170944 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.2111170944
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3846148082
Short name T366
Test name
Test status
Simulation time 494708428 ps
CPU time 2.43 seconds
Started Sep 18 07:53:34 AM UTC 24
Finished Sep 18 07:53:37 AM UTC 24
Peak memory 215384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846148082 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_aliasing.3846148082
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3798727296
Short name T365
Test name
Test status
Simulation time 11536306963 ps
CPU time 10.42 seconds
Started Sep 18 07:53:34 AM UTC 24
Finished Sep 18 07:53:45 AM UTC 24
Peak memory 215664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798727296 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_bit_bash.3798727296
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2651551498
Short name T363
Test name
Test status
Simulation time 617631208 ps
CPU time 1.53 seconds
Started Sep 18 07:53:34 AM UTC 24
Finished Sep 18 07:53:36 AM UTC 24
Peak memory 215312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651551498 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_hw_reset.2651551498
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.300450032
Short name T364
Test name
Test status
Simulation time 715094119 ps
CPU time 1.93 seconds
Started Sep 18 07:53:34 AM UTC 24
Finished Sep 18 07:53:37 AM UTC 24
Peak memory 215252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300450032 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.300450032
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_partial_access.824924788
Short name T368
Test name
Test status
Simulation time 39680618 ps
CPU time 1.04 seconds
Started Sep 18 07:53:37 AM UTC 24
Finished Sep 18 07:53:39 AM UTC 24
Peak memory 215312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824924788 -assert nopostproc +UVM_
TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_partial_access.824924788
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/4.rv_dm_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_walk.1485586699
Short name T367
Test name
Test status
Simulation time 71517549 ps
CPU time 0.76 seconds
Started Sep 18 07:53:36 AM UTC 24
Finished Sep 18 07:53:38 AM UTC 24
Peak memory 215308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485586699 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.1485586699
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/4.rv_dm_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2363604866
Short name T168
Test name
Test status
Simulation time 189662292 ps
CPU time 5.61 seconds
Started Sep 18 07:53:39 AM UTC 24
Finished Sep 18 07:53:45 AM UTC 24
Peak memory 215276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363604866 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_csr_outstanding.2363604866
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/4.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_errors.1959463032
Short name T370
Test name
Test status
Simulation time 164360180 ps
CPU time 4.74 seconds
Started Sep 18 07:53:36 AM UTC 24
Finished Sep 18 07:53:42 AM UTC 24
Peak memory 225840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959463032 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.1959463032
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/4.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2623912614
Short name T226
Test name
Test status
Simulation time 2975813282 ps
CPU time 18.23 seconds
Started Sep 18 07:53:36 AM UTC 24
Finished Sep 18 07:53:56 AM UTC 24
Peak memory 232732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623912614 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.2623912614
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/4.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2373297597
Short name T113
Test name
Test status
Simulation time 84676119 ps
CPU time 3.56 seconds
Started Sep 18 07:53:42 AM UTC 24
Finished Sep 18 07:53:47 AM UTC 24
Peak memory 230228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=2373297597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_r
and_reset.2373297597
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_rw.875115172
Short name T373
Test name
Test status
Simulation time 689135267 ps
CPU time 3.1 seconds
Started Sep 18 07:53:41 AM UTC 24
Finished Sep 18 07:53:45 AM UTC 24
Peak memory 225792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875115172 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/r
v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.875115172
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/5.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.593069406
Short name T383
Test name
Test status
Simulation time 4477026233 ps
CPU time 13.73 seconds
Started Sep 18 07:53:40 AM UTC 24
Finished Sep 18 07:53:55 AM UTC 24
Peak memory 215604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593069406 -assert nopostpro
c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_bit_bash.593069406
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2211821293
Short name T372
Test name
Test status
Simulation time 2267199235 ps
CPU time 3.33 seconds
Started Sep 18 07:53:40 AM UTC 24
Finished Sep 18 07:53:44 AM UTC 24
Peak memory 215596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211821293 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.2211821293
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3857471771
Short name T369
Test name
Test status
Simulation time 454365882 ps
CPU time 1.47 seconds
Started Sep 18 07:53:39 AM UTC 24
Finished Sep 18 07:53:41 AM UTC 24
Peak memory 215068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857471771 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.3857471771
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3778432629
Short name T169
Test name
Test status
Simulation time 243152147 ps
CPU time 7.55 seconds
Started Sep 18 07:53:42 AM UTC 24
Finished Sep 18 07:53:51 AM UTC 24
Peak memory 215608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778432629 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_csr_outstanding.3778432629
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/5.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_errors.1232983635
Short name T375
Test name
Test status
Simulation time 270172469 ps
CPU time 6.09 seconds
Started Sep 18 07:53:41 AM UTC 24
Finished Sep 18 07:53:48 AM UTC 24
Peak memory 225836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232983635 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.1232983635
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/5.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_intg_err.89401463
Short name T233
Test name
Test status
Simulation time 1623304787 ps
CPU time 16.13 seconds
Started Sep 18 07:53:41 AM UTC 24
Finished Sep 18 07:53:58 AM UTC 24
Peak memory 228028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89401463 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.89401463
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/5.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3115263663
Short name T378
Test name
Test status
Simulation time 164734051 ps
CPU time 3.33 seconds
Started Sep 18 07:53:46 AM UTC 24
Finished Sep 18 07:53:50 AM UTC 24
Peak memory 225916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=3115263663 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_r
and_reset.3115263663
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_rw.3555946505
Short name T159
Test name
Test status
Simulation time 156016367 ps
CPU time 1.89 seconds
Started Sep 18 07:53:45 AM UTC 24
Finished Sep 18 07:53:48 AM UTC 24
Peak memory 225424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555946505 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.3555946505
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/6.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3745264332
Short name T414
Test name
Test status
Simulation time 15448223786 ps
CPU time 28.14 seconds
Started Sep 18 07:53:43 AM UTC 24
Finished Sep 18 07:54:12 AM UTC 24
Peak memory 215756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745264332 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_bit_bash.3745264332
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2028422208
Short name T382
Test name
Test status
Simulation time 12773334526 ps
CPU time 10.6 seconds
Started Sep 18 07:53:42 AM UTC 24
Finished Sep 18 07:53:54 AM UTC 24
Peak memory 215724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028422208 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.2028422208
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.698187673
Short name T341
Test name
Test status
Simulation time 401811251 ps
CPU time 1.4 seconds
Started Sep 18 07:53:42 AM UTC 24
Finished Sep 18 07:53:45 AM UTC 24
Peak memory 215252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698187673 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.698187673
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2224946124
Short name T170
Test name
Test status
Simulation time 402193554 ps
CPU time 7.88 seconds
Started Sep 18 07:53:45 AM UTC 24
Finished Sep 18 07:53:54 AM UTC 24
Peak memory 215548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224946124 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_csr_outstanding.2224946124
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/6.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_errors.2516789568
Short name T374
Test name
Test status
Simulation time 130249378 ps
CPU time 2.67 seconds
Started Sep 18 07:53:44 AM UTC 24
Finished Sep 18 07:53:47 AM UTC 24
Peak memory 225896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516789568 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.2516789568
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/6.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3445336914
Short name T399
Test name
Test status
Simulation time 2770714464 ps
CPU time 19.82 seconds
Started Sep 18 07:53:44 AM UTC 24
Finished Sep 18 07:54:05 AM UTC 24
Peak memory 232724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445336914 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.3445336914
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/6.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3180940785
Short name T105
Test name
Test status
Simulation time 236145166 ps
CPU time 5.01 seconds
Started Sep 18 07:53:50 AM UTC 24
Finished Sep 18 07:53:56 AM UTC 24
Peak memory 232256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=3180940785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_r
and_reset.3180940785
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_rw.3033480578
Short name T160
Test name
Test status
Simulation time 77189204 ps
CPU time 2.74 seconds
Started Sep 18 07:53:49 AM UTC 24
Finished Sep 18 07:53:53 AM UTC 24
Peak memory 225760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033480578 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.3033480578
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/7.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1745313026
Short name T392
Test name
Test status
Simulation time 10267295641 ps
CPU time 14.39 seconds
Started Sep 18 07:53:46 AM UTC 24
Finished Sep 18 07:54:02 AM UTC 24
Peak memory 215604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745313026 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_bit_bash.1745313026
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1370556333
Short name T388
Test name
Test status
Simulation time 5944569548 ps
CPU time 11.3 seconds
Started Sep 18 07:53:46 AM UTC 24
Finished Sep 18 07:53:59 AM UTC 24
Peak memory 215600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370556333 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.1370556333
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2802198986
Short name T377
Test name
Test status
Simulation time 547751137 ps
CPU time 1.7 seconds
Started Sep 18 07:53:46 AM UTC 24
Finished Sep 18 07:53:49 AM UTC 24
Peak memory 215308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802198986 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.2802198986
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.909283199
Short name T151
Test name
Test status
Simulation time 351424774 ps
CPU time 6.19 seconds
Started Sep 18 07:53:50 AM UTC 24
Finished Sep 18 07:53:57 AM UTC 24
Peak memory 215604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909283199 -assert nopostproc +UV
M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_csr_outstanding.909283199
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/7.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_errors.196115098
Short name T380
Test name
Test status
Simulation time 117888172 ps
CPU time 2.62 seconds
Started Sep 18 07:53:48 AM UTC 24
Finished Sep 18 07:53:52 AM UTC 24
Peak memory 225964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196115098 -assert nopostproc +UVM_TESTNAME=rv_dm_base
_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_d
m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.196115098
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/7.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3828177184
Short name T234
Test name
Test status
Simulation time 2395190816 ps
CPU time 21.3 seconds
Started Sep 18 07:53:48 AM UTC 24
Finished Sep 18 07:54:11 AM UTC 24
Peak memory 228080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828177184 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.3828177184
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/7.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2065187539
Short name T389
Test name
Test status
Simulation time 81024659 ps
CPU time 2.85 seconds
Started Sep 18 07:53:55 AM UTC 24
Finished Sep 18 07:53:59 AM UTC 24
Peak memory 230204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=2065187539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_r
and_reset.2065187539
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_rw.1413106143
Short name T162
Test name
Test status
Simulation time 247586184 ps
CPU time 3.43 seconds
Started Sep 18 07:53:54 AM UTC 24
Finished Sep 18 07:53:58 AM UTC 24
Peak memory 225836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413106143 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.1413106143
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/8.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.28650792
Short name T446
Test name
Test status
Simulation time 8480451798 ps
CPU time 31.57 seconds
Started Sep 18 07:53:52 AM UTC 24
Finished Sep 18 07:54:25 AM UTC 24
Peak memory 215524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28650792 -assert nopostproc
+UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_bit_bash.28650792
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1386725148
Short name T439
Test name
Test status
Simulation time 7717678784 ps
CPU time 29.23 seconds
Started Sep 18 07:53:52 AM UTC 24
Finished Sep 18 07:54:22 AM UTC 24
Peak memory 215748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386725148 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.1386725148
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3860177425
Short name T384
Test name
Test status
Simulation time 688508172 ps
CPU time 2.1 seconds
Started Sep 18 07:53:52 AM UTC 24
Finished Sep 18 07:53:55 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860177425 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.3860177425
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2289846949
Short name T171
Test name
Test status
Simulation time 181781920 ps
CPU time 4.58 seconds
Started Sep 18 07:53:55 AM UTC 24
Finished Sep 18 07:54:01 AM UTC 24
Peak memory 215544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289846949 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_csr_outstanding.2289846949
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/8.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.2184610506
Short name T461
Test name
Test status
Simulation time 1917268779 ps
CPU time 36.55 seconds
Started Sep 18 07:53:53 AM UTC 24
Finished Sep 18 07:54:31 AM UTC 24
Peak memory 228024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2184610506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_re
set.2184610506
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_errors.547569001
Short name T386
Test name
Test status
Simulation time 124371431 ps
CPU time 3.47 seconds
Started Sep 18 07:53:53 AM UTC 24
Finished Sep 18 07:53:57 AM UTC 24
Peak memory 226116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547569001 -assert nopostproc +UVM_TESTNAME=rv_dm_base
_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_d
m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.547569001
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/8.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3867749373
Short name T228
Test name
Test status
Simulation time 6230950491 ps
CPU time 14.67 seconds
Started Sep 18 07:53:54 AM UTC 24
Finished Sep 18 07:54:10 AM UTC 24
Peak memory 232244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867749373 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.3867749373
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/8.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.4186626389
Short name T397
Test name
Test status
Simulation time 116981630 ps
CPU time 4.14 seconds
Started Sep 18 07:53:59 AM UTC 24
Finished Sep 18 07:54:04 AM UTC 24
Peak memory 230072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=4186626389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_r
and_reset.4186626389
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.1436409230
Short name T409
Test name
Test status
Simulation time 11422375889 ps
CPU time 12.14 seconds
Started Sep 18 07:53:56 AM UTC 24
Finished Sep 18 07:54:10 AM UTC 24
Peak memory 215352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436409230 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_bit_bash.1436409230
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.834643644
Short name T394
Test name
Test status
Simulation time 5243295460 ps
CPU time 6.14 seconds
Started Sep 18 07:53:55 AM UTC 24
Finished Sep 18 07:54:02 AM UTC 24
Peak memory 215608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834643644 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.834643644
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2147613213
Short name T387
Test name
Test status
Simulation time 1125663892 ps
CPU time 1.65 seconds
Started Sep 18 07:53:55 AM UTC 24
Finished Sep 18 07:53:58 AM UTC 24
Peak memory 215308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147613213 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.2147613213
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3386992776
Short name T172
Test name
Test status
Simulation time 484858344 ps
CPU time 3.99 seconds
Started Sep 18 07:53:58 AM UTC 24
Finished Sep 18 07:54:03 AM UTC 24
Peak memory 215604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386992776 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_csr_outstanding.3386992776
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/9.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.4082820329
Short name T474
Test name
Test status
Simulation time 13813029395 ps
CPU time 49.31 seconds
Started Sep 18 07:53:56 AM UTC 24
Finished Sep 18 07:54:47 AM UTC 24
Peak memory 227716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=4082820329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_re
set.4082820329
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_errors.4242173745
Short name T395
Test name
Test status
Simulation time 772621678 ps
CPU time 4.99 seconds
Started Sep 18 07:53:56 AM UTC 24
Finished Sep 18 07:54:02 AM UTC 24
Peak memory 225964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242173745 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.4242173745
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/9.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.1291445038
Short name T58
Test name
Test status
Simulation time 136804139 ps
CPU time 1.3 seconds
Started Sep 18 08:22:07 AM UTC 24
Finished Sep 18 08:22:10 AM UTC 24
Peak memory 215276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291445038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_abstractcmd_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.1291445038
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_abstractcmd_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.1734050337
Short name T43
Test name
Test status
Simulation time 1835200266 ps
CPU time 12.58 seconds
Started Sep 18 08:21:58 AM UTC 24
Finished Sep 18 08:22:12 AM UTC 24
Peak memory 226276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734050337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.1734050337
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_busy.3728957405
Short name T3
Test name
Test status
Simulation time 933469171 ps
CPU time 1.87 seconds
Started Sep 18 08:21:59 AM UTC 24
Finished Sep 18 08:22:02 AM UTC 24
Peak memory 215336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728957405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.3728957405
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_cmderr_busy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.440520133
Short name T14
Test name
Test status
Simulation time 664793772 ps
CPU time 5.07 seconds
Started Sep 18 08:21:59 AM UTC 24
Finished Sep 18 08:22:06 AM UTC 24
Peak memory 215600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440520133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.440520133
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_cmderr_not_supported/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_dataaddr_rw_access.3487033415
Short name T6
Test name
Test status
Simulation time 48835929 ps
CPU time 1.42 seconds
Started Sep 18 08:22:03 AM UTC 24
Finished Sep 18 08:22:07 AM UTC 24
Peak memory 215276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487033415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.3487033415
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_dataaddr_rw_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_debug_disabled.513767001
Short name T87
Test name
Test status
Simulation time 76818809 ps
CPU time 1.49 seconds
Started Sep 18 08:22:08 AM UTC 24
Finished Sep 18 08:22:11 AM UTC 24
Peak memory 236924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513767001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.513767001
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_debug_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.741479487
Short name T117
Test name
Test status
Simulation time 5135857725 ps
CPU time 21.76 seconds
Started Sep 18 08:21:58 AM UTC 24
Finished Sep 18 08:22:21 AM UTC 24
Peak memory 226268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741479487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_tl_access.741479487
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.874534737
Short name T41
Test name
Test status
Simulation time 503052364 ps
CPU time 2.26 seconds
Started Sep 18 08:22:04 AM UTC 24
Finished Sep 18 08:22:08 AM UTC 24
Peak memory 215596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874534737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.874534737
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_halt_resume_whereto/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_hart_unavail.3532849753
Short name T4
Test name
Test status
Simulation time 197297998 ps
CPU time 1.4 seconds
Started Sep 18 08:22:02 AM UTC 24
Finished Sep 18 08:22:06 AM UTC 24
Peak memory 215336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532849753 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.3532849753
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_hart_unavail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_hartsel_warl.1074075957
Short name T26
Test name
Test status
Simulation time 126078063 ps
CPU time 1.31 seconds
Started Sep 18 08:22:10 AM UTC 24
Finished Sep 18 08:22:12 AM UTC 24
Peak memory 215336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074075957 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.1074075957
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_hartsel_warl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.2166614519
Short name T7
Test name
Test status
Simulation time 138151705 ps
CPU time 0.99 seconds
Started Sep 18 08:22:06 AM UTC 24
Finished Sep 18 08:22:08 AM UTC 24
Peak memory 215168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166614519 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.2166614519
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.3729535754
Short name T8
Test name
Test status
Simulation time 490240080 ps
CPU time 1.34 seconds
Started Sep 18 08:22:06 AM UTC 24
Finished Sep 18 08:22:08 AM UTC 24
Peak memory 215280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729535754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.3729535754
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_hard_reset.417842698
Short name T16
Test name
Test status
Simulation time 137926150 ps
CPU time 1.52 seconds
Started Sep 18 08:22:06 AM UTC 24
Finished Sep 18 08:22:09 AM UTC 24
Peak memory 215332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417842698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.417842698
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_idle_hint.1129367775
Short name T24
Test name
Test status
Simulation time 186118014 ps
CPU time 1 seconds
Started Sep 18 08:22:05 AM UTC 24
Finished Sep 18 08:22:07 AM UTC 24
Peak memory 215276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129367775 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.1129367775
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_halted.719500329
Short name T12
Test name
Test status
Simulation time 135996281 ps
CPU time 1.11 seconds
Started Sep 18 08:22:00 AM UTC 24
Finished Sep 18 08:22:02 AM UTC 24
Peak memory 215388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719500329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.719500329
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_halted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_resuming.3076407038
Short name T13
Test name
Test status
Simulation time 680046130 ps
CPU time 2.97 seconds
Started Sep 18 08:22:00 AM UTC 24
Finished Sep 18 08:22:04 AM UTC 24
Peak memory 215608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076407038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.3076407038
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.823704052
Short name T15
Test name
Test status
Simulation time 824219061 ps
CPU time 1.81 seconds
Started Sep 18 08:22:05 AM UTC 24
Finished Sep 18 08:22:08 AM UTC 24
Peak memory 224656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823704052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.823704052
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_ndmreset_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_tl_access.3000620276
Short name T37
Test name
Test status
Simulation time 5612711792 ps
CPU time 12.6 seconds
Started Sep 18 08:21:57 AM UTC 24
Finished Sep 18 08:22:11 AM UTC 24
Peak memory 216228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000620276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.3000620276
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.3042585670
Short name T48
Test name
Test status
Simulation time 660946536 ps
CPU time 3.92 seconds
Started Sep 18 08:22:11 AM UTC 24
Finished Sep 18 08:22:16 AM UTC 24
Peak memory 254408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042585670 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3042585670
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_smoke.999080146
Short name T1
Test name
Test status
Simulation time 638754850 ps
CPU time 3.96 seconds
Started Sep 18 08:21:55 AM UTC 24
Finished Sep 18 08:22:00 AM UTC 24
Peak memory 215584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999080146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.999080146
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.3583080216
Short name T25
Test name
Test status
Simulation time 21550358369 ps
CPU time 57.1 seconds
Started Sep 18 08:22:10 AM UTC 24
Finished Sep 18 08:23:09 AM UTC 24
Peak memory 232948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=3583080216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stres
s_all_with_rand_reset.3583080216
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_abstractcmd_status.1346502919
Short name T60
Test name
Test status
Simulation time 191434207 ps
CPU time 1.57 seconds
Started Sep 18 08:22:17 AM UTC 24
Finished Sep 18 08:22:20 AM UTC 24
Peak memory 215276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346502919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_abstractcmd_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.1346502919
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_abstractcmd_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_alert_test.309431855
Short name T46
Test name
Test status
Simulation time 106742877 ps
CPU time 1.68 seconds
Started Sep 18 08:22:21 AM UTC 24
Finished Sep 18 08:22:24 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309431855 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.309431855
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_autoincr_sba_tl_access.3338849758
Short name T333
Test name
Test status
Simulation time 58195109083 ps
CPU time 114.66 seconds
Started Sep 18 08:22:12 AM UTC 24
Finished Sep 18 08:24:09 AM UTC 24
Peak memory 230620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338849758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.3338849758
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_buffered_enable.1154237928
Short name T82
Test name
Test status
Simulation time 422231731 ps
CPU time 1.28 seconds
Started Sep 18 08:22:19 AM UTC 24
Finished Sep 18 08:22:21 AM UTC 24
Peak memory 244584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154237928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_buffered_enable.1154237928
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_busy.4218526577
Short name T32
Test name
Test status
Simulation time 1160245078 ps
CPU time 4.86 seconds
Started Sep 18 08:22:12 AM UTC 24
Finished Sep 18 08:22:18 AM UTC 24
Peak memory 215796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218526577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.4218526577
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_cmderr_busy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.579521677
Short name T27
Test name
Test status
Simulation time 382063244 ps
CPU time 1.56 seconds
Started Sep 18 08:22:14 AM UTC 24
Finished Sep 18 08:22:17 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579521677 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_cmderr_exception_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.579521677
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_cmderr_exception/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.3690953480
Short name T64
Test name
Test status
Simulation time 115714505 ps
CPU time 1.35 seconds
Started Sep 18 08:22:14 AM UTC 24
Finished Sep 18 08:22:17 AM UTC 24
Peak memory 215276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690953480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.3690953480
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_cmderr_halt_resume/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_not_supported.709110316
Short name T50
Test name
Test status
Simulation time 214093377 ps
CPU time 1.5 seconds
Started Sep 18 08:22:12 AM UTC 24
Finished Sep 18 08:22:15 AM UTC 24
Peak memory 215396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709110316 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.709110316
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_cmderr_not_supported/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_dataaddr_rw_access.383646694
Short name T38
Test name
Test status
Simulation time 57708604 ps
CPU time 1.33 seconds
Started Sep 18 08:22:15 AM UTC 24
Finished Sep 18 08:22:18 AM UTC 24
Peak memory 215392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383646694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_dataaddr_rw_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.383646694
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_dataaddr_rw_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_debug_disabled.988331945
Short name T88
Test name
Test status
Simulation time 58470707 ps
CPU time 1.37 seconds
Started Sep 18 08:22:19 AM UTC 24
Finished Sep 18 08:22:21 AM UTC 24
Peak memory 236808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988331945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.988331945
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_debug_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.1225051302
Short name T79
Test name
Test status
Simulation time 2403376881 ps
CPU time 3.68 seconds
Started Sep 18 08:22:11 AM UTC 24
Finished Sep 18 08:22:16 AM UTC 24
Peak memory 226388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225051302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_tl_access.1225051302
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.1688878106
Short name T74
Test name
Test status
Simulation time 236071738 ps
CPU time 2.13 seconds
Started Sep 18 08:22:19 AM UTC 24
Finished Sep 18 08:22:22 AM UTC 24
Peak memory 215528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688878106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.1688878106
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_dmi_failed_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_halt_resume_whereto.4190149434
Short name T51
Test name
Test status
Simulation time 231279245 ps
CPU time 2.13 seconds
Started Sep 18 08:22:15 AM UTC 24
Finished Sep 18 08:22:19 AM UTC 24
Peak memory 215596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190149434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.4190149434
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_halt_resume_whereto/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_hart_unavail.2882193349
Short name T93
Test name
Test status
Simulation time 117684038 ps
CPU time 1.59 seconds
Started Sep 18 08:22:14 AM UTC 24
Finished Sep 18 08:22:17 AM UTC 24
Peak memory 215336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882193349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.2882193349
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_hart_unavail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.2192247147
Short name T89
Test name
Test status
Simulation time 212539529 ps
CPU time 2.24 seconds
Started Sep 18 08:22:17 AM UTC 24
Finished Sep 18 08:22:21 AM UTC 24
Peak memory 215604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192247147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.2192247147
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.89391562
Short name T180
Test name
Test status
Simulation time 325591639 ps
CPU time 1.92 seconds
Started Sep 18 08:22:17 AM UTC 24
Finished Sep 18 08:22:21 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89391562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv
_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.89391562
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_hard_reset.557052506
Short name T76
Test name
Test status
Simulation time 429896728 ps
CPU time 3.19 seconds
Started Sep 18 08:22:17 AM UTC 24
Finished Sep 18 08:22:22 AM UTC 24
Peak memory 215528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557052506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.557052506
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_idle_hint.2771100128
Short name T97
Test name
Test status
Simulation time 653962644 ps
CPU time 5.31 seconds
Started Sep 18 08:22:17 AM UTC 24
Finished Sep 18 08:22:24 AM UTC 24
Peak memory 215536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771100128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.2771100128
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_halted.2194342901
Short name T94
Test name
Test status
Simulation time 471807900 ps
CPU time 2.22 seconds
Started Sep 18 08:22:14 AM UTC 24
Finished Sep 18 08:22:17 AM UTC 24
Peak memory 215540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194342901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.2194342901
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_mem_tl_access_halted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_resuming.4090278561
Short name T92
Test name
Test status
Simulation time 182644158 ps
CPU time 1.16 seconds
Started Sep 18 08:22:14 AM UTC 24
Finished Sep 18 08:22:16 AM UTC 24
Peak memory 215276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090278561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.4090278561
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_progbuf_read_write_execute.650124107
Short name T57
Test name
Test status
Simulation time 1035168518 ps
CPU time 3.11 seconds
Started Sep 18 08:22:18 AM UTC 24
Finished Sep 18 08:22:22 AM UTC 24
Peak memory 215532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650124107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_progbuf_read_write_execute_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.650124107
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_rom_read_access.2415620095
Short name T62
Test name
Test status
Simulation time 93297549 ps
CPU time 1.42 seconds
Started Sep 18 08:22:18 AM UTC 24
Finished Sep 18 08:22:20 AM UTC 24
Peak memory 225140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415620095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_rom_read_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.2415620095
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_rom_read_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_debug_disabled.2011927674
Short name T95
Test name
Test status
Simulation time 3133714994 ps
CPU time 5.44 seconds
Started Sep 18 08:22:16 AM UTC 24
Finished Sep 18 08:22:22 AM UTC 24
Peak memory 216260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011927674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.2011927674
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_sba_debug_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_tl_access.2738323609
Short name T96
Test name
Test status
Simulation time 2078358526 ps
CPU time 10.24 seconds
Started Sep 18 08:22:11 AM UTC 24
Finished Sep 18 08:22:23 AM UTC 24
Peak memory 216028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738323609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.2738323609
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_sec_cm.518497424
Short name T84
Test name
Test status
Simulation time 508405831 ps
CPU time 3.52 seconds
Started Sep 18 08:22:21 AM UTC 24
Finished Sep 18 08:22:26 AM UTC 24
Peak memory 256128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518497424 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.518497424
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_smoke.2760216350
Short name T86
Test name
Test status
Simulation time 1269337134 ps
CPU time 3.98 seconds
Started Sep 18 08:22:11 AM UTC 24
Finished Sep 18 08:22:16 AM UTC 24
Peak memory 215388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760216350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.2760216350
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.1453599850
Short name T40
Test name
Test status
Simulation time 2690364599 ps
CPU time 7.7 seconds
Started Sep 18 08:22:20 AM UTC 24
Finished Sep 18 08:22:29 AM UTC 24
Peak memory 226172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453599850 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.1453599850
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/1.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/10.rv_dm_alert_test.949887734
Short name T122
Test name
Test status
Simulation time 109072872 ps
CPU time 1.08 seconds
Started Sep 18 08:23:02 AM UTC 24
Finished Sep 18 08:23:04 AM UTC 24
Peak memory 215208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949887734 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.949887734
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/10.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/10.rv_dm_autoincr_sba_tl_access.1773337158
Short name T265
Test name
Test status
Simulation time 12441303629 ps
CPU time 14 seconds
Started Sep 18 08:23:01 AM UTC 24
Finished Sep 18 08:23:16 AM UTC 24
Peak memory 233180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773337158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.1773337158
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/10.rv_dm_bad_sba_tl_access.37838061
Short name T124
Test name
Test status
Simulation time 2996535225 ps
CPU time 4.17 seconds
Started Sep 18 08:23:00 AM UTC 24
Finished Sep 18 08:23:05 AM UTC 24
Peak memory 226596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37838061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv
_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.37838061
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/10.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.1433358727
Short name T268
Test name
Test status
Simulation time 4126286049 ps
CPU time 16.5 seconds
Started Sep 18 08:23:00 AM UTC 24
Finished Sep 18 08:23:17 AM UTC 24
Peak memory 216060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433358727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_tl_access.1433358727
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/10.rv_dm_sba_tl_access.3803189421
Short name T272
Test name
Test status
Simulation time 6464002558 ps
CPU time 23.42 seconds
Started Sep 18 08:23:00 AM UTC 24
Finished Sep 18 08:23:24 AM UTC 24
Peak memory 216072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803189421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.3803189421
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/10.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/11.rv_dm_alert_test.1003095574
Short name T244
Test name
Test status
Simulation time 67048880 ps
CPU time 1.11 seconds
Started Sep 18 08:23:06 AM UTC 24
Finished Sep 18 08:23:08 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003095574 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.1003095574
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/11.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/11.rv_dm_autoincr_sba_tl_access.1572168505
Short name T328
Test name
Test status
Simulation time 20777304512 ps
CPU time 47.01 seconds
Started Sep 18 08:23:06 AM UTC 24
Finished Sep 18 08:23:54 AM UTC 24
Peak memory 226408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572168505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.1572168505
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/11.rv_dm_bad_sba_tl_access.3410656400
Short name T290
Test name
Test status
Simulation time 6306532825 ps
CPU time 26.87 seconds
Started Sep 18 08:23:04 AM UTC 24
Finished Sep 18 08:23:32 AM UTC 24
Peak memory 226460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410656400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.3410656400
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/11.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.2366620344
Short name T263
Test name
Test status
Simulation time 3593229543 ps
CPU time 8.24 seconds
Started Sep 18 08:23:04 AM UTC 24
Finished Sep 18 08:23:13 AM UTC 24
Peak memory 216156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366620344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_tl_access.2366620344
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/11.rv_dm_sba_tl_access.1516798605
Short name T257
Test name
Test status
Simulation time 1180528675 ps
CPU time 4.95 seconds
Started Sep 18 08:23:04 AM UTC 24
Finished Sep 18 08:23:10 AM UTC 24
Peak memory 215968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516798605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.1516798605
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/11.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/11.rv_dm_stress_all.724261293
Short name T36
Test name
Test status
Simulation time 3240069144 ps
CPU time 5.03 seconds
Started Sep 18 08:23:06 AM UTC 24
Finished Sep 18 08:23:12 AM UTC 24
Peak memory 216024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724261293 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.724261293
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/11.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/12.rv_dm_alert_test.3220023811
Short name T254
Test name
Test status
Simulation time 42418687 ps
CPU time 1.01 seconds
Started Sep 18 08:23:07 AM UTC 24
Finished Sep 18 08:23:09 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220023811 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.3220023811
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/12.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/12.rv_dm_autoincr_sba_tl_access.1364197906
Short name T334
Test name
Test status
Simulation time 55005796140 ps
CPU time 69.45 seconds
Started Sep 18 08:23:07 AM UTC 24
Finished Sep 18 08:24:18 AM UTC 24
Peak memory 226524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364197906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.1364197906
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/12.rv_dm_bad_sba_tl_access.1895022672
Short name T255
Test name
Test status
Simulation time 1405533898 ps
CPU time 2.41 seconds
Started Sep 18 08:23:06 AM UTC 24
Finished Sep 18 08:23:09 AM UTC 24
Peak memory 216032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895022672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.1895022672
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/12.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.3158000888
Short name T258
Test name
Test status
Simulation time 1495987908 ps
CPU time 3.63 seconds
Started Sep 18 08:23:06 AM UTC 24
Finished Sep 18 08:23:10 AM UTC 24
Peak memory 216216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158000888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_tl_access.3158000888
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/12.rv_dm_sba_tl_access.3828159201
Short name T259
Test name
Test status
Simulation time 2295495894 ps
CPU time 3.93 seconds
Started Sep 18 08:23:06 AM UTC 24
Finished Sep 18 08:23:11 AM UTC 24
Peak memory 216176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828159201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.3828159201
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/12.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/13.rv_dm_alert_test.3065201410
Short name T260
Test name
Test status
Simulation time 54603220 ps
CPU time 1.21 seconds
Started Sep 18 08:23:10 AM UTC 24
Finished Sep 18 08:23:12 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065201410 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.3065201410
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/13.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/13.rv_dm_autoincr_sba_tl_access.928418534
Short name T185
Test name
Test status
Simulation time 2037952365 ps
CPU time 5.67 seconds
Started Sep 18 08:23:10 AM UTC 24
Finished Sep 18 08:23:16 AM UTC 24
Peak memory 226528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928418534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.928418534
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/13.rv_dm_bad_sba_tl_access.1895370619
Short name T188
Test name
Test status
Simulation time 13554760452 ps
CPU time 6.7 seconds
Started Sep 18 08:23:10 AM UTC 24
Finished Sep 18 08:23:17 AM UTC 24
Peak memory 226324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895370619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.1895370619
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/13.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.2416536280
Short name T261
Test name
Test status
Simulation time 2845005741 ps
CPU time 2.94 seconds
Started Sep 18 08:23:08 AM UTC 24
Finished Sep 18 08:23:12 AM UTC 24
Peak memory 216352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416536280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_tl_access.2416536280
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/13.rv_dm_sba_tl_access.2092440195
Short name T200
Test name
Test status
Simulation time 10533584476 ps
CPU time 26.66 seconds
Started Sep 18 08:23:07 AM UTC 24
Finished Sep 18 08:23:35 AM UTC 24
Peak memory 216092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092440195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.2092440195
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/13.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/13.rv_dm_stress_all.4074677745
Short name T211
Test name
Test status
Simulation time 3071192594 ps
CPU time 16.04 seconds
Started Sep 18 08:23:10 AM UTC 24
Finished Sep 18 08:23:27 AM UTC 24
Peak memory 215912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074677745 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.4074677745
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/13.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/14.rv_dm_alert_test.3819008951
Short name T262
Test name
Test status
Simulation time 61042449 ps
CPU time 1.15 seconds
Started Sep 18 08:23:11 AM UTC 24
Finished Sep 18 08:23:13 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819008951 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.3819008951
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/14.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.546061849
Short name T270
Test name
Test status
Simulation time 4770502943 ps
CPU time 9.66 seconds
Started Sep 18 08:23:11 AM UTC 24
Finished Sep 18 08:23:22 AM UTC 24
Peak memory 216084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546061849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_tl_access.546061849
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/14.rv_dm_sba_tl_access.4280371289
Short name T264
Test name
Test status
Simulation time 3630393355 ps
CPU time 4.46 seconds
Started Sep 18 08:23:10 AM UTC 24
Finished Sep 18 08:23:15 AM UTC 24
Peak memory 216168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280371289 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.4280371289
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/14.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/14.rv_dm_stress_all.1661462178
Short name T66
Test name
Test status
Simulation time 1846317205 ps
CPU time 7.58 seconds
Started Sep 18 08:23:11 AM UTC 24
Finished Sep 18 08:23:20 AM UTC 24
Peak memory 215860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661462178 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.1661462178
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/14.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/15.rv_dm_alert_test.2157241561
Short name T267
Test name
Test status
Simulation time 110391472 ps
CPU time 1.35 seconds
Started Sep 18 08:23:15 AM UTC 24
Finished Sep 18 08:23:17 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157241561 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.2157241561
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/15.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/15.rv_dm_bad_sba_tl_access.1846265227
Short name T269
Test name
Test status
Simulation time 1732179388 ps
CPU time 6.62 seconds
Started Sep 18 08:23:14 AM UTC 24
Finished Sep 18 08:23:21 AM UTC 24
Peak memory 215964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846265227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.1846265227
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/15.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.1399566575
Short name T286
Test name
Test status
Simulation time 3798073597 ps
CPU time 17.37 seconds
Started Sep 18 08:23:12 AM UTC 24
Finished Sep 18 08:23:31 AM UTC 24
Peak memory 216276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399566575 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_tl_access.1399566575
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/15.rv_dm_sba_tl_access.3617729425
Short name T308
Test name
Test status
Simulation time 4689919719 ps
CPU time 26.02 seconds
Started Sep 18 08:23:12 AM UTC 24
Finished Sep 18 08:23:40 AM UTC 24
Peak memory 216164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617729425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.3617729425
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/15.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/15.rv_dm_stress_all.3644253677
Short name T11
Test name
Test status
Simulation time 6821034738 ps
CPU time 15.47 seconds
Started Sep 18 08:23:15 AM UTC 24
Finished Sep 18 08:23:31 AM UTC 24
Peak memory 215928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644253677 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.3644253677
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/15.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/16.rv_dm_alert_test.2128946644
Short name T239
Test name
Test status
Simulation time 268031927 ps
CPU time 0.85 seconds
Started Sep 18 08:23:17 AM UTC 24
Finished Sep 18 08:23:19 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128946644 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.2128946644
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/16.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/16.rv_dm_autoincr_sba_tl_access.1064586821
Short name T311
Test name
Test status
Simulation time 6660779251 ps
CPU time 22.4 seconds
Started Sep 18 08:23:17 AM UTC 24
Finished Sep 18 08:23:41 AM UTC 24
Peak memory 226408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064586821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.1064586821
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/16.rv_dm_bad_sba_tl_access.2668510854
Short name T310
Test name
Test status
Simulation time 7443695887 ps
CPU time 22.25 seconds
Started Sep 18 08:23:17 AM UTC 24
Finished Sep 18 08:23:41 AM UTC 24
Peak memory 226344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668510854 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.2668510854
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/16.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.3502142892
Short name T282
Test name
Test status
Simulation time 3279541152 ps
CPU time 12.68 seconds
Started Sep 18 08:23:16 AM UTC 24
Finished Sep 18 08:23:30 AM UTC 24
Peak memory 216012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502142892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_tl_access.3502142892
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/16.rv_dm_sba_tl_access.1270548068
Short name T276
Test name
Test status
Simulation time 6402394134 ps
CPU time 9.7 seconds
Started Sep 18 08:23:15 AM UTC 24
Finished Sep 18 08:23:26 AM UTC 24
Peak memory 226600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270548068 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.1270548068
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/16.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/16.rv_dm_stress_all.1472759742
Short name T219
Test name
Test status
Simulation time 6696827321 ps
CPU time 5.83 seconds
Started Sep 18 08:23:17 AM UTC 24
Finished Sep 18 08:23:24 AM UTC 24
Peak memory 226296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472759742 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.1472759742
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/16.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/17.rv_dm_alert_test.1766438167
Short name T271
Test name
Test status
Simulation time 62242766 ps
CPU time 1.21 seconds
Started Sep 18 08:23:20 AM UTC 24
Finished Sep 18 08:23:22 AM UTC 24
Peak memory 215328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766438167 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.1766438167
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/17.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/17.rv_dm_autoincr_sba_tl_access.2480147126
Short name T196
Test name
Test status
Simulation time 2171712043 ps
CPU time 3.58 seconds
Started Sep 18 08:23:19 AM UTC 24
Finished Sep 18 08:23:23 AM UTC 24
Peak memory 216160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480147126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.2480147126
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/17.rv_dm_bad_sba_tl_access.871740796
Short name T274
Test name
Test status
Simulation time 3124433223 ps
CPU time 5.54 seconds
Started Sep 18 08:23:19 AM UTC 24
Finished Sep 18 08:23:25 AM UTC 24
Peak memory 216348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871740796 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.871740796
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/17.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.3671958679
Short name T280
Test name
Test status
Simulation time 6702396434 ps
CPU time 9.26 seconds
Started Sep 18 08:23:19 AM UTC 24
Finished Sep 18 08:23:29 AM UTC 24
Peak memory 216352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671958679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_tl_access.3671958679
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/17.rv_dm_sba_tl_access.824836730
Short name T288
Test name
Test status
Simulation time 3155806099 ps
CPU time 12.37 seconds
Started Sep 18 08:23:19 AM UTC 24
Finished Sep 18 08:23:32 AM UTC 24
Peak memory 216092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824836730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.824836730
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/17.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/17.rv_dm_stress_all.514813464
Short name T218
Test name
Test status
Simulation time 602218091 ps
CPU time 2.29 seconds
Started Sep 18 08:23:19 AM UTC 24
Finished Sep 18 08:23:22 AM UTC 24
Peak memory 225976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514813464 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.514813464
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/17.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/18.rv_dm_alert_test.3171243965
Short name T273
Test name
Test status
Simulation time 51654182 ps
CPU time 1.01 seconds
Started Sep 18 08:23:22 AM UTC 24
Finished Sep 18 08:23:24 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171243965 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.3171243965
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/18.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/18.rv_dm_autoincr_sba_tl_access.50634184
Short name T327
Test name
Test status
Simulation time 13741726147 ps
CPU time 30.71 seconds
Started Sep 18 08:23:21 AM UTC 24
Finished Sep 18 08:23:53 AM UTC 24
Peak memory 226512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50634184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv
_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.50634184
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/18.rv_dm_bad_sba_tl_access.4095143935
Short name T283
Test name
Test status
Simulation time 5244508957 ps
CPU time 8.87 seconds
Started Sep 18 08:23:20 AM UTC 24
Finished Sep 18 08:23:30 AM UTC 24
Peak memory 226344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095143935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.4095143935
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/18.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.1615872924
Short name T275
Test name
Test status
Simulation time 4886843964 ps
CPU time 4.33 seconds
Started Sep 18 08:23:20 AM UTC 24
Finished Sep 18 08:23:25 AM UTC 24
Peak memory 216268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615872924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_tl_access.1615872924
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/18.rv_dm_sba_tl_access.2805138928
Short name T202
Test name
Test status
Simulation time 4850448254 ps
CPU time 3.69 seconds
Started Sep 18 08:23:20 AM UTC 24
Finished Sep 18 08:23:25 AM UTC 24
Peak memory 216092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805138928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.2805138928
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/18.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/18.rv_dm_stress_all.4121395848
Short name T210
Test name
Test status
Simulation time 2697539981 ps
CPU time 8.23 seconds
Started Sep 18 08:23:22 AM UTC 24
Finished Sep 18 08:23:32 AM UTC 24
Peak memory 216112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121395848 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.4121395848
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/18.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/19.rv_dm_alert_test.3934543748
Short name T277
Test name
Test status
Simulation time 69698753 ps
CPU time 1.38 seconds
Started Sep 18 08:23:25 AM UTC 24
Finished Sep 18 08:23:27 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934543748 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.3934543748
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/19.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.3862929740
Short name T332
Test name
Test status
Simulation time 8472815293 ps
CPU time 34.9 seconds
Started Sep 18 08:23:25 AM UTC 24
Finished Sep 18 08:24:01 AM UTC 24
Peak memory 226328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862929740 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.3862929740
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/19.rv_dm_bad_sba_tl_access.3224885470
Short name T198
Test name
Test status
Simulation time 2295211982 ps
CPU time 9.48 seconds
Started Sep 18 08:23:25 AM UTC 24
Finished Sep 18 08:23:35 AM UTC 24
Peak memory 226284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224885470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.3224885470
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/19.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.3080120579
Short name T281
Test name
Test status
Simulation time 1261125442 ps
CPU time 5.05 seconds
Started Sep 18 08:23:24 AM UTC 24
Finished Sep 18 08:23:30 AM UTC 24
Peak memory 216160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080120579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_tl_access.3080120579
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/19.rv_dm_sba_tl_access.1755108419
Short name T197
Test name
Test status
Simulation time 873521019 ps
CPU time 3.77 seconds
Started Sep 18 08:23:22 AM UTC 24
Finished Sep 18 08:23:27 AM UTC 24
Peak memory 216040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755108419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.1755108419
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/19.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.379507489
Short name T47
Test name
Test status
Simulation time 45036926 ps
CPU time 1.11 seconds
Started Sep 18 08:22:25 AM UTC 24
Finished Sep 18 08:22:27 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379507489 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.379507489
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/2.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.4073093933
Short name T191
Test name
Test status
Simulation time 69920951271 ps
CPU time 282.16 seconds
Started Sep 18 08:22:23 AM UTC 24
Finished Sep 18 08:27:09 AM UTC 24
Peak memory 226296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073093933 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.4073093933
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.3563701273
Short name T144
Test name
Test status
Simulation time 7956195637 ps
CPU time 10.75 seconds
Started Sep 18 08:22:23 AM UTC 24
Finished Sep 18 08:22:34 AM UTC 24
Peak memory 226404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563701273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.3563701273
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/2.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.2333850749
Short name T118
Test name
Test status
Simulation time 5343047742 ps
CPU time 5.23 seconds
Started Sep 18 08:22:22 AM UTC 24
Finished Sep 18 08:22:29 AM UTC 24
Peak memory 216084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333850749 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_tl_access.2333850749
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.1056915728
Short name T53
Test name
Test status
Simulation time 298585356 ps
CPU time 2.52 seconds
Started Sep 18 08:22:23 AM UTC 24
Finished Sep 18 08:22:26 AM UTC 24
Peak memory 215412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056915728 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_halt_resume_whereto.1056915728
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/2.rv_dm_halt_resume_whereto/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.3567864415
Short name T98
Test name
Test status
Simulation time 124370185 ps
CPU time 1.17 seconds
Started Sep 18 08:22:23 AM UTC 24
Finished Sep 18 08:22:25 AM UTC 24
Peak memory 215336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567864415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.3567864415
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/2.rv_dm_hart_unavail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.3965263640
Short name T249
Test name
Test status
Simulation time 6556269344 ps
CPU time 18.19 seconds
Started Sep 18 08:22:21 AM UTC 24
Finished Sep 18 08:22:41 AM UTC 24
Peak memory 216356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965263640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.3965263640
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/2.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/2.rv_dm_sparse_lc_gate_fsm.2147937252
Short name T78
Test name
Test status
Simulation time 137584612 ps
CPU time 0.97 seconds
Started Sep 18 08:22:24 AM UTC 24
Finished Sep 18 08:22:27 AM UTC 24
Peak memory 225136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147937252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sparse_lc_gate_fsm.2147937252
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/2.rv_dm_sparse_lc_gate_fsm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all.1572477249
Short name T217
Test name
Test status
Simulation time 3330805903 ps
CPU time 19.04 seconds
Started Sep 18 08:22:24 AM UTC 24
Finished Sep 18 08:22:45 AM UTC 24
Peak memory 216248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572477249 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.1572477249
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/2.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.1998448201
Short name T68
Test name
Test status
Simulation time 2336975364 ps
CPU time 37.16 seconds
Started Sep 18 08:22:25 AM UTC 24
Finished Sep 18 08:23:03 AM UTC 24
Peak memory 228612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=1998448201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stres
s_all_with_rand_reset.1998448201
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/20.rv_dm_alert_test.3546026182
Short name T279
Test name
Test status
Simulation time 134933311 ps
CPU time 1.38 seconds
Started Sep 18 08:23:26 AM UTC 24
Finished Sep 18 08:23:29 AM UTC 24
Peak memory 215148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546026182 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.3546026182
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/20.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.2857338516
Short name T17
Test name
Test status
Simulation time 3955100586 ps
CPU time 5.03 seconds
Started Sep 18 08:23:26 AM UTC 24
Finished Sep 18 08:23:32 AM UTC 24
Peak memory 226160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857338516 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.2857338516
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/20.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/21.rv_dm_alert_test.1393595113
Short name T278
Test name
Test status
Simulation time 84913037 ps
CPU time 1.13 seconds
Started Sep 18 08:23:26 AM UTC 24
Finished Sep 18 08:23:28 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393595113 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.1393595113
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/21.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/21.rv_dm_stress_all.2780187559
Short name T223
Test name
Test status
Simulation time 2457267810 ps
CPU time 2.21 seconds
Started Sep 18 08:23:26 AM UTC 24
Finished Sep 18 08:23:29 AM UTC 24
Peak memory 215912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780187559 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.2780187559
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/21.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/22.rv_dm_alert_test.2610855546
Short name T285
Test name
Test status
Simulation time 159307220 ps
CPU time 1.15 seconds
Started Sep 18 08:23:29 AM UTC 24
Finished Sep 18 08:23:31 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610855546 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.2610855546
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/22.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.635505769
Short name T212
Test name
Test status
Simulation time 2433083224 ps
CPU time 2.79 seconds
Started Sep 18 08:23:27 AM UTC 24
Finished Sep 18 08:23:31 AM UTC 24
Peak memory 215856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635505769 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.635505769
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/22.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/23.rv_dm_alert_test.2169573138
Short name T284
Test name
Test status
Simulation time 36029308 ps
CPU time 1.04 seconds
Started Sep 18 08:23:29 AM UTC 24
Finished Sep 18 08:23:31 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169573138 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.2169573138
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/23.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/23.rv_dm_stress_all.3386367989
Short name T295
Test name
Test status
Simulation time 2460337218 ps
CPU time 5.17 seconds
Started Sep 18 08:23:29 AM UTC 24
Finished Sep 18 08:23:35 AM UTC 24
Peak memory 215996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386367989 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.3386367989
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/23.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/24.rv_dm_alert_test.674684113
Short name T287
Test name
Test status
Simulation time 67509046 ps
CPU time 1.07 seconds
Started Sep 18 08:23:30 AM UTC 24
Finished Sep 18 08:23:32 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674684113 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.674684113
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/24.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/24.rv_dm_stress_all.992834918
Short name T306
Test name
Test status
Simulation time 2324076255 ps
CPU time 7.43 seconds
Started Sep 18 08:23:30 AM UTC 24
Finished Sep 18 08:23:38 AM UTC 24
Peak memory 226168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992834918 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.992834918
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/24.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/25.rv_dm_alert_test.3081861197
Short name T289
Test name
Test status
Simulation time 53297151 ps
CPU time 1.09 seconds
Started Sep 18 08:23:30 AM UTC 24
Finished Sep 18 08:23:32 AM UTC 24
Peak memory 215004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081861197 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.3081861197
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/25.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.4116297597
Short name T207
Test name
Test status
Simulation time 3291097747 ps
CPU time 7.3 seconds
Started Sep 18 08:23:30 AM UTC 24
Finished Sep 18 08:23:38 AM UTC 24
Peak memory 215700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116297597 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.4116297597
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/25.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/26.rv_dm_alert_test.3459642158
Short name T292
Test name
Test status
Simulation time 80350294 ps
CPU time 1.02 seconds
Started Sep 18 08:23:31 AM UTC 24
Finished Sep 18 08:23:33 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459642158 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.3459642158
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/26.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/26.rv_dm_stress_all.853035151
Short name T213
Test name
Test status
Simulation time 2630294025 ps
CPU time 7.96 seconds
Started Sep 18 08:23:31 AM UTC 24
Finished Sep 18 08:23:40 AM UTC 24
Peak memory 226172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853035151 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.853035151
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/26.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/27.rv_dm_alert_test.3504927903
Short name T293
Test name
Test status
Simulation time 111036413 ps
CPU time 1.18 seconds
Started Sep 18 08:23:31 AM UTC 24
Finished Sep 18 08:23:34 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504927903 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.3504927903
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/27.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/28.rv_dm_alert_test.3913052795
Short name T294
Test name
Test status
Simulation time 89314848 ps
CPU time 1.04 seconds
Started Sep 18 08:23:33 AM UTC 24
Finished Sep 18 08:23:35 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913052795 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.3913052795
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/28.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/28.rv_dm_stress_all.3735717216
Short name T220
Test name
Test status
Simulation time 991898592 ps
CPU time 2.68 seconds
Started Sep 18 08:23:31 AM UTC 24
Finished Sep 18 08:23:35 AM UTC 24
Peak memory 226108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735717216 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.3735717216
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/28.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/29.rv_dm_alert_test.3029155933
Short name T296
Test name
Test status
Simulation time 79658126 ps
CPU time 1.14 seconds
Started Sep 18 08:23:33 AM UTC 24
Finished Sep 18 08:23:35 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029155933 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.3029155933
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/29.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/29.rv_dm_stress_all.4271998915
Short name T203
Test name
Test status
Simulation time 4145344651 ps
CPU time 5.58 seconds
Started Sep 18 08:23:33 AM UTC 24
Finished Sep 18 08:23:39 AM UTC 24
Peak memory 215848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271998915 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.4271998915
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/29.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.616222486
Short name T143
Test name
Test status
Simulation time 160607610 ps
CPU time 1.32 seconds
Started Sep 18 08:22:30 AM UTC 24
Finished Sep 18 08:22:32 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616222486 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.616222486
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/3.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.2628427355
Short name T22
Test name
Test status
Simulation time 8178699423 ps
CPU time 13.22 seconds
Started Sep 18 08:22:26 AM UTC 24
Finished Sep 18 08:22:40 AM UTC 24
Peak memory 226344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628427355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.2628427355
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.2333279724
Short name T240
Test name
Test status
Simulation time 17351979776 ps
CPU time 16.01 seconds
Started Sep 18 08:22:26 AM UTC 24
Finished Sep 18 08:22:43 AM UTC 24
Peak memory 226404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333279724 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.2333279724
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/3.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.3967804668
Short name T138
Test name
Test status
Simulation time 162091059 ps
CPU time 1.8 seconds
Started Sep 18 08:22:28 AM UTC 24
Finished Sep 18 08:22:31 AM UTC 24
Peak memory 250892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967804668 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_buffered_enable.3967804668
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/3.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.2085765910
Short name T136
Test name
Test status
Simulation time 1008497037 ps
CPU time 3.24 seconds
Started Sep 18 08:22:26 AM UTC 24
Finished Sep 18 08:22:30 AM UTC 24
Peak memory 216224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085765910 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_tl_access.2085765910
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.3327768064
Short name T56
Test name
Test status
Simulation time 865531964 ps
CPU time 2.96 seconds
Started Sep 18 08:22:27 AM UTC 24
Finished Sep 18 08:22:31 AM UTC 24
Peak memory 215524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327768064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_halt_resume_whereto.3327768064
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/3.rv_dm_halt_resume_whereto/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/3.rv_dm_hart_unavail.656657871
Short name T247
Test name
Test status
Simulation time 135076883 ps
CPU time 1.33 seconds
Started Sep 18 08:22:27 AM UTC 24
Finished Sep 18 08:22:29 AM UTC 24
Peak memory 215332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656657871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.656657871
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/3.rv_dm_hart_unavail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.3175690757
Short name T251
Test name
Test status
Simulation time 13996530463 ps
CPU time 19.59 seconds
Started Sep 18 08:22:26 AM UTC 24
Finished Sep 18 08:22:47 AM UTC 24
Peak memory 226544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175690757 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.3175690757
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/3.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/3.rv_dm_sec_cm.1360383682
Short name T91
Test name
Test status
Simulation time 278234423 ps
CPU time 2.66 seconds
Started Sep 18 08:22:30 AM UTC 24
Finished Sep 18 08:22:33 AM UTC 24
Peak memory 256120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360383682 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.1360383682
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/3.rv_dm_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.475551511
Short name T81
Test name
Test status
Simulation time 253903723 ps
CPU time 1.79 seconds
Started Sep 18 08:22:28 AM UTC 24
Finished Sep 18 08:22:31 AM UTC 24
Peak memory 225252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475551511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sparse_lc_gate_fsm.475551511
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/3.rv_dm_sparse_lc_gate_fsm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.3396496026
Short name T34
Test name
Test status
Simulation time 4890928454 ps
CPU time 8.83 seconds
Started Sep 18 08:22:28 AM UTC 24
Finished Sep 18 08:22:38 AM UTC 24
Peak memory 226184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396496026 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.3396496026
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/3.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/30.rv_dm_alert_test.2140863108
Short name T298
Test name
Test status
Simulation time 98781271 ps
CPU time 1.53 seconds
Started Sep 18 08:23:33 AM UTC 24
Finished Sep 18 08:23:35 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140863108 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.2140863108
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/30.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.2043190622
Short name T205
Test name
Test status
Simulation time 1025221805 ps
CPU time 4.14 seconds
Started Sep 18 08:23:33 AM UTC 24
Finished Sep 18 08:23:38 AM UTC 24
Peak memory 226296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043190622 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.2043190622
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/30.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/31.rv_dm_alert_test.783783499
Short name T297
Test name
Test status
Simulation time 42832632 ps
CPU time 1 seconds
Started Sep 18 08:23:33 AM UTC 24
Finished Sep 18 08:23:35 AM UTC 24
Peak memory 215208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783783499 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.783783499
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/31.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/32.rv_dm_alert_test.2712350972
Short name T300
Test name
Test status
Simulation time 51324796 ps
CPU time 1.25 seconds
Started Sep 18 08:23:34 AM UTC 24
Finished Sep 18 08:23:37 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712350972 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.2712350972
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/32.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/33.rv_dm_alert_test.1916814683
Short name T299
Test name
Test status
Simulation time 62230707 ps
CPU time 1 seconds
Started Sep 18 08:23:34 AM UTC 24
Finished Sep 18 08:23:36 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916814683 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.1916814683
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/33.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/34.rv_dm_alert_test.1600338968
Short name T304
Test name
Test status
Simulation time 47370669 ps
CPU time 1.23 seconds
Started Sep 18 08:23:36 AM UTC 24
Finished Sep 18 08:23:38 AM UTC 24
Peak memory 215248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600338968 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.1600338968
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/34.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/35.rv_dm_alert_test.1864158067
Short name T302
Test name
Test status
Simulation time 188380729 ps
CPU time 1.13 seconds
Started Sep 18 08:23:36 AM UTC 24
Finished Sep 18 08:23:38 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864158067 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.1864158067
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/35.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/35.rv_dm_stress_all.1835553082
Short name T224
Test name
Test status
Simulation time 3912486436 ps
CPU time 3.37 seconds
Started Sep 18 08:23:36 AM UTC 24
Finished Sep 18 08:23:40 AM UTC 24
Peak memory 226236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835553082 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.1835553082
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/35.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/36.rv_dm_alert_test.1262662729
Short name T303
Test name
Test status
Simulation time 116092305 ps
CPU time 1.04 seconds
Started Sep 18 08:23:36 AM UTC 24
Finished Sep 18 08:23:38 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262662729 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.1262662729
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/36.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/36.rv_dm_stress_all.845830983
Short name T222
Test name
Test status
Simulation time 4858851471 ps
CPU time 18.7 seconds
Started Sep 18 08:23:36 AM UTC 24
Finished Sep 18 08:23:56 AM UTC 24
Peak memory 216056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845830983 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.845830983
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/36.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/37.rv_dm_alert_test.521578554
Short name T305
Test name
Test status
Simulation time 105761934 ps
CPU time 1.18 seconds
Started Sep 18 08:23:36 AM UTC 24
Finished Sep 18 08:23:38 AM UTC 24
Peak memory 215208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521578554 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.521578554
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/37.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/37.rv_dm_stress_all.4144223393
Short name T313
Test name
Test status
Simulation time 1388469140 ps
CPU time 3.84 seconds
Started Sep 18 08:23:36 AM UTC 24
Finished Sep 18 08:23:41 AM UTC 24
Peak memory 226040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144223393 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.4144223393
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/37.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/38.rv_dm_alert_test.3403330921
Short name T301
Test name
Test status
Simulation time 149282446 ps
CPU time 0.81 seconds
Started Sep 18 08:23:36 AM UTC 24
Finished Sep 18 08:23:38 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403330921 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.3403330921
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/38.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/38.rv_dm_stress_all.4155924842
Short name T209
Test name
Test status
Simulation time 4861654450 ps
CPU time 6.7 seconds
Started Sep 18 08:23:36 AM UTC 24
Finished Sep 18 08:23:44 AM UTC 24
Peak memory 216176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155924842 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.4155924842
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/38.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/39.rv_dm_alert_test.2943443288
Short name T309
Test name
Test status
Simulation time 46928584 ps
CPU time 1.29 seconds
Started Sep 18 08:23:38 AM UTC 24
Finished Sep 18 08:23:40 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943443288 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.2943443288
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/39.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/39.rv_dm_stress_all.1552538833
Short name T216
Test name
Test status
Simulation time 4238439596 ps
CPU time 2.99 seconds
Started Sep 18 08:23:37 AM UTC 24
Finished Sep 18 08:23:41 AM UTC 24
Peak memory 215924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552538833 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.1552538833
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/39.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/4.rv_dm_alert_test.2237081692
Short name T147
Test name
Test status
Simulation time 49265183 ps
CPU time 1.27 seconds
Started Sep 18 08:22:36 AM UTC 24
Finished Sep 18 08:22:38 AM UTC 24
Peak memory 215208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237081692 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.2237081692
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/4.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/4.rv_dm_autoincr_sba_tl_access.1201064164
Short name T23
Test name
Test status
Simulation time 4200787435 ps
CPU time 8.5 seconds
Started Sep 18 08:22:32 AM UTC 24
Finished Sep 18 08:22:42 AM UTC 24
Peak memory 226388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201064164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.1201064164
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/4.rv_dm_bad_sba_tl_access.1141312736
Short name T291
Test name
Test status
Simulation time 14814139808 ps
CPU time 60.2 seconds
Started Sep 18 08:22:31 AM UTC 24
Finished Sep 18 08:23:33 AM UTC 24
Peak memory 226268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141312736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.1141312736
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/4.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/4.rv_dm_buffered_enable.74852038
Short name T146
Test name
Test status
Simulation time 362222139 ps
CPU time 2.93 seconds
Started Sep 18 08:22:32 AM UTC 24
Finished Sep 18 08:22:36 AM UTC 24
Peak memory 252124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74852038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv
_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_buffered_enable.74852038
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/4.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3389670700
Short name T201
Test name
Test status
Simulation time 1803993491 ps
CPU time 10.11 seconds
Started Sep 18 08:22:31 AM UTC 24
Finished Sep 18 08:22:42 AM UTC 24
Peak memory 216144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389670700 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_tl_access.3389670700
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.2238339254
Short name T54
Test name
Test status
Simulation time 965657816 ps
CPU time 1.47 seconds
Started Sep 18 08:22:32 AM UTC 24
Finished Sep 18 08:22:35 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238339254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_halt_resume_whereto.2238339254
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/4.rv_dm_halt_resume_whereto/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.3044170499
Short name T145
Test name
Test status
Simulation time 165786179 ps
CPU time 1.91 seconds
Started Sep 18 08:22:32 AM UTC 24
Finished Sep 18 08:22:35 AM UTC 24
Peak memory 215336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044170499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.3044170499
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/4.rv_dm_hart_unavail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/4.rv_dm_sba_tl_access.167794809
Short name T137
Test name
Test status
Simulation time 1110856612 ps
CPU time 2.16 seconds
Started Sep 18 08:22:31 AM UTC 24
Finished Sep 18 08:22:34 AM UTC 24
Peak memory 215992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167794809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.167794809
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/4.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/4.rv_dm_sec_cm.1224593081
Short name T85
Test name
Test status
Simulation time 371828483 ps
CPU time 2.09 seconds
Started Sep 18 08:22:35 AM UTC 24
Finished Sep 18 08:22:38 AM UTC 24
Peak memory 254076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224593081 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.1224593081
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/4.rv_dm_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.2941250114
Short name T111
Test name
Test status
Simulation time 3356237523 ps
CPU time 43.01 seconds
Started Sep 18 08:22:35 AM UTC 24
Finished Sep 18 08:23:19 AM UTC 24
Peak memory 232864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=2941250114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stres
s_all_with_rand_reset.2941250114
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/40.rv_dm_alert_test.2330492113
Short name T307
Test name
Test status
Simulation time 129587866 ps
CPU time 1.04 seconds
Started Sep 18 08:23:38 AM UTC 24
Finished Sep 18 08:23:40 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330492113 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.2330492113
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/40.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/40.rv_dm_stress_all.1712277613
Short name T323
Test name
Test status
Simulation time 6773077069 ps
CPU time 6.74 seconds
Started Sep 18 08:23:38 AM UTC 24
Finished Sep 18 08:23:45 AM UTC 24
Peak memory 226168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712277613 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.1712277613
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/40.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/41.rv_dm_alert_test.2015102341
Short name T315
Test name
Test status
Simulation time 135749180 ps
CPU time 1.62 seconds
Started Sep 18 08:23:39 AM UTC 24
Finished Sep 18 08:23:42 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015102341 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.2015102341
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/41.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/41.rv_dm_stress_all.276761587
Short name T326
Test name
Test status
Simulation time 3840387245 ps
CPU time 8.55 seconds
Started Sep 18 08:23:39 AM UTC 24
Finished Sep 18 08:23:49 AM UTC 24
Peak memory 216120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276761587 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.276761587
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/41.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/42.rv_dm_alert_test.656891226
Short name T314
Test name
Test status
Simulation time 70048386 ps
CPU time 1.29 seconds
Started Sep 18 08:23:39 AM UTC 24
Finished Sep 18 08:23:41 AM UTC 24
Peak memory 215208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656891226 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.656891226
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/42.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/42.rv_dm_stress_all.1835418958
Short name T330
Test name
Test status
Simulation time 5554371220 ps
CPU time 18.35 seconds
Started Sep 18 08:23:39 AM UTC 24
Finished Sep 18 08:23:59 AM UTC 24
Peak memory 215860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835418958 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.1835418958
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/42.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/43.rv_dm_alert_test.1720525358
Short name T316
Test name
Test status
Simulation time 147038942 ps
CPU time 1.45 seconds
Started Sep 18 08:23:39 AM UTC 24
Finished Sep 18 08:23:42 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720525358 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.1720525358
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/43.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/44.rv_dm_alert_test.1726528443
Short name T312
Test name
Test status
Simulation time 65326291 ps
CPU time 1.25 seconds
Started Sep 18 08:23:39 AM UTC 24
Finished Sep 18 08:23:42 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726528443 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.1726528443
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/44.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.4181966171
Short name T321
Test name
Test status
Simulation time 2922248474 ps
CPU time 4.17 seconds
Started Sep 18 08:23:39 AM UTC 24
Finished Sep 18 08:23:45 AM UTC 24
Peak memory 215904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181966171 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.4181966171
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/44.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/45.rv_dm_alert_test.866655392
Short name T317
Test name
Test status
Simulation time 38795786 ps
CPU time 1.09 seconds
Started Sep 18 08:23:41 AM UTC 24
Finished Sep 18 08:23:43 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866655392 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.866655392
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/45.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/45.rv_dm_stress_all.3637299827
Short name T325
Test name
Test status
Simulation time 3947969917 ps
CPU time 5.62 seconds
Started Sep 18 08:23:41 AM UTC 24
Finished Sep 18 08:23:47 AM UTC 24
Peak memory 215916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637299827 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.3637299827
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/45.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/46.rv_dm_alert_test.3220033595
Short name T320
Test name
Test status
Simulation time 50773769 ps
CPU time 1.31 seconds
Started Sep 18 08:23:41 AM UTC 24
Finished Sep 18 08:23:43 AM UTC 24
Peak memory 215240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220033595 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3220033595
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/46.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.3846732252
Short name T331
Test name
Test status
Simulation time 8498414296 ps
CPU time 17.64 seconds
Started Sep 18 08:23:41 AM UTC 24
Finished Sep 18 08:24:00 AM UTC 24
Peak memory 216100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846732252 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.3846732252
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/46.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/47.rv_dm_alert_test.2744312651
Short name T318
Test name
Test status
Simulation time 147957629 ps
CPU time 1.03 seconds
Started Sep 18 08:23:41 AM UTC 24
Finished Sep 18 08:23:43 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744312651 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.2744312651
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/47.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/47.rv_dm_stress_all.2402833152
Short name T215
Test name
Test status
Simulation time 3832241124 ps
CPU time 4.19 seconds
Started Sep 18 08:23:41 AM UTC 24
Finished Sep 18 08:23:46 AM UTC 24
Peak memory 215932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402833152 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.2402833152
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/47.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/48.rv_dm_alert_test.3489208779
Short name T319
Test name
Test status
Simulation time 43491217 ps
CPU time 1.04 seconds
Started Sep 18 08:23:41 AM UTC 24
Finished Sep 18 08:23:43 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489208779 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.3489208779
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/48.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/48.rv_dm_stress_all.644214396
Short name T324
Test name
Test status
Simulation time 2160066848 ps
CPU time 5.15 seconds
Started Sep 18 08:23:41 AM UTC 24
Finished Sep 18 08:23:47 AM UTC 24
Peak memory 215924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644214396 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.644214396
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/48.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/49.rv_dm_alert_test.857930173
Short name T322
Test name
Test status
Simulation time 38158694 ps
CPU time 1.09 seconds
Started Sep 18 08:23:43 AM UTC 24
Finished Sep 18 08:23:45 AM UTC 24
Peak memory 215208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857930173 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.857930173
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/49.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/49.rv_dm_stress_all.368917079
Short name T221
Test name
Test status
Simulation time 2756618303 ps
CPU time 6.04 seconds
Started Sep 18 08:23:41 AM UTC 24
Finished Sep 18 08:23:48 AM UTC 24
Peak memory 226172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368917079 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.368917079
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/49.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/5.rv_dm_alert_test.2501618869
Short name T245
Test name
Test status
Simulation time 246202964 ps
CPU time 1.11 seconds
Started Sep 18 08:22:42 AM UTC 24
Finished Sep 18 08:22:44 AM UTC 24
Peak memory 215208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501618869 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.2501618869
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/5.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.2848848303
Short name T119
Test name
Test status
Simulation time 23739166067 ps
CPU time 21.49 seconds
Started Sep 18 08:22:38 AM UTC 24
Finished Sep 18 08:23:01 AM UTC 24
Peak memory 226324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848848303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.2848848303
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.1902198211
Short name T252
Test name
Test status
Simulation time 11834967380 ps
CPU time 12.3 seconds
Started Sep 18 08:22:37 AM UTC 24
Finished Sep 18 08:22:50 AM UTC 24
Peak memory 226404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902198211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.1902198211
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/5.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/5.rv_dm_buffered_enable.641939754
Short name T236
Test name
Test status
Simulation time 147934685 ps
CPU time 2.08 seconds
Started Sep 18 08:22:39 AM UTC 24
Finished Sep 18 08:22:42 AM UTC 24
Peak memory 252124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641939754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_buffered_enable.641939754
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/5.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.3444705276
Short name T193
Test name
Test status
Simulation time 941187159 ps
CPU time 2.96 seconds
Started Sep 18 08:22:36 AM UTC 24
Finished Sep 18 08:22:40 AM UTC 24
Peak memory 215968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444705276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl_access.3444705276
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/5.rv_dm_halt_resume_whereto.2896786227
Short name T55
Test name
Test status
Simulation time 594981374 ps
CPU time 1.72 seconds
Started Sep 18 08:22:39 AM UTC 24
Finished Sep 18 08:22:42 AM UTC 24
Peak memory 215332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896786227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_halt_resume_whereto.2896786227
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/5.rv_dm_halt_resume_whereto/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/5.rv_dm_sba_tl_access.935583416
Short name T250
Test name
Test status
Simulation time 3175586997 ps
CPU time 5.08 seconds
Started Sep 18 08:22:36 AM UTC 24
Finished Sep 18 08:22:42 AM UTC 24
Peak memory 216292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935583416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.935583416
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/5.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.2020817642
Short name T10
Test name
Test status
Simulation time 13271368367 ps
CPU time 35.47 seconds
Started Sep 18 08:22:41 AM UTC 24
Finished Sep 18 08:23:18 AM UTC 24
Peak memory 230732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=2020817642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stres
s_all_with_rand_reset.2020817642
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/6.rv_dm_alert_test.1978784730
Short name T241
Test name
Test status
Simulation time 120989984 ps
CPU time 1.35 seconds
Started Sep 18 08:22:43 AM UTC 24
Finished Sep 18 08:22:46 AM UTC 24
Peak memory 215200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978784730 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.1978784730
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/6.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/6.rv_dm_bad_sba_tl_access.2316859912
Short name T243
Test name
Test status
Simulation time 1498152547 ps
CPU time 6.26 seconds
Started Sep 18 08:22:43 AM UTC 24
Finished Sep 18 08:22:50 AM UTC 24
Peak memory 216036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316859912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.2316859912
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/6.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/6.rv_dm_buffered_enable.1341674395
Short name T237
Test name
Test status
Simulation time 657413597 ps
CPU time 3.74 seconds
Started Sep 18 08:22:43 AM UTC 24
Finished Sep 18 08:22:48 AM UTC 24
Peak memory 258256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341674395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_buffered_enable.1341674395
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/6.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.1927369652
Short name T121
Test name
Test status
Simulation time 11692994272 ps
CPU time 19.71 seconds
Started Sep 18 08:22:43 AM UTC 24
Finished Sep 18 08:23:04 AM UTC 24
Peak memory 226452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927369652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_tl_access.1927369652
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/6.rv_dm_halt_resume_whereto.1666819075
Short name T189
Test name
Test status
Simulation time 220515623 ps
CPU time 1.54 seconds
Started Sep 18 08:22:43 AM UTC 24
Finished Sep 18 08:22:46 AM UTC 24
Peak memory 215332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666819075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_halt_resume_whereto.1666819075
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/6.rv_dm_halt_resume_whereto/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/6.rv_dm_sba_tl_access.2080794956
Short name T194
Test name
Test status
Simulation time 1307295414 ps
CPU time 2.14 seconds
Started Sep 18 08:22:42 AM UTC 24
Finished Sep 18 08:22:45 AM UTC 24
Peak memory 216232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080794956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.2080794956
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/6.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all.3809265100
Short name T206
Test name
Test status
Simulation time 4011911335 ps
CPU time 6.94 seconds
Started Sep 18 08:22:43 AM UTC 24
Finished Sep 18 08:22:51 AM UTC 24
Peak memory 215988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809265100 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.3809265100
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/6.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/7.rv_dm_alert_test.1448818686
Short name T246
Test name
Test status
Simulation time 131646549 ps
CPU time 1.39 seconds
Started Sep 18 08:22:48 AM UTC 24
Finished Sep 18 08:22:50 AM UTC 24
Peak memory 215208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448818686 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.1448818686
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/7.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.2219057057
Short name T123
Test name
Test status
Simulation time 21556441757 ps
CPU time 17.48 seconds
Started Sep 18 08:22:46 AM UTC 24
Finished Sep 18 08:23:04 AM UTC 24
Peak memory 226332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219057057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.2219057057
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/7.rv_dm_buffered_enable.2679035440
Short name T71
Test name
Test status
Simulation time 505902936 ps
CPU time 2 seconds
Started Sep 18 08:22:47 AM UTC 24
Finished Sep 18 08:22:50 AM UTC 24
Peak memory 257148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679035440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_buffered_enable.2679035440
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/7.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.2916001824
Short name T253
Test name
Test status
Simulation time 6247346950 ps
CPU time 11.95 seconds
Started Sep 18 08:22:44 AM UTC 24
Finished Sep 18 08:22:57 AM UTC 24
Peak memory 216276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916001824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_tl_access.2916001824
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/7.rv_dm_sba_tl_access.3404942750
Short name T242
Test name
Test status
Simulation time 1477117661 ps
CPU time 4.71 seconds
Started Sep 18 08:22:44 AM UTC 24
Finished Sep 18 08:22:50 AM UTC 24
Peak memory 215892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404942750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.3404942750
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/7.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all.352277059
Short name T65
Test name
Test status
Simulation time 3594270162 ps
CPU time 4.53 seconds
Started Sep 18 08:22:47 AM UTC 24
Finished Sep 18 08:22:52 AM UTC 24
Peak memory 215916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352277059 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.352277059
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/7.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.1250731543
Short name T112
Test name
Test status
Simulation time 1419150611 ps
CPU time 38.87 seconds
Started Sep 18 08:22:47 AM UTC 24
Finished Sep 18 08:23:27 AM UTC 24
Peak memory 228592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=1250731543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stres
s_all_with_rand_reset.1250731543
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/8.rv_dm_alert_test.2802533270
Short name T248
Test name
Test status
Simulation time 84554828 ps
CPU time 1.16 seconds
Started Sep 18 08:22:53 AM UTC 24
Finished Sep 18 08:22:55 AM UTC 24
Peak memory 214908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802533270 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.2802533270
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/8.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.299364166
Short name T329
Test name
Test status
Simulation time 35521494807 ps
CPU time 65.28 seconds
Started Sep 18 08:22:51 AM UTC 24
Finished Sep 18 08:23:58 AM UTC 24
Peak memory 226524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299364166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.299364166
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/8.rv_dm_bad_sba_tl_access.2027307464
Short name T199
Test name
Test status
Simulation time 2765222911 ps
CPU time 6.35 seconds
Started Sep 18 08:22:50 AM UTC 24
Finished Sep 18 08:22:58 AM UTC 24
Peak memory 216108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027307464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.2027307464
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/8.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/8.rv_dm_buffered_enable.3609683525
Short name T72
Test name
Test status
Simulation time 110600545 ps
CPU time 1.54 seconds
Started Sep 18 08:22:51 AM UTC 24
Finished Sep 18 08:22:54 AM UTC 24
Peak memory 257024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609683525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_buffered_enable.3609683525
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/8.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.2073743033
Short name T266
Test name
Test status
Simulation time 6450982894 ps
CPU time 26.53 seconds
Started Sep 18 08:22:49 AM UTC 24
Finished Sep 18 08:23:17 AM UTC 24
Peak memory 226572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073743033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl_access.2073743033
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/8.rv_dm_sba_tl_access.1779922436
Short name T238
Test name
Test status
Simulation time 5105034304 ps
CPU time 8.53 seconds
Started Sep 18 08:22:49 AM UTC 24
Finished Sep 18 08:22:59 AM UTC 24
Peak memory 216084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779922436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.1779922436
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/8.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.3241131723
Short name T67
Test name
Test status
Simulation time 4183737015 ps
CPU time 13.32 seconds
Started Sep 18 08:22:51 AM UTC 24
Finished Sep 18 08:23:06 AM UTC 24
Peak memory 226168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241131723 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.3241131723
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/8.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.3035684213
Short name T120
Test name
Test status
Simulation time 84936260 ps
CPU time 1.05 seconds
Started Sep 18 08:22:59 AM UTC 24
Finished Sep 18 08:23:01 AM UTC 24
Peak memory 215208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035684213 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.3035684213
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/9.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/9.rv_dm_autoincr_sba_tl_access.3828256049
Short name T178
Test name
Test status
Simulation time 4033365606 ps
CPU time 8.34 seconds
Started Sep 18 08:22:56 AM UTC 24
Finished Sep 18 08:23:05 AM UTC 24
Peak memory 216084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828256049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.3828256049
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/9.rv_dm_buffered_enable.1269523862
Short name T184
Test name
Test status
Simulation time 189569627 ps
CPU time 1.63 seconds
Started Sep 18 08:22:56 AM UTC 24
Finished Sep 18 08:22:59 AM UTC 24
Peak memory 256452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269523862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_buffered_enable.1269523862
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/9.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.138918340
Short name T125
Test name
Test status
Simulation time 3563841838 ps
CPU time 10.37 seconds
Started Sep 18 08:22:54 AM UTC 24
Finished Sep 18 08:23:05 AM UTC 24
Peak memory 216348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138918340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_tl_access.138918340
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.4048632335
Short name T195
Test name
Test status
Simulation time 5312809373 ps
CPU time 21.86 seconds
Started Sep 18 08:22:53 AM UTC 24
Finished Sep 18 08:23:16 AM UTC 24
Peak memory 215700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048632335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.4048632335
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/9.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.3396707289
Short name T35
Test name
Test status
Simulation time 2768933528 ps
CPU time 4.82 seconds
Started Sep 18 08:22:58 AM UTC 24
Finished Sep 18 08:23:04 AM UTC 24
Peak memory 216108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396707289 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.3396707289
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/9.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.264522050
Short name T116
Test name
Test status
Simulation time 2331074182 ps
CPU time 39.24 seconds
Started Sep 18 08:22:58 AM UTC 24
Finished Sep 18 08:23:39 AM UTC 24
Peak memory 228424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=264522050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress
_all_with_rand_reset.264522050
Directory /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest