Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.33 96.34 89.82 92.10 93.33 90.27 98.74 57.72


Total tests in report: 483
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
53.43 53.43 84.37 84.37 55.30 55.30 29.58 29.58 44.00 44.00 64.60 64.60 92.75 92.75 3.40 3.40 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.1125163472
63.99 10.57 87.25 2.89 67.19 11.88 33.11 3.53 50.67 6.67 72.57 7.96 93.80 1.05 43.38 39.98 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.3212527864
72.43 8.43 90.45 3.20 72.98 5.80 61.76 28.66 62.67 12.00 78.58 6.02 95.69 1.89 44.84 1.46 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_bad_sba_tl_access.4252615307
78.89 6.46 93.91 3.46 78.93 5.94 78.95 17.18 73.33 10.67 84.78 6.19 95.90 0.21 46.42 1.58 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.3317683512
80.04 1.16 94.84 0.93 80.34 1.41 81.60 2.65 74.67 1.33 86.19 1.42 96.01 0.11 46.66 0.24 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.3604027458
80.90 0.85 94.84 0.00 80.62 0.28 81.60 0.00 80.00 5.33 86.55 0.35 96.01 0.00 46.66 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.3054276689
81.64 0.74 94.89 0.05 81.61 0.99 81.93 0.34 80.00 0.00 86.73 0.18 96.01 0.00 50.30 3.65 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.354005198
82.33 0.69 95.05 0.15 82.46 0.85 85.25 3.32 80.00 0.00 87.26 0.53 96.01 0.00 50.30 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.183037516
82.90 0.57 95.05 0.00 82.46 0.00 85.25 0.00 84.00 4.00 87.26 0.00 96.01 0.00 50.30 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2024668641
83.37 0.46 95.05 0.00 83.31 0.85 87.23 1.97 84.00 0.00 87.43 0.18 96.01 0.00 50.55 0.24 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.2684006022
83.78 0.41 95.10 0.05 83.88 0.57 88.32 1.09 84.00 0.00 87.79 0.35 96.85 0.84 50.55 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3316154252
84.18 0.39 95.30 0.21 84.44 0.57 88.49 0.17 85.33 1.33 88.14 0.35 96.85 0.00 50.67 0.12 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all_with_rand_reset.2422153887
84.53 0.36 95.36 0.05 86.70 2.26 88.49 0.00 85.33 0.00 88.32 0.18 96.85 0.00 50.67 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.3344127123
84.87 0.34 95.36 0.00 86.70 0.00 89.66 1.18 85.33 0.00 88.32 0.00 96.85 0.00 51.88 1.22 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/14.rv_dm_autoincr_sba_tl_access.3915638472
85.14 0.27 95.36 0.00 87.13 0.42 90.42 0.76 85.33 0.00 88.32 0.00 96.95 0.11 52.49 0.61 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.1695343093
85.38 0.24 95.72 0.36 87.55 0.42 90.42 0.00 85.33 0.00 88.85 0.53 96.95 0.00 52.86 0.36 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/34.rv_dm_stress_all.3813655582
85.60 0.21 95.72 0.00 87.55 0.00 90.59 0.17 86.67 1.33 88.85 0.00 96.95 0.00 52.86 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.1265998099
85.81 0.21 95.72 0.00 87.55 0.00 90.59 0.00 88.00 1.33 88.85 0.00 96.95 0.00 52.98 0.12 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.975669932
86.01 0.21 95.72 0.00 87.55 0.00 90.59 0.00 89.33 1.33 88.85 0.00 96.95 0.00 53.10 0.12 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.1801367338
86.20 0.19 95.72 0.00 87.55 0.00 90.59 0.00 90.67 1.33 88.85 0.00 96.95 0.00 53.10 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.4238235720
86.39 0.19 95.72 0.00 87.55 0.00 90.59 0.00 92.00 1.33 88.85 0.00 96.95 0.00 53.10 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.2903122274
86.58 0.19 95.72 0.00 87.55 0.00 90.59 0.00 93.33 1.33 88.85 0.00 96.95 0.00 53.10 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.1330573241
86.76 0.17 95.72 0.00 87.55 0.00 90.84 0.25 93.33 0.00 88.85 0.00 96.95 0.00 54.07 0.97 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/15.rv_dm_autoincr_sba_tl_access.1856202000
86.91 0.15 95.87 0.15 88.26 0.71 91.05 0.21 93.33 0.00 88.85 0.00 96.95 0.00 54.07 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.286696430
87.05 0.14 96.08 0.21 88.54 0.28 91.05 0.00 93.33 0.00 89.20 0.35 96.95 0.00 54.19 0.12 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.3787564271
87.17 0.12 96.08 0.00 88.54 0.00 91.89 0.84 93.33 0.00 89.20 0.00 96.95 0.00 54.19 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/6.rv_dm_autoincr_sba_tl_access.205063797
87.28 0.11 96.08 0.00 88.54 0.00 91.89 0.00 93.33 0.00 89.20 0.00 97.69 0.74 54.19 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_rw.2852205725
87.37 0.09 96.08 0.00 88.83 0.28 91.89 0.00 93.33 0.00 89.20 0.00 97.69 0.00 54.56 0.36 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/43.rv_dm_stress_all.2101260076
87.46 0.09 96.13 0.05 88.97 0.14 91.97 0.08 93.33 0.00 89.56 0.35 97.69 0.00 54.56 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.1632367456
87.54 0.09 96.18 0.05 89.39 0.42 91.97 0.00 93.33 0.00 89.56 0.00 97.69 0.00 54.68 0.12 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.1469661520
87.62 0.08 96.18 0.00 89.39 0.00 91.97 0.00 93.33 0.00 89.56 0.00 98.21 0.53 54.68 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.291661202
87.69 0.07 96.18 0.00 89.39 0.00 91.97 0.00 93.33 0.00 89.56 0.00 98.21 0.00 55.16 0.49 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/31.rv_dm_stress_all.2835066801
87.74 0.05 96.23 0.05 89.53 0.14 91.97 0.00 93.33 0.00 89.73 0.18 98.21 0.00 55.16 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.1616741191
87.79 0.05 96.23 0.00 89.53 0.00 91.97 0.00 93.33 0.00 89.73 0.00 98.21 0.00 55.53 0.36 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2605132632
87.85 0.05 96.23 0.00 89.53 0.00 91.97 0.00 93.33 0.00 89.73 0.00 98.21 0.00 55.89 0.36 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.2288676505
87.90 0.05 96.23 0.00 89.53 0.00 91.97 0.00 93.33 0.00 89.73 0.00 98.21 0.00 56.26 0.36 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.3638609250
87.94 0.05 96.23 0.00 89.67 0.14 91.97 0.00 93.33 0.00 89.91 0.18 98.21 0.00 56.26 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.3794272388
87.98 0.03 96.23 0.00 89.67 0.00 91.97 0.00 93.33 0.00 89.91 0.00 98.21 0.00 56.50 0.24 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3105298100
88.01 0.03 96.23 0.00 89.67 0.00 91.97 0.00 93.33 0.00 89.91 0.00 98.21 0.00 56.74 0.24 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/32.rv_dm_stress_all.3492892616
88.05 0.03 96.23 0.00 89.67 0.00 91.97 0.00 93.33 0.00 89.91 0.00 98.21 0.00 56.99 0.24 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.2792875464
88.08 0.03 96.28 0.05 89.67 0.00 91.97 0.00 93.33 0.00 90.09 0.18 98.21 0.00 56.99 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1172891071
88.11 0.03 96.34 0.05 89.67 0.00 91.97 0.00 93.33 0.00 90.27 0.18 98.21 0.00 56.99 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.2325959464
88.14 0.03 96.34 0.00 89.67 0.00 91.97 0.00 93.33 0.00 90.27 0.00 98.42 0.21 56.99 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3936714070
88.17 0.03 96.34 0.00 89.82 0.14 92.02 0.04 93.33 0.00 90.27 0.00 98.42 0.00 56.99 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.2707821672
88.19 0.02 96.34 0.00 89.82 0.00 92.02 0.00 93.33 0.00 90.27 0.00 98.42 0.00 57.11 0.12 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_ndmreset_req.2804438647
88.20 0.02 96.34 0.00 89.82 0.00 92.02 0.00 93.33 0.00 90.27 0.00 98.42 0.00 57.23 0.12 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/10.rv_dm_stress_all.3432972060
88.22 0.02 96.34 0.00 89.82 0.00 92.02 0.00 93.33 0.00 90.27 0.00 98.42 0.00 57.35 0.12 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/12.rv_dm_stress_all.1706868326
88.24 0.02 96.34 0.00 89.82 0.00 92.02 0.00 93.33 0.00 90.27 0.00 98.42 0.00 57.47 0.12 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/14.rv_dm_bad_sba_tl_access.3953601729
88.26 0.02 96.34 0.00 89.82 0.00 92.02 0.00 93.33 0.00 90.27 0.00 98.42 0.00 57.59 0.12 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.2196047051
88.27 0.02 96.34 0.00 89.82 0.00 92.02 0.00 93.33 0.00 90.27 0.00 98.42 0.00 57.72 0.12 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.758381901
88.29 0.02 96.34 0.00 89.82 0.00 92.02 0.00 93.33 0.00 90.27 0.00 98.53 0.11 57.72 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_rw.3045200829
88.30 0.02 96.34 0.00 89.82 0.00 92.02 0.00 93.33 0.00 90.27 0.00 98.63 0.11 57.72 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.467793502
88.32 0.02 96.34 0.00 89.82 0.00 92.02 0.00 93.33 0.00 90.27 0.00 98.74 0.11 57.72 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.1165409235
88.33 0.01 96.34 0.00 89.82 0.00 92.10 0.08 93.33 0.00 90.27 0.00 98.74 0.00 57.72 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3142460272

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.4248672197
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.4017691054
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3738098754
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.574876246
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1005448279
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1910911291
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3649967917
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1599074262
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1232625563
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.582229115
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1525359650
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.2851792944
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1302720761
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.3902253775
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.429542584
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2752971925
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2536686328
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.4293524810
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.701779013
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2324927083
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.432863293
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1266462620
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.447517804
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2838447596
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3595296833
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1830691228
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.4013754931
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.179402206
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.1479587561
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3883786184
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.540543261
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.2216509647
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3900017940
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2297444860
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.774844863
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3516600190
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.4272058232
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.841558901
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/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.264522050



Total test records in report: 483
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_smoke.999080146 Sep 18 08:21:55 AM UTC 24 Sep 18 08:22:00 AM UTC 24 638754850 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.1125163472 Sep 18 08:21:59 AM UTC 24 Sep 18 08:22:02 AM UTC 24 272222489 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_busy.3728957405 Sep 18 08:21:59 AM UTC 24 Sep 18 08:22:02 AM UTC 24 933469171 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_halted.719500329 Sep 18 08:22:00 AM UTC 24 Sep 18 08:22:02 AM UTC 24 135996281 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_resuming.3076407038 Sep 18 08:22:00 AM UTC 24 Sep 18 08:22:04 AM UTC 24 680046130 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.440520133 Sep 18 08:21:59 AM UTC 24 Sep 18 08:22:06 AM UTC 24 664793772 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_hart_unavail.3532849753 Sep 18 08:22:02 AM UTC 24 Sep 18 08:22:06 AM UTC 24 197297998 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.3604027458 Sep 18 08:22:24 AM UTC 24 Sep 18 08:22:28 AM UTC 24 239282429 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_dataaddr_rw_access.3487033415 Sep 18 08:22:03 AM UTC 24 Sep 18 08:22:07 AM UTC 24 48835929 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.2707821672 Sep 18 08:22:03 AM UTC 24 Sep 18 08:22:07 AM UTC 24 213377724 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_idle_hint.1129367775 Sep 18 08:22:05 AM UTC 24 Sep 18 08:22:07 AM UTC 24 186118014 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.874534737 Sep 18 08:22:04 AM UTC 24 Sep 18 08:22:08 AM UTC 24 503052364 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.823704052 Sep 18 08:22:05 AM UTC 24 Sep 18 08:22:08 AM UTC 24 824219061 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.2166614519 Sep 18 08:22:06 AM UTC 24 Sep 18 08:22:08 AM UTC 24 138151705 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.3729535754 Sep 18 08:22:06 AM UTC 24 Sep 18 08:22:08 AM UTC 24 490240080 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_hard_reset.417842698 Sep 18 08:22:06 AM UTC 24 Sep 18 08:22:09 AM UTC 24 137926150 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.183037516 Sep 18 08:21:59 AM UTC 24 Sep 18 08:22:09 AM UTC 24 6589933026 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.1632367456 Sep 18 08:22:07 AM UTC 24 Sep 18 08:22:09 AM UTC 24 129496316 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.1291445038 Sep 18 08:22:07 AM UTC 24 Sep 18 08:22:10 AM UTC 24 136804139 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.3794272388 Sep 18 08:22:04 AM UTC 24 Sep 18 08:22:10 AM UTC 24 768695562 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_tl_access.3000620276 Sep 18 08:21:57 AM UTC 24 Sep 18 08:22:11 AM UTC 24 5612711792 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.2684006022 Sep 18 08:22:07 AM UTC 24 Sep 18 08:22:11 AM UTC 24 693781013 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_debug_disabled.513767001 Sep 18 08:22:08 AM UTC 24 Sep 18 08:22:11 AM UTC 24 76818809 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.975669932 Sep 18 08:22:08 AM UTC 24 Sep 18 08:22:11 AM UTC 24 379992159 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.1734050337 Sep 18 08:21:58 AM UTC 24 Sep 18 08:22:12 AM UTC 24 1835200266 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.3344127123 Sep 18 08:22:10 AM UTC 24 Sep 18 08:22:12 AM UTC 24 117507644 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_hartsel_warl.1074075957 Sep 18 08:22:10 AM UTC 24 Sep 18 08:22:12 AM UTC 24 126078063 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.467793502 Sep 18 08:22:10 AM UTC 24 Sep 18 08:22:12 AM UTC 24 69482875 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.286696430 Sep 18 08:22:11 AM UTC 24 Sep 18 08:22:13 AM UTC 24 40657562 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.1616741191 Sep 18 08:22:10 AM UTC 24 Sep 18 08:22:14 AM UTC 24 263517604 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.3317683512 Sep 18 08:22:10 AM UTC 24 Sep 18 08:22:15 AM UTC 24 3651908012 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_not_supported.709110316 Sep 18 08:22:12 AM UTC 24 Sep 18 08:22:15 AM UTC 24 214093377 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.3042585670 Sep 18 08:22:11 AM UTC 24 Sep 18 08:22:16 AM UTC 24 660946536 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_smoke.2760216350 Sep 18 08:22:11 AM UTC 24 Sep 18 08:22:16 AM UTC 24 1269337134 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.1225051302 Sep 18 08:22:11 AM UTC 24 Sep 18 08:22:16 AM UTC 24 2403376881 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_resuming.4090278561 Sep 18 08:22:14 AM UTC 24 Sep 18 08:22:16 AM UTC 24 182644158 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.3690953480 Sep 18 08:22:14 AM UTC 24 Sep 18 08:22:17 AM UTC 24 115714505 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.579521677 Sep 18 08:22:14 AM UTC 24 Sep 18 08:22:17 AM UTC 24 382063244 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_hart_unavail.2882193349 Sep 18 08:22:14 AM UTC 24 Sep 18 08:22:17 AM UTC 24 117684038 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_halted.2194342901 Sep 18 08:22:14 AM UTC 24 Sep 18 08:22:17 AM UTC 24 471807900 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_dataaddr_rw_access.383646694 Sep 18 08:22:15 AM UTC 24 Sep 18 08:22:18 AM UTC 24 57708604 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_busy.4218526577 Sep 18 08:22:12 AM UTC 24 Sep 18 08:22:18 AM UTC 24 1160245078 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_halt_resume_whereto.4190149434 Sep 18 08:22:15 AM UTC 24 Sep 18 08:22:19 AM UTC 24 231279245 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_bad_sba_tl_access.4252615307 Sep 18 08:22:12 AM UTC 24 Sep 18 08:22:19 AM UTC 24 3291607274 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_ndmreset_req.2804438647 Sep 18 08:22:16 AM UTC 24 Sep 18 08:22:19 AM UTC 24 308163931 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_rom_read_access.2415620095 Sep 18 08:22:18 AM UTC 24 Sep 18 08:22:20 AM UTC 24 93297549 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_abstractcmd_status.1346502919 Sep 18 08:22:17 AM UTC 24 Sep 18 08:22:20 AM UTC 24 191434207 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.89391562 Sep 18 08:22:17 AM UTC 24 Sep 18 08:22:21 AM UTC 24 325591639 ps
T117 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.741479487 Sep 18 08:21:58 AM UTC 24 Sep 18 08:22:21 AM UTC 24 5135857725 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.2192247147 Sep 18 08:22:17 AM UTC 24 Sep 18 08:22:21 AM UTC 24 212539529 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_buffered_enable.1154237928 Sep 18 08:22:19 AM UTC 24 Sep 18 08:22:21 AM UTC 24 422231731 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_debug_disabled.988331945 Sep 18 08:22:19 AM UTC 24 Sep 18 08:22:21 AM UTC 24 58470707 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.1801367338 Sep 18 08:21:56 AM UTC 24 Sep 18 08:22:22 AM UTC 24 10195162086 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_hard_reset.557052506 Sep 18 08:22:17 AM UTC 24 Sep 18 08:22:22 AM UTC 24 429896728 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_progbuf_read_write_execute.650124107 Sep 18 08:22:18 AM UTC 24 Sep 18 08:22:22 AM UTC 24 1035168518 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.1165409235 Sep 18 08:22:20 AM UTC 24 Sep 18 08:22:22 AM UTC 24 45605434 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.1688878106 Sep 18 08:22:19 AM UTC 24 Sep 18 08:22:22 AM UTC 24 236071738 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_debug_disabled.2011927674 Sep 18 08:22:16 AM UTC 24 Sep 18 08:22:22 AM UTC 24 3133714994 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_tl_access.2738323609 Sep 18 08:22:11 AM UTC 24 Sep 18 08:22:23 AM UTC 24 2078358526 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_idle_hint.2771100128 Sep 18 08:22:17 AM UTC 24 Sep 18 08:22:24 AM UTC 24 653962644 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_alert_test.309431855 Sep 18 08:22:21 AM UTC 24 Sep 18 08:22:24 AM UTC 24 106742877 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.3567864415 Sep 18 08:22:23 AM UTC 24 Sep 18 08:22:25 AM UTC 24 124370185 ps
T84 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_sec_cm.518497424 Sep 18 08:22:21 AM UTC 24 Sep 18 08:22:26 AM UTC 24 508405831 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.1056915728 Sep 18 08:22:23 AM UTC 24 Sep 18 08:22:26 AM UTC 24 298585356 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/4.rv_dm_sec_cm.1224593081 Sep 18 08:22:35 AM UTC 24 Sep 18 08:22:38 AM UTC 24 371828483 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/2.rv_dm_sparse_lc_gate_fsm.2147937252 Sep 18 08:22:24 AM UTC 24 Sep 18 08:22:27 AM UTC 24 137584612 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.379507489 Sep 18 08:22:25 AM UTC 24 Sep 18 08:22:27 AM UTC 24 45036926 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.1453599850 Sep 18 08:22:20 AM UTC 24 Sep 18 08:22:29 AM UTC 24 2690364599 ps
T118 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.2333850749 Sep 18 08:22:22 AM UTC 24 Sep 18 08:22:29 AM UTC 24 5343047742 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/3.rv_dm_hart_unavail.656657871 Sep 18 08:22:27 AM UTC 24 Sep 18 08:22:29 AM UTC 24 135076883 ps
T136 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.2085765910 Sep 18 08:22:26 AM UTC 24 Sep 18 08:22:30 AM UTC 24 1008497037 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.1695343093 Sep 18 08:22:25 AM UTC 24 Sep 18 08:22:30 AM UTC 24 983157201 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.3327768064 Sep 18 08:22:27 AM UTC 24 Sep 18 08:22:31 AM UTC 24 865531964 ps
T138 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.3967804668 Sep 18 08:22:28 AM UTC 24 Sep 18 08:22:31 AM UTC 24 162091059 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.475551511 Sep 18 08:22:28 AM UTC 24 Sep 18 08:22:31 AM UTC 24 253903723 ps
T143 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.616222486 Sep 18 08:22:30 AM UTC 24 Sep 18 08:22:32 AM UTC 24 160607610 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/3.rv_dm_sec_cm.1360383682 Sep 18 08:22:30 AM UTC 24 Sep 18 08:22:33 AM UTC 24 278234423 ps
T137 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/4.rv_dm_sba_tl_access.167794809 Sep 18 08:22:31 AM UTC 24 Sep 18 08:22:34 AM UTC 24 1110856612 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.3563701273 Sep 18 08:22:23 AM UTC 24 Sep 18 08:22:34 AM UTC 24 7956195637 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.2238339254 Sep 18 08:22:32 AM UTC 24 Sep 18 08:22:35 AM UTC 24 965657816 ps
T145 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.3044170499 Sep 18 08:22:32 AM UTC 24 Sep 18 08:22:35 AM UTC 24 165786179 ps
T146 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/4.rv_dm_buffered_enable.74852038 Sep 18 08:22:32 AM UTC 24 Sep 18 08:22:36 AM UTC 24 362222139 ps
T147 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/4.rv_dm_alert_test.2237081692 Sep 18 08:22:36 AM UTC 24 Sep 18 08:22:38 AM UTC 24 49265183 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.3396496026 Sep 18 08:22:28 AM UTC 24 Sep 18 08:22:38 AM UTC 24 4890928454 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.2196047051 Sep 18 08:22:33 AM UTC 24 Sep 18 08:22:40 AM UTC 24 2754358418 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.3444705276 Sep 18 08:22:36 AM UTC 24 Sep 18 08:22:40 AM UTC 24 941187159 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.2628427355 Sep 18 08:22:26 AM UTC 24 Sep 18 08:22:40 AM UTC 24 8178699423 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.3965263640 Sep 18 08:22:21 AM UTC 24 Sep 18 08:22:41 AM UTC 24 6556269344 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/4.rv_dm_autoincr_sba_tl_access.1201064164 Sep 18 08:22:32 AM UTC 24 Sep 18 08:22:42 AM UTC 24 4200787435 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/5.rv_dm_halt_resume_whereto.2896786227 Sep 18 08:22:39 AM UTC 24 Sep 18 08:22:42 AM UTC 24 594981374 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3389670700 Sep 18 08:22:31 AM UTC 24 Sep 18 08:22:42 AM UTC 24 1803993491 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/10.rv_dm_stress_all.3432972060 Sep 18 08:23:02 AM UTC 24 Sep 18 08:23:17 AM UTC 24 3933592210 ps
T250 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/5.rv_dm_sba_tl_access.935583416 Sep 18 08:22:36 AM UTC 24 Sep 18 08:22:42 AM UTC 24 3175586997 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/5.rv_dm_buffered_enable.641939754 Sep 18 08:22:39 AM UTC 24 Sep 18 08:22:42 AM UTC 24 147934685 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.2333279724 Sep 18 08:22:26 AM UTC 24 Sep 18 08:22:43 AM UTC 24 17351979776 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/5.rv_dm_alert_test.2501618869 Sep 18 08:22:42 AM UTC 24 Sep 18 08:22:44 AM UTC 24 246202964 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.2792875464 Sep 18 08:22:40 AM UTC 24 Sep 18 08:22:44 AM UTC 24 2085739243 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/6.rv_dm_sba_tl_access.2080794956 Sep 18 08:22:42 AM UTC 24 Sep 18 08:22:45 AM UTC 24 1307295414 ps
T217 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all.1572477249 Sep 18 08:22:24 AM UTC 24 Sep 18 08:22:45 AM UTC 24 3330805903 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/6.rv_dm_halt_resume_whereto.1666819075 Sep 18 08:22:43 AM UTC 24 Sep 18 08:22:46 AM UTC 24 220515623 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/6.rv_dm_alert_test.1978784730 Sep 18 08:22:43 AM UTC 24 Sep 18 08:22:46 AM UTC 24 120989984 ps
T251 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.3175690757 Sep 18 08:22:26 AM UTC 24 Sep 18 08:22:47 AM UTC 24 13996530463 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/6.rv_dm_buffered_enable.1341674395 Sep 18 08:22:43 AM UTC 24 Sep 18 08:22:48 AM UTC 24 657413597 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.1469661520 Sep 18 08:22:46 AM UTC 24 Sep 18 08:22:48 AM UTC 24 420103197 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/7.rv_dm_buffered_enable.2679035440 Sep 18 08:22:47 AM UTC 24 Sep 18 08:22:50 AM UTC 24 505902936 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/7.rv_dm_sba_tl_access.3404942750 Sep 18 08:22:44 AM UTC 24 Sep 18 08:22:50 AM UTC 24 1477117661 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/6.rv_dm_bad_sba_tl_access.2316859912 Sep 18 08:22:43 AM UTC 24 Sep 18 08:22:50 AM UTC 24 1498152547 ps
T246 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/7.rv_dm_alert_test.1448818686 Sep 18 08:22:48 AM UTC 24 Sep 18 08:22:50 AM UTC 24 131646549 ps
T252 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.1902198211 Sep 18 08:22:37 AM UTC 24 Sep 18 08:22:50 AM UTC 24 11834967380 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all.3809265100 Sep 18 08:22:43 AM UTC 24 Sep 18 08:22:51 AM UTC 24 4011911335 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all.352277059 Sep 18 08:22:47 AM UTC 24 Sep 18 08:22:52 AM UTC 24 3594270162 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/8.rv_dm_buffered_enable.3609683525 Sep 18 08:22:51 AM UTC 24 Sep 18 08:22:54 AM UTC 24 110600545 ps
T248 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/8.rv_dm_alert_test.2802533270 Sep 18 08:22:53 AM UTC 24 Sep 18 08:22:55 AM UTC 24 84554828 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.2916001824 Sep 18 08:22:44 AM UTC 24 Sep 18 08:22:57 AM UTC 24 6247346950 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/16.rv_dm_alert_test.2128946644 Sep 18 08:23:17 AM UTC 24 Sep 18 08:23:19 AM UTC 24 268031927 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/8.rv_dm_bad_sba_tl_access.2027307464 Sep 18 08:22:50 AM UTC 24 Sep 18 08:22:58 AM UTC 24 2765222911 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/8.rv_dm_sba_tl_access.1779922436 Sep 18 08:22:49 AM UTC 24 Sep 18 08:22:59 AM UTC 24 5105034304 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/9.rv_dm_buffered_enable.1269523862 Sep 18 08:22:56 AM UTC 24 Sep 18 08:22:59 AM UTC 24 189569627 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.758381901 Sep 18 08:22:46 AM UTC 24 Sep 18 08:22:59 AM UTC 24 3578305646 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/14.rv_dm_stress_all.1661462178 Sep 18 08:23:11 AM UTC 24 Sep 18 08:23:20 AM UTC 24 1846317205 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.3212527864 Sep 18 08:22:20 AM UTC 24 Sep 18 08:23:00 AM UTC 24 10532101697 ps
T119 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.2848848303 Sep 18 08:22:38 AM UTC 24 Sep 18 08:23:01 AM UTC 24 23739166067 ps
T120 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.3035684213 Sep 18 08:22:59 AM UTC 24 Sep 18 08:23:01 AM UTC 24 84936260 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.1998448201 Sep 18 08:22:25 AM UTC 24 Sep 18 08:23:03 AM UTC 24 2336975364 ps
T121 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.1927369652 Sep 18 08:22:43 AM UTC 24 Sep 18 08:23:04 AM UTC 24 11692994272 ps
T122 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/10.rv_dm_alert_test.949887734 Sep 18 08:23:02 AM UTC 24 Sep 18 08:23:04 AM UTC 24 109072872 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.3396707289 Sep 18 08:22:58 AM UTC 24 Sep 18 08:23:04 AM UTC 24 2768933528 ps
T123 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.2219057057 Sep 18 08:22:46 AM UTC 24 Sep 18 08:23:04 AM UTC 24 21556441757 ps
T124 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/10.rv_dm_bad_sba_tl_access.37838061 Sep 18 08:23:00 AM UTC 24 Sep 18 08:23:05 AM UTC 24 2996535225 ps
T125 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.138918340 Sep 18 08:22:54 AM UTC 24 Sep 18 08:23:05 AM UTC 24 3563841838 ps
T178 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/9.rv_dm_autoincr_sba_tl_access.3828256049 Sep 18 08:22:56 AM UTC 24 Sep 18 08:23:05 AM UTC 24 4033365606 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.3638609250 Sep 18 08:22:55 AM UTC 24 Sep 18 08:23:05 AM UTC 24 2640939316 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.3241131723 Sep 18 08:22:51 AM UTC 24 Sep 18 08:23:06 AM UTC 24 4183737015 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/11.rv_dm_alert_test.1003095574 Sep 18 08:23:06 AM UTC 24 Sep 18 08:23:08 AM UTC 24 67048880 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.1265998099 Sep 18 08:22:28 AM UTC 24 Sep 18 08:23:08 AM UTC 24 3556803336 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.3583080216 Sep 18 08:22:10 AM UTC 24 Sep 18 08:23:09 AM UTC 24 21550358369 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/12.rv_dm_alert_test.3220023811 Sep 18 08:23:07 AM UTC 24 Sep 18 08:23:09 AM UTC 24 42418687 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/12.rv_dm_bad_sba_tl_access.1895022672 Sep 18 08:23:06 AM UTC 24 Sep 18 08:23:09 AM UTC 24 1405533898 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/6.rv_dm_autoincr_sba_tl_access.205063797 Sep 18 08:22:43 AM UTC 24 Sep 18 08:23:09 AM UTC 24 12886928425 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/11.rv_dm_sba_tl_access.1516798605 Sep 18 08:23:04 AM UTC 24 Sep 18 08:23:10 AM UTC 24 1180528675 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.3158000888 Sep 18 08:23:06 AM UTC 24 Sep 18 08:23:10 AM UTC 24 1495987908 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/12.rv_dm_sba_tl_access.3828159201 Sep 18 08:23:06 AM UTC 24 Sep 18 08:23:11 AM UTC 24 2295495894 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/12.rv_dm_stress_all.1706868326 Sep 18 08:23:07 AM UTC 24 Sep 18 08:23:11 AM UTC 24 2303768164 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/11.rv_dm_stress_all.724261293 Sep 18 08:23:06 AM UTC 24 Sep 18 08:23:12 AM UTC 24 3240069144 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/13.rv_dm_alert_test.3065201410 Sep 18 08:23:10 AM UTC 24 Sep 18 08:23:12 AM UTC 24 54603220 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.2416536280 Sep 18 08:23:08 AM UTC 24 Sep 18 08:23:12 AM UTC 24 2845005741 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/14.rv_dm_alert_test.3819008951 Sep 18 08:23:11 AM UTC 24 Sep 18 08:23:13 AM UTC 24 61042449 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.2366620344 Sep 18 08:23:04 AM UTC 24 Sep 18 08:23:13 AM UTC 24 3593229543 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/14.rv_dm_sba_tl_access.4280371289 Sep 18 08:23:10 AM UTC 24 Sep 18 08:23:15 AM UTC 24 3630393355 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/10.rv_dm_autoincr_sba_tl_access.1773337158 Sep 18 08:23:01 AM UTC 24 Sep 18 08:23:16 AM UTC 24 12441303629 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.4048632335 Sep 18 08:22:53 AM UTC 24 Sep 18 08:23:16 AM UTC 24 5312809373 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/13.rv_dm_autoincr_sba_tl_access.928418534 Sep 18 08:23:10 AM UTC 24 Sep 18 08:23:16 AM UTC 24 2037952365 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/14.rv_dm_autoincr_sba_tl_access.3915638472 Sep 18 08:23:11 AM UTC 24 Sep 18 08:23:16 AM UTC 24 5167786933 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.2073743033 Sep 18 08:22:49 AM UTC 24 Sep 18 08:23:17 AM UTC 24 6450982894 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/15.rv_dm_alert_test.2157241561 Sep 18 08:23:15 AM UTC 24 Sep 18 08:23:17 AM UTC 24 110391472 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.1433358727 Sep 18 08:23:00 AM UTC 24 Sep 18 08:23:17 AM UTC 24 4126286049 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/13.rv_dm_bad_sba_tl_access.1895370619 Sep 18 08:23:10 AM UTC 24 Sep 18 08:23:17 AM UTC 24 13554760452 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.2020817642 Sep 18 08:22:41 AM UTC 24 Sep 18 08:23:18 AM UTC 24 13271368367 ps
T111 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.2941250114 Sep 18 08:22:35 AM UTC 24 Sep 18 08:23:19 AM UTC 24 3356237523 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/15.rv_dm_bad_sba_tl_access.1846265227 Sep 18 08:23:14 AM UTC 24 Sep 18 08:23:21 AM UTC 24 1732179388 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.546061849 Sep 18 08:23:11 AM UTC 24 Sep 18 08:23:22 AM UTC 24 4770502943 ps
T218 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/17.rv_dm_stress_all.514813464 Sep 18 08:23:19 AM UTC 24 Sep 18 08:23:22 AM UTC 24 602218091 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/17.rv_dm_alert_test.1766438167 Sep 18 08:23:20 AM UTC 24 Sep 18 08:23:22 AM UTC 24 62242766 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/17.rv_dm_autoincr_sba_tl_access.2480147126 Sep 18 08:23:19 AM UTC 24 Sep 18 08:23:23 AM UTC 24 2171712043 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/10.rv_dm_sba_tl_access.3803189421 Sep 18 08:23:00 AM UTC 24 Sep 18 08:23:24 AM UTC 24 6464002558 ps
T219 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/16.rv_dm_stress_all.1472759742 Sep 18 08:23:17 AM UTC 24 Sep 18 08:23:24 AM UTC 24 6696827321 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/18.rv_dm_alert_test.3171243965 Sep 18 08:23:22 AM UTC 24 Sep 18 08:23:24 AM UTC 24 51654182 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/18.rv_dm_sba_tl_access.2805138928 Sep 18 08:23:20 AM UTC 24 Sep 18 08:23:25 AM UTC 24 4850448254 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/17.rv_dm_bad_sba_tl_access.871740796 Sep 18 08:23:19 AM UTC 24 Sep 18 08:23:25 AM UTC 24 3124433223 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.1615872924 Sep 18 08:23:20 AM UTC 24 Sep 18 08:23:25 AM UTC 24 4886843964 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/16.rv_dm_sba_tl_access.1270548068 Sep 18 08:23:15 AM UTC 24 Sep 18 08:23:26 AM UTC 24 6402394134 ps
T211 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/13.rv_dm_stress_all.4074677745 Sep 18 08:23:10 AM UTC 24 Sep 18 08:23:27 AM UTC 24 3071192594 ps
T112 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.1250731543 Sep 18 08:22:47 AM UTC 24 Sep 18 08:23:27 AM UTC 24 1419150611 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/19.rv_dm_sba_tl_access.1755108419 Sep 18 08:23:22 AM UTC 24 Sep 18 08:23:27 AM UTC 24 873521019 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/19.rv_dm_alert_test.3934543748 Sep 18 08:23:25 AM UTC 24 Sep 18 08:23:27 AM UTC 24 69698753 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/21.rv_dm_alert_test.1393595113 Sep 18 08:23:26 AM UTC 24 Sep 18 08:23:28 AM UTC 24 84913037 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/20.rv_dm_alert_test.3546026182 Sep 18 08:23:26 AM UTC 24 Sep 18 08:23:29 AM UTC 24 134933311 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.3671958679 Sep 18 08:23:19 AM UTC 24 Sep 18 08:23:29 AM UTC 24 6702396434 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/21.rv_dm_stress_all.2780187559 Sep 18 08:23:26 AM UTC 24 Sep 18 08:23:29 AM UTC 24 2457267810 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.3080120579 Sep 18 08:23:24 AM UTC 24 Sep 18 08:23:30 AM UTC 24 1261125442 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.3502142892 Sep 18 08:23:16 AM UTC 24 Sep 18 08:23:30 AM UTC 24 3279541152 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/18.rv_dm_bad_sba_tl_access.4095143935 Sep 18 08:23:20 AM UTC 24 Sep 18 08:23:30 AM UTC 24 5244508957 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/23.rv_dm_alert_test.2169573138 Sep 18 08:23:29 AM UTC 24 Sep 18 08:23:31 AM UTC 24 36029308 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/22.rv_dm_alert_test.2610855546 Sep 18 08:23:29 AM UTC 24 Sep 18 08:23:31 AM UTC 24 159307220 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.1399566575 Sep 18 08:23:12 AM UTC 24 Sep 18 08:23:31 AM UTC 24 3798073597 ps
T212 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.635505769 Sep 18 08:23:27 AM UTC 24 Sep 18 08:23:31 AM UTC 24 2433083224 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/15.rv_dm_stress_all.3644253677 Sep 18 08:23:15 AM UTC 24 Sep 18 08:23:31 AM UTC 24 6821034738 ps
T210 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/18.rv_dm_stress_all.4121395848 Sep 18 08:23:22 AM UTC 24 Sep 18 08:23:32 AM UTC 24 2697539981 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/24.rv_dm_alert_test.674684113 Sep 18 08:23:30 AM UTC 24 Sep 18 08:23:32 AM UTC 24 67509046 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/17.rv_dm_sba_tl_access.824836730 Sep 18 08:23:19 AM UTC 24 Sep 18 08:23:32 AM UTC 24 3155806099 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/25.rv_dm_alert_test.3081861197 Sep 18 08:23:30 AM UTC 24 Sep 18 08:23:32 AM UTC 24 53297151 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.2857338516 Sep 18 08:23:26 AM UTC 24 Sep 18 08:23:32 AM UTC 24 3955100586 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/11.rv_dm_bad_sba_tl_access.3410656400 Sep 18 08:23:04 AM UTC 24 Sep 18 08:23:32 AM UTC 24 6306532825 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/4.rv_dm_bad_sba_tl_access.1141312736 Sep 18 08:22:31 AM UTC 24 Sep 18 08:23:33 AM UTC 24 14814139808 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/26.rv_dm_alert_test.3459642158 Sep 18 08:23:31 AM UTC 24 Sep 18 08:23:33 AM UTC 24 80350294 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/27.rv_dm_alert_test.3504927903 Sep 18 08:23:31 AM UTC 24 Sep 18 08:23:34 AM UTC 24 111036413 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/28.rv_dm_alert_test.3913052795 Sep 18 08:23:33 AM UTC 24 Sep 18 08:23:35 AM UTC 24 89314848 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/23.rv_dm_stress_all.3386367989 Sep 18 08:23:29 AM UTC 24 Sep 18 08:23:35 AM UTC 24 2460337218 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.1330573241 Sep 18 08:22:52 AM UTC 24 Sep 18 08:23:35 AM UTC 24 2796916430 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/29.rv_dm_alert_test.3029155933 Sep 18 08:23:33 AM UTC 24 Sep 18 08:23:35 AM UTC 24 79658126 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/13.rv_dm_sba_tl_access.2092440195 Sep 18 08:23:07 AM UTC 24 Sep 18 08:23:35 AM UTC 24 10533584476 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/31.rv_dm_alert_test.783783499 Sep 18 08:23:33 AM UTC 24 Sep 18 08:23:35 AM UTC 24 42832632 ps
T220 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/28.rv_dm_stress_all.3735717216 Sep 18 08:23:31 AM UTC 24 Sep 18 08:23:35 AM UTC 24 991898592 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/19.rv_dm_bad_sba_tl_access.3224885470 Sep 18 08:23:25 AM UTC 24 Sep 18 08:23:35 AM UTC 24 2295211982 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/30.rv_dm_alert_test.2140863108 Sep 18 08:23:33 AM UTC 24 Sep 18 08:23:35 AM UTC 24 98781271 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/33.rv_dm_alert_test.1916814683 Sep 18 08:23:34 AM UTC 24 Sep 18 08:23:36 AM UTC 24 62230707 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/32.rv_dm_alert_test.2712350972 Sep 18 08:23:34 AM UTC 24 Sep 18 08:23:37 AM UTC 24 51324796 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all_with_rand_reset.2422153887 Sep 18 08:22:43 AM UTC 24 Sep 18 08:23:37 AM UTC 24 30872543323 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/14.rv_dm_bad_sba_tl_access.3953601729 Sep 18 08:23:11 AM UTC 24 Sep 18 08:23:37 AM UTC 24 5665768190 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/38.rv_dm_alert_test.3403330921 Sep 18 08:23:36 AM UTC 24 Sep 18 08:23:38 AM UTC 24 149282446 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/35.rv_dm_alert_test.1864158067 Sep 18 08:23:36 AM UTC 24 Sep 18 08:23:38 AM UTC 24 188380729 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/36.rv_dm_alert_test.1262662729 Sep 18 08:23:36 AM UTC 24 Sep 18 08:23:38 AM UTC 24 116092305 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/34.rv_dm_alert_test.1600338968 Sep 18 08:23:36 AM UTC 24 Sep 18 08:23:38 AM UTC 24 47370669 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.2043190622 Sep 18 08:23:33 AM UTC 24 Sep 18 08:23:38 AM UTC 24 1025221805 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/37.rv_dm_alert_test.521578554 Sep 18 08:23:36 AM UTC 24 Sep 18 08:23:38 AM UTC 24 105761934 ps
T207 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.4116297597 Sep 18 08:23:30 AM UTC 24 Sep 18 08:23:38 AM UTC 24 3291097747 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/24.rv_dm_stress_all.992834918 Sep 18 08:23:30 AM UTC 24 Sep 18 08:23:38 AM UTC 24 2324076255 ps
T116 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.264522050 Sep 18 08:22:58 AM UTC 24 Sep 18 08:23:39 AM UTC 24 2331074182 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.3787564271 Sep 18 08:23:34 AM UTC 24 Sep 18 08:23:39 AM UTC 24 1721350992 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/29.rv_dm_stress_all.4271998915 Sep 18 08:23:33 AM UTC 24 Sep 18 08:23:39 AM UTC 24 4145344651 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/40.rv_dm_alert_test.2330492113 Sep 18 08:23:38 AM UTC 24 Sep 18 08:23:40 AM UTC 24 129587866 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/15.rv_dm_sba_tl_access.3617729425 Sep 18 08:23:12 AM UTC 24 Sep 18 08:23:40 AM UTC 24 4689919719 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/39.rv_dm_alert_test.2943443288 Sep 18 08:23:38 AM UTC 24 Sep 18 08:23:40 AM UTC 24 46928584 ps
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T225 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/34.rv_dm_stress_all.3813655582 Sep 18 08:23:35 AM UTC 24 Sep 18 08:23:40 AM UTC 24 4826137269 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/16.rv_dm_bad_sba_tl_access.2668510854 Sep 18 08:23:17 AM UTC 24 Sep 18 08:23:41 AM UTC 24 7443695887 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/31.rv_dm_stress_all.2835066801 Sep 18 08:23:33 AM UTC 24 Sep 18 08:23:41 AM UTC 24 3010591749 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/16.rv_dm_autoincr_sba_tl_access.1064586821 Sep 18 08:23:17 AM UTC 24 Sep 18 08:23:41 AM UTC 24 6660779251 ps
T312 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/44.rv_dm_alert_test.1726528443 Sep 18 08:23:39 AM UTC 24 Sep 18 08:23:42 AM UTC 24 65326291 ps
T313 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/37.rv_dm_stress_all.4144223393 Sep 18 08:23:36 AM UTC 24 Sep 18 08:23:41 AM UTC 24 1388469140 ps
T216 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/39.rv_dm_stress_all.1552538833 Sep 18 08:23:37 AM UTC 24 Sep 18 08:23:41 AM UTC 24 4238439596 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/42.rv_dm_alert_test.656891226 Sep 18 08:23:39 AM UTC 24 Sep 18 08:23:41 AM UTC 24 70048386 ps
T214 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/32.rv_dm_stress_all.3492892616 Sep 18 08:23:33 AM UTC 24 Sep 18 08:23:42 AM UTC 24 1971398024 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/41.rv_dm_alert_test.2015102341 Sep 18 08:23:39 AM UTC 24 Sep 18 08:23:42 AM UTC 24 135749180 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/43.rv_dm_alert_test.1720525358 Sep 18 08:23:39 AM UTC 24 Sep 18 08:23:42 AM UTC 24 147038942 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.2325959464 Sep 18 08:23:31 AM UTC 24 Sep 18 08:23:42 AM UTC 24 8579417503 ps
T317 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/45.rv_dm_alert_test.866655392 Sep 18 08:23:41 AM UTC 24 Sep 18 08:23:43 AM UTC 24 38795786 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/47.rv_dm_alert_test.2744312651 Sep 18 08:23:41 AM UTC 24 Sep 18 08:23:43 AM UTC 24 147957629 ps
T319 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/48.rv_dm_alert_test.3489208779 Sep 18 08:23:41 AM UTC 24 Sep 18 08:23:43 AM UTC 24 43491217 ps
T320 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/46.rv_dm_alert_test.3220033595 Sep 18 08:23:41 AM UTC 24 Sep 18 08:23:43 AM UTC 24 50773769 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/43.rv_dm_stress_all.2101260076 Sep 18 08:23:39 AM UTC 24 Sep 18 08:23:43 AM UTC 24 2764440257 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/38.rv_dm_stress_all.4155924842 Sep 18 08:23:36 AM UTC 24 Sep 18 08:23:44 AM UTC 24 4861654450 ps
T321 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.4181966171 Sep 18 08:23:39 AM UTC 24 Sep 18 08:23:45 AM UTC 24 2922248474 ps
T322 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/49.rv_dm_alert_test.857930173 Sep 18 08:23:43 AM UTC 24 Sep 18 08:23:45 AM UTC 24 38158694 ps
T323 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/40.rv_dm_stress_all.1712277613 Sep 18 08:23:38 AM UTC 24 Sep 18 08:23:45 AM UTC 24 6773077069 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.2288676505 Sep 18 08:23:25 AM UTC 24 Sep 18 08:23:46 AM UTC 24 5897743266 ps
T215 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/47.rv_dm_stress_all.2402833152 Sep 18 08:23:41 AM UTC 24 Sep 18 08:23:46 AM UTC 24 3832241124 ps
T324 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/48.rv_dm_stress_all.644214396 Sep 18 08:23:41 AM UTC 24 Sep 18 08:23:47 AM UTC 24 2160066848 ps
T325 /workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/coverage/default/45.rv_dm_stress_all.3637299827 Sep 18 08:23:41 AM UTC 24 Sep 18 08:23:47 AM UTC 24 3947969917 ps
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