Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.01 96.34 90.10 92.10 93.33 90.27 98.63 55.30


Total test records in report: 483
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T331 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/4.rv_dm_autoincr_sba_tl_access.2451691095 Sep 24 08:13:27 AM UTC 24 Sep 24 08:14:46 AM UTC 24 81825132822 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/49.rv_dm_stress_all.3379463969 Sep 24 08:14:31 AM UTC 24 Sep 24 08:14:46 AM UTC 24 4492359063 ps
T332 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/40.rv_dm_stress_all.940003047 Sep 24 08:14:26 AM UTC 24 Sep 24 08:14:47 AM UTC 24 3742579010 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/47.rv_dm_stress_all.584177720 Sep 24 08:14:30 AM UTC 24 Sep 24 08:14:50 AM UTC 24 4118768060 ps
T333 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/16.rv_dm_bad_sba_tl_access.1903326950 Sep 24 08:14:04 AM UTC 24 Sep 24 08:14:52 AM UTC 24 16197684719 ps
T126 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.2549712033 Sep 24 08:13:42 AM UTC 24 Sep 24 08:14:55 AM UTC 24 30999879189 ps
T334 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/38.rv_dm_stress_all.1225037148 Sep 24 08:14:25 AM UTC 24 Sep 24 08:15:00 AM UTC 24 7453565996 ps
T127 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.285578787 Sep 24 08:13:19 AM UTC 24 Sep 24 08:15:00 AM UTC 24 25223315409 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.822862323 Sep 24 08:13:40 AM UTC 24 Sep 24 08:15:05 AM UTC 24 17317565416 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.475415491 Sep 24 08:13:33 AM UTC 24 Sep 24 08:15:10 AM UTC 24 15467441440 ps
T335 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.2585059126 Sep 24 08:14:13 AM UTC 24 Sep 24 08:16:21 AM UTC 24 70234306664 ps
T207 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/18.rv_dm_autoincr_sba_tl_access.1740311895 Sep 24 08:14:12 AM UTC 24 Sep 24 08:17:09 AM UTC 24 69654798411 ps
T224 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/17.rv_dm_autoincr_sba_tl_access.872519223 Sep 24 08:14:11 AM UTC 24 Sep 24 08:21:08 AM UTC 24 127487762712 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3139060990 Sep 24 08:10:26 AM UTC 24 Sep 24 08:10:29 AM UTC 24 326403460 ps
T111 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.526974645 Sep 24 08:10:26 AM UTC 24 Sep 24 08:10:29 AM UTC 24 568677266 ps
T336 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.228172484 Sep 24 08:10:27 AM UTC 24 Sep 24 08:10:31 AM UTC 24 2627976947 ps
T112 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1342183260 Sep 24 08:10:27 AM UTC 24 Sep 24 08:10:31 AM UTC 24 565546638 ps
T337 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2026568347 Sep 24 08:10:30 AM UTC 24 Sep 24 08:10:32 AM UTC 24 161750655 ps
T338 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.3639418251 Sep 24 08:10:29 AM UTC 24 Sep 24 08:10:32 AM UTC 24 81678441 ps
T339 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3840402605 Sep 24 08:10:27 AM UTC 24 Sep 24 08:10:33 AM UTC 24 3981426251 ps
T133 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.747718555 Sep 24 08:10:30 AM UTC 24 Sep 24 08:10:33 AM UTC 24 94096420 ps
T134 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.2498516073 Sep 24 08:10:30 AM UTC 24 Sep 24 08:10:34 AM UTC 24 119433481 ps
T340 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.576871551 Sep 24 08:10:33 AM UTC 24 Sep 24 08:10:35 AM UTC 24 220260355 ps
T177 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.1063627018 Sep 24 08:10:28 AM UTC 24 Sep 24 08:10:37 AM UTC 24 813268250 ps
T135 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2697618616 Sep 24 08:10:31 AM UTC 24 Sep 24 08:10:37 AM UTC 24 277475233 ps
T341 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.4194988201 Sep 24 08:10:33 AM UTC 24 Sep 24 08:10:38 AM UTC 24 906969771 ps
T118 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3425698192 Sep 24 08:10:32 AM UTC 24 Sep 24 08:10:37 AM UTC 24 380620154 ps
T342 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.888695741 Sep 24 08:10:34 AM UTC 24 Sep 24 08:10:43 AM UTC 24 2127440815 ps
T343 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2649318884 Sep 24 08:10:36 AM UTC 24 Sep 24 08:10:44 AM UTC 24 1565118365 ps
T344 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.2060491372 Sep 24 08:10:44 AM UTC 24 Sep 24 08:10:46 AM UTC 24 66127479 ps
T345 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1542051472 Sep 24 08:10:44 AM UTC 24 Sep 24 08:10:46 AM UTC 24 105379333 ps
T346 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.3895514253 Sep 24 08:10:38 AM UTC 24 Sep 24 08:10:47 AM UTC 24 230400388 ps
T136 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.4158521672 Sep 24 08:10:45 AM UTC 24 Sep 24 08:10:49 AM UTC 24 364068506 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.990710749 Sep 24 08:10:28 AM UTC 24 Sep 24 08:10:50 AM UTC 24 3126865453 ps
T137 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.2562475211 Sep 24 08:10:47 AM UTC 24 Sep 24 08:10:51 AM UTC 24 146740489 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3006080028 Sep 24 08:10:28 AM UTC 24 Sep 24 08:10:51 AM UTC 24 2275884730 ps
T347 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1694490332 Sep 24 08:10:36 AM UTC 24 Sep 24 08:10:52 AM UTC 24 2268525968 ps
T120 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2509753782 Sep 24 08:10:50 AM UTC 24 Sep 24 08:10:54 AM UTC 24 87021858 ps
T348 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1205193448 Sep 24 08:10:52 AM UTC 24 Sep 24 08:10:55 AM UTC 24 177535910 ps
T349 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3433278348 Sep 24 08:10:52 AM UTC 24 Sep 24 08:10:55 AM UTC 24 486034427 ps
T138 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2912478600 Sep 24 08:10:48 AM UTC 24 Sep 24 08:10:55 AM UTC 24 255560167 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3881069757 Sep 24 08:10:38 AM UTC 24 Sep 24 08:10:57 AM UTC 24 3048040283 ps
T350 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2074197996 Sep 24 08:10:27 AM UTC 24 Sep 24 08:10:58 AM UTC 24 17786514396 ps
T351 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1836184163 Sep 24 08:10:55 AM UTC 24 Sep 24 08:11:00 AM UTC 24 539551623 ps
T352 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1638014953 Sep 24 08:10:55 AM UTC 24 Sep 24 08:11:04 AM UTC 24 1140365809 ps
T353 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1365823638 Sep 24 08:10:34 AM UTC 24 Sep 24 08:11:05 AM UTC 24 17827642524 ps
T354 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_errors.4243270189 Sep 24 08:10:58 AM UTC 24 Sep 24 08:11:05 AM UTC 24 151197810 ps
T355 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1681971160 Sep 24 08:10:55 AM UTC 24 Sep 24 08:11:06 AM UTC 24 6244079512 ps
T356 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_walk.2240569107 Sep 24 08:11:05 AM UTC 24 Sep 24 08:11:07 AM UTC 24 71753711 ps
T357 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1367449801 Sep 24 08:11:05 AM UTC 24 Sep 24 08:11:07 AM UTC 24 115323631 ps
T139 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1087177560 Sep 24 08:11:06 AM UTC 24 Sep 24 08:11:09 AM UTC 24 253233530 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_rw.2191509138 Sep 24 08:11:06 AM UTC 24 Sep 24 08:11:10 AM UTC 24 118019487 ps
T358 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.4266658578 Sep 24 08:10:55 AM UTC 24 Sep 24 08:11:10 AM UTC 24 9051241520 ps
T147 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.440291546 Sep 24 08:10:35 AM UTC 24 Sep 24 08:11:13 AM UTC 24 6223939891 ps
T116 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3722677731 Sep 24 08:11:08 AM UTC 24 Sep 24 08:11:13 AM UTC 24 301691827 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1176814563 Sep 24 08:10:26 AM UTC 24 Sep 24 08:11:13 AM UTC 24 3445487926 ps
T359 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3581810012 Sep 24 08:11:10 AM UTC 24 Sep 24 08:11:14 AM UTC 24 604715314 ps
T360 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3449054579 Sep 24 08:11:11 AM UTC 24 Sep 24 08:11:14 AM UTC 24 965543328 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.617007894 Sep 24 08:11:01 AM UTC 24 Sep 24 08:11:15 AM UTC 24 585247549 ps
T361 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.643902632 Sep 24 08:11:10 AM UTC 24 Sep 24 08:11:17 AM UTC 24 843223366 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.872616878 Sep 24 08:11:07 AM UTC 24 Sep 24 08:11:18 AM UTC 24 298740679 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3594077767 Sep 24 08:10:32 AM UTC 24 Sep 24 08:11:19 AM UTC 24 8319130497 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.1660621989 Sep 24 08:10:38 AM UTC 24 Sep 24 08:11:19 AM UTC 24 3738126538 ps
T362 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_errors.3135822393 Sep 24 08:11:16 AM UTC 24 Sep 24 08:11:20 AM UTC 24 221091860 ps
T363 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1200003473 Sep 24 08:11:18 AM UTC 24 Sep 24 08:11:20 AM UTC 24 29778502 ps
T364 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_walk.2657292592 Sep 24 08:11:18 AM UTC 24 Sep 24 08:11:20 AM UTC 24 107298050 ps
T365 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2515671408 Sep 24 08:10:53 AM UTC 24 Sep 24 08:11:21 AM UTC 24 5007780914 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.477734396 Sep 24 08:11:19 AM UTC 24 Sep 24 08:11:22 AM UTC 24 235419518 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_rw.20636732 Sep 24 08:11:20 AM UTC 24 Sep 24 08:11:23 AM UTC 24 110081699 ps
T366 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1126043897 Sep 24 08:11:21 AM UTC 24 Sep 24 08:11:25 AM UTC 24 62101905 ps
T367 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2119304136 Sep 24 08:11:22 AM UTC 24 Sep 24 08:11:25 AM UTC 24 230608912 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1201649001 Sep 24 08:11:20 AM UTC 24 Sep 24 08:11:26 AM UTC 24 309548976 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.4103285227 Sep 24 08:10:30 AM UTC 24 Sep 24 08:11:26 AM UTC 24 2990130087 ps
T368 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.966680647 Sep 24 08:11:23 AM UTC 24 Sep 24 08:11:28 AM UTC 24 436565604 ps
T369 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.119028621 Sep 24 08:11:13 AM UTC 24 Sep 24 08:11:30 AM UTC 24 4397896440 ps
T370 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.686242847 Sep 24 08:11:25 AM UTC 24 Sep 24 08:11:30 AM UTC 24 697670042 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3733113914 Sep 24 08:11:25 AM UTC 24 Sep 24 08:11:31 AM UTC 24 4122936991 ps
T371 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2653776388 Sep 24 08:10:27 AM UTC 24 Sep 24 08:11:32 AM UTC 24 20365112252 ps
T121 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.2892866444 Sep 24 08:11:15 AM UTC 24 Sep 24 08:11:32 AM UTC 24 679794050 ps
T372 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3326780858 Sep 24 08:11:10 AM UTC 24 Sep 24 08:11:33 AM UTC 24 8606975601 ps
T149 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.4048005423 Sep 24 08:11:13 AM UTC 24 Sep 24 08:11:33 AM UTC 24 11052194572 ps
T373 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_walk.174990419 Sep 24 08:11:33 AM UTC 24 Sep 24 08:11:35 AM UTC 24 103688275 ps
T374 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1688114415 Sep 24 08:11:33 AM UTC 24 Sep 24 08:11:35 AM UTC 24 72233723 ps
T178 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2624338214 Sep 24 08:11:16 AM UTC 24 Sep 24 08:11:36 AM UTC 24 2910026318 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_rw.31735216 Sep 24 08:11:33 AM UTC 24 Sep 24 08:11:37 AM UTC 24 181390812 ps
T375 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_errors.4288194325 Sep 24 08:11:31 AM UTC 24 Sep 24 08:11:37 AM UTC 24 543387809 ps
T160 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2744541301 Sep 24 08:11:33 AM UTC 24 Sep 24 08:11:37 AM UTC 24 168318892 ps
T376 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.839256452 Sep 24 08:11:27 AM UTC 24 Sep 24 08:11:39 AM UTC 24 3517310145 ps
T377 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3702663870 Sep 24 08:11:37 AM UTC 24 Sep 24 08:11:40 AM UTC 24 187981173 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2712175604 Sep 24 08:11:07 AM UTC 24 Sep 24 08:11:41 AM UTC 24 10704116045 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2289700523 Sep 24 08:11:36 AM UTC 24 Sep 24 08:11:41 AM UTC 24 483506904 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_errors.3119980312 Sep 24 08:11:40 AM UTC 24 Sep 24 08:11:45 AM UTC 24 204110926 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3351823173 Sep 24 08:11:36 AM UTC 24 Sep 24 08:11:41 AM UTC 24 504831590 ps
T378 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2772107928 Sep 24 08:10:47 AM UTC 24 Sep 24 08:11:42 AM UTC 24 3777827748 ps
T379 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1661797236 Sep 24 08:11:38 AM UTC 24 Sep 24 08:11:43 AM UTC 24 1624825180 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2860767602 Sep 24 08:11:08 AM UTC 24 Sep 24 08:11:43 AM UTC 24 1280723003 ps
T380 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.352836000 Sep 24 08:11:24 AM UTC 24 Sep 24 08:11:44 AM UTC 24 2818490951 ps
T381 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1780318879 Sep 24 08:10:56 AM UTC 24 Sep 24 08:11:45 AM UTC 24 26947647655 ps
T382 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1037987017 Sep 24 08:11:43 AM UTC 24 Sep 24 08:11:45 AM UTC 24 529334465 ps
T161 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_rw.953699718 Sep 24 08:11:42 AM UTC 24 Sep 24 08:11:45 AM UTC 24 137146430 ps
T383 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.884072232 Sep 24 08:11:15 AM UTC 24 Sep 24 08:11:47 AM UTC 24 34153689047 ps
T384 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2711997816 Sep 24 08:11:43 AM UTC 24 Sep 24 08:11:49 AM UTC 24 119331597 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_rw.666360574 Sep 24 08:11:46 AM UTC 24 Sep 24 08:11:50 AM UTC 24 131231371 ps
T385 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1592340028 Sep 24 08:11:49 AM UTC 24 Sep 24 08:11:52 AM UTC 24 232568766 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.4153693318 Sep 24 08:11:46 AM UTC 24 Sep 24 08:11:52 AM UTC 24 638232922 ps
T119 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2144298151 Sep 24 08:11:48 AM UTC 24 Sep 24 08:11:52 AM UTC 24 84698613 ps
T386 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2853666808 Sep 24 08:12:40 AM UTC 24 Sep 24 08:12:43 AM UTC 24 194390616 ps
T387 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.1288773982 Sep 24 08:11:38 AM UTC 24 Sep 24 08:11:53 AM UTC 24 3130804509 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2270876639 Sep 24 08:11:42 AM UTC 24 Sep 24 08:11:54 AM UTC 24 1673974271 ps
T227 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3750217738 Sep 24 08:11:32 AM UTC 24 Sep 24 08:11:54 AM UTC 24 3138551230 ps
T388 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.731869683 Sep 24 08:11:20 AM UTC 24 Sep 24 08:11:56 AM UTC 24 777940942 ps
T389 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_errors.2802071080 Sep 24 08:11:46 AM UTC 24 Sep 24 08:11:56 AM UTC 24 216104413 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_rw.2315254564 Sep 24 08:11:54 AM UTC 24 Sep 24 08:11:56 AM UTC 24 90847600 ps
T390 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2790890306 Sep 24 08:11:51 AM UTC 24 Sep 24 08:11:56 AM UTC 24 940522371 ps
T391 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_errors.1733251460 Sep 24 08:11:54 AM UTC 24 Sep 24 08:11:59 AM UTC 24 247829232 ps
T392 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2517086628 Sep 24 08:11:55 AM UTC 24 Sep 24 08:11:59 AM UTC 24 194170537 ps
T393 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3997006506 Sep 24 08:11:57 AM UTC 24 Sep 24 08:11:59 AM UTC 24 163451391 ps
T394 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.4023705210 Sep 24 08:11:57 AM UTC 24 Sep 24 08:12:00 AM UTC 24 1214283145 ps
T395 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2072435225 Sep 24 08:11:44 AM UTC 24 Sep 24 08:12:03 AM UTC 24 11381187195 ps
T396 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.3019964766 Sep 24 08:11:52 AM UTC 24 Sep 24 08:12:03 AM UTC 24 15672917197 ps
T397 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_rw.2374978993 Sep 24 08:12:00 AM UTC 24 Sep 24 08:12:04 AM UTC 24 143111824 ps
T398 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2710921754 Sep 24 08:11:41 AM UTC 24 Sep 24 08:12:05 AM UTC 24 2208515842 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.236286751 Sep 24 08:11:55 AM UTC 24 Sep 24 08:12:06 AM UTC 24 2226574023 ps
T399 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3066398954 Sep 24 08:12:03 AM UTC 24 Sep 24 08:12:06 AM UTC 24 221200259 ps
T123 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2956747290 Sep 24 08:12:03 AM UTC 24 Sep 24 08:12:07 AM UTC 24 216484217 ps
T400 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_errors.1320904361 Sep 24 08:11:59 AM UTC 24 Sep 24 08:12:07 AM UTC 24 750989895 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1285411523 Sep 24 08:12:01 AM UTC 24 Sep 24 08:12:09 AM UTC 24 942906961 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2807535374 Sep 24 08:11:54 AM UTC 24 Sep 24 08:12:11 AM UTC 24 2302092185 ps
T401 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_errors.1650270518 Sep 24 08:12:07 AM UTC 24 Sep 24 08:12:11 AM UTC 24 192797603 ps
T164 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_rw.3640116612 Sep 24 08:12:08 AM UTC 24 Sep 24 08:12:12 AM UTC 24 192167995 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2526430573 Sep 24 08:12:00 AM UTC 24 Sep 24 08:12:13 AM UTC 24 1681123867 ps
T402 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2144301111 Sep 24 08:12:12 AM UTC 24 Sep 24 08:12:15 AM UTC 24 313475115 ps
T403 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3431179083 Sep 24 08:12:11 AM UTC 24 Sep 24 08:12:17 AM UTC 24 434954083 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3473807 Sep 24 08:12:10 AM UTC 24 Sep 24 08:12:18 AM UTC 24 435035768 ps
T230 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1952629413 Sep 24 08:11:46 AM UTC 24 Sep 24 08:12:18 AM UTC 24 8739625762 ps
T113 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3954423983 Sep 24 08:11:57 AM UTC 24 Sep 24 08:12:19 AM UTC 24 1755856988 ps
T404 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.4090871237 Sep 24 08:12:14 AM UTC 24 Sep 24 08:12:19 AM UTC 24 123290498 ps
T165 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.1707066757 Sep 24 08:12:17 AM UTC 24 Sep 24 08:12:21 AM UTC 24 99703886 ps
T405 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3426365988 Sep 24 08:12:19 AM UTC 24 Sep 24 08:12:22 AM UTC 24 279092647 ps
T406 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2885464278 Sep 24 08:12:18 AM UTC 24 Sep 24 08:12:23 AM UTC 24 292819010 ps
T407 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.128625159 Sep 24 08:12:18 AM UTC 24 Sep 24 08:12:26 AM UTC 24 253346395 ps
T408 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1101219803 Sep 24 08:12:04 AM UTC 24 Sep 24 08:12:26 AM UTC 24 7097013013 ps
T409 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3801928298 Sep 24 08:11:44 AM UTC 24 Sep 24 08:12:26 AM UTC 24 13822356649 ps
T410 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2488205324 Sep 24 08:12:13 AM UTC 24 Sep 24 08:12:28 AM UTC 24 6104773268 ps
T411 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_rw.1775791744 Sep 24 08:12:24 AM UTC 24 Sep 24 08:12:28 AM UTC 24 353714638 ps
T412 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3699249306 Sep 24 08:11:27 AM UTC 24 Sep 24 08:12:28 AM UTC 24 26607885820 ps
T413 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_errors.2896323681 Sep 24 08:12:38 AM UTC 24 Sep 24 08:12:43 AM UTC 24 1261825789 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3286988411 Sep 24 08:12:08 AM UTC 24 Sep 24 08:12:29 AM UTC 24 5676644765 ps
T414 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1196340046 Sep 24 08:12:22 AM UTC 24 Sep 24 08:12:29 AM UTC 24 3021184708 ps
T415 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2063220986 Sep 24 08:12:27 AM UTC 24 Sep 24 08:12:29 AM UTC 24 103643631 ps
T416 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1025479379 Sep 24 08:11:57 AM UTC 24 Sep 24 08:12:31 AM UTC 24 8680765355 ps
T417 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2973104049 Sep 24 08:12:27 AM UTC 24 Sep 24 08:12:31 AM UTC 24 104596102 ps
T418 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1897131333 Sep 24 08:10:51 AM UTC 24 Sep 24 08:12:32 AM UTC 24 4112600777 ps
T419 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.3632185104 Sep 24 08:10:57 AM UTC 24 Sep 24 08:12:32 AM UTC 24 5831286747 ps
T420 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_errors.4253630404 Sep 24 08:12:23 AM UTC 24 Sep 24 08:12:32 AM UTC 24 886947888 ps
T421 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2442696184 Sep 24 08:12:29 AM UTC 24 Sep 24 08:12:32 AM UTC 24 979501237 ps
T422 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_errors.2017961938 Sep 24 08:12:29 AM UTC 24 Sep 24 08:12:34 AM UTC 24 563027614 ps
T423 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_rw.1133711709 Sep 24 08:12:30 AM UTC 24 Sep 24 08:12:35 AM UTC 24 450796041 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3126975626 Sep 24 08:12:27 AM UTC 24 Sep 24 08:12:35 AM UTC 24 379885858 ps
T424 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.610407078 Sep 24 08:12:32 AM UTC 24 Sep 24 08:12:35 AM UTC 24 151468559 ps
T425 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2343947720 Sep 24 08:12:32 AM UTC 24 Sep 24 08:12:37 AM UTC 24 4121655581 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3798531776 Sep 24 08:12:30 AM UTC 24 Sep 24 08:12:37 AM UTC 24 1079504134 ps
T426 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_rw.3218855012 Sep 24 08:12:35 AM UTC 24 Sep 24 08:12:38 AM UTC 24 99566025 ps
T427 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_errors.2539232334 Sep 24 08:12:34 AM UTC 24 Sep 24 08:12:38 AM UTC 24 127336994 ps
T428 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.495995127 Sep 24 08:12:32 AM UTC 24 Sep 24 08:12:38 AM UTC 24 56701628 ps
T429 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1084592666 Sep 24 08:12:36 AM UTC 24 Sep 24 08:12:39 AM UTC 24 112141058 ps
T430 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.4055324727 Sep 24 08:12:32 AM UTC 24 Sep 24 08:12:39 AM UTC 24 2498504870 ps
T431 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1878067184 Sep 24 08:12:36 AM UTC 24 Sep 24 08:12:40 AM UTC 24 97878074 ps
T432 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.884068927 Sep 24 08:12:12 AM UTC 24 Sep 24 08:12:40 AM UTC 24 4798187305 ps
T433 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2893310215 Sep 24 08:12:36 AM UTC 24 Sep 24 08:12:41 AM UTC 24 3517416585 ps
T434 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2881158088 Sep 24 08:11:38 AM UTC 24 Sep 24 08:12:42 AM UTC 24 10083171625 ps
T159 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_rw.86357127 Sep 24 08:12:39 AM UTC 24 Sep 24 08:12:44 AM UTC 24 145367507 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3404972738 Sep 24 08:11:45 AM UTC 24 Sep 24 08:12:44 AM UTC 24 4754467887 ps
T435 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.757439909 Sep 24 08:12:35 AM UTC 24 Sep 24 08:12:45 AM UTC 24 511089122 ps
T436 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2542904070 Sep 24 08:12:39 AM UTC 24 Sep 24 08:12:45 AM UTC 24 448237198 ps
T437 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3783358050 Sep 24 08:11:21 AM UTC 24 Sep 24 08:12:46 AM UTC 24 3550826338 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_intg_err.914199014 Sep 24 08:12:34 AM UTC 24 Sep 24 08:12:46 AM UTC 24 3415631718 ps
T438 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1020500916 Sep 24 08:12:39 AM UTC 24 Sep 24 08:12:47 AM UTC 24 1107663408 ps
T439 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_errors.3066149984 Sep 24 08:12:43 AM UTC 24 Sep 24 08:12:48 AM UTC 24 186810762 ps
T440 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3041178637 Sep 24 08:12:40 AM UTC 24 Sep 24 08:12:48 AM UTC 24 16608532846 ps
T117 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.473361093 Sep 24 08:11:31 AM UTC 24 Sep 24 08:12:48 AM UTC 24 6331061752 ps
T441 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2243045866 Sep 24 08:12:45 AM UTC 24 Sep 24 08:12:48 AM UTC 24 349826958 ps
T442 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_rw.888467348 Sep 24 08:12:44 AM UTC 24 Sep 24 08:12:48 AM UTC 24 1959781395 ps
T443 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.807001636 Sep 24 08:12:19 AM UTC 24 Sep 24 08:12:48 AM UTC 24 5199442024 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2255495315 Sep 24 08:12:16 AM UTC 24 Sep 24 08:12:48 AM UTC 24 8662191805 ps
T444 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_rw.992812627 Sep 24 08:12:47 AM UTC 24 Sep 24 08:12:50 AM UTC 24 182907258 ps
T122 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2600181281 Sep 24 08:12:45 AM UTC 24 Sep 24 08:12:50 AM UTC 24 103307577 ps
T226 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3978208794 Sep 24 08:12:30 AM UTC 24 Sep 24 08:12:50 AM UTC 24 1441335378 ps
T445 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.212546318 Sep 24 08:12:48 AM UTC 24 Sep 24 08:12:50 AM UTC 24 124192097 ps
T446 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3343853760 Sep 24 08:12:45 AM UTC 24 Sep 24 08:12:53 AM UTC 24 376274451 ps
T447 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_rw.3656199755 Sep 24 08:12:51 AM UTC 24 Sep 24 08:12:53 AM UTC 24 111397738 ps
T448 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3619663422 Sep 24 08:12:48 AM UTC 24 Sep 24 08:12:54 AM UTC 24 145843453 ps
T449 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.674668390 Sep 24 08:12:52 AM UTC 24 Sep 24 08:12:55 AM UTC 24 454598763 ps
T450 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.4053268734 Sep 24 08:12:49 AM UTC 24 Sep 24 08:12:56 AM UTC 24 2249914105 ps
T451 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_errors.3017770672 Sep 24 08:12:46 AM UTC 24 Sep 24 08:12:56 AM UTC 24 329250501 ps
T452 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.455957863 Sep 24 08:12:52 AM UTC 24 Sep 24 08:12:57 AM UTC 24 132631973 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2941287065 Sep 24 08:12:07 AM UTC 24 Sep 24 08:12:58 AM UTC 24 2528185708 ps
T453 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_errors.647617312 Sep 24 08:12:49 AM UTC 24 Sep 24 08:12:58 AM UTC 24 1294953243 ps
T454 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3542758552 Sep 24 08:12:48 AM UTC 24 Sep 24 08:12:58 AM UTC 24 262439396 ps
T455 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3056248734 Sep 24 08:12:40 AM UTC 24 Sep 24 08:12:58 AM UTC 24 4254205690 ps
T456 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.4066908405 Sep 24 08:12:54 AM UTC 24 Sep 24 08:12:58 AM UTC 24 1740116628 ps
T457 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_rw.1277903962 Sep 24 08:12:56 AM UTC 24 Sep 24 08:12:59 AM UTC 24 108401625 ps
T458 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2237545677 Sep 24 08:12:46 AM UTC 24 Sep 24 08:12:59 AM UTC 24 2412922383 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2830819343 Sep 24 08:12:43 AM UTC 24 Sep 24 08:12:59 AM UTC 24 3144098893 ps
T459 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.4093171473 Sep 24 08:12:52 AM UTC 24 Sep 24 08:12:59 AM UTC 24 677722411 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_intg_err.4286383756 Sep 24 08:12:39 AM UTC 24 Sep 24 08:12:59 AM UTC 24 4083366754 ps
T460 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2899131711 Sep 24 08:11:34 AM UTC 24 Sep 24 08:12:59 AM UTC 24 8733060093 ps
T461 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_errors.645531850 Sep 24 08:12:55 AM UTC 24 Sep 24 08:13:00 AM UTC 24 187390083 ps
T462 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1577105987 Sep 24 08:12:58 AM UTC 24 Sep 24 08:13:01 AM UTC 24 312551523 ps
T463 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.1601566891 Sep 24 08:12:06 AM UTC 24 Sep 24 08:13:01 AM UTC 24 9030332596 ps
T233 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1270430975 Sep 24 08:12:23 AM UTC 24 Sep 24 08:13:01 AM UTC 24 6502922985 ps
T464 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2675731538 Sep 24 08:12:57 AM UTC 24 Sep 24 08:13:01 AM UTC 24 147887248 ps
T465 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_rw.4080318926 Sep 24 08:12:59 AM UTC 24 Sep 24 08:13:03 AM UTC 24 147743181 ps
T466 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2738998597 Sep 24 08:13:01 AM UTC 24 Sep 24 08:13:04 AM UTC 24 144570610 ps
T467 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.671310612 Sep 24 08:12:56 AM UTC 24 Sep 24 08:13:05 AM UTC 24 1716253481 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3118735398 Sep 24 08:12:47 AM UTC 24 Sep 24 08:13:07 AM UTC 24 1670647523 ps
T468 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_errors.609229988 Sep 24 08:12:59 AM UTC 24 Sep 24 08:13:07 AM UTC 24 1404361369 ps
T469 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3480488349 Sep 24 08:13:00 AM UTC 24 Sep 24 08:13:08 AM UTC 24 836790449 ps
T470 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.2829321580 Sep 24 08:11:52 AM UTC 24 Sep 24 08:13:09 AM UTC 24 16807225787 ps
T471 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2663331317 Sep 24 08:11:29 AM UTC 24 Sep 24 08:13:14 AM UTC 24 76915493867 ps
T472 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1482303597 Sep 24 08:12:58 AM UTC 24 Sep 24 08:13:16 AM UTC 24 5316504697 ps
T235 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.380127028 Sep 24 08:12:49 AM UTC 24 Sep 24 08:13:18 AM UTC 24 5625486266 ps
T473 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_intg_err.746752799 Sep 24 08:12:55 AM UTC 24 Sep 24 08:13:19 AM UTC 24 5886899301 ps
T474 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.3050127948 Sep 24 08:12:58 AM UTC 24 Sep 24 08:13:20 AM UTC 24 9803864267 ps
T475 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3245384605 Sep 24 08:10:37 AM UTC 24 Sep 24 08:13:21 AM UTC 24 43192146880 ps
T476 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1457204113 Sep 24 08:12:38 AM UTC 24 Sep 24 08:13:26 AM UTC 24 44377350325 ps
T477 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.4100139616 Sep 24 08:12:29 AM UTC 24 Sep 24 08:13:28 AM UTC 24 33443837088 ps
T478 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_intg_err.4245967361 Sep 24 08:12:59 AM UTC 24 Sep 24 08:13:39 AM UTC 24 4868298586 ps
T479 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.434916102 Sep 24 08:12:46 AM UTC 24 Sep 24 08:13:44 AM UTC 24 13461293447 ps
T480 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1108181402 Sep 24 08:12:54 AM UTC 24 Sep 24 08:13:48 AM UTC 24 12369250098 ps
T481 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3592693803 Sep 24 08:12:49 AM UTC 24 Sep 24 08:14:23 AM UTC 24 34206365475 ps
T482 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3154550368 Sep 24 08:11:15 AM UTC 24 Sep 24 08:14:29 AM UTC 24 62386378274 ps
T483 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.10992550 Sep 24 08:10:28 AM UTC 24 Sep 24 08:17:50 AM UTC 24 138077369500 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.4226564349
Short name T45
Test name
Test status
Simulation time 435805015 ps
CPU time 2.28 seconds
Started Sep 24 08:13:05 AM UTC 24
Finished Sep 24 08:13:09 AM UTC 24
Peak memory 215596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226564349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.4226564349
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_halt_resume_whereto/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.740391042
Short name T27
Test name
Test status
Simulation time 11869715811 ps
CPU time 23.71 seconds
Started Sep 24 08:13:24 AM UTC 24
Finished Sep 24 08:13:49 AM UTC 24
Peak memory 232912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=740391042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress
_all_with_rand_reset.740391042
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_tl_access.224917910
Short name T105
Test name
Test status
Simulation time 1513829225 ps
CPU time 2.27 seconds
Started Sep 24 08:13:13 AM UTC 24
Finished Sep 24 08:13:16 AM UTC 24
Peak memory 216116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224917910 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.224917910
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.3381698824
Short name T43
Test name
Test status
Simulation time 563199495 ps
CPU time 3.48 seconds
Started Sep 24 08:13:11 AM UTC 24
Finished Sep 24 08:13:16 AM UTC 24
Peak memory 226108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381698824 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.3381698824
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.2562066448
Short name T77
Test name
Test status
Simulation time 280302658 ps
CPU time 1.96 seconds
Started Sep 24 08:13:09 AM UTC 24
Finished Sep 24 08:13:12 AM UTC 24
Peak memory 215340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562066448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.2562066448
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_dmi_failed_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.3003995043
Short name T23
Test name
Test status
Simulation time 5413315329 ps
CPU time 6.39 seconds
Started Sep 24 08:13:20 AM UTC 24
Finished Sep 24 08:13:28 AM UTC 24
Peak memory 228452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003995043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.3003995043
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.188758560
Short name T60
Test name
Test status
Simulation time 1161569014 ps
CPU time 22.4 seconds
Started Sep 24 08:13:11 AM UTC 24
Finished Sep 24 08:13:35 AM UTC 24
Peak memory 226216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=188758560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress
_all_with_rand_reset.188758560
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3006080028
Short name T183
Test name
Test status
Simulation time 2275884730 ps
CPU time 21.47 seconds
Started Sep 24 08:10:28 AM UTC 24
Finished Sep 24 08:10:51 AM UTC 24
Peak memory 225960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006080028 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.3006080028
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.603694392
Short name T94
Test name
Test status
Simulation time 21564794 ps
CPU time 1 seconds
Started Sep 24 08:13:10 AM UTC 24
Finished Sep 24 08:13:12 AM UTC 24
Peak memory 215332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603694392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_scanmode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 0.rv_dm_scanmode.603694392
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_scanmode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.1839809170
Short name T21
Test name
Test status
Simulation time 491503746 ps
CPU time 1.67 seconds
Started Sep 24 08:13:10 AM UTC 24
Finished Sep 24 08:13:13 AM UTC 24
Peak memory 250800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839809170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_buffered_enable.1839809170
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.1554975572
Short name T48
Test name
Test status
Simulation time 511456104 ps
CPU time 2.49 seconds
Started Sep 24 08:13:11 AM UTC 24
Finished Sep 24 08:13:15 AM UTC 24
Peak memory 254352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554975572 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.1554975572
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.165436312
Short name T85
Test name
Test status
Simulation time 3507373986 ps
CPU time 48.88 seconds
Started Sep 24 08:13:47 AM UTC 24
Finished Sep 24 08:14:37 AM UTC 24
Peak memory 233012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=165436312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress
_all_with_rand_reset.165436312
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.292279018
Short name T46
Test name
Test status
Simulation time 9244883896 ps
CPU time 9.86 seconds
Started Sep 24 08:13:01 AM UTC 24
Finished Sep 24 08:13:12 AM UTC 24
Peak memory 216008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292279018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.292279018
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.4206824465
Short name T245
Test name
Test status
Simulation time 21859254798 ps
CPU time 51.73 seconds
Started Sep 24 08:13:02 AM UTC 24
Finished Sep 24 08:13:55 AM UTC 24
Peak memory 226520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206824465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.4206824465
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.2829321580
Short name T470
Test name
Test status
Simulation time 16807225787 ps
CPU time 74.65 seconds
Started Sep 24 08:11:52 AM UTC 24
Finished Sep 24 08:13:09 AM UTC 24
Peak memory 230224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2829321580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_re
set.2829321580
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.3532664423
Short name T15
Test name
Test status
Simulation time 167494243 ps
CPU time 1.79 seconds
Started Sep 24 08:13:06 AM UTC 24
Finished Sep 24 08:13:09 AM UTC 24
Peak memory 225188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532664423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.3532664423
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_ndmreset_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3722677731
Short name T116
Test name
Test status
Simulation time 301691827 ps
CPU time 4.18 seconds
Started Sep 24 08:11:08 AM UTC 24
Finished Sep 24 08:11:13 AM UTC 24
Peak memory 226116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=3722677731 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_r
and_reset.3722677731
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.3338993860
Short name T78
Test name
Test status
Simulation time 463675890 ps
CPU time 1.68 seconds
Started Sep 24 08:13:18 AM UTC 24
Finished Sep 24 08:13:21 AM UTC 24
Peak memory 215340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338993860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.3338993860
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_dmi_failed_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.1660621989
Short name T83
Test name
Test status
Simulation time 3738126538 ps
CPU time 39.33 seconds
Started Sep 24 08:10:38 AM UTC 24
Finished Sep 24 08:11:19 AM UTC 24
Peak memory 230196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=1660621989 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_re
set.1660621989
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2600181281
Short name T122
Test name
Test status
Simulation time 103307577 ps
CPU time 4.24 seconds
Started Sep 24 08:12:45 AM UTC 24
Finished Sep 24 08:12:50 AM UTC 24
Peak memory 230244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=2600181281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_
rand_reset.2600181281
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.2241602179
Short name T193
Test name
Test status
Simulation time 4085392859 ps
CPU time 2.91 seconds
Started Sep 24 08:14:19 AM UTC 24
Finished Sep 24 08:14:23 AM UTC 24
Peak memory 215920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241602179 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.2241602179
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/25.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2860767602
Short name T155
Test name
Test status
Simulation time 1280723003 ps
CPU time 33.73 seconds
Started Sep 24 08:11:08 AM UTC 24
Finished Sep 24 08:11:43 AM UTC 24
Peak memory 225820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860767602 -ass
ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_aliasing.2860767602
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/3.rv_dm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.2005132440
Short name T31
Test name
Test status
Simulation time 391986170 ps
CPU time 2.18 seconds
Started Sep 24 08:13:14 AM UTC 24
Finished Sep 24 08:13:17 AM UTC 24
Peak memory 215792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005132440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.2005132440
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_cmderr_exception/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/35.rv_dm_stress_all.2957567436
Short name T19
Test name
Test status
Simulation time 1567115590 ps
CPU time 5.57 seconds
Started Sep 24 08:14:23 AM UTC 24
Finished Sep 24 08:14:30 AM UTC 24
Peak memory 226036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957567436 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.2957567436
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/35.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.2765695366
Short name T55
Test name
Test status
Simulation time 4073842626 ps
CPU time 4.92 seconds
Started Sep 24 08:13:41 AM UTC 24
Finished Sep 24 08:13:47 AM UTC 24
Peak memory 226164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765695366 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.2765695366
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/8.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/13.rv_dm_bad_sba_tl_access.3328615531
Short name T206
Test name
Test status
Simulation time 2854172141 ps
CPU time 6.91 seconds
Started Sep 24 08:13:55 AM UTC 24
Finished Sep 24 08:14:03 AM UTC 24
Peak memory 226400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328615531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.3328615531
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/13.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.407933588
Short name T24
Test name
Test status
Simulation time 2383104133 ps
CPU time 5.62 seconds
Started Sep 24 08:13:30 AM UTC 24
Finished Sep 24 08:13:37 AM UTC 24
Peak memory 216156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407933588 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.407933588
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/32.rv_dm_stress_all.570112850
Short name T34
Test name
Test status
Simulation time 6698300893 ps
CPU time 11.82 seconds
Started Sep 24 08:14:22 AM UTC 24
Finished Sep 24 08:14:35 AM UTC 24
Peak memory 215884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570112850 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.570112850
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/32.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.1833055933
Short name T49
Test name
Test status
Simulation time 140468794 ps
CPU time 1.17 seconds
Started Sep 24 08:13:12 AM UTC 24
Finished Sep 24 08:13:15 AM UTC 24
Peak memory 215204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833055933 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.1833055933
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.867375331
Short name T64
Test name
Test status
Simulation time 188776380 ps
CPU time 1.17 seconds
Started Sep 24 08:13:09 AM UTC 24
Finished Sep 24 08:13:11 AM UTC 24
Peak memory 225200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867375331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_rom_read_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.867375331
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_rom_read_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2697618616
Short name T135
Test name
Test status
Simulation time 277475233 ps
CPU time 5.1 seconds
Started Sep 24 08:10:31 AM UTC 24
Finished Sep 24 08:10:37 AM UTC 24
Peak memory 215532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697618616 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_csr_outstanding.2697618616
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/49.rv_dm_stress_all.3379463969
Short name T72
Test name
Test status
Simulation time 4492359063 ps
CPU time 14.28 seconds
Started Sep 24 08:14:31 AM UTC 24
Finished Sep 24 08:14:46 AM UTC 24
Peak memory 216176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379463969 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.3379463969
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/49.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.1322518949
Short name T92
Test name
Test status
Simulation time 423869121 ps
CPU time 2.13 seconds
Started Sep 24 08:13:21 AM UTC 24
Finished Sep 24 08:13:24 AM UTC 24
Peak memory 258360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322518949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_buffered_enable.1322518949
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/2.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1952629413
Short name T230
Test name
Test status
Simulation time 8739625762 ps
CPU time 30.39 seconds
Started Sep 24 08:11:46 AM UTC 24
Finished Sep 24 08:12:18 AM UTC 24
Peak memory 226088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952629413 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.1952629413
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/6.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.529208383
Short name T214
Test name
Test status
Simulation time 13171406437 ps
CPU time 33.46 seconds
Started Sep 24 08:13:45 AM UTC 24
Finished Sep 24 08:14:19 AM UTC 24
Peak memory 226320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529208383 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.529208383
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/9.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.2912415098
Short name T10
Test name
Test status
Simulation time 3933461433 ps
CPU time 4.88 seconds
Started Sep 24 08:14:14 AM UTC 24
Finished Sep 24 08:14:20 AM UTC 24
Peak memory 226184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912415098 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.2912415098
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/20.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_errors.3119980312
Short name T180
Test name
Test status
Simulation time 204110926 ps
CPU time 4.87 seconds
Started Sep 24 08:11:40 AM UTC 24
Finished Sep 24 08:11:45 AM UTC 24
Peak memory 225972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119980312 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.3119980312
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/5.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.578609717
Short name T42
Test name
Test status
Simulation time 4026485016 ps
CPU time 6.64 seconds
Started Sep 24 08:13:05 AM UTC 24
Finished Sep 24 08:13:13 AM UTC 24
Peak memory 215932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578609717 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_sba_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.578609717
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_sba_debug_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.4049737461
Short name T61
Test name
Test status
Simulation time 244932113 ps
CPU time 1.36 seconds
Started Sep 24 08:13:09 AM UTC 24
Finished Sep 24 08:13:11 AM UTC 24
Peak memory 215332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049737461 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_abstractcmd_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.4049737461
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_abstractcmd_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/36.rv_dm_stress_all.3779095740
Short name T199
Test name
Test status
Simulation time 5146558724 ps
CPU time 13.28 seconds
Started Sep 24 08:14:23 AM UTC 24
Finished Sep 24 08:14:38 AM UTC 24
Peak memory 226096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779095740 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.3779095740
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/36.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.494770121
Short name T218
Test name
Test status
Simulation time 7910548268 ps
CPU time 28.3 seconds
Started Sep 24 08:13:20 AM UTC 24
Finished Sep 24 08:13:50 AM UTC 24
Peak memory 226340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494770121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.494770121
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/2.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.1046202048
Short name T217
Test name
Test status
Simulation time 27488351609 ps
CPU time 58.98 seconds
Started Sep 24 08:13:22 AM UTC 24
Finished Sep 24 08:14:23 AM UTC 24
Peak memory 226316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046202048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.1046202048
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/39.rv_dm_stress_all.2503952842
Short name T197
Test name
Test status
Simulation time 1852886272 ps
CPU time 3.02 seconds
Started Sep 24 08:14:25 AM UTC 24
Finished Sep 24 08:14:29 AM UTC 24
Peak memory 215864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503952842 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.2503952842
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/39.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.2289430092
Short name T97
Test name
Test status
Simulation time 1046903456 ps
CPU time 4.56 seconds
Started Sep 24 08:13:33 AM UTC 24
Finished Sep 24 08:13:38 AM UTC 24
Peak memory 226300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289430092 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.2289430092
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/5.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1342183260
Short name T112
Test name
Test status
Simulation time 565546638 ps
CPU time 2.2 seconds
Started Sep 24 08:10:27 AM UTC 24
Finished Sep 24 08:10:31 AM UTC 24
Peak memory 215392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342183260 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_aliasing.1342183260
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3118735398
Short name T236
Test name
Test status
Simulation time 1670647523 ps
CPU time 18.74 seconds
Started Sep 24 08:12:47 AM UTC 24
Finished Sep 24 08:13:07 AM UTC 24
Peak memory 232248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118735398 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.3118735398
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/16.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_autoincr_sba_tl_access.2675254081
Short name T176
Test name
Test status
Simulation time 6382369898 ps
CPU time 31.38 seconds
Started Sep 24 08:13:13 AM UTC 24
Finished Sep 24 08:13:46 AM UTC 24
Peak memory 226396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675254081 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.2675254081
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.1769871456
Short name T4
Test name
Test status
Simulation time 1143774420 ps
CPU time 2.87 seconds
Started Sep 24 08:13:04 AM UTC 24
Finished Sep 24 08:13:08 AM UTC 24
Peak memory 215600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769871456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.1769871456
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_cmderr_halt_resume/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1270430975
Short name T233
Test name
Test status
Simulation time 6502922985 ps
CPU time 36.94 seconds
Started Sep 24 08:12:23 AM UTC 24
Finished Sep 24 08:13:01 AM UTC 24
Peak memory 232112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270430975 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.1270430975
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/11.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.380127028
Short name T235
Test name
Test status
Simulation time 5625486266 ps
CPU time 26.82 seconds
Started Sep 24 08:12:49 AM UTC 24
Finished Sep 24 08:13:18 AM UTC 24
Peak memory 225936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380127028 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.380127028
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/17.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_halt_resume_whereto.1274431376
Short name T54
Test name
Test status
Simulation time 509925632 ps
CPU time 1.8 seconds
Started Sep 24 08:13:15 AM UTC 24
Finished Sep 24 08:13:18 AM UTC 24
Peak memory 215332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274431376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.1274431376
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_halt_resume_whereto/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/10.rv_dm_bad_sba_tl_access.3467437167
Short name T213
Test name
Test status
Simulation time 15070886147 ps
CPU time 24.6 seconds
Started Sep 24 08:13:49 AM UTC 24
Finished Sep 24 08:14:15 AM UTC 24
Peak memory 226336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467437167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.3467437167
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/10.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/16.rv_dm_stress_all.2586078480
Short name T28
Test name
Test status
Simulation time 4210753933 ps
CPU time 8.06 seconds
Started Sep 24 08:14:07 AM UTC 24
Finished Sep 24 08:14:16 AM UTC 24
Peak memory 216128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586078480 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.2586078480
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/16.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/18.rv_dm_autoincr_sba_tl_access.1740311895
Short name T207
Test name
Test status
Simulation time 69654798411 ps
CPU time 174.42 seconds
Started Sep 24 08:14:12 AM UTC 24
Finished Sep 24 08:17:09 AM UTC 24
Peak memory 226596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740311895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.1740311895
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.2117522448
Short name T196
Test name
Test status
Simulation time 2254776973 ps
CPU time 4.28 seconds
Started Sep 24 08:14:17 AM UTC 24
Finished Sep 24 08:14:22 AM UTC 24
Peak memory 226116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117522448 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.2117522448
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/22.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.2213619305
Short name T212
Test name
Test status
Simulation time 13866739685 ps
CPU time 16.97 seconds
Started Sep 24 08:13:38 AM UTC 24
Finished Sep 24 08:13:56 AM UTC 24
Peak memory 226396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213619305 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.2213619305
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1176814563
Short name T151
Test name
Test status
Simulation time 3445487926 ps
CPU time 45.44 seconds
Started Sep 24 08:10:26 AM UTC 24
Finished Sep 24 08:11:13 AM UTC 24
Peak memory 215672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176814563 -ass
ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_aliasing.1176814563
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.489483426
Short name T47
Test name
Test status
Simulation time 108922634 ps
CPU time 1.02 seconds
Started Sep 24 08:13:10 AM UTC 24
Finished Sep 24 08:13:12 AM UTC 24
Peak memory 225072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489483426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sparse_lc_gate_fsm.489483426
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_sparse_lc_gate_fsm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.1788079686
Short name T90
Test name
Test status
Simulation time 95279927 ps
CPU time 1.29 seconds
Started Sep 24 08:13:24 AM UTC 24
Finished Sep 24 08:13:27 AM UTC 24
Peak memory 225132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788079686 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sparse_lc_gate_fsm.1788079686
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/3.rv_dm_sparse_lc_gate_fsm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.4103285227
Short name T154
Test name
Test status
Simulation time 2990130087 ps
CPU time 54.81 seconds
Started Sep 24 08:10:30 AM UTC 24
Finished Sep 24 08:11:26 AM UTC 24
Peak memory 215648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103285227 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.4103285227
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.747718555
Short name T133
Test name
Test status
Simulation time 94096420 ps
CPU time 2.53 seconds
Started Sep 24 08:10:30 AM UTC 24
Finished Sep 24 08:10:33 AM UTC 24
Peak memory 225872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747718555 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.747718555
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3425698192
Short name T118
Test name
Test status
Simulation time 380620154 ps
CPU time 4.35 seconds
Started Sep 24 08:10:32 AM UTC 24
Finished Sep 24 08:10:37 AM UTC 24
Peak memory 230156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=3425698192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_r
and_reset.3425698192
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.2498516073
Short name T134
Test name
Test status
Simulation time 119433481 ps
CPU time 3.65 seconds
Started Sep 24 08:10:30 AM UTC 24
Finished Sep 24 08:10:34 AM UTC 24
Peak memory 232004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498516073 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.2498516073
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.10992550
Short name T483
Test name
Test status
Simulation time 138077369500 ps
CPU time 435.88 seconds
Started Sep 24 08:10:28 AM UTC 24
Finished Sep 24 08:17:50 AM UTC 24
Peak memory 215544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10992550 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_aliasing.10992550
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2074197996
Short name T350
Test name
Test status
Simulation time 17786514396 ps
CPU time 28.88 seconds
Started Sep 24 08:10:27 AM UTC 24
Finished Sep 24 08:10:58 AM UTC 24
Peak memory 215604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074197996 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_bit_bash.2074197996
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.228172484
Short name T336
Test name
Test status
Simulation time 2627976947 ps
CPU time 2.07 seconds
Started Sep 24 08:10:27 AM UTC 24
Finished Sep 24 08:10:31 AM UTC 24
Peak memory 215604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228172484 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_hw_reset.228172484
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3840402605
Short name T339
Test name
Test status
Simulation time 3981426251 ps
CPU time 4.23 seconds
Started Sep 24 08:10:27 AM UTC 24
Finished Sep 24 08:10:33 AM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840402605 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.3840402605
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2653776388
Short name T371
Test name
Test status
Simulation time 20365112252 ps
CPU time 63.1 seconds
Started Sep 24 08:10:27 AM UTC 24
Finished Sep 24 08:11:32 AM UTC 24
Peak memory 215632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653776388 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_bit_bash.2653776388
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.526974645
Short name T111
Test name
Test status
Simulation time 568677266 ps
CPU time 1.79 seconds
Started Sep 24 08:10:26 AM UTC 24
Finished Sep 24 08:10:29 AM UTC 24
Peak memory 215320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526974645 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_hw_reset.526974645
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3139060990
Short name T110
Test name
Test status
Simulation time 326403460 ps
CPU time 1.37 seconds
Started Sep 24 08:10:26 AM UTC 24
Finished Sep 24 08:10:29 AM UTC 24
Peak memory 214604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139060990 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.3139060990
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2026568347
Short name T337
Test name
Test status
Simulation time 161750655 ps
CPU time 1.23 seconds
Started Sep 24 08:10:30 AM UTC 24
Finished Sep 24 08:10:32 AM UTC 24
Peak memory 215376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026568347 -assert nopostproc +UVM
_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_partial_access.2026568347
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.3639418251
Short name T338
Test name
Test status
Simulation time 81678441 ps
CPU time 1.1 seconds
Started Sep 24 08:10:29 AM UTC 24
Finished Sep 24 08:10:32 AM UTC 24
Peak memory 215316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639418251 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.3639418251
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.990710749
Short name T82
Test name
Test status
Simulation time 3126865453 ps
CPU time 20.24 seconds
Started Sep 24 08:10:28 AM UTC 24
Finished Sep 24 08:10:50 AM UTC 24
Peak memory 226032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=990710749 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.990710749
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.1063627018
Short name T177
Test name
Test status
Simulation time 813268250 ps
CPU time 7.11 seconds
Started Sep 24 08:10:28 AM UTC 24
Finished Sep 24 08:10:37 AM UTC 24
Peak memory 225976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063627018 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.1063627018
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3594077767
Short name T152
Test name
Test status
Simulation time 8319130497 ps
CPU time 45.07 seconds
Started Sep 24 08:10:32 AM UTC 24
Finished Sep 24 08:11:19 AM UTC 24
Peak memory 225868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594077767 -ass
ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_aliasing.3594077767
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2772107928
Short name T378
Test name
Test status
Simulation time 3777827748 ps
CPU time 53.55 seconds
Started Sep 24 08:10:47 AM UTC 24
Finished Sep 24 08:11:42 AM UTC 24
Peak memory 226004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772107928 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.2772107928
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.4158521672
Short name T136
Test name
Test status
Simulation time 364068506 ps
CPU time 3.8 seconds
Started Sep 24 08:10:45 AM UTC 24
Finished Sep 24 08:10:49 AM UTC 24
Peak memory 225788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158521672 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.4158521672
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2509753782
Short name T120
Test name
Test status
Simulation time 87021858 ps
CPU time 3.44 seconds
Started Sep 24 08:10:50 AM UTC 24
Finished Sep 24 08:10:54 AM UTC 24
Peak memory 226052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=2509753782 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_r
and_reset.2509753782
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.2562475211
Short name T137
Test name
Test status
Simulation time 146740489 ps
CPU time 3.14 seconds
Started Sep 24 08:10:47 AM UTC 24
Finished Sep 24 08:10:51 AM UTC 24
Peak memory 230036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562475211 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.2562475211
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3245384605
Short name T475
Test name
Test status
Simulation time 43192146880 ps
CPU time 161.26 seconds
Started Sep 24 08:10:37 AM UTC 24
Finished Sep 24 08:13:21 AM UTC 24
Peak memory 215608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245384605 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_aliasing.3245384605
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2649318884
Short name T343
Test name
Test status
Simulation time 1565118365 ps
CPU time 6.76 seconds
Started Sep 24 08:10:36 AM UTC 24
Finished Sep 24 08:10:44 AM UTC 24
Peak memory 215468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649318884 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_bit_bash.2649318884
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.440291546
Short name T147
Test name
Test status
Simulation time 6223939891 ps
CPU time 36.33 seconds
Started Sep 24 08:10:35 AM UTC 24
Finished Sep 24 08:11:13 AM UTC 24
Peak memory 215800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440291546 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_hw_reset.440291546
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1694490332
Short name T347
Test name
Test status
Simulation time 2268525968 ps
CPU time 14.51 seconds
Started Sep 24 08:10:36 AM UTC 24
Finished Sep 24 08:10:52 AM UTC 24
Peak memory 215792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694490332 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.1694490332
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.888695741
Short name T342
Test name
Test status
Simulation time 2127440815 ps
CPU time 7.37 seconds
Started Sep 24 08:10:34 AM UTC 24
Finished Sep 24 08:10:43 AM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888695741 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_aliasing.888695741
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1365823638
Short name T353
Test name
Test status
Simulation time 17827642524 ps
CPU time 29.6 seconds
Started Sep 24 08:10:34 AM UTC 24
Finished Sep 24 08:11:05 AM UTC 24
Peak memory 215696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365823638 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_bit_bash.1365823638
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.576871551
Short name T340
Test name
Test status
Simulation time 220260355 ps
CPU time 1.09 seconds
Started Sep 24 08:10:33 AM UTC 24
Finished Sep 24 08:10:35 AM UTC 24
Peak memory 215320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576871551 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_hw_reset.576871551
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.4194988201
Short name T341
Test name
Test status
Simulation time 906969771 ps
CPU time 3.49 seconds
Started Sep 24 08:10:33 AM UTC 24
Finished Sep 24 08:10:38 AM UTC 24
Peak memory 215384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194988201 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.4194988201
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1542051472
Short name T345
Test name
Test status
Simulation time 105379333 ps
CPU time 1.11 seconds
Started Sep 24 08:10:44 AM UTC 24
Finished Sep 24 08:10:46 AM UTC 24
Peak memory 215376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542051472 -assert nopostproc +UVM
_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_partial_access.1542051472
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.2060491372
Short name T344
Test name
Test status
Simulation time 66127479 ps
CPU time 1.05 seconds
Started Sep 24 08:10:44 AM UTC 24
Finished Sep 24 08:10:46 AM UTC 24
Peak memory 215316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060491372 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.2060491372
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2912478600
Short name T138
Test name
Test status
Simulation time 255560167 ps
CPU time 6.16 seconds
Started Sep 24 08:10:48 AM UTC 24
Finished Sep 24 08:10:55 AM UTC 24
Peak memory 215544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912478600 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_csr_outstanding.2912478600
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.3895514253
Short name T346
Test name
Test status
Simulation time 230400388 ps
CPU time 7.5 seconds
Started Sep 24 08:10:38 AM UTC 24
Finished Sep 24 08:10:47 AM UTC 24
Peak memory 225928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895514253 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.3895514253
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3881069757
Short name T184
Test name
Test status
Simulation time 3048040283 ps
CPU time 17.04 seconds
Started Sep 24 08:10:38 AM UTC 24
Finished Sep 24 08:10:57 AM UTC 24
Peak memory 225908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881069757 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.3881069757
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2885464278
Short name T406
Test name
Test status
Simulation time 292819010 ps
CPU time 3.97 seconds
Started Sep 24 08:12:18 AM UTC 24
Finished Sep 24 08:12:23 AM UTC 24
Peak memory 232124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=2885464278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_
rand_reset.2885464278
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.1707066757
Short name T165
Test name
Test status
Simulation time 99703886 ps
CPU time 2.69 seconds
Started Sep 24 08:12:17 AM UTC 24
Finished Sep 24 08:12:21 AM UTC 24
Peak memory 225904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707066757 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.1707066757
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/10.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2488205324
Short name T410
Test name
Test status
Simulation time 6104773268 ps
CPU time 13.5 seconds
Started Sep 24 08:12:13 AM UTC 24
Finished Sep 24 08:12:28 AM UTC 24
Peak memory 215700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488205324 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_bit_bash.2488205324
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.884068927
Short name T432
Test name
Test status
Simulation time 4798187305 ps
CPU time 26.82 seconds
Started Sep 24 08:12:12 AM UTC 24
Finished Sep 24 08:12:40 AM UTC 24
Peak memory 215640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884068927 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.884068927
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2144301111
Short name T402
Test name
Test status
Simulation time 313475115 ps
CPU time 1.93 seconds
Started Sep 24 08:12:12 AM UTC 24
Finished Sep 24 08:12:15 AM UTC 24
Peak memory 215312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144301111 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.2144301111
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.128625159
Short name T407
Test name
Test status
Simulation time 253346395 ps
CPU time 6.13 seconds
Started Sep 24 08:12:18 AM UTC 24
Finished Sep 24 08:12:26 AM UTC 24
Peak memory 215564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128625159 -assert nopostproc +UV
M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_csr_outstanding.128625159
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/10.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.4090871237
Short name T404
Test name
Test status
Simulation time 123290498 ps
CPU time 3.49 seconds
Started Sep 24 08:12:14 AM UTC 24
Finished Sep 24 08:12:19 AM UTC 24
Peak memory 225920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090871237 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.4090871237
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/10.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2255495315
Short name T228
Test name
Test status
Simulation time 8662191805 ps
CPU time 30.75 seconds
Started Sep 24 08:12:16 AM UTC 24
Finished Sep 24 08:12:48 AM UTC 24
Peak memory 226008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255495315 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.2255495315
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/10.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2973104049
Short name T417
Test name
Test status
Simulation time 104596102 ps
CPU time 3.06 seconds
Started Sep 24 08:12:27 AM UTC 24
Finished Sep 24 08:12:31 AM UTC 24
Peak memory 227964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=2973104049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_
rand_reset.2973104049
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_rw.1775791744
Short name T411
Test name
Test status
Simulation time 353714638 ps
CPU time 2.96 seconds
Started Sep 24 08:12:24 AM UTC 24
Finished Sep 24 08:12:28 AM UTC 24
Peak memory 231920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775791744 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.1775791744
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/11.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1196340046
Short name T414
Test name
Test status
Simulation time 3021184708 ps
CPU time 6.37 seconds
Started Sep 24 08:12:22 AM UTC 24
Finished Sep 24 08:12:29 AM UTC 24
Peak memory 215700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196340046 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_bit_bash.1196340046
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.807001636
Short name T443
Test name
Test status
Simulation time 5199442024 ps
CPU time 27.41 seconds
Started Sep 24 08:12:19 AM UTC 24
Finished Sep 24 08:12:48 AM UTC 24
Peak memory 215540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807001636 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.807001636
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3426365988
Short name T405
Test name
Test status
Simulation time 279092647 ps
CPU time 1.48 seconds
Started Sep 24 08:12:19 AM UTC 24
Finished Sep 24 08:12:22 AM UTC 24
Peak memory 215312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426365988 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.3426365988
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3126975626
Short name T157
Test name
Test status
Simulation time 379885858 ps
CPU time 6.89 seconds
Started Sep 24 08:12:27 AM UTC 24
Finished Sep 24 08:12:35 AM UTC 24
Peak memory 215680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126975626 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_csr_outstanding.3126975626
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/11.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_errors.4253630404
Short name T420
Test name
Test status
Simulation time 886947888 ps
CPU time 8.44 seconds
Started Sep 24 08:12:23 AM UTC 24
Finished Sep 24 08:12:32 AM UTC 24
Peak memory 226004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253630404 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.4253630404
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/11.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.495995127
Short name T428
Test name
Test status
Simulation time 56701628 ps
CPU time 4.45 seconds
Started Sep 24 08:12:32 AM UTC 24
Finished Sep 24 08:12:38 AM UTC 24
Peak memory 226048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=495995127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_r
and_reset.495995127
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_rw.1133711709
Short name T423
Test name
Test status
Simulation time 450796041 ps
CPU time 3.45 seconds
Started Sep 24 08:12:30 AM UTC 24
Finished Sep 24 08:12:35 AM UTC 24
Peak memory 229936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133711709 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.1133711709
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/12.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.4100139616
Short name T477
Test name
Test status
Simulation time 33443837088 ps
CPU time 57.28 seconds
Started Sep 24 08:12:29 AM UTC 24
Finished Sep 24 08:13:28 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100139616 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_bit_bash.4100139616
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2442696184
Short name T421
Test name
Test status
Simulation time 979501237 ps
CPU time 2.45 seconds
Started Sep 24 08:12:29 AM UTC 24
Finished Sep 24 08:12:32 AM UTC 24
Peak memory 215472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442696184 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.2442696184
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2063220986
Short name T415
Test name
Test status
Simulation time 103643631 ps
CPU time 1.17 seconds
Started Sep 24 08:12:27 AM UTC 24
Finished Sep 24 08:12:29 AM UTC 24
Peak memory 215312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063220986 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.2063220986
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3798531776
Short name T158
Test name
Test status
Simulation time 1079504134 ps
CPU time 5.4 seconds
Started Sep 24 08:12:30 AM UTC 24
Finished Sep 24 08:12:37 AM UTC 24
Peak memory 215608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798531776 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same_csr_outstanding.3798531776
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/12.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_errors.2017961938
Short name T422
Test name
Test status
Simulation time 563027614 ps
CPU time 3.77 seconds
Started Sep 24 08:12:29 AM UTC 24
Finished Sep 24 08:12:34 AM UTC 24
Peak memory 225904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017961938 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.2017961938
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/12.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3978208794
Short name T226
Test name
Test status
Simulation time 1441335378 ps
CPU time 18.8 seconds
Started Sep 24 08:12:30 AM UTC 24
Finished Sep 24 08:12:50 AM UTC 24
Peak memory 232576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978208794 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.3978208794
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/12.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1878067184
Short name T431
Test name
Test status
Simulation time 97878074 ps
CPU time 2.59 seconds
Started Sep 24 08:12:36 AM UTC 24
Finished Sep 24 08:12:40 AM UTC 24
Peak memory 225912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=1878067184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_
rand_reset.1878067184
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_rw.3218855012
Short name T426
Test name
Test status
Simulation time 99566025 ps
CPU time 2.02 seconds
Started Sep 24 08:12:35 AM UTC 24
Finished Sep 24 08:12:38 AM UTC 24
Peak memory 230000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218855012 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.3218855012
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/13.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2343947720
Short name T425
Test name
Test status
Simulation time 4121655581 ps
CPU time 3.02 seconds
Started Sep 24 08:12:32 AM UTC 24
Finished Sep 24 08:12:37 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343947720 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_bit_bash.2343947720
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.4055324727
Short name T430
Test name
Test status
Simulation time 2498504870 ps
CPU time 5.55 seconds
Started Sep 24 08:12:32 AM UTC 24
Finished Sep 24 08:12:39 AM UTC 24
Peak memory 215688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055324727 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.4055324727
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.610407078
Short name T424
Test name
Test status
Simulation time 151468559 ps
CPU time 1.6 seconds
Started Sep 24 08:12:32 AM UTC 24
Finished Sep 24 08:12:35 AM UTC 24
Peak memory 215320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610407078 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.610407078
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.757439909
Short name T435
Test name
Test status
Simulation time 511089122 ps
CPU time 8.75 seconds
Started Sep 24 08:12:35 AM UTC 24
Finished Sep 24 08:12:45 AM UTC 24
Peak memory 215540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757439909 -assert nopostproc +UV
M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_csr_outstanding.757439909
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/13.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_errors.2539232334
Short name T427
Test name
Test status
Simulation time 127336994 ps
CPU time 3.37 seconds
Started Sep 24 08:12:34 AM UTC 24
Finished Sep 24 08:12:38 AM UTC 24
Peak memory 225964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539232334 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.2539232334
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/13.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_intg_err.914199014
Short name T234
Test name
Test status
Simulation time 3415631718 ps
CPU time 11.58 seconds
Started Sep 24 08:12:34 AM UTC 24
Finished Sep 24 08:12:46 AM UTC 24
Peak memory 226044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914199014 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.914199014
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/13.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2542904070
Short name T436
Test name
Test status
Simulation time 448237198 ps
CPU time 4.65 seconds
Started Sep 24 08:12:39 AM UTC 24
Finished Sep 24 08:12:45 AM UTC 24
Peak memory 230176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=2542904070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_
rand_reset.2542904070
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_rw.86357127
Short name T159
Test name
Test status
Simulation time 145367507 ps
CPU time 3.71 seconds
Started Sep 24 08:12:39 AM UTC 24
Finished Sep 24 08:12:44 AM UTC 24
Peak memory 225740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86357127 -assert nopostproc +UVM_TESTNAME=rv_dm_ba
se_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv
_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.86357127
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/14.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1457204113
Short name T476
Test name
Test status
Simulation time 44377350325 ps
CPU time 46.64 seconds
Started Sep 24 08:12:38 AM UTC 24
Finished Sep 24 08:13:26 AM UTC 24
Peak memory 215536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457204113 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_bit_bash.1457204113
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2893310215
Short name T433
Test name
Test status
Simulation time 3517416585 ps
CPU time 4.34 seconds
Started Sep 24 08:12:36 AM UTC 24
Finished Sep 24 08:12:41 AM UTC 24
Peak memory 215728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893310215 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.2893310215
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1084592666
Short name T429
Test name
Test status
Simulation time 112141058 ps
CPU time 1.55 seconds
Started Sep 24 08:12:36 AM UTC 24
Finished Sep 24 08:12:39 AM UTC 24
Peak memory 215312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084592666 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.1084592666
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1020500916
Short name T438
Test name
Test status
Simulation time 1107663408 ps
CPU time 6.38 seconds
Started Sep 24 08:12:39 AM UTC 24
Finished Sep 24 08:12:47 AM UTC 24
Peak memory 215536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020500916 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same_csr_outstanding.1020500916
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/14.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_errors.2896323681
Short name T413
Test name
Test status
Simulation time 1261825789 ps
CPU time 3.67 seconds
Started Sep 24 08:12:38 AM UTC 24
Finished Sep 24 08:12:43 AM UTC 24
Peak memory 225908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896323681 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.2896323681
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/14.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_intg_err.4286383756
Short name T232
Test name
Test status
Simulation time 4083366754 ps
CPU time 18.92 seconds
Started Sep 24 08:12:39 AM UTC 24
Finished Sep 24 08:12:59 AM UTC 24
Peak memory 226004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286383756 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.4286383756
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/14.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_rw.888467348
Short name T442
Test name
Test status
Simulation time 1959781395 ps
CPU time 3.39 seconds
Started Sep 24 08:12:44 AM UTC 24
Finished Sep 24 08:12:48 AM UTC 24
Peak memory 229972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888467348 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/r
v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.888467348
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/15.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3041178637
Short name T440
Test name
Test status
Simulation time 16608532846 ps
CPU time 6.22 seconds
Started Sep 24 08:12:40 AM UTC 24
Finished Sep 24 08:12:48 AM UTC 24
Peak memory 215676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041178637 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_bit_bash.3041178637
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3056248734
Short name T455
Test name
Test status
Simulation time 4254205690 ps
CPU time 16.62 seconds
Started Sep 24 08:12:40 AM UTC 24
Finished Sep 24 08:12:58 AM UTC 24
Peak memory 215664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056248734 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.3056248734
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2853666808
Short name T386
Test name
Test status
Simulation time 194390616 ps
CPU time 2.06 seconds
Started Sep 24 08:12:40 AM UTC 24
Finished Sep 24 08:12:43 AM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853666808 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.2853666808
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3343853760
Short name T446
Test name
Test status
Simulation time 376274451 ps
CPU time 6.71 seconds
Started Sep 24 08:12:45 AM UTC 24
Finished Sep 24 08:12:53 AM UTC 24
Peak memory 215608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343853760 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_csr_outstanding.3343853760
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/15.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_errors.3066149984
Short name T439
Test name
Test status
Simulation time 186810762 ps
CPU time 4.02 seconds
Started Sep 24 08:12:43 AM UTC 24
Finished Sep 24 08:12:48 AM UTC 24
Peak memory 226028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066149984 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.3066149984
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/15.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2830819343
Short name T229
Test name
Test status
Simulation time 3144098893 ps
CPU time 15.41 seconds
Started Sep 24 08:12:43 AM UTC 24
Finished Sep 24 08:12:59 AM UTC 24
Peak memory 232180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830819343 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2830819343
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/15.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3619663422
Short name T448
Test name
Test status
Simulation time 145843453 ps
CPU time 4.34 seconds
Started Sep 24 08:12:48 AM UTC 24
Finished Sep 24 08:12:54 AM UTC 24
Peak memory 232592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=3619663422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_
rand_reset.3619663422
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_rw.992812627
Short name T444
Test name
Test status
Simulation time 182907258 ps
CPU time 1.87 seconds
Started Sep 24 08:12:47 AM UTC 24
Finished Sep 24 08:12:50 AM UTC 24
Peak memory 225416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992812627 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/r
v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.992812627
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/16.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.434916102
Short name T479
Test name
Test status
Simulation time 13461293447 ps
CPU time 56.77 seconds
Started Sep 24 08:12:46 AM UTC 24
Finished Sep 24 08:13:44 AM UTC 24
Peak memory 215532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434916102 -assert nopostpro
c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_bit_bash.434916102
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2237545677
Short name T458
Test name
Test status
Simulation time 2412922383 ps
CPU time 11.99 seconds
Started Sep 24 08:12:46 AM UTC 24
Finished Sep 24 08:12:59 AM UTC 24
Peak memory 215540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237545677 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.2237545677
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2243045866
Short name T441
Test name
Test status
Simulation time 349826958 ps
CPU time 2.14 seconds
Started Sep 24 08:12:45 AM UTC 24
Finished Sep 24 08:12:48 AM UTC 24
Peak memory 215384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243045866 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.2243045866
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3542758552
Short name T454
Test name
Test status
Simulation time 262439396 ps
CPU time 8.86 seconds
Started Sep 24 08:12:48 AM UTC 24
Finished Sep 24 08:12:58 AM UTC 24
Peak memory 215700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542758552 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_csr_outstanding.3542758552
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/16.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_errors.3017770672
Short name T451
Test name
Test status
Simulation time 329250501 ps
CPU time 8.65 seconds
Started Sep 24 08:12:46 AM UTC 24
Finished Sep 24 08:12:56 AM UTC 24
Peak memory 226012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017770672 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.3017770672
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/16.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.455957863
Short name T452
Test name
Test status
Simulation time 132631973 ps
CPU time 4.71 seconds
Started Sep 24 08:12:52 AM UTC 24
Finished Sep 24 08:12:57 AM UTC 24
Peak memory 230040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=455957863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_r
and_reset.455957863
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_rw.3656199755
Short name T447
Test name
Test status
Simulation time 111397738 ps
CPU time 1.78 seconds
Started Sep 24 08:12:51 AM UTC 24
Finished Sep 24 08:12:53 AM UTC 24
Peak memory 225336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656199755 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.3656199755
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/17.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3592693803
Short name T481
Test name
Test status
Simulation time 34206365475 ps
CPU time 91.96 seconds
Started Sep 24 08:12:49 AM UTC 24
Finished Sep 24 08:14:23 AM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592693803 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_bit_bash.3592693803
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.4053268734
Short name T450
Test name
Test status
Simulation time 2249914105 ps
CPU time 5.12 seconds
Started Sep 24 08:12:49 AM UTC 24
Finished Sep 24 08:12:56 AM UTC 24
Peak memory 215532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053268734 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.4053268734
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.212546318
Short name T445
Test name
Test status
Simulation time 124192097 ps
CPU time 1.15 seconds
Started Sep 24 08:12:48 AM UTC 24
Finished Sep 24 08:12:50 AM UTC 24
Peak memory 215320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212546318 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.212546318
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.4093171473
Short name T459
Test name
Test status
Simulation time 677722411 ps
CPU time 6.63 seconds
Started Sep 24 08:12:52 AM UTC 24
Finished Sep 24 08:12:59 AM UTC 24
Peak memory 215544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093171473 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same_csr_outstanding.4093171473
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/17.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_errors.647617312
Short name T453
Test name
Test status
Simulation time 1294953243 ps
CPU time 7.31 seconds
Started Sep 24 08:12:49 AM UTC 24
Finished Sep 24 08:12:58 AM UTC 24
Peak memory 226036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647617312 -assert nopostproc +UVM_TESTNAME=rv_dm_base
_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_d
m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.647617312
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/17.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2675731538
Short name T464
Test name
Test status
Simulation time 147887248 ps
CPU time 3.29 seconds
Started Sep 24 08:12:57 AM UTC 24
Finished Sep 24 08:13:01 AM UTC 24
Peak memory 232592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=2675731538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_
rand_reset.2675731538
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_rw.1277903962
Short name T457
Test name
Test status
Simulation time 108401625 ps
CPU time 2.08 seconds
Started Sep 24 08:12:56 AM UTC 24
Finished Sep 24 08:12:59 AM UTC 24
Peak memory 225968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277903962 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.1277903962
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/18.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1108181402
Short name T480
Test name
Test status
Simulation time 12369250098 ps
CPU time 52.2 seconds
Started Sep 24 08:12:54 AM UTC 24
Finished Sep 24 08:13:48 AM UTC 24
Peak memory 215764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108181402 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_bit_bash.1108181402
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.4066908405
Short name T456
Test name
Test status
Simulation time 1740116628 ps
CPU time 3.49 seconds
Started Sep 24 08:12:54 AM UTC 24
Finished Sep 24 08:12:58 AM UTC 24
Peak memory 215464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066908405 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.4066908405
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.674668390
Short name T449
Test name
Test status
Simulation time 454598763 ps
CPU time 2.69 seconds
Started Sep 24 08:12:52 AM UTC 24
Finished Sep 24 08:12:55 AM UTC 24
Peak memory 215396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674668390 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.674668390
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.671310612
Short name T467
Test name
Test status
Simulation time 1716253481 ps
CPU time 8.25 seconds
Started Sep 24 08:12:56 AM UTC 24
Finished Sep 24 08:13:05 AM UTC 24
Peak memory 215672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671310612 -assert nopostproc +UV
M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same_csr_outstanding.671310612
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/18.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_errors.645531850
Short name T461
Test name
Test status
Simulation time 187390083 ps
CPU time 4.56 seconds
Started Sep 24 08:12:55 AM UTC 24
Finished Sep 24 08:13:00 AM UTC 24
Peak memory 225916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645531850 -assert nopostproc +UVM_TESTNAME=rv_dm_base
_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_d
m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.645531850
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/18.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_intg_err.746752799
Short name T473
Test name
Test status
Simulation time 5886899301 ps
CPU time 23.26 seconds
Started Sep 24 08:12:55 AM UTC 24
Finished Sep 24 08:13:19 AM UTC 24
Peak memory 225912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746752799 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.746752799
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/18.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2738998597
Short name T466
Test name
Test status
Simulation time 144570610 ps
CPU time 2.79 seconds
Started Sep 24 08:13:01 AM UTC 24
Finished Sep 24 08:13:04 AM UTC 24
Peak memory 227920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=2738998597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_
rand_reset.2738998597
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_rw.4080318926
Short name T465
Test name
Test status
Simulation time 147743181 ps
CPU time 2.83 seconds
Started Sep 24 08:12:59 AM UTC 24
Finished Sep 24 08:13:03 AM UTC 24
Peak memory 229876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080318926 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.4080318926
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/19.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.3050127948
Short name T474
Test name
Test status
Simulation time 9803864267 ps
CPU time 21.12 seconds
Started Sep 24 08:12:58 AM UTC 24
Finished Sep 24 08:13:20 AM UTC 24
Peak memory 215700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050127948 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_bit_bash.3050127948
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1482303597
Short name T472
Test name
Test status
Simulation time 5316504697 ps
CPU time 16.42 seconds
Started Sep 24 08:12:58 AM UTC 24
Finished Sep 24 08:13:16 AM UTC 24
Peak memory 215504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482303597 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.1482303597
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1577105987
Short name T462
Test name
Test status
Simulation time 312551523 ps
CPU time 1.4 seconds
Started Sep 24 08:12:58 AM UTC 24
Finished Sep 24 08:13:01 AM UTC 24
Peak memory 215000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577105987 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.1577105987
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3480488349
Short name T469
Test name
Test status
Simulation time 836790449 ps
CPU time 6.1 seconds
Started Sep 24 08:13:00 AM UTC 24
Finished Sep 24 08:13:08 AM UTC 24
Peak memory 215536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480488349 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_csr_outstanding.3480488349
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/19.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_errors.609229988
Short name T468
Test name
Test status
Simulation time 1404361369 ps
CPU time 7.02 seconds
Started Sep 24 08:12:59 AM UTC 24
Finished Sep 24 08:13:07 AM UTC 24
Peak memory 225840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609229988 -assert nopostproc +UVM_TESTNAME=rv_dm_base
_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_d
m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.609229988
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/19.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_intg_err.4245967361
Short name T478
Test name
Test status
Simulation time 4868298586 ps
CPU time 37.86 seconds
Started Sep 24 08:12:59 AM UTC 24
Finished Sep 24 08:13:39 AM UTC 24
Peak memory 226036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245967361 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.4245967361
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/19.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1897131333
Short name T418
Test name
Test status
Simulation time 4112600777 ps
CPU time 98.56 seconds
Started Sep 24 08:10:51 AM UTC 24
Finished Sep 24 08:12:32 AM UTC 24
Peak memory 226036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897131333 -ass
ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_aliasing.1897131333
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/2.rv_dm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2712175604
Short name T179
Test name
Test status
Simulation time 10704116045 ps
CPU time 32.97 seconds
Started Sep 24 08:11:07 AM UTC 24
Finished Sep 24 08:11:41 AM UTC 24
Peak memory 225868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712175604 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.2712175604
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/2.rv_dm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1087177560
Short name T139
Test name
Test status
Simulation time 253233530 ps
CPU time 2.45 seconds
Started Sep 24 08:11:06 AM UTC 24
Finished Sep 24 08:11:09 AM UTC 24
Peak memory 225936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087177560 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.1087177560
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/2.rv_dm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_rw.2191509138
Short name T140
Test name
Test status
Simulation time 118019487 ps
CPU time 2.68 seconds
Started Sep 24 08:11:06 AM UTC 24
Finished Sep 24 08:11:10 AM UTC 24
Peak memory 229932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191509138 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.2191509138
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/2.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1780318879
Short name T381
Test name
Test status
Simulation time 26947647655 ps
CPU time 47.36 seconds
Started Sep 24 08:10:56 AM UTC 24
Finished Sep 24 08:11:45 AM UTC 24
Peak memory 215600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780318879 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_aliasing.1780318879
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.4266658578
Short name T358
Test name
Test status
Simulation time 9051241520 ps
CPU time 13.96 seconds
Started Sep 24 08:10:55 AM UTC 24
Finished Sep 24 08:11:10 AM UTC 24
Peak memory 215604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266658578 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_bit_bash.4266658578
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1638014953
Short name T352
Test name
Test status
Simulation time 1140365809 ps
CPU time 7.66 seconds
Started Sep 24 08:10:55 AM UTC 24
Finished Sep 24 08:11:04 AM UTC 24
Peak memory 215544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638014953 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_hw_reset.1638014953
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1681971160
Short name T355
Test name
Test status
Simulation time 6244079512 ps
CPU time 9.86 seconds
Started Sep 24 08:10:55 AM UTC 24
Finished Sep 24 08:11:06 AM UTC 24
Peak memory 215664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681971160 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1681971160
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1836184163
Short name T351
Test name
Test status
Simulation time 539551623 ps
CPU time 3.85 seconds
Started Sep 24 08:10:55 AM UTC 24
Finished Sep 24 08:11:00 AM UTC 24
Peak memory 215392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836184163 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_aliasing.1836184163
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2515671408
Short name T365
Test name
Test status
Simulation time 5007780914 ps
CPU time 26.56 seconds
Started Sep 24 08:10:53 AM UTC 24
Finished Sep 24 08:11:21 AM UTC 24
Peak memory 215636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515671408 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_bit_bash.2515671408
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3433278348
Short name T349
Test name
Test status
Simulation time 486034427 ps
CPU time 1.82 seconds
Started Sep 24 08:10:52 AM UTC 24
Finished Sep 24 08:10:55 AM UTC 24
Peak memory 215320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433278348 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_hw_reset.3433278348
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1205193448
Short name T348
Test name
Test status
Simulation time 177535910 ps
CPU time 1.86 seconds
Started Sep 24 08:10:52 AM UTC 24
Finished Sep 24 08:10:55 AM UTC 24
Peak memory 215316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205193448 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.1205193448
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1367449801
Short name T357
Test name
Test status
Simulation time 115323631 ps
CPU time 1.24 seconds
Started Sep 24 08:11:05 AM UTC 24
Finished Sep 24 08:11:07 AM UTC 24
Peak memory 215376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367449801 -assert nopostproc +UVM
_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_partial_access.1367449801
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/2.rv_dm_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_walk.2240569107
Short name T356
Test name
Test status
Simulation time 71753711 ps
CPU time 0.99 seconds
Started Sep 24 08:11:05 AM UTC 24
Finished Sep 24 08:11:07 AM UTC 24
Peak memory 215316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240569107 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.2240569107
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/2.rv_dm_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.872616878
Short name T141
Test name
Test status
Simulation time 298740679 ps
CPU time 9.51 seconds
Started Sep 24 08:11:07 AM UTC 24
Finished Sep 24 08:11:18 AM UTC 24
Peak memory 215472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872616878 -assert nopostproc +UV
M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_csr_outstanding.872616878
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/2.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.3632185104
Short name T419
Test name
Test status
Simulation time 5831286747 ps
CPU time 92.23 seconds
Started Sep 24 08:10:57 AM UTC 24
Finished Sep 24 08:12:32 AM UTC 24
Peak memory 232800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3632185104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_re
set.3632185104
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_errors.4243270189
Short name T354
Test name
Test status
Simulation time 151197810 ps
CPU time 5.69 seconds
Started Sep 24 08:10:58 AM UTC 24
Finished Sep 24 08:11:05 AM UTC 24
Peak memory 225900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243270189 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.4243270189
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/2.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.617007894
Short name T185
Test name
Test status
Simulation time 585247549 ps
CPU time 13.48 seconds
Started Sep 24 08:11:01 AM UTC 24
Finished Sep 24 08:11:15 AM UTC 24
Peak memory 225980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617007894 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.617007894
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/2.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.731869683
Short name T388
Test name
Test status
Simulation time 777940942 ps
CPU time 34.06 seconds
Started Sep 24 08:11:20 AM UTC 24
Finished Sep 24 08:11:56 AM UTC 24
Peak memory 215520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731869683 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.731869683
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/3.rv_dm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.477734396
Short name T142
Test name
Test status
Simulation time 235419518 ps
CPU time 2.35 seconds
Started Sep 24 08:11:19 AM UTC 24
Finished Sep 24 08:11:22 AM UTC 24
Peak memory 225848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477734396 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.477734396
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/3.rv_dm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1126043897
Short name T366
Test name
Test status
Simulation time 62101905 ps
CPU time 2.71 seconds
Started Sep 24 08:11:21 AM UTC 24
Finished Sep 24 08:11:25 AM UTC 24
Peak memory 225984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=1126043897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_r
and_reset.1126043897
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_rw.20636732
Short name T153
Test name
Test status
Simulation time 110081699 ps
CPU time 2.27 seconds
Started Sep 24 08:11:20 AM UTC 24
Finished Sep 24 08:11:23 AM UTC 24
Peak memory 225912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20636732 -assert nopostproc +UVM_TESTNAME=rv_dm_ba
se_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv
_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.20636732
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/3.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3154550368
Short name T482
Test name
Test status
Simulation time 62386378274 ps
CPU time 191.85 seconds
Started Sep 24 08:11:15 AM UTC 24
Finished Sep 24 08:14:29 AM UTC 24
Peak memory 215624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154550368 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_aliasing.3154550368
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.884072232
Short name T383
Test name
Test status
Simulation time 34153689047 ps
CPU time 31.37 seconds
Started Sep 24 08:11:15 AM UTC 24
Finished Sep 24 08:11:47 AM UTC 24
Peak memory 215692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884072232 -assert nopostpro
c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_bit_bash.884072232
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.4048005423
Short name T149
Test name
Test status
Simulation time 11052194572 ps
CPU time 18.28 seconds
Started Sep 24 08:11:13 AM UTC 24
Finished Sep 24 08:11:33 AM UTC 24
Peak memory 215676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048005423 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_hw_reset.4048005423
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.119028621
Short name T369
Test name
Test status
Simulation time 4397896440 ps
CPU time 15.22 seconds
Started Sep 24 08:11:13 AM UTC 24
Finished Sep 24 08:11:30 AM UTC 24
Peak memory 215608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119028621 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.119028621
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3449054579
Short name T360
Test name
Test status
Simulation time 965543328 ps
CPU time 2.01 seconds
Started Sep 24 08:11:11 AM UTC 24
Finished Sep 24 08:11:14 AM UTC 24
Peak memory 215456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449054579 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_aliasing.3449054579
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3326780858
Short name T372
Test name
Test status
Simulation time 8606975601 ps
CPU time 21.03 seconds
Started Sep 24 08:11:10 AM UTC 24
Finished Sep 24 08:11:33 AM UTC 24
Peak memory 215636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326780858 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_bit_bash.3326780858
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3581810012
Short name T359
Test name
Test status
Simulation time 604715314 ps
CPU time 2.52 seconds
Started Sep 24 08:11:10 AM UTC 24
Finished Sep 24 08:11:14 AM UTC 24
Peak memory 215392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581810012 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_hw_reset.3581810012
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.643902632
Short name T361
Test name
Test status
Simulation time 843223366 ps
CPU time 5.28 seconds
Started Sep 24 08:11:10 AM UTC 24
Finished Sep 24 08:11:17 AM UTC 24
Peak memory 215456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643902632 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.643902632
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1200003473
Short name T363
Test name
Test status
Simulation time 29778502 ps
CPU time 1.09 seconds
Started Sep 24 08:11:18 AM UTC 24
Finished Sep 24 08:11:20 AM UTC 24
Peak memory 215376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200003473 -assert nopostproc +UVM
_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_partial_access.1200003473
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/3.rv_dm_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_walk.2657292592
Short name T364
Test name
Test status
Simulation time 107298050 ps
CPU time 1.63 seconds
Started Sep 24 08:11:18 AM UTC 24
Finished Sep 24 08:11:20 AM UTC 24
Peak memory 215316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657292592 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.2657292592
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/3.rv_dm_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1201649001
Short name T166
Test name
Test status
Simulation time 309548976 ps
CPU time 4.93 seconds
Started Sep 24 08:11:20 AM UTC 24
Finished Sep 24 08:11:26 AM UTC 24
Peak memory 215540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201649001 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_csr_outstanding.1201649001
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/3.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.2892866444
Short name T121
Test name
Test status
Simulation time 679794050 ps
CPU time 16.64 seconds
Started Sep 24 08:11:15 AM UTC 24
Finished Sep 24 08:11:32 AM UTC 24
Peak memory 225944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2892866444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_re
set.2892866444
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_errors.3135822393
Short name T362
Test name
Test status
Simulation time 221091860 ps
CPU time 2.84 seconds
Started Sep 24 08:11:16 AM UTC 24
Finished Sep 24 08:11:20 AM UTC 24
Peak memory 225884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135822393 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.3135822393
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/3.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2624338214
Short name T178
Test name
Test status
Simulation time 2910026318 ps
CPU time 19.53 seconds
Started Sep 24 08:11:16 AM UTC 24
Finished Sep 24 08:11:36 AM UTC 24
Peak memory 232684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624338214 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.2624338214
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/3.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3783358050
Short name T437
Test name
Test status
Simulation time 3550826338 ps
CPU time 82.44 seconds
Started Sep 24 08:11:21 AM UTC 24
Finished Sep 24 08:12:46 AM UTC 24
Peak memory 226128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783358050 -ass
ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_aliasing.3783358050
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/4.rv_dm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2899131711
Short name T460
Test name
Test status
Simulation time 8733060093 ps
CPU time 83.33 seconds
Started Sep 24 08:11:34 AM UTC 24
Finished Sep 24 08:12:59 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899131711 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.2899131711
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/4.rv_dm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2744541301
Short name T160
Test name
Test status
Simulation time 168318892 ps
CPU time 3.21 seconds
Started Sep 24 08:11:33 AM UTC 24
Finished Sep 24 08:11:37 AM UTC 24
Peak memory 225800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744541301 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.2744541301
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/4.rv_dm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3351823173
Short name T181
Test name
Test status
Simulation time 504831590 ps
CPU time 4.28 seconds
Started Sep 24 08:11:36 AM UTC 24
Finished Sep 24 08:11:41 AM UTC 24
Peak memory 230088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=3351823173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_r
and_reset.3351823173
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_rw.31735216
Short name T182
Test name
Test status
Simulation time 181390812 ps
CPU time 3.02 seconds
Started Sep 24 08:11:33 AM UTC 24
Finished Sep 24 08:11:37 AM UTC 24
Peak memory 225744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31735216 -assert nopostproc +UVM_TESTNAME=rv_dm_ba
se_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv
_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.31735216
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/4.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2663331317
Short name T471
Test name
Test status
Simulation time 76915493867 ps
CPU time 103.28 seconds
Started Sep 24 08:11:29 AM UTC 24
Finished Sep 24 08:13:14 AM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663331317 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_aliasing.2663331317
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3699249306
Short name T412
Test name
Test status
Simulation time 26607885820 ps
CPU time 60.04 seconds
Started Sep 24 08:11:27 AM UTC 24
Finished Sep 24 08:12:28 AM UTC 24
Peak memory 215520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699249306 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_bit_bash.3699249306
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3733113914
Short name T148
Test name
Test status
Simulation time 4122936991 ps
CPU time 4.76 seconds
Started Sep 24 08:11:25 AM UTC 24
Finished Sep 24 08:11:31 AM UTC 24
Peak memory 215676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733113914 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_hw_reset.3733113914
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.839256452
Short name T376
Test name
Test status
Simulation time 3517310145 ps
CPU time 10.65 seconds
Started Sep 24 08:11:27 AM UTC 24
Finished Sep 24 08:11:39 AM UTC 24
Peak memory 215524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839256452 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.839256452
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.686242847
Short name T370
Test name
Test status
Simulation time 697670042 ps
CPU time 3.4 seconds
Started Sep 24 08:11:25 AM UTC 24
Finished Sep 24 08:11:30 AM UTC 24
Peak memory 215388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686242847 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_aliasing.686242847
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.352836000
Short name T380
Test name
Test status
Simulation time 2818490951 ps
CPU time 17.98 seconds
Started Sep 24 08:11:24 AM UTC 24
Finished Sep 24 08:11:44 AM UTC 24
Peak memory 215700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352836000 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_bit_bash.352836000
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2119304136
Short name T367
Test name
Test status
Simulation time 230608912 ps
CPU time 1.57 seconds
Started Sep 24 08:11:22 AM UTC 24
Finished Sep 24 08:11:25 AM UTC 24
Peak memory 215320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119304136 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_hw_reset.2119304136
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.966680647
Short name T368
Test name
Test status
Simulation time 436565604 ps
CPU time 3.41 seconds
Started Sep 24 08:11:23 AM UTC 24
Finished Sep 24 08:11:28 AM UTC 24
Peak memory 215320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966680647 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.966680647
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1688114415
Short name T374
Test name
Test status
Simulation time 72233723 ps
CPU time 1.36 seconds
Started Sep 24 08:11:33 AM UTC 24
Finished Sep 24 08:11:35 AM UTC 24
Peak memory 215376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688114415 -assert nopostproc +UVM
_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_partial_access.1688114415
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/4.rv_dm_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_walk.174990419
Short name T373
Test name
Test status
Simulation time 103688275 ps
CPU time 1.12 seconds
Started Sep 24 08:11:33 AM UTC 24
Finished Sep 24 08:11:35 AM UTC 24
Peak memory 215316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174990419 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.174990419
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/4.rv_dm_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2289700523
Short name T167
Test name
Test status
Simulation time 483506904 ps
CPU time 4.08 seconds
Started Sep 24 08:11:36 AM UTC 24
Finished Sep 24 08:11:41 AM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289700523 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_csr_outstanding.2289700523
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/4.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.473361093
Short name T117
Test name
Test status
Simulation time 6331061752 ps
CPU time 75.23 seconds
Started Sep 24 08:11:31 AM UTC 24
Finished Sep 24 08:12:48 AM UTC 24
Peak memory 225964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=473361093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.473361093
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_errors.4288194325
Short name T375
Test name
Test status
Simulation time 543387809 ps
CPU time 5.36 seconds
Started Sep 24 08:11:31 AM UTC 24
Finished Sep 24 08:11:37 AM UTC 24
Peak memory 225952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288194325 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.4288194325
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/4.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3750217738
Short name T227
Test name
Test status
Simulation time 3138551230 ps
CPU time 21.27 seconds
Started Sep 24 08:11:32 AM UTC 24
Finished Sep 24 08:11:54 AM UTC 24
Peak memory 227952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750217738 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.3750217738
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/4.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2711997816
Short name T384
Test name
Test status
Simulation time 119331597 ps
CPU time 4.86 seconds
Started Sep 24 08:11:43 AM UTC 24
Finished Sep 24 08:11:49 AM UTC 24
Peak memory 232132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=2711997816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_r
and_reset.2711997816
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_rw.953699718
Short name T161
Test name
Test status
Simulation time 137146430 ps
CPU time 2.8 seconds
Started Sep 24 08:11:42 AM UTC 24
Finished Sep 24 08:11:45 AM UTC 24
Peak memory 225872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953699718 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/r
v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.953699718
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/5.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.1288773982
Short name T387
Test name
Test status
Simulation time 3130804509 ps
CPU time 13.54 seconds
Started Sep 24 08:11:38 AM UTC 24
Finished Sep 24 08:11:53 AM UTC 24
Peak memory 215604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288773982 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_bit_bash.1288773982
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1661797236
Short name T379
Test name
Test status
Simulation time 1624825180 ps
CPU time 3.49 seconds
Started Sep 24 08:11:38 AM UTC 24
Finished Sep 24 08:11:43 AM UTC 24
Peak memory 215572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661797236 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.1661797236
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3702663870
Short name T377
Test name
Test status
Simulation time 187981173 ps
CPU time 1.7 seconds
Started Sep 24 08:11:37 AM UTC 24
Finished Sep 24 08:11:40 AM UTC 24
Peak memory 215312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702663870 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.3702663870
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2270876639
Short name T169
Test name
Test status
Simulation time 1673974271 ps
CPU time 11.44 seconds
Started Sep 24 08:11:42 AM UTC 24
Finished Sep 24 08:11:54 AM UTC 24
Peak memory 215476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270876639 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_csr_outstanding.2270876639
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/5.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2881158088
Short name T434
Test name
Test status
Simulation time 10083171625 ps
CPU time 61.81 seconds
Started Sep 24 08:11:38 AM UTC 24
Finished Sep 24 08:12:42 AM UTC 24
Peak memory 230140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2881158088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_re
set.2881158088
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2710921754
Short name T398
Test name
Test status
Simulation time 2208515842 ps
CPU time 23.4 seconds
Started Sep 24 08:11:41 AM UTC 24
Finished Sep 24 08:12:05 AM UTC 24
Peak memory 232180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710921754 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.2710921754
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/5.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2144298151
Short name T119
Test name
Test status
Simulation time 84698613 ps
CPU time 2.89 seconds
Started Sep 24 08:11:48 AM UTC 24
Finished Sep 24 08:11:52 AM UTC 24
Peak memory 230176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=2144298151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_r
and_reset.2144298151
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_rw.666360574
Short name T162
Test name
Test status
Simulation time 131231371 ps
CPU time 3.22 seconds
Started Sep 24 08:11:46 AM UTC 24
Finished Sep 24 08:11:50 AM UTC 24
Peak memory 225836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666360574 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/r
v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.666360574
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/6.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3801928298
Short name T409
Test name
Test status
Simulation time 13822356649 ps
CPU time 41.06 seconds
Started Sep 24 08:11:44 AM UTC 24
Finished Sep 24 08:12:26 AM UTC 24
Peak memory 215732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801928298 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_bit_bash.3801928298
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2072435225
Short name T395
Test name
Test status
Simulation time 11381187195 ps
CPU time 17.46 seconds
Started Sep 24 08:11:44 AM UTC 24
Finished Sep 24 08:12:03 AM UTC 24
Peak memory 215540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072435225 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.2072435225
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1037987017
Short name T382
Test name
Test status
Simulation time 529334465 ps
CPU time 1.69 seconds
Started Sep 24 08:11:43 AM UTC 24
Finished Sep 24 08:11:45 AM UTC 24
Peak memory 215312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037987017 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.1037987017
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.4153693318
Short name T168
Test name
Test status
Simulation time 638232922 ps
CPU time 4.88 seconds
Started Sep 24 08:11:46 AM UTC 24
Finished Sep 24 08:11:52 AM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153693318 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_csr_outstanding.4153693318
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/6.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3404972738
Short name T114
Test name
Test status
Simulation time 4754467887 ps
CPU time 57.6 seconds
Started Sep 24 08:11:45 AM UTC 24
Finished Sep 24 08:12:44 AM UTC 24
Peak memory 230224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3404972738 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_re
set.3404972738
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_errors.2802071080
Short name T389
Test name
Test status
Simulation time 216104413 ps
CPU time 8.5 seconds
Started Sep 24 08:11:46 AM UTC 24
Finished Sep 24 08:11:56 AM UTC 24
Peak memory 225904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802071080 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.2802071080
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/6.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2517086628
Short name T392
Test name
Test status
Simulation time 194170537 ps
CPU time 2.9 seconds
Started Sep 24 08:11:55 AM UTC 24
Finished Sep 24 08:11:59 AM UTC 24
Peak memory 225848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=2517086628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_r
and_reset.2517086628
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_rw.2315254564
Short name T163
Test name
Test status
Simulation time 90847600 ps
CPU time 1.55 seconds
Started Sep 24 08:11:54 AM UTC 24
Finished Sep 24 08:11:56 AM UTC 24
Peak memory 225432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315254564 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.2315254564
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/7.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.3019964766
Short name T396
Test name
Test status
Simulation time 15672917197 ps
CPU time 9.2 seconds
Started Sep 24 08:11:52 AM UTC 24
Finished Sep 24 08:12:03 AM UTC 24
Peak memory 215692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019964766 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_bit_bash.3019964766
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2790890306
Short name T390
Test name
Test status
Simulation time 940522371 ps
CPU time 3.87 seconds
Started Sep 24 08:11:51 AM UTC 24
Finished Sep 24 08:11:56 AM UTC 24
Peak memory 215476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790890306 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.2790890306
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1592340028
Short name T385
Test name
Test status
Simulation time 232568766 ps
CPU time 1.29 seconds
Started Sep 24 08:11:49 AM UTC 24
Finished Sep 24 08:11:52 AM UTC 24
Peak memory 215316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592340028 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1592340028
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.236286751
Short name T170
Test name
Test status
Simulation time 2226574023 ps
CPU time 9.67 seconds
Started Sep 24 08:11:55 AM UTC 24
Finished Sep 24 08:12:06 AM UTC 24
Peak memory 215624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236286751 -assert nopostproc +UV
M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_csr_outstanding.236286751
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/7.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_errors.1733251460
Short name T391
Test name
Test status
Simulation time 247829232 ps
CPU time 3.97 seconds
Started Sep 24 08:11:54 AM UTC 24
Finished Sep 24 08:11:59 AM UTC 24
Peak memory 226000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733251460 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.1733251460
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/7.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2807535374
Short name T225
Test name
Test status
Simulation time 2302092185 ps
CPU time 15.83 seconds
Started Sep 24 08:11:54 AM UTC 24
Finished Sep 24 08:12:11 AM UTC 24
Peak memory 226036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807535374 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2807535374
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/7.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2956747290
Short name T123
Test name
Test status
Simulation time 216484217 ps
CPU time 2.71 seconds
Started Sep 24 08:12:03 AM UTC 24
Finished Sep 24 08:12:07 AM UTC 24
Peak memory 225908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=2956747290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_r
and_reset.2956747290
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_rw.2374978993
Short name T397
Test name
Test status
Simulation time 143111824 ps
CPU time 2.7 seconds
Started Sep 24 08:12:00 AM UTC 24
Finished Sep 24 08:12:04 AM UTC 24
Peak memory 225904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374978993 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.2374978993
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/8.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1025479379
Short name T416
Test name
Test status
Simulation time 8680765355 ps
CPU time 32.99 seconds
Started Sep 24 08:11:57 AM UTC 24
Finished Sep 24 08:12:31 AM UTC 24
Peak memory 215532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025479379 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_bit_bash.1025479379
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.4023705210
Short name T394
Test name
Test status
Simulation time 1214283145 ps
CPU time 2.15 seconds
Started Sep 24 08:11:57 AM UTC 24
Finished Sep 24 08:12:00 AM UTC 24
Peak memory 215476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023705210 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.4023705210
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3997006506
Short name T393
Test name
Test status
Simulation time 163451391 ps
CPU time 1.2 seconds
Started Sep 24 08:11:57 AM UTC 24
Finished Sep 24 08:11:59 AM UTC 24
Peak memory 215316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997006506 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.3997006506
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1285411523
Short name T171
Test name
Test status
Simulation time 942906961 ps
CPU time 6.35 seconds
Started Sep 24 08:12:01 AM UTC 24
Finished Sep 24 08:12:09 AM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285411523 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_csr_outstanding.1285411523
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/8.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3954423983
Short name T113
Test name
Test status
Simulation time 1755856988 ps
CPU time 20.29 seconds
Started Sep 24 08:11:57 AM UTC 24
Finished Sep 24 08:12:19 AM UTC 24
Peak memory 228024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3954423983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_re
set.3954423983
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_errors.1320904361
Short name T400
Test name
Test status
Simulation time 750989895 ps
CPU time 6.93 seconds
Started Sep 24 08:11:59 AM UTC 24
Finished Sep 24 08:12:07 AM UTC 24
Peak memory 225972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320904361 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.1320904361
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/8.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2526430573
Short name T237
Test name
Test status
Simulation time 1681123867 ps
CPU time 11.48 seconds
Started Sep 24 08:12:00 AM UTC 24
Finished Sep 24 08:12:13 AM UTC 24
Peak memory 225900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526430573 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.2526430573
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/8.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3431179083
Short name T403
Test name
Test status
Simulation time 434954083 ps
CPU time 4.96 seconds
Started Sep 24 08:12:11 AM UTC 24
Finished Sep 24 08:12:17 AM UTC 24
Peak memory 232136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=3431179083 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_r
and_reset.3431179083
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_rw.3640116612
Short name T164
Test name
Test status
Simulation time 192167995 ps
CPU time 3.44 seconds
Started Sep 24 08:12:08 AM UTC 24
Finished Sep 24 08:12:12 AM UTC 24
Peak memory 225776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640116612 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.3640116612
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/9.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.1601566891
Short name T463
Test name
Test status
Simulation time 9030332596 ps
CPU time 52.63 seconds
Started Sep 24 08:12:06 AM UTC 24
Finished Sep 24 08:13:01 AM UTC 24
Peak memory 215756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601566891 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_bit_bash.1601566891
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1101219803
Short name T408
Test name
Test status
Simulation time 7097013013 ps
CPU time 20.52 seconds
Started Sep 24 08:12:04 AM UTC 24
Finished Sep 24 08:12:26 AM UTC 24
Peak memory 215604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101219803 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.1101219803
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3066398954
Short name T399
Test name
Test status
Simulation time 221200259 ps
CPU time 1.81 seconds
Started Sep 24 08:12:03 AM UTC 24
Finished Sep 24 08:12:06 AM UTC 24
Peak memory 215316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066398954 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.3066398954
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3473807
Short name T156
Test name
Test status
Simulation time 435035768 ps
CPU time 6.78 seconds
Started Sep 24 08:12:10 AM UTC 24
Finished Sep 24 08:12:18 AM UTC 24
Peak memory 215540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473807 -assert nopostproc +UVM_
TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_csr_outstanding.3473807
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/9.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2941287065
Short name T115
Test name
Test status
Simulation time 2528185708 ps
CPU time 49.56 seconds
Started Sep 24 08:12:07 AM UTC 24
Finished Sep 24 08:12:58 AM UTC 24
Peak memory 228100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2941287065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_re
set.2941287065
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_errors.1650270518
Short name T401
Test name
Test status
Simulation time 192797603 ps
CPU time 3.75 seconds
Started Sep 24 08:12:07 AM UTC 24
Finished Sep 24 08:12:11 AM UTC 24
Peak memory 225972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650270518 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.1650270518
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/9.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3286988411
Short name T231
Test name
Test status
Simulation time 5676644765 ps
CPU time 19.98 seconds
Started Sep 24 08:12:08 AM UTC 24
Finished Sep 24 08:12:29 AM UTC 24
Peak memory 227928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286988411 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.3286988411
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/9.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.3198326707
Short name T88
Test name
Test status
Simulation time 12440550908 ps
CPU time 13.6 seconds
Started Sep 24 08:13:01 AM UTC 24
Finished Sep 24 08:13:16 AM UTC 24
Peak memory 226592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198326707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.3198326707
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_busy.1407945135
Short name T12
Test name
Test status
Simulation time 460543830 ps
CPU time 2.46 seconds
Started Sep 24 08:13:02 AM UTC 24
Finished Sep 24 08:13:05 AM UTC 24
Peak memory 215736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407945135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.1407945135
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_cmderr_busy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.2149454232
Short name T2
Test name
Test status
Simulation time 154397569 ps
CPU time 1.25 seconds
Started Sep 24 08:13:02 AM UTC 24
Finished Sep 24 08:13:04 AM UTC 24
Peak memory 215208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149454232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.2149454232
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_cmderr_exception/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.436031027
Short name T14
Test name
Test status
Simulation time 712482381 ps
CPU time 4.92 seconds
Started Sep 24 08:13:02 AM UTC 24
Finished Sep 24 08:13:08 AM UTC 24
Peak memory 215600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436031027 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.436031027
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_cmderr_not_supported/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_dataaddr_rw_access.688520423
Short name T6
Test name
Test status
Simulation time 125128961 ps
CPU time 0.95 seconds
Started Sep 24 08:13:05 AM UTC 24
Finished Sep 24 08:13:07 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688520423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_dataaddr_rw_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.688520423
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_dataaddr_rw_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_debug_disabled.3070445025
Short name T91
Test name
Test status
Simulation time 67930805 ps
CPU time 1.28 seconds
Started Sep 24 08:13:09 AM UTC 24
Finished Sep 24 08:13:11 AM UTC 24
Peak memory 236580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070445025 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.3070445025
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_debug_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2658152111
Short name T20
Test name
Test status
Simulation time 3212017718 ps
CPU time 10.59 seconds
Started Sep 24 08:13:01 AM UTC 24
Finished Sep 24 08:13:12 AM UTC 24
Peak memory 216348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658152111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_tl_access.2658152111
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_hart_unavail.3593818232
Short name T5
Test name
Test status
Simulation time 365673003 ps
CPU time 3 seconds
Started Sep 24 08:13:04 AM UTC 24
Finished Sep 24 08:13:08 AM UTC 24
Peak memory 215528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593818232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.3593818232
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_hart_unavail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_hartsel_warl.3129835913
Short name T29
Test name
Test status
Simulation time 95906421 ps
CPU time 1.3 seconds
Started Sep 24 08:13:10 AM UTC 24
Finished Sep 24 08:13:12 AM UTC 24
Peak memory 215328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129835913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.3129835913
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_hartsel_warl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.2970803278
Short name T8
Test name
Test status
Simulation time 645158002 ps
CPU time 2.01 seconds
Started Sep 24 08:13:08 AM UTC 24
Finished Sep 24 08:13:11 AM UTC 24
Peak memory 215332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970803278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.2970803278
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.3016907028
Short name T7
Test name
Test status
Simulation time 549954273 ps
CPU time 1.34 seconds
Started Sep 24 08:13:08 AM UTC 24
Finished Sep 24 08:13:10 AM UTC 24
Peak memory 215332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016907028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.3016907028
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_hard_reset.4011569406
Short name T16
Test name
Test status
Simulation time 272339536 ps
CPU time 2.69 seconds
Started Sep 24 08:13:09 AM UTC 24
Finished Sep 24 08:13:12 AM UTC 24
Peak memory 215600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011569406 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.4011569406
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_idle_hint.3052635842
Short name T26
Test name
Test status
Simulation time 347204708 ps
CPU time 1.45 seconds
Started Sep 24 08:13:07 AM UTC 24
Finished Sep 24 08:13:09 AM UTC 24
Peak memory 215332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052635842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.3052635842
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_halted.75130983
Short name T3
Test name
Test status
Simulation time 92066673 ps
CPU time 1.52 seconds
Started Sep 24 08:13:02 AM UTC 24
Finished Sep 24 08:13:05 AM UTC 24
Peak memory 215336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75130983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv
_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.75130983
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_halted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_resuming.2190576680
Short name T13
Test name
Test status
Simulation time 99692192 ps
CPU time 1.64 seconds
Started Sep 24 08:13:04 AM UTC 24
Finished Sep 24 08:13:07 AM UTC 24
Peak memory 215336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190576680 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.2190576680
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.1845222485
Short name T40
Test name
Test status
Simulation time 353728457 ps
CPU time 1.4 seconds
Started Sep 24 08:13:09 AM UTC 24
Finished Sep 24 08:13:11 AM UTC 24
Peak memory 214972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845222485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_progbuf_read_write_execute_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_d
m-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.1845222485
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_tl_access.2055693851
Short name T87
Test name
Test status
Simulation time 11087894571 ps
CPU time 11.77 seconds
Started Sep 24 08:13:01 AM UTC 24
Finished Sep 24 08:13:14 AM UTC 24
Peak memory 226340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055693851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2055693851
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_smoke.1528505016
Short name T1
Test name
Test status
Simulation time 607391891 ps
CPU time 1.76 seconds
Started Sep 24 08:13:01 AM UTC 24
Finished Sep 24 08:13:03 AM UTC 24
Peak memory 214876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528505016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.1528505016
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/0.rv_dm_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_abstractcmd_status.440029044
Short name T62
Test name
Test status
Simulation time 467279574 ps
CPU time 2.32 seconds
Started Sep 24 08:13:17 AM UTC 24
Finished Sep 24 08:13:20 AM UTC 24
Peak memory 215604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440029044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_abstractcmd_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.440029044
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_abstractcmd_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_alert_test.3891542058
Short name T50
Test name
Test status
Simulation time 73979051 ps
CPU time 0.81 seconds
Started Sep 24 08:13:19 AM UTC 24
Finished Sep 24 08:13:21 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891542058 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.3891542058
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_bad_sba_tl_access.3130377404
Short name T175
Test name
Test status
Simulation time 11075243610 ps
CPU time 20.76 seconds
Started Sep 24 08:13:13 AM UTC 24
Finished Sep 24 08:13:35 AM UTC 24
Peak memory 226332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130377404 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.3130377404
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_buffered_enable.290106554
Short name T63
Test name
Test status
Simulation time 146852178 ps
CPU time 1.7 seconds
Started Sep 24 08:13:18 AM UTC 24
Finished Sep 24 08:13:21 AM UTC 24
Peak memory 257036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290106554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_buffered_enable.290106554
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_busy.3662203271
Short name T38
Test name
Test status
Simulation time 1001985436 ps
CPU time 2.66 seconds
Started Sep 24 08:13:13 AM UTC 24
Finished Sep 24 08:13:17 AM UTC 24
Peak memory 215604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662203271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.3662203271
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_cmderr_busy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.3240350841
Short name T67
Test name
Test status
Simulation time 1653781331 ps
CPU time 7.8 seconds
Started Sep 24 08:13:14 AM UTC 24
Finished Sep 24 08:13:23 AM UTC 24
Peak memory 215852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240350841 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.3240350841
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_cmderr_halt_resume/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_not_supported.1426342706
Short name T53
Test name
Test status
Simulation time 903632353 ps
CPU time 4.13 seconds
Started Sep 24 08:13:14 AM UTC 24
Finished Sep 24 08:13:19 AM UTC 24
Peak memory 215788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426342706 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.1426342706
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_cmderr_not_supported/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_dataaddr_rw_access.1267797394
Short name T209
Test name
Test status
Simulation time 200231460 ps
CPU time 1.24 seconds
Started Sep 24 08:13:15 AM UTC 24
Finished Sep 24 08:13:18 AM UTC 24
Peak memory 215332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267797394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.1267797394
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_dataaddr_rw_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_debug_disabled.2384594820
Short name T89
Test name
Test status
Simulation time 118406042 ps
CPU time 1.1 seconds
Started Sep 24 08:13:18 AM UTC 24
Finished Sep 24 08:13:20 AM UTC 24
Peak memory 236580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384594820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.2384594820
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_debug_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.1079441958
Short name T101
Test name
Test status
Simulation time 3014136568 ps
CPU time 2.11 seconds
Started Sep 24 08:13:13 AM UTC 24
Finished Sep 24 08:13:16 AM UTC 24
Peak memory 216292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079441958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_tl_access.1079441958
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_hart_unavail.3390914088
Short name T103
Test name
Test status
Simulation time 298128682 ps
CPU time 1.33 seconds
Started Sep 24 08:13:14 AM UTC 24
Finished Sep 24 08:13:16 AM UTC 24
Peak memory 215328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390914088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.3390914088
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_hart_unavail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.3591055127
Short name T98
Test name
Test status
Simulation time 293092338 ps
CPU time 2.14 seconds
Started Sep 24 08:13:17 AM UTC 24
Finished Sep 24 08:13:20 AM UTC 24
Peak memory 215788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591055127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.3591055127
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.2992942915
Short name T246
Test name
Test status
Simulation time 355430264 ps
CPU time 1.87 seconds
Started Sep 24 08:13:17 AM UTC 24
Finished Sep 24 08:13:19 AM UTC 24
Peak memory 215332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992942915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.2992942915
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3138228435
Short name T79
Test name
Test status
Simulation time 183949611 ps
CPU time 2.07 seconds
Started Sep 24 08:13:17 AM UTC 24
Finished Sep 24 08:13:20 AM UTC 24
Peak memory 215788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138228435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.3138228435
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_idle_hint.3887349052
Short name T81
Test name
Test status
Simulation time 512714191 ps
CPU time 1.4 seconds
Started Sep 24 08:13:16 AM UTC 24
Finished Sep 24 08:13:19 AM UTC 24
Peak memory 215332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887349052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.3887349052
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_halted.878471026
Short name T106
Test name
Test status
Simulation time 332522683 ps
CPU time 1.44 seconds
Started Sep 24 08:13:14 AM UTC 24
Finished Sep 24 08:13:17 AM UTC 24
Peak memory 215396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878471026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.878471026
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_mem_tl_access_halted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_resuming.54677158
Short name T30
Test name
Test status
Simulation time 493000070 ps
CPU time 1.65 seconds
Started Sep 24 08:13:14 AM UTC 24
Finished Sep 24 08:13:17 AM UTC 24
Peak memory 215276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54677158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv
_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.54677158
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_ndmreset_req.2764961949
Short name T44
Test name
Test status
Simulation time 595892201 ps
CPU time 1.34 seconds
Started Sep 24 08:13:16 AM UTC 24
Finished Sep 24 08:13:19 AM UTC 24
Peak memory 225128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764961949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.2764961949
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_ndmreset_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_progbuf_read_write_execute.3452075705
Short name T59
Test name
Test status
Simulation time 368862291 ps
CPU time 1.67 seconds
Started Sep 24 08:13:18 AM UTC 24
Finished Sep 24 08:13:20 AM UTC 24
Peak memory 215336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452075705 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_progbuf_read_write_execute_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_d
m-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.3452075705
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_rom_read_access.3069414997
Short name T65
Test name
Test status
Simulation time 65856477 ps
CPU time 1.27 seconds
Started Sep 24 08:13:18 AM UTC 24
Finished Sep 24 08:13:20 AM UTC 24
Peak memory 225132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069414997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_rom_read_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.3069414997
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_rom_read_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_debug_disabled.2361265357
Short name T22
Test name
Test status
Simulation time 5251156472 ps
CPU time 9.22 seconds
Started Sep 24 08:13:15 AM UTC 24
Finished Sep 24 08:13:26 AM UTC 24
Peak memory 216128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361265357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.2361265357
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_sba_debug_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_sec_cm.2187291496
Short name T95
Test name
Test status
Simulation time 388278873 ps
CPU time 1.52 seconds
Started Sep 24 08:13:19 AM UTC 24
Finished Sep 24 08:13:22 AM UTC 24
Peak memory 254956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187291496 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.2187291496
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_smoke.3114442514
Short name T84
Test name
Test status
Simulation time 1387746094 ps
CPU time 3.64 seconds
Started Sep 24 08:13:13 AM UTC 24
Finished Sep 24 08:13:17 AM UTC 24
Peak memory 215524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114442514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.3114442514
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.3634566067
Short name T52
Test name
Test status
Simulation time 81505449 ps
CPU time 0.96 seconds
Started Sep 24 08:13:18 AM UTC 24
Finished Sep 24 08:13:20 AM UTC 24
Peak memory 225132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634566067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sparse_lc_gate_fsm.3634566067
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_sparse_lc_gate_fsm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.2949085730
Short name T80
Test name
Test status
Simulation time 7422958826 ps
CPU time 9.42 seconds
Started Sep 24 08:13:19 AM UTC 24
Finished Sep 24 08:13:30 AM UTC 24
Peak memory 226164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949085730 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.2949085730
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.285578787
Short name T127
Test name
Test status
Simulation time 25223315409 ps
CPU time 98.37 seconds
Started Sep 24 08:13:19 AM UTC 24
Finished Sep 24 08:15:00 AM UTC 24
Peak memory 243132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=285578787 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress
_all_with_rand_reset.285578787
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/10.rv_dm_alert_test.1832145121
Short name T251
Test name
Test status
Simulation time 57871305 ps
CPU time 1 seconds
Started Sep 24 08:13:50 AM UTC 24
Finished Sep 24 08:13:52 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832145121 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.1832145121
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/10.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/10.rv_dm_autoincr_sba_tl_access.3483586367
Short name T261
Test name
Test status
Simulation time 10862910036 ps
CPU time 11.51 seconds
Started Sep 24 08:13:50 AM UTC 24
Finished Sep 24 08:14:03 AM UTC 24
Peak memory 226256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483586367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.3483586367
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.1025157577
Short name T222
Test name
Test status
Simulation time 2881432428 ps
CPU time 11.22 seconds
Started Sep 24 08:13:48 AM UTC 24
Finished Sep 24 08:14:00 AM UTC 24
Peak memory 216084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025157577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_tl_access.1025157577
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/10.rv_dm_sba_tl_access.477290488
Short name T216
Test name
Test status
Simulation time 2945717558 ps
CPU time 5.31 seconds
Started Sep 24 08:13:48 AM UTC 24
Finished Sep 24 08:13:54 AM UTC 24
Peak memory 216160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477290488 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.477290488
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/10.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/10.rv_dm_stress_all.493627233
Short name T17
Test name
Test status
Simulation time 2133315801 ps
CPU time 6.28 seconds
Started Sep 24 08:13:50 AM UTC 24
Finished Sep 24 08:13:58 AM UTC 24
Peak memory 215976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493627233 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.493627233
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/10.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/11.rv_dm_alert_test.2335353828
Short name T242
Test name
Test status
Simulation time 72401824 ps
CPU time 0.9 seconds
Started Sep 24 08:13:53 AM UTC 24
Finished Sep 24 08:13:54 AM UTC 24
Peak memory 215156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335353828 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.2335353828
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/11.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/11.rv_dm_autoincr_sba_tl_access.662330582
Short name T256
Test name
Test status
Simulation time 584431077 ps
CPU time 4.87 seconds
Started Sep 24 08:13:51 AM UTC 24
Finished Sep 24 08:13:57 AM UTC 24
Peak memory 226260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662330582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.662330582
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/11.rv_dm_bad_sba_tl_access.3899382631
Short name T268
Test name
Test status
Simulation time 9914945398 ps
CPU time 16.69 seconds
Started Sep 24 08:13:51 AM UTC 24
Finished Sep 24 08:14:09 AM UTC 24
Peak memory 216288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899382631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.3899382631
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/11.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.3749556247
Short name T220
Test name
Test status
Simulation time 2665044093 ps
CPU time 9.12 seconds
Started Sep 24 08:13:50 AM UTC 24
Finished Sep 24 08:14:01 AM UTC 24
Peak memory 216036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749556247 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_tl_access.3749556247
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/11.rv_dm_sba_tl_access.846795848
Short name T254
Test name
Test status
Simulation time 1937682934 ps
CPU time 2.99 seconds
Started Sep 24 08:13:50 AM UTC 24
Finished Sep 24 08:13:54 AM UTC 24
Peak memory 216156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846795848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.846795848
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/11.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/11.rv_dm_stress_all.2592155987
Short name T191
Test name
Test status
Simulation time 2690534815 ps
CPU time 8.53 seconds
Started Sep 24 08:13:53 AM UTC 24
Finished Sep 24 08:14:02 AM UTC 24
Peak memory 226168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592155987 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.2592155987
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/11.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/12.rv_dm_alert_test.3766157794
Short name T255
Test name
Test status
Simulation time 53672443 ps
CPU time 1.05 seconds
Started Sep 24 08:13:55 AM UTC 24
Finished Sep 24 08:13:57 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766157794 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.3766157794
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/12.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/12.rv_dm_autoincr_sba_tl_access.4110732888
Short name T266
Test name
Test status
Simulation time 8875858004 ps
CPU time 13.96 seconds
Started Sep 24 08:13:54 AM UTC 24
Finished Sep 24 08:14:09 AM UTC 24
Peak memory 226524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110732888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.4110732888
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/12.rv_dm_bad_sba_tl_access.2530165811
Short name T291
Test name
Test status
Simulation time 10894926771 ps
CPU time 25.39 seconds
Started Sep 24 08:13:54 AM UTC 24
Finished Sep 24 08:14:20 AM UTC 24
Peak memory 226332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530165811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.2530165811
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/12.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.1955761746
Short name T277
Test name
Test status
Simulation time 9033223909 ps
CPU time 20.09 seconds
Started Sep 24 08:13:53 AM UTC 24
Finished Sep 24 08:14:14 AM UTC 24
Peak memory 226396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955761746 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_tl_access.1955761746
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/12.rv_dm_sba_tl_access.3222316255
Short name T186
Test name
Test status
Simulation time 8993493467 ps
CPU time 16.6 seconds
Started Sep 24 08:13:53 AM UTC 24
Finished Sep 24 08:14:10 AM UTC 24
Peak memory 226332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222316255 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.3222316255
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/12.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/12.rv_dm_stress_all.3643671857
Short name T201
Test name
Test status
Simulation time 1428497977 ps
CPU time 6.53 seconds
Started Sep 24 08:13:55 AM UTC 24
Finished Sep 24 08:14:03 AM UTC 24
Peak memory 226040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643671857 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.3643671857
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/12.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/13.rv_dm_alert_test.2572462708
Short name T257
Test name
Test status
Simulation time 76217381 ps
CPU time 1.12 seconds
Started Sep 24 08:13:56 AM UTC 24
Finished Sep 24 08:13:58 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572462708 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.2572462708
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/13.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/13.rv_dm_autoincr_sba_tl_access.2155310245
Short name T273
Test name
Test status
Simulation time 8857495730 ps
CPU time 15.17 seconds
Started Sep 24 08:13:56 AM UTC 24
Finished Sep 24 08:14:13 AM UTC 24
Peak memory 226588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155310245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.2155310245
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.1450913608
Short name T259
Test name
Test status
Simulation time 1743420245 ps
CPU time 5.66 seconds
Started Sep 24 08:13:55 AM UTC 24
Finished Sep 24 08:14:02 AM UTC 24
Peak memory 226200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450913608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_tl_access.1450913608
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/13.rv_dm_sba_tl_access.1551895350
Short name T271
Test name
Test status
Simulation time 7536209555 ps
CPU time 13.83 seconds
Started Sep 24 08:13:55 AM UTC 24
Finished Sep 24 08:14:10 AM UTC 24
Peak memory 216168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551895350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.1551895350
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/13.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/13.rv_dm_stress_all.1724259249
Short name T36
Test name
Test status
Simulation time 7794282454 ps
CPU time 13.78 seconds
Started Sep 24 08:13:56 AM UTC 24
Finished Sep 24 08:14:11 AM UTC 24
Peak memory 215856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724259249 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.1724259249
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/13.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/14.rv_dm_alert_test.365857532
Short name T262
Test name
Test status
Simulation time 58148698 ps
CPU time 1.04 seconds
Started Sep 24 08:14:02 AM UTC 24
Finished Sep 24 08:14:04 AM UTC 24
Peak memory 215016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365857532 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.365857532
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/14.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/14.rv_dm_autoincr_sba_tl_access.464551705
Short name T269
Test name
Test status
Simulation time 8099784964 ps
CPU time 8.82 seconds
Started Sep 24 08:14:00 AM UTC 24
Finished Sep 24 08:14:09 AM UTC 24
Peak memory 226248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464551705 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.464551705
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/14.rv_dm_bad_sba_tl_access.563393946
Short name T289
Test name
Test status
Simulation time 11264179813 ps
CPU time 19.93 seconds
Started Sep 24 08:13:58 AM UTC 24
Finished Sep 24 08:14:20 AM UTC 24
Peak memory 226596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563393946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.563393946
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/14.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.1431291986
Short name T258
Test name
Test status
Simulation time 1695138428 ps
CPU time 1.71 seconds
Started Sep 24 08:13:58 AM UTC 24
Finished Sep 24 08:14:01 AM UTC 24
Peak memory 214976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431291986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_tl_access.1431291986
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/14.rv_dm_sba_tl_access.665838278
Short name T260
Test name
Test status
Simulation time 1270475676 ps
CPU time 3.87 seconds
Started Sep 24 08:13:57 AM UTC 24
Finished Sep 24 08:14:02 AM UTC 24
Peak memory 215956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665838278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.665838278
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/14.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/14.rv_dm_stress_all.4190346517
Short name T200
Test name
Test status
Simulation time 5572563711 ps
CPU time 9.16 seconds
Started Sep 24 08:14:01 AM UTC 24
Finished Sep 24 08:14:11 AM UTC 24
Peak memory 226240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190346517 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.4190346517
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/14.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/15.rv_dm_alert_test.439408326
Short name T263
Test name
Test status
Simulation time 42781015 ps
CPU time 1.06 seconds
Started Sep 24 08:14:04 AM UTC 24
Finished Sep 24 08:14:06 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439408326 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.439408326
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/15.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/15.rv_dm_autoincr_sba_tl_access.3090001647
Short name T264
Test name
Test status
Simulation time 2165457038 ps
CPU time 2.54 seconds
Started Sep 24 08:14:03 AM UTC 24
Finished Sep 24 08:14:07 AM UTC 24
Peak memory 226248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090001647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.3090001647
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/15.rv_dm_bad_sba_tl_access.2643786425
Short name T275
Test name
Test status
Simulation time 6044688845 ps
CPU time 9.1 seconds
Started Sep 24 08:14:03 AM UTC 24
Finished Sep 24 08:14:13 AM UTC 24
Peak memory 226260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643786425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.2643786425
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/15.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.1610352141
Short name T300
Test name
Test status
Simulation time 12775153442 ps
CPU time 19.72 seconds
Started Sep 24 08:14:03 AM UTC 24
Finished Sep 24 08:14:24 AM UTC 24
Peak memory 226404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610352141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_tl_access.1610352141
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/15.rv_dm_sba_tl_access.2714439132
Short name T267
Test name
Test status
Simulation time 2386138237 ps
CPU time 6.44 seconds
Started Sep 24 08:14:02 AM UTC 24
Finished Sep 24 08:14:09 AM UTC 24
Peak memory 216096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714439132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.2714439132
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/15.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/15.rv_dm_stress_all.1084025182
Short name T189
Test name
Test status
Simulation time 2038769168 ps
CPU time 7.6 seconds
Started Sep 24 08:14:03 AM UTC 24
Finished Sep 24 08:14:12 AM UTC 24
Peak memory 226300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084025182 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.1084025182
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/15.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/16.rv_dm_alert_test.218766972
Short name T172
Test name
Test status
Simulation time 142264793 ps
CPU time 1.07 seconds
Started Sep 24 08:14:07 AM UTC 24
Finished Sep 24 08:14:09 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218766972 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.218766972
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/16.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/16.rv_dm_autoincr_sba_tl_access.1239542610
Short name T284
Test name
Test status
Simulation time 3311062040 ps
CPU time 10.53 seconds
Started Sep 24 08:14:06 AM UTC 24
Finished Sep 24 08:14:18 AM UTC 24
Peak memory 226340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239542610 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.1239542610
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/16.rv_dm_bad_sba_tl_access.1903326950
Short name T333
Test name
Test status
Simulation time 16197684719 ps
CPU time 46.31 seconds
Started Sep 24 08:14:04 AM UTC 24
Finished Sep 24 08:14:52 AM UTC 24
Peak memory 226256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903326950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.1903326950
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/16.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.3435255540
Short name T272
Test name
Test status
Simulation time 2227944420 ps
CPU time 5.04 seconds
Started Sep 24 08:14:04 AM UTC 24
Finished Sep 24 08:14:10 AM UTC 24
Peak memory 216028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435255540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_tl_access.3435255540
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/16.rv_dm_sba_tl_access.85990410
Short name T265
Test name
Test status
Simulation time 1361850813 ps
CPU time 1.73 seconds
Started Sep 24 08:14:04 AM UTC 24
Finished Sep 24 08:14:07 AM UTC 24
Peak memory 214864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85990410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv
_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.85990410
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/16.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/17.rv_dm_alert_test.998234551
Short name T274
Test name
Test status
Simulation time 53837237 ps
CPU time 1.02 seconds
Started Sep 24 08:14:11 AM UTC 24
Finished Sep 24 08:14:13 AM UTC 24
Peak memory 215204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998234551 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.998234551
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/17.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/17.rv_dm_autoincr_sba_tl_access.872519223
Short name T224
Test name
Test status
Simulation time 127487762712 ps
CPU time 412.12 seconds
Started Sep 24 08:14:11 AM UTC 24
Finished Sep 24 08:21:08 AM UTC 24
Peak memory 226228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872519223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.872519223
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/17.rv_dm_bad_sba_tl_access.42039141
Short name T283
Test name
Test status
Simulation time 2822870536 ps
CPU time 6.1 seconds
Started Sep 24 08:14:11 AM UTC 24
Finished Sep 24 08:14:18 AM UTC 24
Peak memory 216296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42039141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv
_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.42039141
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/17.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.1096266098
Short name T309
Test name
Test status
Simulation time 7906059496 ps
CPU time 15.66 seconds
Started Sep 24 08:14:09 AM UTC 24
Finished Sep 24 08:14:26 AM UTC 24
Peak memory 226520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096266098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_tl_access.1096266098
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/17.rv_dm_sba_tl_access.1606394949
Short name T279
Test name
Test status
Simulation time 10407566432 ps
CPU time 6.61 seconds
Started Sep 24 08:14:07 AM UTC 24
Finished Sep 24 08:14:15 AM UTC 24
Peak memory 216032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606394949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.1606394949
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/17.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/17.rv_dm_stress_all.3779132504
Short name T205
Test name
Test status
Simulation time 3449938957 ps
CPU time 5.66 seconds
Started Sep 24 08:14:11 AM UTC 24
Finished Sep 24 08:14:17 AM UTC 24
Peak memory 215916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779132504 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.3779132504
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/17.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/18.rv_dm_alert_test.1803896002
Short name T278
Test name
Test status
Simulation time 77249024 ps
CPU time 1.13 seconds
Started Sep 24 08:14:12 AM UTC 24
Finished Sep 24 08:14:14 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803896002 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.1803896002
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/18.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/18.rv_dm_bad_sba_tl_access.1380005967
Short name T282
Test name
Test status
Simulation time 976350145 ps
CPU time 5.72 seconds
Started Sep 24 08:14:11 AM UTC 24
Finished Sep 24 08:14:18 AM UTC 24
Peak memory 216224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380005967 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.1380005967
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/18.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.2465028234
Short name T313
Test name
Test status
Simulation time 10890479472 ps
CPU time 15.22 seconds
Started Sep 24 08:14:11 AM UTC 24
Finished Sep 24 08:14:27 AM UTC 24
Peak memory 226444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465028234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_tl_access.2465028234
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/18.rv_dm_sba_tl_access.209227366
Short name T286
Test name
Test status
Simulation time 5098029057 ps
CPU time 6.02 seconds
Started Sep 24 08:14:11 AM UTC 24
Finished Sep 24 08:14:18 AM UTC 24
Peak memory 216160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209227366 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.209227366
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/18.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/18.rv_dm_stress_all.2462611459
Short name T37
Test name
Test status
Simulation time 1825662617 ps
CPU time 2.89 seconds
Started Sep 24 08:14:12 AM UTC 24
Finished Sep 24 08:14:16 AM UTC 24
Peak memory 216128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462611459 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.2462611459
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/18.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/19.rv_dm_alert_test.2199303974
Short name T281
Test name
Test status
Simulation time 140466814 ps
CPU time 1.19 seconds
Started Sep 24 08:14:14 AM UTC 24
Finished Sep 24 08:14:17 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199303974 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.2199303974
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/19.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.2585059126
Short name T335
Test name
Test status
Simulation time 70234306664 ps
CPU time 125.91 seconds
Started Sep 24 08:14:13 AM UTC 24
Finished Sep 24 08:16:21 AM UTC 24
Peak memory 226400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585059126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.2585059126
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/19.rv_dm_bad_sba_tl_access.658978085
Short name T208
Test name
Test status
Simulation time 1769486264 ps
CPU time 4.7 seconds
Started Sep 24 08:14:13 AM UTC 24
Finished Sep 24 08:14:19 AM UTC 24
Peak memory 226468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658978085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.658978085
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/19.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.1696224182
Short name T280
Test name
Test status
Simulation time 1491011800 ps
CPU time 2.74 seconds
Started Sep 24 08:14:12 AM UTC 24
Finished Sep 24 08:14:16 AM UTC 24
Peak memory 215960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696224182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_tl_access.1696224182
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/19.rv_dm_sba_tl_access.1218174736
Short name T295
Test name
Test status
Simulation time 1998504787 ps
CPU time 8.46 seconds
Started Sep 24 08:14:12 AM UTC 24
Finished Sep 24 08:14:22 AM UTC 24
Peak memory 215956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218174736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.1218174736
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/19.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.4042081472
Short name T190
Test name
Test status
Simulation time 2309729512 ps
CPU time 4.3 seconds
Started Sep 24 08:14:14 AM UTC 24
Finished Sep 24 08:14:20 AM UTC 24
Peak memory 215924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042081472 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.4042081472
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/19.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.737521049
Short name T51
Test name
Test status
Simulation time 96359259 ps
CPU time 1.18 seconds
Started Sep 24 08:13:22 AM UTC 24
Finished Sep 24 08:13:24 AM UTC 24
Peak memory 215264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737521049 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.737521049
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/2.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.1700813944
Short name T124
Test name
Test status
Simulation time 1853512053 ps
CPU time 1.85 seconds
Started Sep 24 08:13:20 AM UTC 24
Finished Sep 24 08:13:23 AM UTC 24
Peak memory 225024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700813944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_tl_access.1700813944
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.1045702129
Short name T56
Test name
Test status
Simulation time 1128903587 ps
CPU time 3.07 seconds
Started Sep 24 08:13:21 AM UTC 24
Finished Sep 24 08:13:25 AM UTC 24
Peak memory 215528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045702129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_halt_resume_whereto.1045702129
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/2.rv_dm_halt_resume_whereto/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.1111972515
Short name T102
Test name
Test status
Simulation time 72923205 ps
CPU time 0.93 seconds
Started Sep 24 08:13:20 AM UTC 24
Finished Sep 24 08:13:22 AM UTC 24
Peak memory 215328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111972515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.1111972515
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/2.rv_dm_hart_unavail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.3958219993
Short name T270
Test name
Test status
Simulation time 16649106938 ps
CPU time 47.92 seconds
Started Sep 24 08:13:20 AM UTC 24
Finished Sep 24 08:14:10 AM UTC 24
Peak memory 216096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958219993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.3958219993
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/2.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.3968733153
Short name T96
Test name
Test status
Simulation time 665849351 ps
CPU time 2.22 seconds
Started Sep 24 08:13:22 AM UTC 24
Finished Sep 24 08:13:25 AM UTC 24
Peak memory 254080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968733153 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.3968733153
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/2.rv_dm_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/2.rv_dm_sparse_lc_gate_fsm.3837200995
Short name T86
Test name
Test status
Simulation time 140601477 ps
CPU time 1.52 seconds
Started Sep 24 08:13:21 AM UTC 24
Finished Sep 24 08:13:23 AM UTC 24
Peak memory 225192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837200995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sparse_lc_gate_fsm.3837200995
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/2.rv_dm_sparse_lc_gate_fsm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all.2708166242
Short name T35
Test name
Test status
Simulation time 1542532346 ps
CPU time 2.46 seconds
Started Sep 24 08:13:21 AM UTC 24
Finished Sep 24 08:13:24 AM UTC 24
Peak memory 226108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708166242 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.2708166242
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/2.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.2375446276
Short name T68
Test name
Test status
Simulation time 6594296161 ps
CPU time 32.39 seconds
Started Sep 24 08:13:22 AM UTC 24
Finished Sep 24 08:13:56 AM UTC 24
Peak memory 230636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=2375446276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stres
s_all_with_rand_reset.2375446276
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/20.rv_dm_alert_test.1408043037
Short name T287
Test name
Test status
Simulation time 122895487 ps
CPU time 1.64 seconds
Started Sep 24 08:14:16 AM UTC 24
Finished Sep 24 08:14:18 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408043037 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.1408043037
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/20.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/21.rv_dm_alert_test.1179041444
Short name T285
Test name
Test status
Simulation time 149638708 ps
CPU time 1.18 seconds
Started Sep 24 08:14:16 AM UTC 24
Finished Sep 24 08:14:18 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179041444 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.1179041444
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/21.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/21.rv_dm_stress_all.2035281142
Short name T321
Test name
Test status
Simulation time 4106706323 ps
CPU time 14.48 seconds
Started Sep 24 08:14:16 AM UTC 24
Finished Sep 24 08:14:31 AM UTC 24
Peak memory 226172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035281142 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.2035281142
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/21.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/22.rv_dm_alert_test.2935874079
Short name T288
Test name
Test status
Simulation time 117383745 ps
CPU time 1.31 seconds
Started Sep 24 08:14:17 AM UTC 24
Finished Sep 24 08:14:19 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935874079 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.2935874079
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/22.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/23.rv_dm_alert_test.935869447
Short name T290
Test name
Test status
Simulation time 44052026 ps
CPU time 1.1 seconds
Started Sep 24 08:14:18 AM UTC 24
Finished Sep 24 08:14:20 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935869447 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.935869447
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/23.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/23.rv_dm_stress_all.3106895680
Short name T296
Test name
Test status
Simulation time 2455110075 ps
CPU time 4.61 seconds
Started Sep 24 08:14:17 AM UTC 24
Finished Sep 24 08:14:22 AM UTC 24
Peak memory 215920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106895680 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.3106895680
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/23.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/24.rv_dm_alert_test.3999044302
Short name T292
Test name
Test status
Simulation time 29820306 ps
CPU time 1.01 seconds
Started Sep 24 08:14:19 AM UTC 24
Finished Sep 24 08:14:21 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999044302 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.3999044302
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/24.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/24.rv_dm_stress_all.132822985
Short name T41
Test name
Test status
Simulation time 3022246222 ps
CPU time 12.08 seconds
Started Sep 24 08:14:18 AM UTC 24
Finished Sep 24 08:14:31 AM UTC 24
Peak memory 216068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132822985 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.132822985
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/24.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/25.rv_dm_alert_test.2337940094
Short name T294
Test name
Test status
Simulation time 39685296 ps
CPU time 1.06 seconds
Started Sep 24 08:14:19 AM UTC 24
Finished Sep 24 08:14:21 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337940094 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.2337940094
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/25.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/26.rv_dm_alert_test.2813811597
Short name T293
Test name
Test status
Simulation time 107442120 ps
CPU time 0.96 seconds
Started Sep 24 08:14:19 AM UTC 24
Finished Sep 24 08:14:21 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813811597 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.2813811597
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/26.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/26.rv_dm_stress_all.504229226
Short name T305
Test name
Test status
Simulation time 7145452736 ps
CPU time 4.44 seconds
Started Sep 24 08:14:19 AM UTC 24
Finished Sep 24 08:14:25 AM UTC 24
Peak memory 215872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504229226 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.504229226
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/26.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/27.rv_dm_alert_test.2160508111
Short name T298
Test name
Test status
Simulation time 137931823 ps
CPU time 1.14 seconds
Started Sep 24 08:14:20 AM UTC 24
Finished Sep 24 08:14:23 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160508111 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.2160508111
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/27.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.2416074792
Short name T195
Test name
Test status
Simulation time 3804350583 ps
CPU time 7.84 seconds
Started Sep 24 08:14:19 AM UTC 24
Finished Sep 24 08:14:28 AM UTC 24
Peak memory 216000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416074792 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.2416074792
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/27.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/28.rv_dm_alert_test.4281203376
Short name T297
Test name
Test status
Simulation time 56062213 ps
CPU time 1 seconds
Started Sep 24 08:14:20 AM UTC 24
Finished Sep 24 08:14:23 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281203376 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.4281203376
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/28.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/28.rv_dm_stress_all.2278666147
Short name T198
Test name
Test status
Simulation time 2848721818 ps
CPU time 4.79 seconds
Started Sep 24 08:14:20 AM UTC 24
Finished Sep 24 08:14:26 AM UTC 24
Peak memory 215656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278666147 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.2278666147
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/28.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/29.rv_dm_alert_test.2634562714
Short name T299
Test name
Test status
Simulation time 174799881 ps
CPU time 1.06 seconds
Started Sep 24 08:14:21 AM UTC 24
Finished Sep 24 08:14:23 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634562714 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.2634562714
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/29.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/29.rv_dm_stress_all.2816096083
Short name T194
Test name
Test status
Simulation time 1685192703 ps
CPU time 6.92 seconds
Started Sep 24 08:14:21 AM UTC 24
Finished Sep 24 08:14:28 AM UTC 24
Peak memory 215984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816096083 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.2816096083
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/29.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.2309302126
Short name T100
Test name
Test status
Simulation time 139146597 ps
CPU time 1.46 seconds
Started Sep 24 08:13:26 AM UTC 24
Finished Sep 24 08:13:28 AM UTC 24
Peak memory 215204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309302126 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.2309302126
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/3.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.1470508238
Short name T130
Test name
Test status
Simulation time 2909064064 ps
CPU time 12.6 seconds
Started Sep 24 08:13:22 AM UTC 24
Finished Sep 24 08:13:36 AM UTC 24
Peak memory 216072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470508238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.1470508238
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/3.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.2449534321
Short name T107
Test name
Test status
Simulation time 159948607 ps
CPU time 1.76 seconds
Started Sep 24 08:13:24 AM UTC 24
Finished Sep 24 08:13:27 AM UTC 24
Peak memory 251308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449534321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_buffered_enable.2449534321
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/3.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.3241889404
Short name T125
Test name
Test status
Simulation time 880160636 ps
CPU time 2.8 seconds
Started Sep 24 08:13:22 AM UTC 24
Finished Sep 24 08:13:26 AM UTC 24
Peak memory 215888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241889404 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_tl_access.3241889404
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.2677210969
Short name T69
Test name
Test status
Simulation time 601371703 ps
CPU time 1.64 seconds
Started Sep 24 08:13:23 AM UTC 24
Finished Sep 24 08:13:26 AM UTC 24
Peak memory 215332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677210969 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_halt_resume_whereto.2677210969
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/3.rv_dm_halt_resume_whereto/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/3.rv_dm_hart_unavail.595640856
Short name T150
Test name
Test status
Simulation time 145505485 ps
CPU time 1.66 seconds
Started Sep 24 08:13:23 AM UTC 24
Finished Sep 24 08:13:26 AM UTC 24
Peak memory 215328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595640856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.595640856
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/3.rv_dm_hart_unavail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.4057369835
Short name T143
Test name
Test status
Simulation time 8153911642 ps
CPU time 9.96 seconds
Started Sep 24 08:13:22 AM UTC 24
Finished Sep 24 08:13:33 AM UTC 24
Peak memory 216364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057369835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.4057369835
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/3.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/3.rv_dm_sec_cm.2984860717
Short name T93
Test name
Test status
Simulation time 645120047 ps
CPU time 4.83 seconds
Started Sep 24 08:13:25 AM UTC 24
Finished Sep 24 08:13:31 AM UTC 24
Peak memory 254424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984860717 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.2984860717
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/3.rv_dm_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.3783278487
Short name T99
Test name
Test status
Simulation time 2850601335 ps
CPU time 14 seconds
Started Sep 24 08:13:24 AM UTC 24
Finished Sep 24 08:13:40 AM UTC 24
Peak memory 216244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783278487 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.3783278487
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/3.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/30.rv_dm_alert_test.2767153048
Short name T301
Test name
Test status
Simulation time 29823108 ps
CPU time 1.17 seconds
Started Sep 24 08:14:22 AM UTC 24
Finished Sep 24 08:14:24 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767153048 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.2767153048
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/30.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.2473845414
Short name T33
Test name
Test status
Simulation time 2796150497 ps
CPU time 8.35 seconds
Started Sep 24 08:14:21 AM UTC 24
Finished Sep 24 08:14:30 AM UTC 24
Peak memory 216000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473845414 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.2473845414
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/30.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/31.rv_dm_alert_test.2736921996
Short name T303
Test name
Test status
Simulation time 57009968 ps
CPU time 1.32 seconds
Started Sep 24 08:14:22 AM UTC 24
Finished Sep 24 08:14:24 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736921996 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.2736921996
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/31.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/31.rv_dm_stress_all.4014535479
Short name T188
Test name
Test status
Simulation time 1985235359 ps
CPU time 4.09 seconds
Started Sep 24 08:14:22 AM UTC 24
Finished Sep 24 08:14:27 AM UTC 24
Peak memory 215944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014535479 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.4014535479
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/31.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/32.rv_dm_alert_test.2964570795
Short name T302
Test name
Test status
Simulation time 92197055 ps
CPU time 1 seconds
Started Sep 24 08:14:22 AM UTC 24
Finished Sep 24 08:14:24 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964570795 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.2964570795
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/32.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/33.rv_dm_alert_test.2154894308
Short name T307
Test name
Test status
Simulation time 149366169 ps
CPU time 1.39 seconds
Started Sep 24 08:14:23 AM UTC 24
Finished Sep 24 08:14:26 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154894308 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.2154894308
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/33.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.1197593251
Short name T203
Test name
Test status
Simulation time 4959214143 ps
CPU time 17.93 seconds
Started Sep 24 08:14:23 AM UTC 24
Finished Sep 24 08:14:42 AM UTC 24
Peak memory 216116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197593251 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.1197593251
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/33.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/34.rv_dm_alert_test.1863913977
Short name T306
Test name
Test status
Simulation time 41513586 ps
CPU time 1.16 seconds
Started Sep 24 08:14:23 AM UTC 24
Finished Sep 24 08:14:25 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863913977 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.1863913977
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/34.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/34.rv_dm_stress_all.683427981
Short name T316
Test name
Test status
Simulation time 2629290485 ps
CPU time 4.5 seconds
Started Sep 24 08:14:23 AM UTC 24
Finished Sep 24 08:14:29 AM UTC 24
Peak memory 215996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683427981 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.683427981
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/34.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/35.rv_dm_alert_test.971982547
Short name T308
Test name
Test status
Simulation time 98502728 ps
CPU time 1.23 seconds
Started Sep 24 08:14:23 AM UTC 24
Finished Sep 24 08:14:26 AM UTC 24
Peak memory 215204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971982547 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.971982547
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/35.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/36.rv_dm_alert_test.2177345319
Short name T311
Test name
Test status
Simulation time 52592355 ps
CPU time 1.14 seconds
Started Sep 24 08:14:24 AM UTC 24
Finished Sep 24 08:14:27 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177345319 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.2177345319
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/36.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/37.rv_dm_alert_test.2581290496
Short name T312
Test name
Test status
Simulation time 97775016 ps
CPU time 1.11 seconds
Started Sep 24 08:14:25 AM UTC 24
Finished Sep 24 08:14:27 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581290496 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.2581290496
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/37.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/37.rv_dm_stress_all.1637231432
Short name T39
Test name
Test status
Simulation time 3743309599 ps
CPU time 5.05 seconds
Started Sep 24 08:14:24 AM UTC 24
Finished Sep 24 08:14:31 AM UTC 24
Peak memory 215916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637231432 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.1637231432
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/37.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/38.rv_dm_alert_test.1260171159
Short name T310
Test name
Test status
Simulation time 90746459 ps
CPU time 0.89 seconds
Started Sep 24 08:14:25 AM UTC 24
Finished Sep 24 08:14:26 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260171159 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.1260171159
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/38.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/38.rv_dm_stress_all.1225037148
Short name T334
Test name
Test status
Simulation time 7453565996 ps
CPU time 33.7 seconds
Started Sep 24 08:14:25 AM UTC 24
Finished Sep 24 08:15:00 AM UTC 24
Peak memory 216116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225037148 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.1225037148
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/38.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/39.rv_dm_alert_test.3039178880
Short name T314
Test name
Test status
Simulation time 121287008 ps
CPU time 1.74 seconds
Started Sep 24 08:14:26 AM UTC 24
Finished Sep 24 08:14:28 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039178880 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.3039178880
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/39.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/4.rv_dm_alert_test.336676410
Short name T109
Test name
Test status
Simulation time 128431203 ps
CPU time 1.11 seconds
Started Sep 24 08:13:29 AM UTC 24
Finished Sep 24 08:13:31 AM UTC 24
Peak memory 215264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336676410 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.336676410
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/4.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/4.rv_dm_autoincr_sba_tl_access.2451691095
Short name T331
Test name
Test status
Simulation time 81825132822 ps
CPU time 76.82 seconds
Started Sep 24 08:13:27 AM UTC 24
Finished Sep 24 08:14:46 AM UTC 24
Peak memory 226588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451691095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.2451691095
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/4.rv_dm_bad_sba_tl_access.114570211
Short name T174
Test name
Test status
Simulation time 2756625818 ps
CPU time 6.08 seconds
Started Sep 24 08:13:27 AM UTC 24
Finished Sep 24 08:13:34 AM UTC 24
Peak memory 226256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114570211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.114570211
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/4.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/4.rv_dm_buffered_enable.2320446497
Short name T76
Test name
Test status
Simulation time 695850159 ps
CPU time 3.73 seconds
Started Sep 24 08:13:27 AM UTC 24
Finished Sep 24 08:13:32 AM UTC 24
Peak memory 258188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320446497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_buffered_enable.2320446497
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/4.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.2268924493
Short name T131
Test name
Test status
Simulation time 3129292845 ps
CPU time 9.94 seconds
Started Sep 24 08:13:26 AM UTC 24
Finished Sep 24 08:13:37 AM UTC 24
Peak memory 216084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268924493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_tl_access.2268924493
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.1735178182
Short name T66
Test name
Test status
Simulation time 574833628 ps
CPU time 3.5 seconds
Started Sep 24 08:13:27 AM UTC 24
Finished Sep 24 08:13:32 AM UTC 24
Peak memory 215528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735178182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_halt_resume_whereto.1735178182
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/4.rv_dm_halt_resume_whereto/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.2891429596
Short name T108
Test name
Test status
Simulation time 238997822 ps
CPU time 1.1 seconds
Started Sep 24 08:13:27 AM UTC 24
Finished Sep 24 08:13:29 AM UTC 24
Peak memory 215328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891429596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.2891429596
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/4.rv_dm_hart_unavail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/4.rv_dm_sba_tl_access.310485539
Short name T244
Test name
Test status
Simulation time 1625682511 ps
CPU time 7.52 seconds
Started Sep 24 08:13:26 AM UTC 24
Finished Sep 24 08:13:34 AM UTC 24
Peak memory 216032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310485539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.310485539
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/4.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/4.rv_dm_sec_cm.3472487891
Short name T104
Test name
Test status
Simulation time 931246275 ps
CPU time 4.57 seconds
Started Sep 24 08:13:29 AM UTC 24
Finished Sep 24 08:13:35 AM UTC 24
Peak memory 256200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472487891 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.3472487891
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/4.rv_dm_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.1305034758
Short name T57
Test name
Test status
Simulation time 8050311487 ps
CPU time 7.54 seconds
Started Sep 24 08:13:28 AM UTC 24
Finished Sep 24 08:13:37 AM UTC 24
Peak memory 216180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305034758 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.1305034758
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/4.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.1030591556
Short name T9
Test name
Test status
Simulation time 7026895053 ps
CPU time 24 seconds
Started Sep 24 08:13:28 AM UTC 24
Finished Sep 24 08:13:53 AM UTC 24
Peak memory 232856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=1030591556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stres
s_all_with_rand_reset.1030591556
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/40.rv_dm_alert_test.2032360141
Short name T315
Test name
Test status
Simulation time 172369304 ps
CPU time 1.78 seconds
Started Sep 24 08:14:26 AM UTC 24
Finished Sep 24 08:14:29 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032360141 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.2032360141
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/40.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/40.rv_dm_stress_all.940003047
Short name T332
Test name
Test status
Simulation time 3742579010 ps
CPU time 20.46 seconds
Started Sep 24 08:14:26 AM UTC 24
Finished Sep 24 08:14:47 AM UTC 24
Peak memory 226436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940003047 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.940003047
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/40.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/41.rv_dm_alert_test.2339068336
Short name T317
Test name
Test status
Simulation time 55885440 ps
CPU time 1 seconds
Started Sep 24 08:14:27 AM UTC 24
Finished Sep 24 08:14:29 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339068336 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.2339068336
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/41.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/41.rv_dm_stress_all.2386895209
Short name T73
Test name
Test status
Simulation time 4689180409 ps
CPU time 5.64 seconds
Started Sep 24 08:14:27 AM UTC 24
Finished Sep 24 08:14:34 AM UTC 24
Peak memory 216192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386895209 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.2386895209
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/41.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/42.rv_dm_alert_test.2264874160
Short name T318
Test name
Test status
Simulation time 126556831 ps
CPU time 1.01 seconds
Started Sep 24 08:14:27 AM UTC 24
Finished Sep 24 08:14:29 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264874160 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.2264874160
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/42.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/42.rv_dm_stress_all.2880016056
Short name T325
Test name
Test status
Simulation time 2295719657 ps
CPU time 4.47 seconds
Started Sep 24 08:14:27 AM UTC 24
Finished Sep 24 08:14:33 AM UTC 24
Peak memory 226188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880016056 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.2880016056
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/42.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/43.rv_dm_alert_test.3231975724
Short name T319
Test name
Test status
Simulation time 134417326 ps
CPU time 1.29 seconds
Started Sep 24 08:14:27 AM UTC 24
Finished Sep 24 08:14:30 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231975724 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.3231975724
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/43.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/43.rv_dm_stress_all.3004033845
Short name T11
Test name
Test status
Simulation time 2637435610 ps
CPU time 3.62 seconds
Started Sep 24 08:14:27 AM UTC 24
Finished Sep 24 08:14:32 AM UTC 24
Peak memory 215920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004033845 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.3004033845
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/43.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/44.rv_dm_alert_test.1889564158
Short name T320
Test name
Test status
Simulation time 69758583 ps
CPU time 1.11 seconds
Started Sep 24 08:14:28 AM UTC 24
Finished Sep 24 08:14:30 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889564158 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.1889564158
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/44.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.3949368117
Short name T323
Test name
Test status
Simulation time 3029079200 ps
CPU time 3.23 seconds
Started Sep 24 08:14:27 AM UTC 24
Finished Sep 24 08:14:32 AM UTC 24
Peak memory 216116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949368117 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.3949368117
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/44.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/45.rv_dm_alert_test.1441850661
Short name T304
Test name
Test status
Simulation time 75847873 ps
CPU time 1.11 seconds
Started Sep 24 08:14:29 AM UTC 24
Finished Sep 24 08:14:32 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441850661 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.1441850661
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/45.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/45.rv_dm_stress_all.555121193
Short name T328
Test name
Test status
Simulation time 2903778550 ps
CPU time 3.7 seconds
Started Sep 24 08:14:28 AM UTC 24
Finished Sep 24 08:14:33 AM UTC 24
Peak memory 215928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555121193 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.555121193
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/45.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/46.rv_dm_alert_test.136455623
Short name T324
Test name
Test status
Simulation time 69669913 ps
CPU time 1.07 seconds
Started Sep 24 08:14:30 AM UTC 24
Finished Sep 24 08:14:32 AM UTC 24
Peak memory 215204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136455623 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.136455623
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/46.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.1441333124
Short name T329
Test name
Test status
Simulation time 7785068370 ps
CPU time 4.71 seconds
Started Sep 24 08:14:30 AM UTC 24
Finished Sep 24 08:14:35 AM UTC 24
Peak memory 215924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441333124 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.1441333124
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/46.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/47.rv_dm_alert_test.235758831
Short name T322
Test name
Test status
Simulation time 34577106 ps
CPU time 0.84 seconds
Started Sep 24 08:14:30 AM UTC 24
Finished Sep 24 08:14:32 AM UTC 24
Peak memory 215204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235758831 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.235758831
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/47.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/47.rv_dm_stress_all.584177720
Short name T202
Test name
Test status
Simulation time 4118768060 ps
CPU time 19.47 seconds
Started Sep 24 08:14:30 AM UTC 24
Finished Sep 24 08:14:50 AM UTC 24
Peak memory 226248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584177720 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.584177720
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/47.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/48.rv_dm_alert_test.2874312573
Short name T327
Test name
Test status
Simulation time 138554254 ps
CPU time 1.21 seconds
Started Sep 24 08:14:31 AM UTC 24
Finished Sep 24 08:14:33 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874312573 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.2874312573
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/48.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/48.rv_dm_stress_all.3532660687
Short name T187
Test name
Test status
Simulation time 1536043514 ps
CPU time 2.1 seconds
Started Sep 24 08:14:30 AM UTC 24
Finished Sep 24 08:14:33 AM UTC 24
Peak memory 215988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532660687 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.3532660687
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/48.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/49.rv_dm_alert_test.3364751916
Short name T326
Test name
Test status
Simulation time 50685942 ps
CPU time 1.18 seconds
Started Sep 24 08:14:31 AM UTC 24
Finished Sep 24 08:14:33 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364751916 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.3364751916
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/49.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/5.rv_dm_alert_test.2557978598
Short name T129
Test name
Test status
Simulation time 135545977 ps
CPU time 0.8 seconds
Started Sep 24 08:13:34 AM UTC 24
Finished Sep 24 08:13:36 AM UTC 24
Peak memory 215204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557978598 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.2557978598
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/5.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.1240459902
Short name T144
Test name
Test status
Simulation time 764945381 ps
CPU time 1.86 seconds
Started Sep 24 08:13:30 AM UTC 24
Finished Sep 24 08:13:34 AM UTC 24
Peak memory 214916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240459902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.1240459902
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/5.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/5.rv_dm_buffered_enable.3355734651
Short name T128
Test name
Test status
Simulation time 675161497 ps
CPU time 1.91 seconds
Started Sep 24 08:13:33 AM UTC 24
Finished Sep 24 08:13:36 AM UTC 24
Peak memory 250860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355734651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_buffered_enable.3355734651
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/5.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.2462940288
Short name T241
Test name
Test status
Simulation time 2941408570 ps
CPU time 13.05 seconds
Started Sep 24 08:13:29 AM UTC 24
Finished Sep 24 08:13:44 AM UTC 24
Peak memory 216088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462940288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl_access.2462940288
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/5.rv_dm_halt_resume_whereto.3518886968
Short name T70
Test name
Test status
Simulation time 537562948 ps
CPU time 2.14 seconds
Started Sep 24 08:13:33 AM UTC 24
Finished Sep 24 08:13:36 AM UTC 24
Peak memory 215796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518886968 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_halt_resume_whereto.3518886968
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/5.rv_dm_halt_resume_whereto/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/5.rv_dm_sba_tl_access.3409117179
Short name T243
Test name
Test status
Simulation time 2241466943 ps
CPU time 3.82 seconds
Started Sep 24 08:13:29 AM UTC 24
Finished Sep 24 08:13:34 AM UTC 24
Peak memory 216296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409117179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.3409117179
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/5.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.475415491
Short name T75
Test name
Test status
Simulation time 15467441440 ps
CPU time 95.01 seconds
Started Sep 24 08:13:33 AM UTC 24
Finished Sep 24 08:15:10 AM UTC 24
Peak memory 243112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=475415491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress
_all_with_rand_reset.475415491
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/6.rv_dm_alert_test.3559353492
Short name T132
Test name
Test status
Simulation time 49649833 ps
CPU time 1.03 seconds
Started Sep 24 08:13:36 AM UTC 24
Finished Sep 24 08:13:38 AM UTC 24
Peak memory 215204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559353492 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.3559353492
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/6.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/6.rv_dm_autoincr_sba_tl_access.886830002
Short name T253
Test name
Test status
Simulation time 7504564010 ps
CPU time 17.33 seconds
Started Sep 24 08:13:35 AM UTC 24
Finished Sep 24 08:13:54 AM UTC 24
Peak memory 226384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886830002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.886830002
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/6.rv_dm_bad_sba_tl_access.2129440900
Short name T248
Test name
Test status
Simulation time 2734473393 ps
CPU time 12.33 seconds
Started Sep 24 08:13:35 AM UTC 24
Finished Sep 24 08:13:48 AM UTC 24
Peak memory 226344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129440900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.2129440900
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/6.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/6.rv_dm_buffered_enable.3466595221
Short name T210
Test name
Test status
Simulation time 137370292 ps
CPU time 1.87 seconds
Started Sep 24 08:13:36 AM UTC 24
Finished Sep 24 08:13:39 AM UTC 24
Peak memory 250680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466595221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_buffered_enable.3466595221
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/6.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.286608791
Short name T330
Test name
Test status
Simulation time 13967493742 ps
CPU time 59.28 seconds
Started Sep 24 08:13:35 AM UTC 24
Finished Sep 24 08:14:36 AM UTC 24
Peak memory 226324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286608791 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_tl_access.286608791
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/6.rv_dm_halt_resume_whereto.1779721655
Short name T71
Test name
Test status
Simulation time 354588889 ps
CPU time 2.32 seconds
Started Sep 24 08:13:36 AM UTC 24
Finished Sep 24 08:13:39 AM UTC 24
Peak memory 215600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779721655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_halt_resume_whereto.1779721655
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/6.rv_dm_halt_resume_whereto/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/6.rv_dm_sba_tl_access.2436943354
Short name T223
Test name
Test status
Simulation time 1909922712 ps
CPU time 2.75 seconds
Started Sep 24 08:13:35 AM UTC 24
Finished Sep 24 08:13:39 AM UTC 24
Peak memory 215912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436943354 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.2436943354
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/6.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all.1345727426
Short name T192
Test name
Test status
Simulation time 9714415876 ps
CPU time 33.99 seconds
Started Sep 24 08:13:36 AM UTC 24
Finished Sep 24 08:14:12 AM UTC 24
Peak memory 215848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345727426 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.1345727426
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/6.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all_with_rand_reset.348962905
Short name T18
Test name
Test status
Simulation time 4038909258 ps
CPU time 44.36 seconds
Started Sep 24 08:13:36 AM UTC 24
Finished Sep 24 08:14:22 AM UTC 24
Peak memory 233140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=348962905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress
_all_with_rand_reset.348962905
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/7.rv_dm_alert_test.1954395201
Short name T173
Test name
Test status
Simulation time 63633234 ps
CPU time 1.27 seconds
Started Sep 24 08:13:40 AM UTC 24
Finished Sep 24 08:13:42 AM UTC 24
Peak memory 215076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954395201 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.1954395201
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/7.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.159317290
Short name T238
Test name
Test status
Simulation time 1752696837 ps
CPU time 10.22 seconds
Started Sep 24 08:13:38 AM UTC 24
Finished Sep 24 08:13:49 AM UTC 24
Peak memory 226268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159317290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.159317290
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/7.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/7.rv_dm_buffered_enable.1817820801
Short name T145
Test name
Test status
Simulation time 103583831 ps
CPU time 1.93 seconds
Started Sep 24 08:13:39 AM UTC 24
Finished Sep 24 08:13:42 AM UTC 24
Peak memory 257140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817820801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_buffered_enable.1817820801
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/7.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.116353679
Short name T247
Test name
Test status
Simulation time 1672461819 ps
CPU time 4.82 seconds
Started Sep 24 08:13:36 AM UTC 24
Finished Sep 24 08:13:42 AM UTC 24
Peak memory 216148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116353679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_tl_access.116353679
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.3878960048
Short name T58
Test name
Test status
Simulation time 230984962 ps
CPU time 1.75 seconds
Started Sep 24 08:13:38 AM UTC 24
Finished Sep 24 08:13:40 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878960048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_halt_resume_whereto.3878960048
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/7.rv_dm_halt_resume_whereto/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/7.rv_dm_sba_tl_access.1458717082
Short name T221
Test name
Test status
Simulation time 3991896919 ps
CPU time 6.95 seconds
Started Sep 24 08:13:36 AM UTC 24
Finished Sep 24 08:13:44 AM UTC 24
Peak memory 216372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458717082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.1458717082
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/7.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all.3161342237
Short name T204
Test name
Test status
Simulation time 6644824258 ps
CPU time 11.57 seconds
Started Sep 24 08:13:40 AM UTC 24
Finished Sep 24 08:13:53 AM UTC 24
Peak memory 215848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161342237 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.3161342237
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/7.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.822862323
Short name T74
Test name
Test status
Simulation time 17317565416 ps
CPU time 83.21 seconds
Started Sep 24 08:13:40 AM UTC 24
Finished Sep 24 08:15:05 AM UTC 24
Peak memory 243200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=822862323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress
_all_with_rand_reset.822862323
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/8.rv_dm_alert_test.2190081607
Short name T239
Test name
Test status
Simulation time 41584093 ps
CPU time 1.14 seconds
Started Sep 24 08:13:43 AM UTC 24
Finished Sep 24 08:13:46 AM UTC 24
Peak memory 215204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190081607 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.2190081607
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/8.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.216193267
Short name T25
Test name
Test status
Simulation time 2808914251 ps
CPU time 9.48 seconds
Started Sep 24 08:13:41 AM UTC 24
Finished Sep 24 08:13:52 AM UTC 24
Peak memory 226256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216193267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.216193267
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/8.rv_dm_bad_sba_tl_access.4163589686
Short name T276
Test name
Test status
Simulation time 8073610317 ps
CPU time 32.1 seconds
Started Sep 24 08:13:40 AM UTC 24
Finished Sep 24 08:14:13 AM UTC 24
Peak memory 226536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163589686 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.4163589686
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/8.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/8.rv_dm_buffered_enable.3825334188
Short name T146
Test name
Test status
Simulation time 191177601 ps
CPU time 1.73 seconds
Started Sep 24 08:13:41 AM UTC 24
Finished Sep 24 08:13:44 AM UTC 24
Peak memory 250740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825334188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_buffered_enable.3825334188
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/8.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.922702532
Short name T219
Test name
Test status
Simulation time 1919493187 ps
CPU time 12.99 seconds
Started Sep 24 08:13:40 AM UTC 24
Finished Sep 24 08:13:54 AM UTC 24
Peak memory 225760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922702532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl_access.922702532
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/8.rv_dm_sba_tl_access.1534143476
Short name T215
Test name
Test status
Simulation time 3776618481 ps
CPU time 7.82 seconds
Started Sep 24 08:13:40 AM UTC 24
Finished Sep 24 08:13:49 AM UTC 24
Peak memory 216028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534143476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.1534143476
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/8.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.2549712033
Short name T126
Test name
Test status
Simulation time 30999879189 ps
CPU time 70.96 seconds
Started Sep 24 08:13:42 AM UTC 24
Finished Sep 24 08:14:55 AM UTC 24
Peak memory 228404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=2549712033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stres
s_all_with_rand_reset.2549712033
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.3724731733
Short name T240
Test name
Test status
Simulation time 115255893 ps
CPU time 1.08 seconds
Started Sep 24 08:13:47 AM UTC 24
Finished Sep 24 08:13:49 AM UTC 24
Peak memory 215204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724731733 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.3724731733
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/9.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/9.rv_dm_autoincr_sba_tl_access.3560126948
Short name T211
Test name
Test status
Simulation time 15618563211 ps
CPU time 15.5 seconds
Started Sep 24 08:13:46 AM UTC 24
Finished Sep 24 08:14:02 AM UTC 24
Peak memory 226392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560126948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.3560126948
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/9.rv_dm_buffered_enable.953517151
Short name T250
Test name
Test status
Simulation time 675829870 ps
CPU time 4.01 seconds
Started Sep 24 08:13:46 AM UTC 24
Finished Sep 24 08:13:51 AM UTC 24
Peak memory 252144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953517151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_buffered_enable.953517151
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/9.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.1362204011
Short name T249
Test name
Test status
Simulation time 9964308799 ps
CPU time 3.68 seconds
Started Sep 24 08:13:45 AM UTC 24
Finished Sep 24 08:13:49 AM UTC 24
Peak memory 226396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362204011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_tl_access.1362204011
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.1975999656
Short name T252
Test name
Test status
Simulation time 3080680880 ps
CPU time 7.62 seconds
Started Sep 24 08:13:43 AM UTC 24
Finished Sep 24 08:13:52 AM UTC 24
Peak memory 216028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975999656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.1975999656
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/9.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.1921828379
Short name T32
Test name
Test status
Simulation time 5626147849 ps
CPU time 4.13 seconds
Started Sep 24 08:13:47 AM UTC 24
Finished Sep 24 08:13:52 AM UTC 24
Peak memory 226436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921828379 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.1921828379
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/9.rv_dm_stress_all/latest