Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.01 96.34 90.10 92.10 93.33 90.27 98.63 55.30


Total tests in report: 483
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
52.43 52.43 85.66 85.66 53.18 53.18 23.03 23.03 42.67 42.67 66.37 66.37 92.86 92.86 3.26 3.26 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.4226564349
62.46 10.03 87.93 2.27 65.49 12.31 26.97 3.95 49.33 6.67 73.81 7.43 93.91 1.05 39.81 36.55 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.740391042
70.28 7.81 90.25 2.32 71.85 6.36 58.45 31.47 57.33 8.00 78.05 4.25 95.38 1.47 40.63 0.81 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_tl_access.224917910
74.87 4.60 92.21 1.96 74.96 3.11 73.19 14.75 65.33 8.00 81.06 3.01 95.90 0.53 41.44 0.81 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.3381698824
76.95 2.08 92.36 0.15 78.36 3.39 77.86 4.66 70.67 5.33 81.95 0.88 95.90 0.00 41.56 0.12 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.2562066448
78.49 1.54 93.40 1.03 80.48 2.12 80.42 2.56 73.33 2.67 84.25 2.30 95.90 0.00 41.68 0.12 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.3003995043
79.92 1.43 94.32 0.93 81.47 0.99 80.67 0.25 77.33 4.00 85.84 1.59 95.90 0.00 43.89 2.21 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.188758560
80.78 0.86 94.43 0.10 83.03 1.56 81.26 0.59 77.33 0.00 86.37 0.53 95.90 0.00 47.15 3.26 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3006080028
81.63 0.85 94.48 0.05 85.57 2.55 82.61 1.34 78.67 1.33 86.73 0.35 96.01 0.11 47.38 0.23 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.603694392
82.28 0.64 95.10 0.62 86.28 0.71 83.74 1.13 80.00 1.33 87.43 0.71 96.01 0.00 47.38 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.1839809170
82.87 0.60 95.10 0.00 86.70 0.42 86.81 3.07 80.00 0.00 87.43 0.00 96.11 0.11 47.96 0.58 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.1554975572
83.39 0.51 95.36 0.26 86.85 0.14 86.97 0.17 82.67 2.67 87.79 0.35 96.11 0.00 47.96 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.165436312
83.85 0.46 95.36 0.00 86.99 0.14 87.10 0.13 85.33 2.67 87.96 0.18 96.11 0.00 48.08 0.12 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.292279018
84.27 0.42 95.36 0.00 86.99 0.00 90.04 2.94 85.33 0.00 87.96 0.00 96.11 0.00 48.08 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.4206824465
84.65 0.38 95.36 0.00 86.99 0.00 90.04 0.00 88.00 2.67 87.96 0.00 96.11 0.00 48.08 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.2829321580
84.88 0.23 95.36 0.00 87.84 0.85 90.55 0.50 88.00 0.00 87.96 0.00 96.11 0.00 48.31 0.23 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.3532664423
85.10 0.23 95.36 0.00 87.84 0.00 90.80 0.25 89.33 1.33 87.96 0.00 96.11 0.00 48.31 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3722677731
85.31 0.21 95.36 0.00 87.84 0.00 90.80 0.00 90.67 1.33 87.96 0.00 96.11 0.00 48.43 0.12 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.3338993860
85.50 0.19 95.36 0.00 87.84 0.00 90.80 0.00 92.00 1.33 87.96 0.00 96.11 0.00 48.43 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.1660621989
85.69 0.19 95.36 0.00 87.84 0.00 90.80 0.00 93.33 1.33 87.96 0.00 96.11 0.00 48.43 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2600181281
85.87 0.18 95.51 0.15 88.12 0.28 90.88 0.08 93.33 0.00 88.14 0.18 96.11 0.00 49.01 0.58 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.2241602179
86.05 0.18 95.51 0.00 88.12 0.00 90.88 0.00 93.33 0.00 88.14 0.00 97.37 1.26 49.01 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2860767602
86.23 0.17 95.77 0.26 88.26 0.14 91.18 0.29 93.33 0.00 88.67 0.53 97.37 0.00 49.01 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.2005132440
86.38 0.15 96.08 0.31 88.54 0.28 91.18 0.00 93.33 0.00 89.03 0.35 97.37 0.00 49.13 0.12 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/35.rv_dm_stress_all.2957567436
86.51 0.13 96.13 0.05 88.54 0.00 91.26 0.08 93.33 0.00 89.20 0.18 97.37 0.00 49.71 0.58 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.2765695366
86.62 0.12 96.13 0.00 88.54 0.00 91.26 0.00 93.33 0.00 89.20 0.00 97.37 0.00 50.52 0.81 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/13.rv_dm_bad_sba_tl_access.3328615531
86.72 0.10 96.13 0.00 88.54 0.00 91.26 0.00 93.33 0.00 89.20 0.00 97.37 0.00 51.22 0.70 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.407933588
86.82 0.10 96.18 0.05 88.68 0.14 91.34 0.08 93.33 0.00 89.38 0.18 97.37 0.00 51.46 0.23 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/32.rv_dm_stress_all.570112850
86.91 0.09 96.18 0.00 89.25 0.57 91.43 0.08 93.33 0.00 89.38 0.00 97.37 0.00 51.46 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.1833055933
87.00 0.09 96.23 0.05 89.39 0.14 91.51 0.08 93.33 0.00 89.73 0.35 97.37 0.00 51.46 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.867375331
87.08 0.08 96.23 0.00 89.39 0.00 91.51 0.00 93.33 0.00 89.73 0.00 97.90 0.53 51.46 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2697618616
87.15 0.07 96.23 0.00 89.67 0.28 91.51 0.00 93.33 0.00 89.73 0.00 97.90 0.00 51.69 0.23 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/49.rv_dm_stress_all.3379463969
87.22 0.07 96.23 0.00 89.82 0.14 91.51 0.00 93.33 0.00 89.73 0.00 98.11 0.21 51.80 0.12 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.1322518949
87.29 0.07 96.23 0.00 89.82 0.00 91.51 0.00 93.33 0.00 89.73 0.00 98.11 0.00 52.27 0.47 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1952629413
87.35 0.07 96.23 0.00 89.82 0.00 91.51 0.00 93.33 0.00 89.73 0.00 98.11 0.00 52.74 0.47 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.529208383
87.42 0.06 96.23 0.00 89.82 0.00 91.60 0.08 93.33 0.00 89.73 0.00 98.11 0.00 53.08 0.35 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.2912415098
87.46 0.05 96.23 0.00 89.82 0.00 91.72 0.13 93.33 0.00 89.73 0.00 98.32 0.21 53.08 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_errors.3119980312
87.51 0.05 96.23 0.00 89.96 0.14 91.72 0.00 93.33 0.00 89.91 0.18 98.32 0.00 53.08 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.578609717
87.55 0.04 96.28 0.05 89.96 0.00 91.81 0.08 93.33 0.00 90.09 0.18 98.32 0.00 53.08 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.4049737461
87.59 0.03 96.28 0.00 89.96 0.00 91.93 0.13 93.33 0.00 90.09 0.00 98.32 0.00 53.20 0.12 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/36.rv_dm_stress_all.3779095740
87.62 0.03 96.28 0.00 89.96 0.00 91.93 0.00 93.33 0.00 90.09 0.00 98.32 0.00 53.43 0.23 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.494770121
87.65 0.03 96.28 0.00 89.96 0.00 91.93 0.00 93.33 0.00 90.09 0.00 98.32 0.00 53.67 0.23 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.1046202048
87.69 0.03 96.28 0.00 89.96 0.00 91.93 0.00 93.33 0.00 90.09 0.00 98.32 0.00 53.90 0.23 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/39.rv_dm_stress_all.2503952842
87.72 0.03 96.28 0.00 89.96 0.00 91.93 0.00 93.33 0.00 90.09 0.00 98.32 0.00 54.13 0.23 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.2289430092
87.75 0.03 96.34 0.05 89.96 0.00 91.93 0.00 93.33 0.00 90.27 0.18 98.32 0.00 54.13 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1342183260
87.78 0.03 96.34 0.00 89.96 0.00 92.02 0.08 93.33 0.00 90.27 0.00 98.32 0.00 54.25 0.12 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3118735398
87.81 0.03 96.34 0.00 89.96 0.00 92.10 0.08 93.33 0.00 90.27 0.00 98.32 0.00 54.37 0.12 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_autoincr_sba_tl_access.2675254081
87.83 0.02 96.34 0.00 90.10 0.14 92.10 0.00 93.33 0.00 90.27 0.00 98.32 0.00 54.37 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.1769871456
87.85 0.02 96.34 0.00 90.10 0.00 92.10 0.00 93.33 0.00 90.27 0.00 98.32 0.00 54.48 0.12 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1270430975
87.86 0.02 96.34 0.00 90.10 0.00 92.10 0.00 93.33 0.00 90.27 0.00 98.32 0.00 54.60 0.12 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.380127028
87.88 0.02 96.34 0.00 90.10 0.00 92.10 0.00 93.33 0.00 90.27 0.00 98.32 0.00 54.71 0.12 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_halt_resume_whereto.1274431376
87.90 0.02 96.34 0.00 90.10 0.00 92.10 0.00 93.33 0.00 90.27 0.00 98.32 0.00 54.83 0.12 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/10.rv_dm_bad_sba_tl_access.3467437167
87.91 0.02 96.34 0.00 90.10 0.00 92.10 0.00 93.33 0.00 90.27 0.00 98.32 0.00 54.95 0.12 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/16.rv_dm_stress_all.2586078480
87.93 0.02 96.34 0.00 90.10 0.00 92.10 0.00 93.33 0.00 90.27 0.00 98.32 0.00 55.06 0.12 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/18.rv_dm_autoincr_sba_tl_access.1740311895
87.95 0.02 96.34 0.00 90.10 0.00 92.10 0.00 93.33 0.00 90.27 0.00 98.32 0.00 55.18 0.12 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.2117522448
87.96 0.02 96.34 0.00 90.10 0.00 92.10 0.00 93.33 0.00 90.27 0.00 98.32 0.00 55.30 0.12 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.2213619305
87.98 0.02 96.34 0.00 90.10 0.00 92.10 0.00 93.33 0.00 90.27 0.00 98.42 0.11 55.30 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1176814563
87.99 0.02 96.34 0.00 90.10 0.00 92.10 0.00 93.33 0.00 90.27 0.00 98.53 0.11 55.30 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.489483426
88.01 0.02 96.34 0.00 90.10 0.00 92.10 0.00 93.33 0.00 90.27 0.00 98.63 0.11 55.30 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.1788079686

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.4103285227
/workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.747718555
/workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3425698192
/workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.2498516073
/workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.10992550
/workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2074197996
/workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.228172484
/workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3840402605
/workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2653776388
/workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.526974645
/workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3139060990
/workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2026568347
/workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.3639418251
/workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.990710749
/workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.1063627018
/workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3594077767
/workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2772107928
/workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.4158521672
/workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2509753782
/workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.2562475211
/workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3245384605
/workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2649318884
/workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.440291546
/workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1694490332
/workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.888695741
/workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1365823638
/workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.576871551
/workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.4194988201
/workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1542051472
/workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.2060491372
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Total test records in report: 483
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_smoke.1528505016 Sep 24 08:13:01 AM UTC 24 Sep 24 08:13:03 AM UTC 24 607391891 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.2149454232 Sep 24 08:13:02 AM UTC 24 Sep 24 08:13:04 AM UTC 24 154397569 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_halted.75130983 Sep 24 08:13:02 AM UTC 24 Sep 24 08:13:05 AM UTC 24 92066673 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_busy.1407945135 Sep 24 08:13:02 AM UTC 24 Sep 24 08:13:05 AM UTC 24 460543830 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_resuming.2190576680 Sep 24 08:13:04 AM UTC 24 Sep 24 08:13:07 AM UTC 24 99692192 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_dataaddr_rw_access.688520423 Sep 24 08:13:05 AM UTC 24 Sep 24 08:13:07 AM UTC 24 125128961 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.436031027 Sep 24 08:13:02 AM UTC 24 Sep 24 08:13:08 AM UTC 24 712482381 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.1769871456 Sep 24 08:13:04 AM UTC 24 Sep 24 08:13:08 AM UTC 24 1143774420 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_hart_unavail.3593818232 Sep 24 08:13:04 AM UTC 24 Sep 24 08:13:08 AM UTC 24 365673003 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.4226564349 Sep 24 08:13:05 AM UTC 24 Sep 24 08:13:09 AM UTC 24 435805015 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_idle_hint.3052635842 Sep 24 08:13:07 AM UTC 24 Sep 24 08:13:09 AM UTC 24 347204708 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.3532664423 Sep 24 08:13:06 AM UTC 24 Sep 24 08:13:09 AM UTC 24 167494243 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.3016907028 Sep 24 08:13:08 AM UTC 24 Sep 24 08:13:10 AM UTC 24 549954273 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.2970803278 Sep 24 08:13:08 AM UTC 24 Sep 24 08:13:11 AM UTC 24 645158002 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.867375331 Sep 24 08:13:09 AM UTC 24 Sep 24 08:13:11 AM UTC 24 188776380 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.4049737461 Sep 24 08:13:09 AM UTC 24 Sep 24 08:13:11 AM UTC 24 244932113 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_debug_disabled.3070445025 Sep 24 08:13:09 AM UTC 24 Sep 24 08:13:11 AM UTC 24 67930805 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.1845222485 Sep 24 08:13:09 AM UTC 24 Sep 24 08:13:11 AM UTC 24 353728457 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.292279018 Sep 24 08:13:01 AM UTC 24 Sep 24 08:13:12 AM UTC 24 9244883896 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.2562066448 Sep 24 08:13:09 AM UTC 24 Sep 24 08:13:12 AM UTC 24 280302658 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.603694392 Sep 24 08:13:10 AM UTC 24 Sep 24 08:13:12 AM UTC 24 21564794 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.489483426 Sep 24 08:13:10 AM UTC 24 Sep 24 08:13:12 AM UTC 24 108922634 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2658152111 Sep 24 08:13:01 AM UTC 24 Sep 24 08:13:12 AM UTC 24 3212017718 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_hartsel_warl.3129835913 Sep 24 08:13:10 AM UTC 24 Sep 24 08:13:12 AM UTC 24 95906421 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_hard_reset.4011569406 Sep 24 08:13:09 AM UTC 24 Sep 24 08:13:12 AM UTC 24 272339536 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.1839809170 Sep 24 08:13:10 AM UTC 24 Sep 24 08:13:13 AM UTC 24 491503746 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_debug_disabled.2361265357 Sep 24 08:13:15 AM UTC 24 Sep 24 08:13:26 AM UTC 24 5251156472 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.578609717 Sep 24 08:13:05 AM UTC 24 Sep 24 08:13:13 AM UTC 24 4026485016 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_tl_access.2055693851 Sep 24 08:13:01 AM UTC 24 Sep 24 08:13:14 AM UTC 24 11087894571 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.1833055933 Sep 24 08:13:12 AM UTC 24 Sep 24 08:13:15 AM UTC 24 140468794 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.1554975572 Sep 24 08:13:11 AM UTC 24 Sep 24 08:13:15 AM UTC 24 511456104 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.3198326707 Sep 24 08:13:01 AM UTC 24 Sep 24 08:13:16 AM UTC 24 12440550908 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.1079441958 Sep 24 08:13:13 AM UTC 24 Sep 24 08:13:16 AM UTC 24 3014136568 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.3381698824 Sep 24 08:13:11 AM UTC 24 Sep 24 08:13:16 AM UTC 24 563199495 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_tl_access.224917910 Sep 24 08:13:13 AM UTC 24 Sep 24 08:13:16 AM UTC 24 1513829225 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_hart_unavail.3390914088 Sep 24 08:13:14 AM UTC 24 Sep 24 08:13:16 AM UTC 24 298128682 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_halted.878471026 Sep 24 08:13:14 AM UTC 24 Sep 24 08:13:17 AM UTC 24 332522683 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_busy.3662203271 Sep 24 08:13:13 AM UTC 24 Sep 24 08:13:17 AM UTC 24 1001985436 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_resuming.54677158 Sep 24 08:13:14 AM UTC 24 Sep 24 08:13:17 AM UTC 24 493000070 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.2005132440 Sep 24 08:13:14 AM UTC 24 Sep 24 08:13:17 AM UTC 24 391986170 ps
T84 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_smoke.3114442514 Sep 24 08:13:13 AM UTC 24 Sep 24 08:13:17 AM UTC 24 1387746094 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_dataaddr_rw_access.1267797394 Sep 24 08:13:15 AM UTC 24 Sep 24 08:13:18 AM UTC 24 200231460 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_halt_resume_whereto.1274431376 Sep 24 08:13:15 AM UTC 24 Sep 24 08:13:18 AM UTC 24 509925632 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_ndmreset_req.2764961949 Sep 24 08:13:16 AM UTC 24 Sep 24 08:13:19 AM UTC 24 595892201 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_idle_hint.3887349052 Sep 24 08:13:16 AM UTC 24 Sep 24 08:13:19 AM UTC 24 512714191 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_not_supported.1426342706 Sep 24 08:13:14 AM UTC 24 Sep 24 08:13:19 AM UTC 24 903632353 ps
T246 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.2992942915 Sep 24 08:13:17 AM UTC 24 Sep 24 08:13:19 AM UTC 24 355430264 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3138228435 Sep 24 08:13:17 AM UTC 24 Sep 24 08:13:20 AM UTC 24 183949611 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.3591055127 Sep 24 08:13:17 AM UTC 24 Sep 24 08:13:20 AM UTC 24 293092338 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_debug_disabled.2384594820 Sep 24 08:13:18 AM UTC 24 Sep 24 08:13:20 AM UTC 24 118406042 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.3634566067 Sep 24 08:13:18 AM UTC 24 Sep 24 08:13:20 AM UTC 24 81505449 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_abstractcmd_status.440029044 Sep 24 08:13:17 AM UTC 24 Sep 24 08:13:20 AM UTC 24 467279574 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_rom_read_access.3069414997 Sep 24 08:13:18 AM UTC 24 Sep 24 08:13:20 AM UTC 24 65856477 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_progbuf_read_write_execute.3452075705 Sep 24 08:13:18 AM UTC 24 Sep 24 08:13:20 AM UTC 24 368862291 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_buffered_enable.290106554 Sep 24 08:13:18 AM UTC 24 Sep 24 08:13:21 AM UTC 24 146852178 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.3338993860 Sep 24 08:13:18 AM UTC 24 Sep 24 08:13:21 AM UTC 24 463675890 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_alert_test.3891542058 Sep 24 08:13:19 AM UTC 24 Sep 24 08:13:21 AM UTC 24 73979051 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_sec_cm.2187291496 Sep 24 08:13:19 AM UTC 24 Sep 24 08:13:22 AM UTC 24 388278873 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.1111972515 Sep 24 08:13:20 AM UTC 24 Sep 24 08:13:22 AM UTC 24 72923205 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.3240350841 Sep 24 08:13:14 AM UTC 24 Sep 24 08:13:23 AM UTC 24 1653781331 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/2.rv_dm_sparse_lc_gate_fsm.3837200995 Sep 24 08:13:21 AM UTC 24 Sep 24 08:13:23 AM UTC 24 140601477 ps
T124 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.1700813944 Sep 24 08:13:20 AM UTC 24 Sep 24 08:13:23 AM UTC 24 1853512053 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.1322518949 Sep 24 08:13:21 AM UTC 24 Sep 24 08:13:24 AM UTC 24 423869121 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.737521049 Sep 24 08:13:22 AM UTC 24 Sep 24 08:13:24 AM UTC 24 96359259 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all.2708166242 Sep 24 08:13:21 AM UTC 24 Sep 24 08:13:24 AM UTC 24 1542532346 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.1045702129 Sep 24 08:13:21 AM UTC 24 Sep 24 08:13:25 AM UTC 24 1128903587 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.3968733153 Sep 24 08:13:22 AM UTC 24 Sep 24 08:13:25 AM UTC 24 665849351 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.2677210969 Sep 24 08:13:23 AM UTC 24 Sep 24 08:13:26 AM UTC 24 601371703 ps
T125 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.3241889404 Sep 24 08:13:22 AM UTC 24 Sep 24 08:13:26 AM UTC 24 880160636 ps
T150 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/3.rv_dm_hart_unavail.595640856 Sep 24 08:13:23 AM UTC 24 Sep 24 08:13:26 AM UTC 24 145505485 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.1788079686 Sep 24 08:13:24 AM UTC 24 Sep 24 08:13:27 AM UTC 24 95279927 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.2449534321 Sep 24 08:13:24 AM UTC 24 Sep 24 08:13:27 AM UTC 24 159948607 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.3003995043 Sep 24 08:13:20 AM UTC 24 Sep 24 08:13:28 AM UTC 24 5413315329 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.2309302126 Sep 24 08:13:26 AM UTC 24 Sep 24 08:13:28 AM UTC 24 139146597 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.2891429596 Sep 24 08:13:27 AM UTC 24 Sep 24 08:13:29 AM UTC 24 238997822 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.2949085730 Sep 24 08:13:19 AM UTC 24 Sep 24 08:13:30 AM UTC 24 7422958826 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/3.rv_dm_sec_cm.2984860717 Sep 24 08:13:25 AM UTC 24 Sep 24 08:13:31 AM UTC 24 645120047 ps
T109 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/4.rv_dm_alert_test.336676410 Sep 24 08:13:29 AM UTC 24 Sep 24 08:13:31 AM UTC 24 128431203 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.1735178182 Sep 24 08:13:27 AM UTC 24 Sep 24 08:13:32 AM UTC 24 574833628 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/4.rv_dm_buffered_enable.2320446497 Sep 24 08:13:27 AM UTC 24 Sep 24 08:13:32 AM UTC 24 695850159 ps
T143 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.4057369835 Sep 24 08:13:22 AM UTC 24 Sep 24 08:13:33 AM UTC 24 8153911642 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.1240459902 Sep 24 08:13:30 AM UTC 24 Sep 24 08:13:34 AM UTC 24 764945381 ps
T174 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/4.rv_dm_bad_sba_tl_access.114570211 Sep 24 08:13:27 AM UTC 24 Sep 24 08:13:34 AM UTC 24 2756625818 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/5.rv_dm_sba_tl_access.3409117179 Sep 24 08:13:29 AM UTC 24 Sep 24 08:13:34 AM UTC 24 2241466943 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/4.rv_dm_sba_tl_access.310485539 Sep 24 08:13:26 AM UTC 24 Sep 24 08:13:34 AM UTC 24 1625682511 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_bad_sba_tl_access.3130377404 Sep 24 08:13:13 AM UTC 24 Sep 24 08:13:35 AM UTC 24 11075243610 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/4.rv_dm_sec_cm.3472487891 Sep 24 08:13:29 AM UTC 24 Sep 24 08:13:35 AM UTC 24 931246275 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.188758560 Sep 24 08:13:11 AM UTC 24 Sep 24 08:13:35 AM UTC 24 1161569014 ps
T128 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/5.rv_dm_buffered_enable.3355734651 Sep 24 08:13:33 AM UTC 24 Sep 24 08:13:36 AM UTC 24 675161497 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/5.rv_dm_alert_test.2557978598 Sep 24 08:13:34 AM UTC 24 Sep 24 08:13:36 AM UTC 24 135545977 ps
T130 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.1470508238 Sep 24 08:13:22 AM UTC 24 Sep 24 08:13:36 AM UTC 24 2909064064 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/5.rv_dm_halt_resume_whereto.3518886968 Sep 24 08:13:33 AM UTC 24 Sep 24 08:13:36 AM UTC 24 537562948 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.1305034758 Sep 24 08:13:28 AM UTC 24 Sep 24 08:13:37 AM UTC 24 8050311487 ps
T131 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.2268924493 Sep 24 08:13:26 AM UTC 24 Sep 24 08:13:37 AM UTC 24 3129292845 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.407933588 Sep 24 08:13:30 AM UTC 24 Sep 24 08:13:37 AM UTC 24 2383104133 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.2289430092 Sep 24 08:13:33 AM UTC 24 Sep 24 08:13:38 AM UTC 24 1046903456 ps
T132 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/6.rv_dm_alert_test.3559353492 Sep 24 08:13:36 AM UTC 24 Sep 24 08:13:38 AM UTC 24 49649833 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/6.rv_dm_sba_tl_access.2436943354 Sep 24 08:13:35 AM UTC 24 Sep 24 08:13:39 AM UTC 24 1909922712 ps
T210 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/6.rv_dm_buffered_enable.3466595221 Sep 24 08:13:36 AM UTC 24 Sep 24 08:13:39 AM UTC 24 137370292 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/6.rv_dm_halt_resume_whereto.1779721655 Sep 24 08:13:36 AM UTC 24 Sep 24 08:13:39 AM UTC 24 354588889 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.3783278487 Sep 24 08:13:24 AM UTC 24 Sep 24 08:13:40 AM UTC 24 2850601335 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.3878960048 Sep 24 08:13:38 AM UTC 24 Sep 24 08:13:40 AM UTC 24 230984962 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/16.rv_dm_alert_test.218766972 Sep 24 08:14:07 AM UTC 24 Sep 24 08:14:09 AM UTC 24 142264793 ps
T145 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/7.rv_dm_buffered_enable.1817820801 Sep 24 08:13:39 AM UTC 24 Sep 24 08:13:42 AM UTC 24 103583831 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/7.rv_dm_alert_test.1954395201 Sep 24 08:13:40 AM UTC 24 Sep 24 08:13:42 AM UTC 24 63633234 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.116353679 Sep 24 08:13:36 AM UTC 24 Sep 24 08:13:42 AM UTC 24 1672461819 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.2462940288 Sep 24 08:13:29 AM UTC 24 Sep 24 08:13:44 AM UTC 24 2941408570 ps
T146 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/8.rv_dm_buffered_enable.3825334188 Sep 24 08:13:41 AM UTC 24 Sep 24 08:13:44 AM UTC 24 191177601 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/7.rv_dm_sba_tl_access.1458717082 Sep 24 08:13:36 AM UTC 24 Sep 24 08:13:44 AM UTC 24 3991896919 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/1.rv_dm_autoincr_sba_tl_access.2675254081 Sep 24 08:13:13 AM UTC 24 Sep 24 08:13:46 AM UTC 24 6382369898 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/8.rv_dm_alert_test.2190081607 Sep 24 08:13:43 AM UTC 24 Sep 24 08:13:46 AM UTC 24 41584093 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.2765695366 Sep 24 08:13:41 AM UTC 24 Sep 24 08:13:47 AM UTC 24 4073842626 ps
T248 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/6.rv_dm_bad_sba_tl_access.2129440900 Sep 24 08:13:35 AM UTC 24 Sep 24 08:13:48 AM UTC 24 2734473393 ps
T215 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/8.rv_dm_sba_tl_access.1534143476 Sep 24 08:13:40 AM UTC 24 Sep 24 08:13:49 AM UTC 24 3776618481 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.159317290 Sep 24 08:13:38 AM UTC 24 Sep 24 08:13:49 AM UTC 24 1752696837 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.3724731733 Sep 24 08:13:47 AM UTC 24 Sep 24 08:13:49 AM UTC 24 115255893 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.1362204011 Sep 24 08:13:45 AM UTC 24 Sep 24 08:13:49 AM UTC 24 9964308799 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.740391042 Sep 24 08:13:24 AM UTC 24 Sep 24 08:13:49 AM UTC 24 11869715811 ps
T218 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.494770121 Sep 24 08:13:20 AM UTC 24 Sep 24 08:13:50 AM UTC 24 7910548268 ps
T250 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/9.rv_dm_buffered_enable.953517151 Sep 24 08:13:46 AM UTC 24 Sep 24 08:13:51 AM UTC 24 675829870 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.216193267 Sep 24 08:13:41 AM UTC 24 Sep 24 08:13:52 AM UTC 24 2808914251 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.1921828379 Sep 24 08:13:47 AM UTC 24 Sep 24 08:13:52 AM UTC 24 5626147849 ps
T251 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/10.rv_dm_alert_test.1832145121 Sep 24 08:13:50 AM UTC 24 Sep 24 08:13:52 AM UTC 24 57871305 ps
T252 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.1975999656 Sep 24 08:13:43 AM UTC 24 Sep 24 08:13:52 AM UTC 24 3080680880 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all.3161342237 Sep 24 08:13:40 AM UTC 24 Sep 24 08:13:53 AM UTC 24 6644824258 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.1030591556 Sep 24 08:13:28 AM UTC 24 Sep 24 08:13:53 AM UTC 24 7026895053 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/6.rv_dm_autoincr_sba_tl_access.886830002 Sep 24 08:13:35 AM UTC 24 Sep 24 08:13:54 AM UTC 24 7504564010 ps
T219 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.922702532 Sep 24 08:13:40 AM UTC 24 Sep 24 08:13:54 AM UTC 24 1919493187 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/11.rv_dm_sba_tl_access.846795848 Sep 24 08:13:50 AM UTC 24 Sep 24 08:13:54 AM UTC 24 1937682934 ps
T216 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/10.rv_dm_sba_tl_access.477290488 Sep 24 08:13:48 AM UTC 24 Sep 24 08:13:54 AM UTC 24 2945717558 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/11.rv_dm_alert_test.2335353828 Sep 24 08:13:53 AM UTC 24 Sep 24 08:13:54 AM UTC 24 72401824 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.4206824465 Sep 24 08:13:02 AM UTC 24 Sep 24 08:13:55 AM UTC 24 21859254798 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.2375446276 Sep 24 08:13:22 AM UTC 24 Sep 24 08:13:56 AM UTC 24 6594296161 ps
T212 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.2213619305 Sep 24 08:13:38 AM UTC 24 Sep 24 08:13:56 AM UTC 24 13866739685 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/12.rv_dm_alert_test.3766157794 Sep 24 08:13:55 AM UTC 24 Sep 24 08:13:57 AM UTC 24 53672443 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/11.rv_dm_autoincr_sba_tl_access.662330582 Sep 24 08:13:51 AM UTC 24 Sep 24 08:13:57 AM UTC 24 584431077 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/10.rv_dm_stress_all.493627233 Sep 24 08:13:50 AM UTC 24 Sep 24 08:13:58 AM UTC 24 2133315801 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/13.rv_dm_alert_test.2572462708 Sep 24 08:13:56 AM UTC 24 Sep 24 08:13:58 AM UTC 24 76217381 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.1025157577 Sep 24 08:13:48 AM UTC 24 Sep 24 08:14:00 AM UTC 24 2881432428 ps
T220 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.3749556247 Sep 24 08:13:50 AM UTC 24 Sep 24 08:14:01 AM UTC 24 2665044093 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.1431291986 Sep 24 08:13:58 AM UTC 24 Sep 24 08:14:01 AM UTC 24 1695138428 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.1450913608 Sep 24 08:13:55 AM UTC 24 Sep 24 08:14:02 AM UTC 24 1743420245 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/14.rv_dm_sba_tl_access.665838278 Sep 24 08:13:57 AM UTC 24 Sep 24 08:14:02 AM UTC 24 1270475676 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/11.rv_dm_stress_all.2592155987 Sep 24 08:13:53 AM UTC 24 Sep 24 08:14:02 AM UTC 24 2690534815 ps
T211 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/9.rv_dm_autoincr_sba_tl_access.3560126948 Sep 24 08:13:46 AM UTC 24 Sep 24 08:14:02 AM UTC 24 15618563211 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/12.rv_dm_stress_all.3643671857 Sep 24 08:13:55 AM UTC 24 Sep 24 08:14:03 AM UTC 24 1428497977 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/10.rv_dm_autoincr_sba_tl_access.3483586367 Sep 24 08:13:50 AM UTC 24 Sep 24 08:14:03 AM UTC 24 10862910036 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/13.rv_dm_bad_sba_tl_access.3328615531 Sep 24 08:13:55 AM UTC 24 Sep 24 08:14:03 AM UTC 24 2854172141 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/14.rv_dm_alert_test.365857532 Sep 24 08:14:02 AM UTC 24 Sep 24 08:14:04 AM UTC 24 58148698 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/15.rv_dm_alert_test.439408326 Sep 24 08:14:04 AM UTC 24 Sep 24 08:14:06 AM UTC 24 42781015 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/15.rv_dm_autoincr_sba_tl_access.3090001647 Sep 24 08:14:03 AM UTC 24 Sep 24 08:14:07 AM UTC 24 2165457038 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/16.rv_dm_sba_tl_access.85990410 Sep 24 08:14:04 AM UTC 24 Sep 24 08:14:07 AM UTC 24 1361850813 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/12.rv_dm_autoincr_sba_tl_access.4110732888 Sep 24 08:13:54 AM UTC 24 Sep 24 08:14:09 AM UTC 24 8875858004 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/15.rv_dm_sba_tl_access.2714439132 Sep 24 08:14:02 AM UTC 24 Sep 24 08:14:09 AM UTC 24 2386138237 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/11.rv_dm_bad_sba_tl_access.3899382631 Sep 24 08:13:51 AM UTC 24 Sep 24 08:14:09 AM UTC 24 9914945398 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/14.rv_dm_autoincr_sba_tl_access.464551705 Sep 24 08:14:00 AM UTC 24 Sep 24 08:14:09 AM UTC 24 8099784964 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.3958219993 Sep 24 08:13:20 AM UTC 24 Sep 24 08:14:10 AM UTC 24 16649106938 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/13.rv_dm_sba_tl_access.1551895350 Sep 24 08:13:55 AM UTC 24 Sep 24 08:14:10 AM UTC 24 7536209555 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.3435255540 Sep 24 08:14:04 AM UTC 24 Sep 24 08:14:10 AM UTC 24 2227944420 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/12.rv_dm_sba_tl_access.3222316255 Sep 24 08:13:53 AM UTC 24 Sep 24 08:14:10 AM UTC 24 8993493467 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/14.rv_dm_stress_all.4190346517 Sep 24 08:14:01 AM UTC 24 Sep 24 08:14:11 AM UTC 24 5572563711 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/13.rv_dm_stress_all.1724259249 Sep 24 08:13:56 AM UTC 24 Sep 24 08:14:11 AM UTC 24 7794282454 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/15.rv_dm_stress_all.1084025182 Sep 24 08:14:03 AM UTC 24 Sep 24 08:14:12 AM UTC 24 2038769168 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all.1345727426 Sep 24 08:13:36 AM UTC 24 Sep 24 08:14:12 AM UTC 24 9714415876 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/13.rv_dm_autoincr_sba_tl_access.2155310245 Sep 24 08:13:56 AM UTC 24 Sep 24 08:14:13 AM UTC 24 8857495730 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/17.rv_dm_alert_test.998234551 Sep 24 08:14:11 AM UTC 24 Sep 24 08:14:13 AM UTC 24 53837237 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/15.rv_dm_bad_sba_tl_access.2643786425 Sep 24 08:14:03 AM UTC 24 Sep 24 08:14:13 AM UTC 24 6044688845 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/8.rv_dm_bad_sba_tl_access.4163589686 Sep 24 08:13:40 AM UTC 24 Sep 24 08:14:13 AM UTC 24 8073610317 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.1955761746 Sep 24 08:13:53 AM UTC 24 Sep 24 08:14:14 AM UTC 24 9033223909 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/18.rv_dm_alert_test.1803896002 Sep 24 08:14:12 AM UTC 24 Sep 24 08:14:14 AM UTC 24 77249024 ps
T213 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/10.rv_dm_bad_sba_tl_access.3467437167 Sep 24 08:13:49 AM UTC 24 Sep 24 08:14:15 AM UTC 24 15070886147 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/17.rv_dm_sba_tl_access.1606394949 Sep 24 08:14:07 AM UTC 24 Sep 24 08:14:15 AM UTC 24 10407566432 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/18.rv_dm_stress_all.2462611459 Sep 24 08:14:12 AM UTC 24 Sep 24 08:14:16 AM UTC 24 1825662617 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.1696224182 Sep 24 08:14:12 AM UTC 24 Sep 24 08:14:16 AM UTC 24 1491011800 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/16.rv_dm_stress_all.2586078480 Sep 24 08:14:07 AM UTC 24 Sep 24 08:14:16 AM UTC 24 4210753933 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/19.rv_dm_alert_test.2199303974 Sep 24 08:14:14 AM UTC 24 Sep 24 08:14:17 AM UTC 24 140466814 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/17.rv_dm_stress_all.3779132504 Sep 24 08:14:11 AM UTC 24 Sep 24 08:14:17 AM UTC 24 3449938957 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/18.rv_dm_bad_sba_tl_access.1380005967 Sep 24 08:14:11 AM UTC 24 Sep 24 08:14:18 AM UTC 24 976350145 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/17.rv_dm_bad_sba_tl_access.42039141 Sep 24 08:14:11 AM UTC 24 Sep 24 08:14:18 AM UTC 24 2822870536 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/16.rv_dm_autoincr_sba_tl_access.1239542610 Sep 24 08:14:06 AM UTC 24 Sep 24 08:14:18 AM UTC 24 3311062040 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/21.rv_dm_alert_test.1179041444 Sep 24 08:14:16 AM UTC 24 Sep 24 08:14:18 AM UTC 24 149638708 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/18.rv_dm_sba_tl_access.209227366 Sep 24 08:14:11 AM UTC 24 Sep 24 08:14:18 AM UTC 24 5098029057 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/20.rv_dm_alert_test.1408043037 Sep 24 08:14:16 AM UTC 24 Sep 24 08:14:18 AM UTC 24 122895487 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/19.rv_dm_bad_sba_tl_access.658978085 Sep 24 08:14:13 AM UTC 24 Sep 24 08:14:19 AM UTC 24 1769486264 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/22.rv_dm_alert_test.2935874079 Sep 24 08:14:17 AM UTC 24 Sep 24 08:14:19 AM UTC 24 117383745 ps
T214 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.529208383 Sep 24 08:13:45 AM UTC 24 Sep 24 08:14:19 AM UTC 24 13171406437 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/14.rv_dm_bad_sba_tl_access.563393946 Sep 24 08:13:58 AM UTC 24 Sep 24 08:14:20 AM UTC 24 11264179813 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.4042081472 Sep 24 08:14:14 AM UTC 24 Sep 24 08:14:20 AM UTC 24 2309729512 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/23.rv_dm_alert_test.935869447 Sep 24 08:14:18 AM UTC 24 Sep 24 08:14:20 AM UTC 24 44052026 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/12.rv_dm_bad_sba_tl_access.2530165811 Sep 24 08:13:54 AM UTC 24 Sep 24 08:14:20 AM UTC 24 10894926771 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.2912415098 Sep 24 08:14:14 AM UTC 24 Sep 24 08:14:20 AM UTC 24 3933461433 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/24.rv_dm_alert_test.3999044302 Sep 24 08:14:19 AM UTC 24 Sep 24 08:14:21 AM UTC 24 29820306 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/26.rv_dm_alert_test.2813811597 Sep 24 08:14:19 AM UTC 24 Sep 24 08:14:21 AM UTC 24 107442120 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/25.rv_dm_alert_test.2337940094 Sep 24 08:14:19 AM UTC 24 Sep 24 08:14:21 AM UTC 24 39685296 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/19.rv_dm_sba_tl_access.1218174736 Sep 24 08:14:12 AM UTC 24 Sep 24 08:14:22 AM UTC 24 1998504787 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.2117522448 Sep 24 08:14:17 AM UTC 24 Sep 24 08:14:22 AM UTC 24 2254776973 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all_with_rand_reset.348962905 Sep 24 08:13:36 AM UTC 24 Sep 24 08:14:22 AM UTC 24 4038909258 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/23.rv_dm_stress_all.3106895680 Sep 24 08:14:17 AM UTC 24 Sep 24 08:14:22 AM UTC 24 2455110075 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/28.rv_dm_alert_test.4281203376 Sep 24 08:14:20 AM UTC 24 Sep 24 08:14:23 AM UTC 24 56062213 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/27.rv_dm_alert_test.2160508111 Sep 24 08:14:20 AM UTC 24 Sep 24 08:14:23 AM UTC 24 137931823 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/29.rv_dm_alert_test.2634562714 Sep 24 08:14:21 AM UTC 24 Sep 24 08:14:23 AM UTC 24 174799881 ps
T217 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.1046202048 Sep 24 08:13:22 AM UTC 24 Sep 24 08:14:23 AM UTC 24 27488351609 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.2241602179 Sep 24 08:14:19 AM UTC 24 Sep 24 08:14:23 AM UTC 24 4085392859 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.1610352141 Sep 24 08:14:03 AM UTC 24 Sep 24 08:14:24 AM UTC 24 12775153442 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/30.rv_dm_alert_test.2767153048 Sep 24 08:14:22 AM UTC 24 Sep 24 08:14:24 AM UTC 24 29823108 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/32.rv_dm_alert_test.2964570795 Sep 24 08:14:22 AM UTC 24 Sep 24 08:14:24 AM UTC 24 92197055 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/31.rv_dm_alert_test.2736921996 Sep 24 08:14:22 AM UTC 24 Sep 24 08:14:24 AM UTC 24 57009968 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/45.rv_dm_alert_test.1441850661 Sep 24 08:14:29 AM UTC 24 Sep 24 08:14:32 AM UTC 24 75847873 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/26.rv_dm_stress_all.504229226 Sep 24 08:14:19 AM UTC 24 Sep 24 08:14:25 AM UTC 24 7145452736 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/34.rv_dm_alert_test.1863913977 Sep 24 08:14:23 AM UTC 24 Sep 24 08:14:25 AM UTC 24 41513586 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/33.rv_dm_alert_test.2154894308 Sep 24 08:14:23 AM UTC 24 Sep 24 08:14:26 AM UTC 24 149366169 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/35.rv_dm_alert_test.971982547 Sep 24 08:14:23 AM UTC 24 Sep 24 08:14:26 AM UTC 24 98502728 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/28.rv_dm_stress_all.2278666147 Sep 24 08:14:20 AM UTC 24 Sep 24 08:14:26 AM UTC 24 2848721818 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.1096266098 Sep 24 08:14:09 AM UTC 24 Sep 24 08:14:26 AM UTC 24 7906059496 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/38.rv_dm_alert_test.1260171159 Sep 24 08:14:25 AM UTC 24 Sep 24 08:14:26 AM UTC 24 90746459 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/36.rv_dm_alert_test.2177345319 Sep 24 08:14:24 AM UTC 24 Sep 24 08:14:27 AM UTC 24 52592355 ps
T312 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/37.rv_dm_alert_test.2581290496 Sep 24 08:14:25 AM UTC 24 Sep 24 08:14:27 AM UTC 24 97775016 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/31.rv_dm_stress_all.4014535479 Sep 24 08:14:22 AM UTC 24 Sep 24 08:14:27 AM UTC 24 1985235359 ps
T313 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.2465028234 Sep 24 08:14:11 AM UTC 24 Sep 24 08:14:27 AM UTC 24 10890479472 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.2416074792 Sep 24 08:14:19 AM UTC 24 Sep 24 08:14:28 AM UTC 24 3804350583 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/39.rv_dm_alert_test.3039178880 Sep 24 08:14:26 AM UTC 24 Sep 24 08:14:28 AM UTC 24 121287008 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/29.rv_dm_stress_all.2816096083 Sep 24 08:14:21 AM UTC 24 Sep 24 08:14:28 AM UTC 24 1685192703 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/40.rv_dm_alert_test.2032360141 Sep 24 08:14:26 AM UTC 24 Sep 24 08:14:29 AM UTC 24 172369304 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/34.rv_dm_stress_all.683427981 Sep 24 08:14:23 AM UTC 24 Sep 24 08:14:29 AM UTC 24 2629290485 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/39.rv_dm_stress_all.2503952842 Sep 24 08:14:25 AM UTC 24 Sep 24 08:14:29 AM UTC 24 1852886272 ps
T317 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/41.rv_dm_alert_test.2339068336 Sep 24 08:14:27 AM UTC 24 Sep 24 08:14:29 AM UTC 24 55885440 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/42.rv_dm_alert_test.2264874160 Sep 24 08:14:27 AM UTC 24 Sep 24 08:14:29 AM UTC 24 126556831 ps
T319 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/43.rv_dm_alert_test.3231975724 Sep 24 08:14:27 AM UTC 24 Sep 24 08:14:30 AM UTC 24 134417326 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/35.rv_dm_stress_all.2957567436 Sep 24 08:14:23 AM UTC 24 Sep 24 08:14:30 AM UTC 24 1567115590 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.2473845414 Sep 24 08:14:21 AM UTC 24 Sep 24 08:14:30 AM UTC 24 2796150497 ps
T320 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/44.rv_dm_alert_test.1889564158 Sep 24 08:14:28 AM UTC 24 Sep 24 08:14:30 AM UTC 24 69758583 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/37.rv_dm_stress_all.1637231432 Sep 24 08:14:24 AM UTC 24 Sep 24 08:14:31 AM UTC 24 3743309599 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/24.rv_dm_stress_all.132822985 Sep 24 08:14:18 AM UTC 24 Sep 24 08:14:31 AM UTC 24 3022246222 ps
T321 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/21.rv_dm_stress_all.2035281142 Sep 24 08:14:16 AM UTC 24 Sep 24 08:14:31 AM UTC 24 4106706323 ps
T322 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/47.rv_dm_alert_test.235758831 Sep 24 08:14:30 AM UTC 24 Sep 24 08:14:32 AM UTC 24 34577106 ps
T323 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.3949368117 Sep 24 08:14:27 AM UTC 24 Sep 24 08:14:32 AM UTC 24 3029079200 ps
T324 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/46.rv_dm_alert_test.136455623 Sep 24 08:14:30 AM UTC 24 Sep 24 08:14:32 AM UTC 24 69669913 ps
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T325 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/42.rv_dm_stress_all.2880016056 Sep 24 08:14:27 AM UTC 24 Sep 24 08:14:33 AM UTC 24 2295719657 ps
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T326 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/49.rv_dm_alert_test.3364751916 Sep 24 08:14:31 AM UTC 24 Sep 24 08:14:33 AM UTC 24 50685942 ps
T327 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/48.rv_dm_alert_test.2874312573 Sep 24 08:14:31 AM UTC 24 Sep 24 08:14:33 AM UTC 24 138554254 ps
T328 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/45.rv_dm_stress_all.555121193 Sep 24 08:14:28 AM UTC 24 Sep 24 08:14:33 AM UTC 24 2903778550 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/41.rv_dm_stress_all.2386895209 Sep 24 08:14:27 AM UTC 24 Sep 24 08:14:34 AM UTC 24 4689180409 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/32.rv_dm_stress_all.570112850 Sep 24 08:14:22 AM UTC 24 Sep 24 08:14:35 AM UTC 24 6698300893 ps
T329 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.1441333124 Sep 24 08:14:30 AM UTC 24 Sep 24 08:14:35 AM UTC 24 7785068370 ps
T330 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.286608791 Sep 24 08:13:35 AM UTC 24 Sep 24 08:14:36 AM UTC 24 13967493742 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.165436312 Sep 24 08:13:47 AM UTC 24 Sep 24 08:14:37 AM UTC 24 3507373986 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/36.rv_dm_stress_all.3779095740 Sep 24 08:14:23 AM UTC 24 Sep 24 08:14:38 AM UTC 24 5146558724 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.1197593251 Sep 24 08:14:23 AM UTC 24 Sep 24 08:14:42 AM UTC 24 4959214143 ps
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