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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.49 96.34 89.82 92.10 94.67 90.27 98.74 57.49


Total test records in report: 483
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T325 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/49.rv_dm_stress_all.3445670608 Oct 02 09:02:31 PM UTC 24 Oct 02 09:02:39 PM UTC 24 2210438331 ps
T326 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/41.rv_dm_stress_all.530850249 Oct 02 09:02:27 PM UTC 24 Oct 02 09:02:40 PM UTC 24 3095509328 ps
T189 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/47.rv_dm_stress_all.4281831456 Oct 02 09:02:31 PM UTC 24 Oct 02 09:02:42 PM UTC 24 7539154484 ps
T215 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.970159826 Oct 02 09:02:13 PM UTC 24 Oct 02 09:02:42 PM UTC 24 14497804111 ps
T190 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/38.rv_dm_stress_all.2248067642 Oct 02 09:02:26 PM UTC 24 Oct 02 09:02:45 PM UTC 24 4582757763 ps
T201 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.1252398626 Oct 02 09:02:20 PM UTC 24 Oct 02 09:02:46 PM UTC 24 7919031009 ps
T327 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/45.rv_dm_stress_all.1557580298 Oct 02 09:02:29 PM UTC 24 Oct 02 09:02:47 PM UTC 24 4817049765 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.80797109 Oct 02 09:01:32 PM UTC 24 Oct 02 09:02:53 PM UTC 24 4721969765 ps
T107 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.707401568 Oct 02 09:01:38 PM UTC 24 Oct 02 09:02:54 PM UTC 24 4592482541 ps
T328 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/17.rv_dm_autoincr_sba_tl_access.149484445 Oct 02 09:02:08 PM UTC 24 Oct 02 09:02:54 PM UTC 24 12424961961 ps
T82 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.1144792356 Oct 02 09:01:22 PM UTC 24 Oct 02 09:03:04 PM UTC 24 3931802217 ps
T329 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/14.rv_dm_autoincr_sba_tl_access.3289960721 Oct 02 09:01:58 PM UTC 24 Oct 02 09:03:14 PM UTC 24 61206878794 ps
T330 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/12.rv_dm_autoincr_sba_tl_access.724316718 Oct 02 09:01:51 PM UTC 24 Oct 02 09:03:42 PM UTC 24 60807270589 ps
T102 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.4245157626 Oct 02 08:58:49 PM UTC 24 Oct 02 08:58:52 PM UTC 24 138343052 ps
T103 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2927235294 Oct 02 08:58:50 PM UTC 24 Oct 02 08:58:53 PM UTC 24 988661259 ps
T104 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3318272337 Oct 02 08:58:52 PM UTC 24 Oct 02 08:58:54 PM UTC 24 369823830 ps
T331 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.113155025 Oct 02 08:58:56 PM UTC 24 Oct 02 08:58:58 PM UTC 24 88624886 ps
T332 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.4076012118 Oct 02 08:58:57 PM UTC 24 Oct 02 08:58:59 PM UTC 24 32110771 ps
T333 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.2029940391 Oct 02 08:58:54 PM UTC 24 Oct 02 08:59:00 PM UTC 24 405124137 ps
T136 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.973053532 Oct 02 08:58:52 PM UTC 24 Oct 02 08:59:01 PM UTC 24 1927845132 ps
T124 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.675028227 Oct 02 08:58:57 PM UTC 24 Oct 02 08:59:01 PM UTC 24 67362872 ps
T125 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.466739983 Oct 02 08:58:57 PM UTC 24 Oct 02 08:59:02 PM UTC 24 118618856 ps
T334 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1822972136 Oct 02 08:59:01 PM UTC 24 Oct 02 08:59:04 PM UTC 24 361191375 ps
T335 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1480764802 Oct 02 08:58:50 PM UTC 24 Oct 02 08:59:05 PM UTC 24 6129120462 ps
T336 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.982044297 Oct 02 08:59:02 PM UTC 24 Oct 02 08:59:06 PM UTC 24 561916679 ps
T337 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2916885071 Oct 02 08:59:01 PM UTC 24 Oct 02 08:59:06 PM UTC 24 110648369 ps
T338 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.852788335 Oct 02 08:59:02 PM UTC 24 Oct 02 08:59:07 PM UTC 24 559601395 ps
T126 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1032707583 Oct 02 08:59:00 PM UTC 24 Oct 02 08:59:07 PM UTC 24 320131501 ps
T339 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2896351022 Oct 02 08:58:53 PM UTC 24 Oct 02 08:59:07 PM UTC 24 4561297716 ps
T340 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.490991227 Oct 02 08:59:08 PM UTC 24 Oct 02 08:59:10 PM UTC 24 154702137 ps
T341 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.4287932458 Oct 02 08:59:08 PM UTC 24 Oct 02 08:59:10 PM UTC 24 46788851 ps
T127 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.2138284292 Oct 02 08:59:08 PM UTC 24 Oct 02 08:59:11 PM UTC 24 73977089 ps
T168 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.4219915122 Oct 02 08:59:07 PM UTC 24 Oct 02 08:59:12 PM UTC 24 2164264901 ps
T128 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.22256140 Oct 02 08:59:08 PM UTC 24 Oct 02 08:59:12 PM UTC 24 658314292 ps
T137 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1039428652 Oct 02 08:59:03 PM UTC 24 Oct 02 08:59:13 PM UTC 24 3782411197 ps
T342 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2417479787 Oct 02 08:59:04 PM UTC 24 Oct 02 08:59:13 PM UTC 24 2911202332 ps
T343 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2254340795 Oct 02 08:59:02 PM UTC 24 Oct 02 08:59:15 PM UTC 24 4423129627 ps
T344 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1784094195 Oct 02 08:58:53 PM UTC 24 Oct 02 08:59:16 PM UTC 24 10687279616 ps
T181 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3703437226 Oct 02 08:58:55 PM UTC 24 Oct 02 08:59:16 PM UTC 24 2060096707 ps
T345 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3173182099 Oct 02 08:59:13 PM UTC 24 Oct 02 08:59:17 PM UTC 24 426748627 ps
T346 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2246999753 Oct 02 08:59:05 PM UTC 24 Oct 02 08:59:17 PM UTC 24 8101166665 ps
T112 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2042285293 Oct 02 08:59:12 PM UTC 24 Oct 02 08:59:17 PM UTC 24 117942899 ps
T129 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3328304546 Oct 02 08:59:11 PM UTC 24 Oct 02 08:59:18 PM UTC 24 170718117 ps
T347 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1936931227 Oct 02 08:58:53 PM UTC 24 Oct 02 08:59:18 PM UTC 24 19162018754 ps
T142 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1759210381 Oct 02 08:58:49 PM UTC 24 Oct 02 08:59:18 PM UTC 24 2461611143 ps
T348 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.4280799823 Oct 02 08:59:17 PM UTC 24 Oct 02 08:59:20 PM UTC 24 463999560 ps
T349 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_walk.3545644917 Oct 02 08:59:19 PM UTC 24 Oct 02 08:59:21 PM UTC 24 46170399 ps
T350 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_partial_access.707367725 Oct 02 08:59:19 PM UTC 24 Oct 02 08:59:21 PM UTC 24 40087586 ps
T351 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1223553122 Oct 02 08:59:13 PM UTC 24 Oct 02 08:59:23 PM UTC 24 1404835076 ps
T169 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2675197568 Oct 02 08:59:08 PM UTC 24 Oct 02 08:59:24 PM UTC 24 4423304286 ps
T352 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1252502726 Oct 02 08:59:17 PM UTC 24 Oct 02 08:59:25 PM UTC 24 3129536275 ps
T130 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1254672315 Oct 02 08:59:21 PM UTC 24 Oct 02 08:59:25 PM UTC 24 313063728 ps
T353 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_errors.1890177128 Oct 02 08:59:18 PM UTC 24 Oct 02 08:59:25 PM UTC 24 105577827 ps
T131 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_rw.2805857961 Oct 02 08:59:21 PM UTC 24 Oct 02 08:59:25 PM UTC 24 112506534 ps
T354 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3125690867 Oct 02 08:59:24 PM UTC 24 Oct 02 08:59:28 PM UTC 24 81593531 ps
T138 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.268097541 Oct 02 08:59:17 PM UTC 24 Oct 02 08:59:29 PM UTC 24 11067516448 ps
T355 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3239759369 Oct 02 08:59:26 PM UTC 24 Oct 02 08:59:29 PM UTC 24 667597848 ps
T356 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3750295198 Oct 02 08:59:26 PM UTC 24 Oct 02 08:59:29 PM UTC 24 971450551 ps
T357 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1734633562 Oct 02 08:59:26 PM UTC 24 Oct 02 08:59:29 PM UTC 24 335907736 ps
T358 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3458159405 Oct 02 08:59:13 PM UTC 24 Oct 02 08:59:31 PM UTC 24 8874431843 ps
T132 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.122450576 Oct 02 08:59:22 PM UTC 24 Oct 02 08:59:31 PM UTC 24 607840569 ps
T359 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3654768690 Oct 02 08:59:32 PM UTC 24 Oct 02 08:59:34 PM UTC 24 97239189 ps
T360 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_walk.2611728217 Oct 02 08:59:32 PM UTC 24 Oct 02 08:59:34 PM UTC 24 47563527 ps
T139 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3708990179 Oct 02 08:59:26 PM UTC 24 Oct 02 08:59:35 PM UTC 24 2407604168 ps
T361 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3633612407 Oct 02 08:59:29 PM UTC 24 Oct 02 08:59:36 PM UTC 24 2685864754 ps
T133 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_rw.3992603383 Oct 02 08:59:35 PM UTC 24 Oct 02 08:59:38 PM UTC 24 211794664 ps
T170 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_errors.802361236 Oct 02 08:59:30 PM UTC 24 Oct 02 08:59:39 PM UTC 24 884939911 ps
T149 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3261825676 Oct 02 08:59:35 PM UTC 24 Oct 02 08:59:40 PM UTC 24 555078630 ps
T362 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1838981848 Oct 02 08:59:26 PM UTC 24 Oct 02 08:59:40 PM UTC 24 4267020399 ps
T182 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1027842951 Oct 02 08:59:19 PM UTC 24 Oct 02 08:59:41 PM UTC 24 4257891354 ps
T363 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3903362541 Oct 02 08:59:39 PM UTC 24 Oct 02 08:59:42 PM UTC 24 229421573 ps
T364 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3896575428 Oct 02 08:59:17 PM UTC 24 Oct 02 08:59:42 PM UTC 24 7813016284 ps
T365 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3556834495 Oct 02 08:59:29 PM UTC 24 Oct 02 08:59:54 PM UTC 24 22045534609 ps
T366 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2350082656 Oct 02 08:59:39 PM UTC 24 Oct 02 08:59:42 PM UTC 24 754605829 ps
T367 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.4286026597 Oct 02 08:59:36 PM UTC 24 Oct 02 08:59:42 PM UTC 24 61937583 ps
T157 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2175119804 Oct 02 08:59:36 PM UTC 24 Oct 02 08:59:49 PM UTC 24 506147603 ps
T368 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_errors.1225232295 Oct 02 08:59:44 PM UTC 24 Oct 02 08:59:50 PM UTC 24 161071867 ps
T224 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2577158713 Oct 02 08:59:31 PM UTC 24 Oct 02 08:59:52 PM UTC 24 4756849358 ps
T369 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_walk.3305334968 Oct 02 08:59:50 PM UTC 24 Oct 02 08:59:52 PM UTC 24 35110761 ps
T370 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2001159205 Oct 02 08:59:18 PM UTC 24 Oct 02 08:59:54 PM UTC 24 58808608519 ps
T371 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1508408822 Oct 02 08:59:53 PM UTC 24 Oct 02 08:59:55 PM UTC 24 118209491 ps
T372 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.270505692 Oct 02 08:59:43 PM UTC 24 Oct 02 08:59:56 PM UTC 24 3320517589 ps
T373 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1641564633 Oct 02 08:59:41 PM UTC 24 Oct 02 08:59:57 PM UTC 24 2542213212 ps
T150 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.823974131 Oct 02 08:59:53 PM UTC 24 Oct 02 08:59:58 PM UTC 24 227863342 ps
T151 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_rw.1503737403 Oct 02 08:59:53 PM UTC 24 Oct 02 08:59:58 PM UTC 24 236434134 ps
T374 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1376043008 Oct 02 08:59:57 PM UTC 24 Oct 02 08:59:59 PM UTC 24 115537379 ps
T158 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1833435412 Oct 02 08:59:56 PM UTC 24 Oct 02 09:00:02 PM UTC 24 826844556 ps
T375 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3556978059 Oct 02 08:59:57 PM UTC 24 Oct 02 09:00:03 PM UTC 24 6372980455 ps
T376 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.4249798030 Oct 02 08:59:57 PM UTC 24 Oct 02 09:00:03 PM UTC 24 199639136 ps
T223 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3354449006 Oct 02 08:59:50 PM UTC 24 Oct 02 09:00:04 PM UTC 24 2108336727 ps
T377 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_errors.1121610066 Oct 02 08:59:59 PM UTC 24 Oct 02 09:00:04 PM UTC 24 678720329 ps
T378 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.493638234 Oct 02 08:59:05 PM UTC 24 Oct 02 09:00:05 PM UTC 24 29508915415 ps
T379 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1599445191 Oct 02 08:59:01 PM UTC 24 Oct 02 09:00:06 PM UTC 24 2339972147 ps
T380 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.4253668515 Oct 02 08:59:43 PM UTC 24 Oct 02 09:00:06 PM UTC 24 6865610327 ps
T79 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.2378684372 Oct 02 08:58:54 PM UTC 24 Oct 02 09:00:07 PM UTC 24 3861189457 ps
T381 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1599804697 Oct 02 08:59:29 PM UTC 24 Oct 02 09:00:08 PM UTC 24 46215782019 ps
T382 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.4053257531 Oct 02 09:00:06 PM UTC 24 Oct 02 09:00:09 PM UTC 24 97443820 ps
T383 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3770598255 Oct 02 08:59:58 PM UTC 24 Oct 02 09:00:10 PM UTC 24 3355415344 ps
T384 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_rw.2456752697 Oct 02 09:00:06 PM UTC 24 Oct 02 09:00:10 PM UTC 24 203496093 ps
T159 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.540199489 Oct 02 09:00:06 PM UTC 24 Oct 02 09:00:11 PM UTC 24 127385586 ps
T385 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1017827617 Oct 02 09:00:06 PM UTC 24 Oct 02 09:00:12 PM UTC 24 99650770 ps
T386 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1956505016 Oct 02 09:00:07 PM UTC 24 Oct 02 09:00:12 PM UTC 24 3255899996 ps
T152 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_rw.1894860339 Oct 02 09:00:09 PM UTC 24 Oct 02 09:00:13 PM UTC 24 276097808 ps
T387 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.4086489300 Oct 02 08:58:59 PM UTC 24 Oct 02 09:00:14 PM UTC 24 4966489521 ps
T388 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.776431220 Oct 02 09:00:11 PM UTC 24 Oct 02 09:00:14 PM UTC 24 162955943 ps
T389 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_errors.23810022 Oct 02 09:00:08 PM UTC 24 Oct 02 09:00:14 PM UTC 24 3333513810 ps
T113 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1270542093 Oct 02 09:00:11 PM UTC 24 Oct 02 09:00:16 PM UTC 24 192886839 ps
T140 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2494754950 Oct 02 08:59:41 PM UTC 24 Oct 02 09:00:16 PM UTC 24 9539533579 ps
T390 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_rw.3879131341 Oct 02 09:00:45 PM UTC 24 Oct 02 09:00:48 PM UTC 24 405489663 ps
T153 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_aliasing.903160248 Oct 02 08:59:37 PM UTC 24 Oct 02 09:00:16 PM UTC 24 18920206950 ps
T391 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3768769792 Oct 02 09:00:12 PM UTC 24 Oct 02 09:00:17 PM UTC 24 1912266487 ps
T160 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2392757 Oct 02 09:00:10 PM UTC 24 Oct 02 09:00:17 PM UTC 24 242399750 ps
T392 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3515585366 Oct 02 08:59:35 PM UTC 24 Oct 02 09:00:17 PM UTC 24 5839504352 ps
T105 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.1165602605 Oct 02 08:59:18 PM UTC 24 Oct 02 09:00:18 PM UTC 24 7212098839 ps
T143 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_rw.3797212438 Oct 02 09:00:15 PM UTC 24 Oct 02 09:00:19 PM UTC 24 50616629 ps
T393 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2825087569 Oct 02 09:00:17 PM UTC 24 Oct 02 09:00:19 PM UTC 24 123109915 ps
T394 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_errors.1805853820 Oct 02 09:00:13 PM UTC 24 Oct 02 09:00:20 PM UTC 24 204462266 ps
T179 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3246110640 Oct 02 09:00:08 PM UTC 24 Oct 02 09:00:21 PM UTC 24 586270365 ps
T161 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2655196205 Oct 02 09:00:16 PM UTC 24 Oct 02 09:00:22 PM UTC 24 382236208 ps
T395 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_errors.4002823719 Oct 02 09:00:18 PM UTC 24 Oct 02 09:00:23 PM UTC 24 202142262 ps
T396 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2663349501 Oct 02 09:00:20 PM UTC 24 Oct 02 09:00:23 PM UTC 24 100798999 ps
T397 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1273628844 Oct 02 09:00:17 PM UTC 24 Oct 02 09:00:23 PM UTC 24 54593964 ps
T156 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_rw.2282182101 Oct 02 09:00:19 PM UTC 24 Oct 02 09:00:24 PM UTC 24 104121590 ps
T144 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1184728137 Oct 02 09:00:19 PM UTC 24 Oct 02 09:00:25 PM UTC 24 663201464 ps
T180 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.126121424 Oct 02 09:00:20 PM UTC 24 Oct 02 09:00:26 PM UTC 24 186300342 ps
T398 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.2639302705 Oct 02 09:00:17 PM UTC 24 Oct 02 09:00:29 PM UTC 24 6078045365 ps
T399 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_errors.1128850660 Oct 02 09:00:24 PM UTC 24 Oct 02 09:00:29 PM UTC 24 161171018 ps
T400 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_rw.4281971684 Oct 02 09:00:24 PM UTC 24 Oct 02 09:00:30 PM UTC 24 1744664318 ps
T401 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1354648531 Oct 02 09:00:27 PM UTC 24 Oct 02 09:00:30 PM UTC 24 591210004 ps
T222 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_intg_err.170585807 Oct 02 09:00:09 PM UTC 24 Oct 02 09:00:30 PM UTC 24 6741181649 ps
T402 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1326171489 Oct 02 09:00:17 PM UTC 24 Oct 02 09:00:31 PM UTC 24 10157585729 ps
T403 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1922798719 Oct 02 08:59:11 PM UTC 24 Oct 02 09:00:31 PM UTC 24 9969638167 ps
T404 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1516695568 Oct 02 09:00:26 PM UTC 24 Oct 02 09:00:32 PM UTC 24 116930287 ps
T229 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2130256846 Oct 02 09:00:00 PM UTC 24 Oct 02 09:00:32 PM UTC 24 1740755761 ps
T405 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3560150179 Oct 02 09:00:23 PM UTC 24 Oct 02 09:00:32 PM UTC 24 4511562473 ps
T406 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.837827183 Oct 02 08:59:56 PM UTC 24 Oct 02 09:00:34 PM UTC 24 14491254873 ps
T407 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.1029663685 Oct 02 09:00:32 PM UTC 24 Oct 02 09:00:35 PM UTC 24 113996227 ps
T219 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1553005712 Oct 02 09:00:18 PM UTC 24 Oct 02 09:00:35 PM UTC 24 4544666917 ps
T408 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1924274401 Oct 02 09:00:33 PM UTC 24 Oct 02 09:00:35 PM UTC 24 266852646 ps
T225 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1068298149 Oct 02 09:00:24 PM UTC 24 Oct 02 09:00:35 PM UTC 24 942792525 ps
T409 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1009622931 Oct 02 09:00:33 PM UTC 24 Oct 02 09:00:36 PM UTC 24 939171348 ps
T410 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1939008408 Oct 02 09:00:32 PM UTC 24 Oct 02 09:00:37 PM UTC 24 223354199 ps
T411 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.1897328891 Oct 02 09:00:30 PM UTC 24 Oct 02 09:00:37 PM UTC 24 218894969 ps
T145 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1918762149 Oct 02 09:00:25 PM UTC 24 Oct 02 09:00:39 PM UTC 24 10270834749 ps
T412 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_errors.2418874012 Oct 02 09:00:35 PM UTC 24 Oct 02 09:00:40 PM UTC 24 148945400 ps
T413 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.4252560167 Oct 02 09:00:37 PM UTC 24 Oct 02 09:00:40 PM UTC 24 168579508 ps
T155 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1299125287 Oct 02 08:59:26 PM UTC 24 Oct 02 09:00:40 PM UTC 24 4370709228 ps
T414 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.324057403 Oct 02 09:00:32 PM UTC 24 Oct 02 09:00:40 PM UTC 24 916992224 ps
T415 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1199633788 Oct 02 09:00:36 PM UTC 24 Oct 02 09:00:41 PM UTC 24 153622625 ps
T416 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.390684942 Oct 02 08:59:40 PM UTC 24 Oct 02 09:00:41 PM UTC 24 17727454162 ps
T417 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_rw.1044649332 Oct 02 09:00:36 PM UTC 24 Oct 02 09:00:41 PM UTC 24 96397833 ps
T418 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1805776427 Oct 02 09:00:33 PM UTC 24 Oct 02 09:00:41 PM UTC 24 3586125860 ps
T419 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.152151234 Oct 02 09:00:37 PM UTC 24 Oct 02 09:00:41 PM UTC 24 1580346445 ps
T420 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3912207501 Oct 02 09:00:30 PM UTC 24 Oct 02 09:00:42 PM UTC 24 1672627150 ps
T220 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_intg_err.4256907110 Oct 02 09:00:15 PM UTC 24 Oct 02 09:00:42 PM UTC 24 2223846781 ps
T421 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_rw.398071852 Oct 02 09:00:40 PM UTC 24 Oct 02 09:00:43 PM UTC 24 186686460 ps
T146 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_aliasing.632112732 Oct 02 08:59:12 PM UTC 24 Oct 02 09:00:43 PM UTC 24 21616094972 ps
T422 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_errors.1408959645 Oct 02 09:00:39 PM UTC 24 Oct 02 09:00:43 PM UTC 24 162563942 ps
T423 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2886840144 Oct 02 09:00:41 PM UTC 24 Oct 02 09:00:44 PM UTC 24 254275335 ps
T424 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.315491905 Oct 02 09:00:41 PM UTC 24 Oct 02 09:00:44 PM UTC 24 99732918 ps
T425 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.546748021 Oct 02 08:59:22 PM UTC 24 Oct 02 09:00:45 PM UTC 24 36409849706 ps
T426 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2042982575 Oct 02 09:00:39 PM UTC 24 Oct 02 09:00:46 PM UTC 24 8457291292 ps
T427 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1455597243 Oct 02 09:00:42 PM UTC 24 Oct 02 09:00:46 PM UTC 24 192882572 ps
T428 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1682351515 Oct 02 09:00:44 PM UTC 24 Oct 02 09:00:46 PM UTC 24 114254097 ps
T429 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3205912195 Oct 02 09:00:41 PM UTC 24 Oct 02 09:00:46 PM UTC 24 2423006743 ps
T109 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3261767291 Oct 02 08:59:07 PM UTC 24 Oct 02 09:00:46 PM UTC 24 3927505944 ps
T430 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3940152088 Oct 02 08:59:30 PM UTC 24 Oct 02 09:00:46 PM UTC 24 2981216932 ps
T147 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3048182445 Oct 02 09:00:41 PM UTC 24 Oct 02 09:00:47 PM UTC 24 488239315 ps
T431 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3899319817 Oct 02 08:59:43 PM UTC 24 Oct 02 09:00:47 PM UTC 24 4505817995 ps
T432 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_rw.757257017 Oct 02 09:00:42 PM UTC 24 Oct 02 09:00:47 PM UTC 24 253893046 ps
T433 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2748878016 Oct 02 09:00:30 PM UTC 24 Oct 02 09:00:47 PM UTC 24 16529233285 ps
T434 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_errors.1747945580 Oct 02 09:00:42 PM UTC 24 Oct 02 09:00:48 PM UTC 24 199331765 ps
T435 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2895824559 Oct 02 09:00:42 PM UTC 24 Oct 02 09:00:48 PM UTC 24 825829547 ps
T148 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3408973651 Oct 02 09:00:36 PM UTC 24 Oct 02 09:00:49 PM UTC 24 631081937 ps
T226 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3777767983 Oct 02 09:00:35 PM UTC 24 Oct 02 09:00:49 PM UTC 24 1012654527 ps
T436 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2098816961 Oct 02 09:00:23 PM UTC 24 Oct 02 09:00:50 PM UTC 24 6721799806 ps
T437 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2129862647 Oct 02 09:00:47 PM UTC 24 Oct 02 09:00:50 PM UTC 24 353208491 ps
T438 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.4005653647 Oct 02 09:00:49 PM UTC 24 Oct 02 09:00:51 PM UTC 24 144087336 ps
T439 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3836119386 Oct 02 09:00:47 PM UTC 24 Oct 02 09:00:51 PM UTC 24 120159319 ps
T440 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_errors.3112976858 Oct 02 09:00:44 PM UTC 24 Oct 02 09:00:51 PM UTC 24 218263272 ps
T441 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.614823140 Oct 02 09:00:49 PM UTC 24 Oct 02 09:00:52 PM UTC 24 246267484 ps
T442 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2409854879 Oct 02 09:00:49 PM UTC 24 Oct 02 09:00:52 PM UTC 24 1719164934 ps
T443 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_errors.3982673845 Oct 02 09:00:47 PM UTC 24 Oct 02 09:00:53 PM UTC 24 163288973 ps
T444 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_rw.2666779539 Oct 02 09:00:49 PM UTC 24 Oct 02 09:00:53 PM UTC 24 147493706 ps
T445 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.4057118040 Oct 02 09:00:51 PM UTC 24 Oct 02 09:00:54 PM UTC 24 308874342 ps
T154 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_rw.984064467 Oct 02 09:00:50 PM UTC 24 Oct 02 09:00:54 PM UTC 24 490366829 ps
T446 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2013561726 Oct 02 09:00:44 PM UTC 24 Oct 02 09:00:54 PM UTC 24 8015257791 ps
T447 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1658202328 Oct 02 09:00:40 PM UTC 24 Oct 02 09:00:55 PM UTC 24 3066589577 ps
T448 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1492281446 Oct 02 09:00:51 PM UTC 24 Oct 02 09:00:56 PM UTC 24 218747647 ps
T449 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1520502255 Oct 02 09:00:46 PM UTC 24 Oct 02 09:00:57 PM UTC 24 506393607 ps
T450 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1079593563 Oct 02 09:00:50 PM UTC 24 Oct 02 09:00:57 PM UTC 24 192927182 ps
T451 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3573361033 Oct 02 09:00:55 PM UTC 24 Oct 02 09:00:57 PM UTC 24 174794389 ps
T452 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_rw.3916287528 Oct 02 09:00:54 PM UTC 24 Oct 02 09:00:57 PM UTC 24 602452603 ps
T106 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.352522757 Oct 02 09:00:24 PM UTC 24 Oct 02 09:00:58 PM UTC 24 7279480545 ps
T453 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_errors.1545010994 Oct 02 09:00:50 PM UTC 24 Oct 02 09:00:58 PM UTC 24 373412648 ps
T454 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_errors.1573953765 Oct 02 09:00:52 PM UTC 24 Oct 02 09:00:59 PM UTC 24 1347642362 ps
T110 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.425285306 Oct 02 09:00:54 PM UTC 24 Oct 02 09:00:59 PM UTC 24 137418050 ps
T455 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1220572903 Oct 02 09:00:49 PM UTC 24 Oct 02 09:00:59 PM UTC 24 1242623230 ps
T108 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2046897656 Oct 02 08:59:59 PM UTC 24 Oct 02 09:01:00 PM UTC 24 3112345227 ps
T456 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2678415353 Oct 02 08:59:43 PM UTC 24 Oct 02 09:01:00 PM UTC 24 43117765384 ps
T457 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2960974602 Oct 02 09:00:58 PM UTC 24 Oct 02 09:01:01 PM UTC 24 405869384 ps
T458 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_rw.2992073065 Oct 02 09:00:58 PM UTC 24 Oct 02 09:01:01 PM UTC 24 53810554 ps
T459 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1854830421 Oct 02 09:00:30 PM UTC 24 Oct 02 09:01:02 PM UTC 24 2991953888 ps
T114 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1816132988 Oct 02 09:00:18 PM UTC 24 Oct 02 09:01:02 PM UTC 24 7214316973 ps
T460 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.580987375 Oct 02 09:00:58 PM UTC 24 Oct 02 09:01:02 PM UTC 24 128081412 ps
T461 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2449779508 Oct 02 09:00:52 PM UTC 24 Oct 02 09:01:02 PM UTC 24 3420122714 ps
T462 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1727155267 Oct 02 09:00:54 PM UTC 24 Oct 02 09:01:02 PM UTC 24 159110840 ps
T463 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_errors.4064447730 Oct 02 09:00:56 PM UTC 24 Oct 02 09:01:04 PM UTC 24 4073917710 ps
T464 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_rw.3955524708 Oct 02 09:01:01 PM UTC 24 Oct 02 09:01:05 PM UTC 24 411640388 ps
T465 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3738441321 Oct 02 09:00:58 PM UTC 24 Oct 02 09:01:07 PM UTC 24 1892653308 ps
T466 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.4003350821 Oct 02 09:01:01 PM UTC 24 Oct 02 09:01:07 PM UTC 24 89329496 ps
T230 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_intg_err.919268313 Oct 02 09:00:45 PM UTC 24 Oct 02 09:01:07 PM UTC 24 3600367203 ps
T467 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2261708744 Oct 02 09:00:47 PM UTC 24 Oct 02 09:01:07 PM UTC 24 27648873463 ps
T468 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3184730057 Oct 02 09:00:42 PM UTC 24 Oct 02 09:01:07 PM UTC 24 4607981918 ps
T469 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.3375288730 Oct 02 09:00:13 PM UTC 24 Oct 02 09:01:08 PM UTC 24 7054683238 ps
T470 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.985654065 Oct 02 09:01:01 PM UTC 24 Oct 02 09:01:09 PM UTC 24 341434737 ps
T471 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_errors.1735517006 Oct 02 09:01:00 PM UTC 24 Oct 02 09:01:09 PM UTC 24 147582663 ps
T472 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1972058310 Oct 02 09:00:47 PM UTC 24 Oct 02 09:01:09 PM UTC 24 4904287840 ps
T473 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1878824120 Oct 02 09:00:55 PM UTC 24 Oct 02 09:01:11 PM UTC 24 3092055105 ps
T474 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3251462624 Oct 02 09:00:47 PM UTC 24 Oct 02 09:01:11 PM UTC 24 1999376892 ps
T221 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2971854135 Oct 02 09:00:57 PM UTC 24 Oct 02 09:01:12 PM UTC 24 2096155972 ps
T475 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.2605683497 Oct 02 09:00:44 PM UTC 24 Oct 02 09:01:12 PM UTC 24 33669448302 ps
T227 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.541645819 Oct 02 09:00:53 PM UTC 24 Oct 02 09:01:13 PM UTC 24 4740649330 ps
T476 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3246798436 Oct 02 09:00:07 PM UTC 24 Oct 02 09:01:14 PM UTC 24 39354906285 ps
T477 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1335174107 Oct 02 09:01:00 PM UTC 24 Oct 02 09:01:14 PM UTC 24 12359377658 ps
T231 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.4211490759 Oct 02 09:00:50 PM UTC 24 Oct 02 09:01:17 PM UTC 24 2260339821 ps
T478 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.3468466494 Oct 02 09:00:42 PM UTC 24 Oct 02 09:01:19 PM UTC 24 12224057268 ps
T479 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.3771046113 Oct 02 09:00:55 PM UTC 24 Oct 02 09:01:30 PM UTC 24 9190763202 ps
T480 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.712803324 Oct 02 09:01:00 PM UTC 24 Oct 02 09:01:30 PM UTC 24 17858290651 ps
T228 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_intg_err.4019504875 Oct 02 09:01:01 PM UTC 24 Oct 02 09:01:41 PM UTC 24 6492615588 ps
T481 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1978027389 Oct 02 09:00:13 PM UTC 24 Oct 02 09:01:52 PM UTC 24 37499348313 ps
T482 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3683642604 Oct 02 09:00:52 PM UTC 24 Oct 02 09:01:54 PM UTC 24 66438072928 ps
T483 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.945916762 Oct 02 09:00:49 PM UTC 24 Oct 02 09:02:37 PM UTC 24 34368824781 ps

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.270717177
Short name T20
Test name
Test status
Simulation time 1606348849 ps
CPU time 3.36 seconds
Started Oct 02 09:01:03 PM UTC 24
Finished Oct 02 09:01:08 PM UTC 24
Peak memory 216212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270717177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_tl_access.270717177
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.3223897393
Short name T18
Test name
Test status
Simulation time 9362711145 ps
CPU time 47.87 seconds
Started Oct 02 09:01:30 PM UTC 24
Finished Oct 02 09:02:19 PM UTC 24
Peak memory 243328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=3223897393 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stres
s_all_with_rand_reset.3223897393
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.759580240
Short name T48
Test name
Test status
Simulation time 97974814 ps
CPU time 1.28 seconds
Started Oct 02 09:01:09 PM UTC 24
Finished Oct 02 09:01:12 PM UTC 24
Peak memory 215212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759580240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_abstractcmd_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.759580240
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_abstractcmd_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all.625481385
Short name T44
Test name
Test status
Simulation time 5006714876 ps
CPU time 4.71 seconds
Started Oct 02 09:01:22 PM UTC 24
Finished Oct 02 09:01:28 PM UTC 24
Peak memory 226100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625481385 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.625481385
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/2.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_busy.4213525611
Short name T14
Test name
Test status
Simulation time 1101477830 ps
CPU time 3.84 seconds
Started Oct 02 09:01:03 PM UTC 24
Finished Oct 02 09:01:09 PM UTC 24
Peak memory 215532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213525611 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.4213525611
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_cmderr_busy/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.2180336319
Short name T22
Test name
Test status
Simulation time 9970174094 ps
CPU time 9.51 seconds
Started Oct 02 09:01:03 PM UTC 24
Finished Oct 02 09:01:14 PM UTC 24
Peak memory 216336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180336319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.2180336319
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_halt_resume_whereto.1459341293
Short name T47
Test name
Test status
Simulation time 249794840 ps
CPU time 1.42 seconds
Started Oct 02 09:01:15 PM UTC 24
Finished Oct 02 09:01:17 PM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459341293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.1459341293
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_halt_resume_whereto/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3703437226
Short name T181
Test name
Test status
Simulation time 2060096707 ps
CPU time 19.36 seconds
Started Oct 02 08:58:55 PM UTC 24
Finished Oct 02 08:59:16 PM UTC 24
Peak memory 226072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703437226 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.3703437226
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.4229835236
Short name T81
Test name
Test status
Simulation time 6742510756 ps
CPU time 29.4 seconds
Started Oct 02 09:01:02 PM UTC 24
Finished Oct 02 09:01:33 PM UTC 24
Peak memory 216144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229835236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.4229835236
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.2378684372
Short name T79
Test name
Test status
Simulation time 3861189457 ps
CPU time 71.42 seconds
Started Oct 02 08:58:54 PM UTC 24
Finished Oct 02 09:00:07 PM UTC 24
Peak memory 230280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2378684372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_re
set.2378684372
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.2086849617
Short name T86
Test name
Test status
Simulation time 566393482 ps
CPU time 2.92 seconds
Started Oct 02 09:01:21 PM UTC 24
Finished Oct 02 09:01:25 PM UTC 24
Peak memory 252096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086849617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_buffered_enable.2086849617
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/2.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.80797109
Short name T28
Test name
Test status
Simulation time 4721969765 ps
CPU time 78.13 seconds
Started Oct 02 09:01:32 PM UTC 24
Finished Oct 02 09:02:53 PM UTC 24
Peak memory 232880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=80797109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_
all_with_rand_reset.80797109
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.3636382525
Short name T74
Test name
Test status
Simulation time 241137015 ps
CPU time 1.69 seconds
Started Oct 02 09:01:12 PM UTC 24
Finished Oct 02 09:01:15 PM UTC 24
Peak memory 215340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636382525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.3636382525
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_dmi_failed_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.101283481
Short name T51
Test name
Test status
Simulation time 91490441 ps
CPU time 1.1 seconds
Started Oct 02 09:01:13 PM UTC 24
Finished Oct 02 09:01:16 PM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101283481 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.101283481
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2046897656
Short name T108
Test name
Test status
Simulation time 3112345227 ps
CPU time 58.77 seconds
Started Oct 02 08:59:59 PM UTC 24
Finished Oct 02 09:01:00 PM UTC 24
Peak memory 232412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2046897656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_re
set.2046897656
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all_with_rand_reset.767430930
Short name T33
Test name
Test status
Simulation time 7211355530 ps
CPU time 35.12 seconds
Started Oct 02 09:01:34 PM UTC 24
Finished Oct 02 09:02:11 PM UTC 24
Peak memory 228552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=767430930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress
_all_with_rand_reset.767430930
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.3524649269
Short name T77
Test name
Test status
Simulation time 42765350 ps
CPU time 0.86 seconds
Started Oct 02 09:01:12 PM UTC 24
Finished Oct 02 09:01:14 PM UTC 24
Peak memory 215336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524649269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_scanmode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_scanmode.3524649269
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_scanmode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.466739983
Short name T125
Test name
Test status
Simulation time 118618856 ps
CPU time 3.69 seconds
Started Oct 02 08:58:57 PM UTC 24
Finished Oct 02 08:59:02 PM UTC 24
Peak memory 225772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466739983 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/r
v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.466739983
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.730571388
Short name T64
Test name
Test status
Simulation time 1817676211 ps
CPU time 42.4 seconds
Started Oct 02 09:01:19 PM UTC 24
Finished Oct 02 09:02:03 PM UTC 24
Peak memory 228268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=730571388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress
_all_with_rand_reset.730571388
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.450554767
Short name T73
Test name
Test status
Simulation time 16258832183 ps
CPU time 66.88 seconds
Started Oct 02 09:01:26 PM UTC 24
Finished Oct 02 09:02:35 PM UTC 24
Peak memory 232492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=450554767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress
_all_with_rand_reset.450554767
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/26.rv_dm_stress_all.2421440998
Short name T40
Test name
Test status
Simulation time 3425356938 ps
CPU time 6.42 seconds
Started Oct 02 09:02:20 PM UTC 24
Finished Oct 02 09:02:28 PM UTC 24
Peak memory 216128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421440998 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.2421440998
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/26.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.4053242213
Short name T31
Test name
Test status
Simulation time 372186018 ps
CPU time 1.63 seconds
Started Oct 02 09:01:15 PM UTC 24
Finished Oct 02 09:01:17 PM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053242213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.4053242213
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_cmderr_exception/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/15.rv_dm_stress_all.1321561341
Short name T11
Test name
Test status
Simulation time 2381385390 ps
CPU time 4.17 seconds
Started Oct 02 09:02:02 PM UTC 24
Finished Oct 02 09:02:07 PM UTC 24
Peak memory 226180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321561341 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.1321561341
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/15.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.3986098699
Short name T207
Test name
Test status
Simulation time 8818824889 ps
CPU time 27.23 seconds
Started Oct 02 09:01:03 PM UTC 24
Finished Oct 02 09:01:32 PM UTC 24
Peak memory 226408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986098699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.3986098699
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.1186131254
Short name T50
Test name
Test status
Simulation time 428544805 ps
CPU time 2.83 seconds
Started Oct 02 09:01:13 PM UTC 24
Finished Oct 02 09:01:17 PM UTC 24
Peak memory 254156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186131254 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.1186131254
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2130256846
Short name T229
Test name
Test status
Simulation time 1740755761 ps
CPU time 26.7 seconds
Started Oct 02 09:00:00 PM UTC 24
Finished Oct 02 09:00:32 PM UTC 24
Peak memory 228008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130256846 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.2130256846
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/5.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/13.rv_dm_autoincr_sba_tl_access.2974442448
Short name T205
Test name
Test status
Simulation time 13214589300 ps
CPU time 17.48 seconds
Started Oct 02 09:01:54 PM UTC 24
Finished Oct 02 09:02:13 PM UTC 24
Peak memory 226324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974442448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.2974442448
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.2067613534
Short name T15
Test name
Test status
Simulation time 639499411 ps
CPU time 2.66 seconds
Started Oct 02 09:01:09 PM UTC 24
Finished Oct 02 09:01:13 PM UTC 24
Peak memory 225840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067613534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.2067613534
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_ndmreset_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.3777482386
Short name T66
Test name
Test status
Simulation time 43304190 ps
CPU time 1.23 seconds
Started Oct 02 09:01:11 PM UTC 24
Finished Oct 02 09:01:13 PM UTC 24
Peak memory 225132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777482386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_rom_read_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.3777482386
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_rom_read_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3777767983
Short name T226
Test name
Test status
Simulation time 1012654527 ps
CPU time 12.98 seconds
Started Oct 02 09:00:35 PM UTC 24
Finished Oct 02 09:00:49 PM UTC 24
Peak memory 225876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777767983 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.3777767983
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/11.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/18.rv_dm_autoincr_sba_tl_access.1756614506
Short name T213
Test name
Test status
Simulation time 6964980224 ps
CPU time 11.15 seconds
Started Oct 02 09:02:10 PM UTC 24
Finished Oct 02 09:02:22 PM UTC 24
Peak memory 216088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756614506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.1756614506
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.1563429154
Short name T21
Test name
Test status
Simulation time 4977120276 ps
CPU time 16.55 seconds
Started Oct 02 09:01:09 PM UTC 24
Finished Oct 02 09:01:27 PM UTC 24
Peak memory 215852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563429154 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.1563429154
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_sba_debug_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/13.rv_dm_bad_sba_tl_access.960252200
Short name T172
Test name
Test status
Simulation time 4871431646 ps
CPU time 20.7 seconds
Started Oct 02 09:01:54 PM UTC 24
Finished Oct 02 09:02:16 PM UTC 24
Peak memory 226264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960252200 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.960252200
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/13.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/28.rv_dm_stress_all.460121276
Short name T184
Test name
Test status
Simulation time 1892539330 ps
CPU time 7.18 seconds
Started Oct 02 09:02:21 PM UTC 24
Finished Oct 02 09:02:29 PM UTC 24
Peak memory 226040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460121276 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.460121276
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/28.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.2389385950
Short name T187
Test name
Test status
Simulation time 4949694108 ps
CPU time 10.39 seconds
Started Oct 02 09:02:24 PM UTC 24
Finished Oct 02 09:02:35 PM UTC 24
Peak memory 216200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389385950 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.2389385950
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/33.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.1859491024
Short name T49
Test name
Test status
Simulation time 79919859 ps
CPU time 1.25 seconds
Started Oct 02 09:01:12 PM UTC 24
Finished Oct 02 09:01:14 PM UTC 24
Peak memory 225192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859491024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sparse_lc_gate_fsm.1859491024
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_sparse_lc_gate_fsm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3708990179
Short name T139
Test name
Test status
Simulation time 2407604168 ps
CPU time 8.17 seconds
Started Oct 02 08:59:26 PM UTC 24
Finished Oct 02 08:59:35 PM UTC 24
Peak memory 215640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708990179 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_hw_reset.3708990179
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.478535879
Short name T71
Test name
Test status
Simulation time 4785082431 ps
CPU time 4.4 seconds
Started Oct 02 09:02:15 PM UTC 24
Finished Oct 02 09:02:20 PM UTC 24
Peak memory 226196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478535879 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.478535879
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/20.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.2934799504
Short name T10
Test name
Test status
Simulation time 2309742753 ps
CPU time 8.12 seconds
Started Oct 02 09:01:25 PM UTC 24
Finished Oct 02 09:01:34 PM UTC 24
Peak memory 226104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934799504 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.2934799504
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/3.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3318272337
Short name T104
Test name
Test status
Simulation time 369823830 ps
CPU time 1.42 seconds
Started Oct 02 08:58:52 PM UTC 24
Finished Oct 02 08:58:54 PM UTC 24
Peak memory 215320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318272337 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_aliasing.3318272337
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1032707583
Short name T126
Test name
Test status
Simulation time 320131501 ps
CPU time 6.37 seconds
Started Oct 02 08:59:00 PM UTC 24
Finished Oct 02 08:59:07 PM UTC 24
Peak memory 215632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032707583 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_csr_outstanding.1032707583
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.30370962
Short name T69
Test name
Test status
Simulation time 469739580 ps
CPU time 1.67 seconds
Started Oct 02 09:01:15 PM UTC 24
Finished Oct 02 09:01:18 PM UTC 24
Peak memory 215340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30370962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv
_dm_cmderr_halt_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.30370962
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_cmderr_halt_resume/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.1211377807
Short name T39
Test name
Test status
Simulation time 16657481553 ps
CPU time 40.2 seconds
Started Oct 02 09:01:42 PM UTC 24
Finished Oct 02 09:02:23 PM UTC 24
Peak memory 233136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=1211377807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stres
s_all_with_rand_reset.1211377807
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2971854135
Short name T221
Test name
Test status
Simulation time 2096155972 ps
CPU time 13.26 seconds
Started Oct 02 09:00:57 PM UTC 24
Finished Oct 02 09:01:12 PM UTC 24
Peak memory 232700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971854135 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.2971854135
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/18.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_intg_err.4019504875
Short name T228
Test name
Test status
Simulation time 6492615588 ps
CPU time 39.16 seconds
Started Oct 02 09:01:01 PM UTC 24
Finished Oct 02 09:01:41 PM UTC 24
Peak memory 229916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019504875 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.4019504875
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/19.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_hart_unavail.3628463297
Short name T4
Test name
Test status
Simulation time 152564475 ps
CPU time 1.28 seconds
Started Oct 02 09:01:08 PM UTC 24
Finished Oct 02 09:01:10 PM UTC 24
Peak memory 215328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628463297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.3628463297
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_hart_unavail/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.4011395699
Short name T56
Test name
Test status
Simulation time 2580330022 ps
CPU time 9.24 seconds
Started Oct 02 09:01:13 PM UTC 24
Finished Oct 02 09:01:24 PM UTC 24
Peak memory 215988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011395699 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.4011395699
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_bad_sba_tl_access.3329490997
Short name T116
Test name
Test status
Simulation time 3933050001 ps
CPU time 9.87 seconds
Started Oct 02 09:01:14 PM UTC 24
Finished Oct 02 09:01:25 PM UTC 24
Peak memory 215948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329490997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.3329490997
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3999088903
Short name T76
Test name
Test status
Simulation time 445894102 ps
CPU time 1.28 seconds
Started Oct 02 09:01:18 PM UTC 24
Finished Oct 02 09:01:20 PM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999088903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.3999088903
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/11.rv_dm_autoincr_sba_tl_access.1530762951
Short name T176
Test name
Test status
Simulation time 6769858025 ps
CPU time 28.03 seconds
Started Oct 02 09:01:48 PM UTC 24
Finished Oct 02 09:02:18 PM UTC 24
Peak memory 228700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530762951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.1530762951
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/11.rv_dm_stress_all.238458297
Short name T37
Test name
Test status
Simulation time 1904330791 ps
CPU time 3.78 seconds
Started Oct 02 09:01:48 PM UTC 24
Finished Oct 02 09:01:53 PM UTC 24
Peak memory 215864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238458297 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.238458297
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/11.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/12.rv_dm_stress_all.1723960590
Short name T196
Test name
Test status
Simulation time 3537053786 ps
CPU time 4.71 seconds
Started Oct 02 09:01:52 PM UTC 24
Finished Oct 02 09:01:58 PM UTC 24
Peak memory 215856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723960590 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.1723960590
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/12.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/13.rv_dm_sba_tl_access.1382947153
Short name T120
Test name
Test status
Simulation time 5968394732 ps
CPU time 11.18 seconds
Started Oct 02 09:01:53 PM UTC 24
Finished Oct 02 09:02:05 PM UTC 24
Peak memory 226604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382947153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.1382947153
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/13.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/13.rv_dm_stress_all.1951521606
Short name T121
Test name
Test status
Simulation time 3068745601 ps
CPU time 8.82 seconds
Started Oct 02 09:01:56 PM UTC 24
Finished Oct 02 09:02:06 PM UTC 24
Peak memory 216192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951521606 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.1951521606
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/13.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/14.rv_dm_stress_all.1968014591
Short name T191
Test name
Test status
Simulation time 3388656653 ps
CPU time 19.22 seconds
Started Oct 02 09:01:59 PM UTC 24
Finished Oct 02 09:02:20 PM UTC 24
Peak memory 215924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968014591 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.1968014591
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/14.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/18.rv_dm_bad_sba_tl_access.1598919154
Short name T174
Test name
Test status
Simulation time 2116865749 ps
CPU time 7.31 seconds
Started Oct 02 09:02:09 PM UTC 24
Finished Oct 02 09:02:17 PM UTC 24
Peak memory 216032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598919154 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.1598919154
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/18.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.1169255270
Short name T214
Test name
Test status
Simulation time 4326813674 ps
CPU time 9.36 seconds
Started Oct 02 09:01:22 PM UTC 24
Finished Oct 02 09:01:33 PM UTC 24
Peak memory 216044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169255270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.1169255270
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/3.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.1479934986
Short name T27
Test name
Test status
Simulation time 3790406641 ps
CPU time 5.49 seconds
Started Oct 02 09:02:22 PM UTC 24
Finished Oct 02 09:02:29 PM UTC 24
Peak memory 216000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479934986 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.1479934986
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/30.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/36.rv_dm_stress_all.126361944
Short name T185
Test name
Test status
Simulation time 1493828689 ps
CPU time 2.89 seconds
Started Oct 02 09:02:24 PM UTC 24
Finished Oct 02 09:02:28 PM UTC 24
Peak memory 215808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126361944 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.126361944
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/36.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/38.rv_dm_stress_all.2248067642
Short name T190
Test name
Test status
Simulation time 4582757763 ps
CPU time 18.2 seconds
Started Oct 02 09:02:26 PM UTC 24
Finished Oct 02 09:02:45 PM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248067642 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.2248067642
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/38.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_rw.984064467
Short name T154
Test name
Test status
Simulation time 490366829 ps
CPU time 3.14 seconds
Started Oct 02 09:00:50 PM UTC 24
Finished Oct 02 09:00:54 PM UTC 24
Peak memory 230000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984064467 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/r
v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.984064467
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/16.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.2930526603
Short name T85
Test name
Test status
Simulation time 99026035 ps
CPU time 1.22 seconds
Started Oct 02 09:01:25 PM UTC 24
Finished Oct 02 09:01:27 PM UTC 24
Peak memory 225192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930526603 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sparse_lc_gate_fsm.2930526603
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/3.rv_dm_sparse_lc_gate_fsm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1759210381
Short name T142
Test name
Test status
Simulation time 2461611143 ps
CPU time 27.93 seconds
Started Oct 02 08:58:49 PM UTC 24
Finished Oct 02 08:59:18 PM UTC 24
Peak memory 225912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759210381 -ass
ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_aliasing.1759210381
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.4086489300
Short name T387
Test name
Test status
Simulation time 4966489521 ps
CPU time 73.26 seconds
Started Oct 02 08:58:59 PM UTC 24
Finished Oct 02 09:00:14 PM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086489300 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.4086489300
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.675028227
Short name T124
Test name
Test status
Simulation time 67362872 ps
CPU time 2.56 seconds
Started Oct 02 08:58:57 PM UTC 24
Finished Oct 02 08:59:01 PM UTC 24
Peak memory 225804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675028227 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.675028227
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2916885071
Short name T337
Test name
Test status
Simulation time 110648369 ps
CPU time 4.59 seconds
Started Oct 02 08:59:01 PM UTC 24
Finished Oct 02 08:59:06 PM UTC 24
Peak memory 230088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=2916885071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_r
and_reset.2916885071
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1936931227
Short name T347
Test name
Test status
Simulation time 19162018754 ps
CPU time 24.12 seconds
Started Oct 02 08:58:53 PM UTC 24
Finished Oct 02 08:59:18 PM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936931227 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_aliasing.1936931227
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1784094195
Short name T344
Test name
Test status
Simulation time 10687279616 ps
CPU time 21.62 seconds
Started Oct 02 08:58:53 PM UTC 24
Finished Oct 02 08:59:16 PM UTC 24
Peak memory 215692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784094195 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_bit_bash.1784094195
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.973053532
Short name T136
Test name
Test status
Simulation time 1927845132 ps
CPU time 8.13 seconds
Started Oct 02 08:58:52 PM UTC 24
Finished Oct 02 08:59:01 PM UTC 24
Peak memory 215608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973053532 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_hw_reset.973053532
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2896351022
Short name T339
Test name
Test status
Simulation time 4561297716 ps
CPU time 13.39 seconds
Started Oct 02 08:58:53 PM UTC 24
Finished Oct 02 08:59:07 PM UTC 24
Peak memory 215604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896351022 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.2896351022
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1480764802
Short name T335
Test name
Test status
Simulation time 6129120462 ps
CPU time 13.28 seconds
Started Oct 02 08:58:50 PM UTC 24
Finished Oct 02 08:59:05 PM UTC 24
Peak memory 215536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480764802 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_bit_bash.1480764802
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.4245157626
Short name T102
Test name
Test status
Simulation time 138343052 ps
CPU time 1.7 seconds
Started Oct 02 08:58:49 PM UTC 24
Finished Oct 02 08:58:52 PM UTC 24
Peak memory 214800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245157626 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_hw_reset.4245157626
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2927235294
Short name T103
Test name
Test status
Simulation time 988661259 ps
CPU time 1.93 seconds
Started Oct 02 08:58:50 PM UTC 24
Finished Oct 02 08:58:53 PM UTC 24
Peak memory 215316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927235294 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.2927235294
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.4076012118
Short name T332
Test name
Test status
Simulation time 32110771 ps
CPU time 1.18 seconds
Started Oct 02 08:58:57 PM UTC 24
Finished Oct 02 08:58:59 PM UTC 24
Peak memory 215376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076012118 -assert nopostproc +UVM
_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_partial_access.4076012118
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.113155025
Short name T331
Test name
Test status
Simulation time 88624886 ps
CPU time 0.97 seconds
Started Oct 02 08:58:56 PM UTC 24
Finished Oct 02 08:58:58 PM UTC 24
Peak memory 215316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113155025 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.113155025
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.2029940391
Short name T333
Test name
Test status
Simulation time 405124137 ps
CPU time 4.59 seconds
Started Oct 02 08:58:54 PM UTC 24
Finished Oct 02 08:59:00 PM UTC 24
Peak memory 226000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029940391 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.2029940391
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1599445191
Short name T379
Test name
Test status
Simulation time 2339972147 ps
CPU time 63.49 seconds
Started Oct 02 08:59:01 PM UTC 24
Finished Oct 02 09:00:06 PM UTC 24
Peak memory 215796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599445191 -ass
ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_aliasing.1599445191
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1922798719
Short name T403
Test name
Test status
Simulation time 9969638167 ps
CPU time 77.96 seconds
Started Oct 02 08:59:11 PM UTC 24
Finished Oct 02 09:00:31 PM UTC 24
Peak memory 215700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922798719 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.1922798719
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.22256140
Short name T128
Test name
Test status
Simulation time 658314292 ps
CPU time 3.4 seconds
Started Oct 02 08:59:08 PM UTC 24
Finished Oct 02 08:59:12 PM UTC 24
Peak memory 225788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22256140 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.22256140
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2042285293
Short name T112
Test name
Test status
Simulation time 117942899 ps
CPU time 4.26 seconds
Started Oct 02 08:59:12 PM UTC 24
Finished Oct 02 08:59:17 PM UTC 24
Peak memory 232260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=2042285293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_r
and_reset.2042285293
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.2138284292
Short name T127
Test name
Test status
Simulation time 73977089 ps
CPU time 2.63 seconds
Started Oct 02 08:59:08 PM UTC 24
Finished Oct 02 08:59:11 PM UTC 24
Peak memory 225976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138284292 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.2138284292
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.493638234
Short name T378
Test name
Test status
Simulation time 29508915415 ps
CPU time 58.09 seconds
Started Oct 02 08:59:05 PM UTC 24
Finished Oct 02 09:00:05 PM UTC 24
Peak memory 215604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493638234 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_aliasing.493638234
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2246999753
Short name T346
Test name
Test status
Simulation time 8101166665 ps
CPU time 10.57 seconds
Started Oct 02 08:59:05 PM UTC 24
Finished Oct 02 08:59:17 PM UTC 24
Peak memory 215756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246999753 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_bit_bash.2246999753
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1039428652
Short name T137
Test name
Test status
Simulation time 3782411197 ps
CPU time 8.36 seconds
Started Oct 02 08:59:03 PM UTC 24
Finished Oct 02 08:59:13 PM UTC 24
Peak memory 215676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039428652 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_hw_reset.1039428652
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2417479787
Short name T342
Test name
Test status
Simulation time 2911202332 ps
CPU time 7.51 seconds
Started Oct 02 08:59:04 PM UTC 24
Finished Oct 02 08:59:13 PM UTC 24
Peak memory 215620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417479787 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.2417479787
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.852788335
Short name T338
Test name
Test status
Simulation time 559601395 ps
CPU time 3.64 seconds
Started Oct 02 08:59:02 PM UTC 24
Finished Oct 02 08:59:07 PM UTC 24
Peak memory 215388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852788335 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_aliasing.852788335
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2254340795
Short name T343
Test name
Test status
Simulation time 4423129627 ps
CPU time 12.22 seconds
Started Oct 02 08:59:02 PM UTC 24
Finished Oct 02 08:59:15 PM UTC 24
Peak memory 215696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254340795 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_bit_bash.2254340795
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1822972136
Short name T334
Test name
Test status
Simulation time 361191375 ps
CPU time 1.79 seconds
Started Oct 02 08:59:01 PM UTC 24
Finished Oct 02 08:59:04 PM UTC 24
Peak memory 215320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822972136 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_hw_reset.1822972136
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.982044297
Short name T336
Test name
Test status
Simulation time 561916679 ps
CPU time 2.68 seconds
Started Oct 02 08:59:02 PM UTC 24
Finished Oct 02 08:59:06 PM UTC 24
Peak memory 215392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982044297 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.982044297
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.4287932458
Short name T341
Test name
Test status
Simulation time 46788851 ps
CPU time 1.13 seconds
Started Oct 02 08:59:08 PM UTC 24
Finished Oct 02 08:59:10 PM UTC 24
Peak memory 215376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287932458 -assert nopostproc +UVM
_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_partial_access.4287932458
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.490991227
Short name T340
Test name
Test status
Simulation time 154702137 ps
CPU time 1.13 seconds
Started Oct 02 08:59:08 PM UTC 24
Finished Oct 02 08:59:10 PM UTC 24
Peak memory 215316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490991227 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.490991227
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3328304546
Short name T129
Test name
Test status
Simulation time 170718117 ps
CPU time 5.52 seconds
Started Oct 02 08:59:11 PM UTC 24
Finished Oct 02 08:59:18 PM UTC 24
Peak memory 215472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328304546 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_csr_outstanding.3328304546
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3261767291
Short name T109
Test name
Test status
Simulation time 3927505944 ps
CPU time 97.88 seconds
Started Oct 02 08:59:07 PM UTC 24
Finished Oct 02 09:00:46 PM UTC 24
Peak memory 230140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3261767291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_re
set.3261767291
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.4219915122
Short name T168
Test name
Test status
Simulation time 2164264901 ps
CPU time 4.1 seconds
Started Oct 02 08:59:07 PM UTC 24
Finished Oct 02 08:59:12 PM UTC 24
Peak memory 226044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219915122 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.4219915122
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2675197568
Short name T169
Test name
Test status
Simulation time 4423304286 ps
CPU time 15.57 seconds
Started Oct 02 08:59:08 PM UTC 24
Finished Oct 02 08:59:24 PM UTC 24
Peak memory 232736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675197568 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.2675197568
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1939008408
Short name T410
Test name
Test status
Simulation time 223354199 ps
CPU time 4.14 seconds
Started Oct 02 09:00:32 PM UTC 24
Finished Oct 02 09:00:37 PM UTC 24
Peak memory 230088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=1939008408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_
rand_reset.1939008408
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.1029663685
Short name T407
Test name
Test status
Simulation time 113996227 ps
CPU time 1.98 seconds
Started Oct 02 09:00:32 PM UTC 24
Finished Oct 02 09:00:35 PM UTC 24
Peak memory 225332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029663685 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.1029663685
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/10.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2748878016
Short name T433
Test name
Test status
Simulation time 16529233285 ps
CPU time 15.81 seconds
Started Oct 02 09:00:30 PM UTC 24
Finished Oct 02 09:00:47 PM UTC 24
Peak memory 215700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748878016 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_bit_bash.2748878016
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3912207501
Short name T420
Test name
Test status
Simulation time 1672627150 ps
CPU time 10.26 seconds
Started Oct 02 09:00:30 PM UTC 24
Finished Oct 02 09:00:42 PM UTC 24
Peak memory 215536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912207501 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.3912207501
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1354648531
Short name T401
Test name
Test status
Simulation time 591210004 ps
CPU time 1.7 seconds
Started Oct 02 09:00:27 PM UTC 24
Finished Oct 02 09:00:30 PM UTC 24
Peak memory 215312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354648531 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.1354648531
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.324057403
Short name T414
Test name
Test status
Simulation time 916992224 ps
CPU time 7.25 seconds
Started Oct 02 09:00:32 PM UTC 24
Finished Oct 02 09:00:40 PM UTC 24
Peak memory 215548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324057403 -assert nopostproc +UV
M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_csr_outstanding.324057403
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/10.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.1897328891
Short name T411
Test name
Test status
Simulation time 218894969 ps
CPU time 5.75 seconds
Started Oct 02 09:00:30 PM UTC 24
Finished Oct 02 09:00:37 PM UTC 24
Peak memory 225964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897328891 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.1897328891
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/10.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1854830421
Short name T459
Test name
Test status
Simulation time 2991953888 ps
CPU time 29.92 seconds
Started Oct 02 09:00:30 PM UTC 24
Finished Oct 02 09:01:02 PM UTC 24
Peak memory 230168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854830421 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.1854830421
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/10.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1199633788
Short name T415
Test name
Test status
Simulation time 153622625 ps
CPU time 3.14 seconds
Started Oct 02 09:00:36 PM UTC 24
Finished Oct 02 09:00:41 PM UTC 24
Peak memory 225948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=1199633788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_
rand_reset.1199633788
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_rw.1044649332
Short name T417
Test name
Test status
Simulation time 96397833 ps
CPU time 3.48 seconds
Started Oct 02 09:00:36 PM UTC 24
Finished Oct 02 09:00:41 PM UTC 24
Peak memory 225764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044649332 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.1044649332
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/11.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1805776427
Short name T418
Test name
Test status
Simulation time 3586125860 ps
CPU time 7.17 seconds
Started Oct 02 09:00:33 PM UTC 24
Finished Oct 02 09:00:41 PM UTC 24
Peak memory 215612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805776427 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_bit_bash.1805776427
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1009622931
Short name T409
Test name
Test status
Simulation time 939171348 ps
CPU time 2 seconds
Started Oct 02 09:00:33 PM UTC 24
Finished Oct 02 09:00:36 PM UTC 24
Peak memory 215332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009622931 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.1009622931
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1924274401
Short name T408
Test name
Test status
Simulation time 266852646 ps
CPU time 1.5 seconds
Started Oct 02 09:00:33 PM UTC 24
Finished Oct 02 09:00:35 PM UTC 24
Peak memory 215312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924274401 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.1924274401
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3408973651
Short name T148
Test name
Test status
Simulation time 631081937 ps
CPU time 11.47 seconds
Started Oct 02 09:00:36 PM UTC 24
Finished Oct 02 09:00:49 PM UTC 24
Peak memory 215584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408973651 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_csr_outstanding.3408973651
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/11.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_errors.2418874012
Short name T412
Test name
Test status
Simulation time 148945400 ps
CPU time 3.42 seconds
Started Oct 02 09:00:35 PM UTC 24
Finished Oct 02 09:00:40 PM UTC 24
Peak memory 225964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418874012 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.2418874012
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/11.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.315491905
Short name T424
Test name
Test status
Simulation time 99732918 ps
CPU time 2.25 seconds
Started Oct 02 09:00:41 PM UTC 24
Finished Oct 02 09:00:44 PM UTC 24
Peak memory 228100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=315491905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_r
and_reset.315491905
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_rw.398071852
Short name T421
Test name
Test status
Simulation time 186686460 ps
CPU time 1.93 seconds
Started Oct 02 09:00:40 PM UTC 24
Finished Oct 02 09:00:43 PM UTC 24
Peak memory 225372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398071852 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/r
v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.398071852
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/12.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2042982575
Short name T426
Test name
Test status
Simulation time 8457291292 ps
CPU time 6.54 seconds
Started Oct 02 09:00:39 PM UTC 24
Finished Oct 02 09:00:46 PM UTC 24
Peak memory 215700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042982575 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_bit_bash.2042982575
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.152151234
Short name T419
Test name
Test status
Simulation time 1580346445 ps
CPU time 3.08 seconds
Started Oct 02 09:00:37 PM UTC 24
Finished Oct 02 09:00:41 PM UTC 24
Peak memory 215548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152151234 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.152151234
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.4252560167
Short name T413
Test name
Test status
Simulation time 168579508 ps
CPU time 1.36 seconds
Started Oct 02 09:00:37 PM UTC 24
Finished Oct 02 09:00:40 PM UTC 24
Peak memory 215312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252560167 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.4252560167
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3048182445
Short name T147
Test name
Test status
Simulation time 488239315 ps
CPU time 4.95 seconds
Started Oct 02 09:00:41 PM UTC 24
Finished Oct 02 09:00:47 PM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048182445 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same_csr_outstanding.3048182445
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/12.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_errors.1408959645
Short name T422
Test name
Test status
Simulation time 162563942 ps
CPU time 3.55 seconds
Started Oct 02 09:00:39 PM UTC 24
Finished Oct 02 09:00:43 PM UTC 24
Peak memory 225968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408959645 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.1408959645
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/12.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1658202328
Short name T447
Test name
Test status
Simulation time 3066589577 ps
CPU time 13.78 seconds
Started Oct 02 09:00:40 PM UTC 24
Finished Oct 02 09:00:55 PM UTC 24
Peak memory 232768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658202328 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.1658202328
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/12.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1455597243
Short name T427
Test name
Test status
Simulation time 192882572 ps
CPU time 2.82 seconds
Started Oct 02 09:00:42 PM UTC 24
Finished Oct 02 09:00:46 PM UTC 24
Peak memory 225992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=1455597243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_
rand_reset.1455597243
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_rw.757257017
Short name T432
Test name
Test status
Simulation time 253893046 ps
CPU time 3.7 seconds
Started Oct 02 09:00:42 PM UTC 24
Finished Oct 02 09:00:47 PM UTC 24
Peak memory 225840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757257017 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/r
v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.757257017
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/13.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.3468466494
Short name T478
Test name
Test status
Simulation time 12224057268 ps
CPU time 35.67 seconds
Started Oct 02 09:00:42 PM UTC 24
Finished Oct 02 09:01:19 PM UTC 24
Peak memory 215700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468466494 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_bit_bash.3468466494
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3205912195
Short name T429
Test name
Test status
Simulation time 2423006743 ps
CPU time 4.32 seconds
Started Oct 02 09:00:41 PM UTC 24
Finished Oct 02 09:00:46 PM UTC 24
Peak memory 215752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205912195 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.3205912195
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2886840144
Short name T423
Test name
Test status
Simulation time 254275335 ps
CPU time 1.69 seconds
Started Oct 02 09:00:41 PM UTC 24
Finished Oct 02 09:00:44 PM UTC 24
Peak memory 215312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886840144 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.2886840144
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2895824559
Short name T435
Test name
Test status
Simulation time 825829547 ps
CPU time 4.94 seconds
Started Oct 02 09:00:42 PM UTC 24
Finished Oct 02 09:00:48 PM UTC 24
Peak memory 215612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895824559 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_csr_outstanding.2895824559
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/13.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_errors.1747945580
Short name T434
Test name
Test status
Simulation time 199331765 ps
CPU time 4.48 seconds
Started Oct 02 09:00:42 PM UTC 24
Finished Oct 02 09:00:48 PM UTC 24
Peak memory 226036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747945580 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.1747945580
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/13.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3184730057
Short name T468
Test name
Test status
Simulation time 4607981918 ps
CPU time 24 seconds
Started Oct 02 09:00:42 PM UTC 24
Finished Oct 02 09:01:07 PM UTC 24
Peak memory 232892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184730057 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.3184730057
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/13.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3836119386
Short name T439
Test name
Test status
Simulation time 120159319 ps
CPU time 2.88 seconds
Started Oct 02 09:00:47 PM UTC 24
Finished Oct 02 09:00:51 PM UTC 24
Peak memory 228052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=3836119386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_
rand_reset.3836119386
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_rw.3879131341
Short name T390
Test name
Test status
Simulation time 405489663 ps
CPU time 2.04 seconds
Started Oct 02 09:00:45 PM UTC 24
Finished Oct 02 09:00:48 PM UTC 24
Peak memory 230064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879131341 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.3879131341
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/14.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.2605683497
Short name T475
Test name
Test status
Simulation time 33669448302 ps
CPU time 27.01 seconds
Started Oct 02 09:00:44 PM UTC 24
Finished Oct 02 09:01:12 PM UTC 24
Peak memory 215472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605683497 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_bit_bash.2605683497
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2013561726
Short name T446
Test name
Test status
Simulation time 8015257791 ps
CPU time 9.33 seconds
Started Oct 02 09:00:44 PM UTC 24
Finished Oct 02 09:00:54 PM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013561726 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.2013561726
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1682351515
Short name T428
Test name
Test status
Simulation time 114254097 ps
CPU time 1.48 seconds
Started Oct 02 09:00:44 PM UTC 24
Finished Oct 02 09:00:46 PM UTC 24
Peak memory 214992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682351515 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.1682351515
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1520502255
Short name T449
Test name
Test status
Simulation time 506393607 ps
CPU time 9.68 seconds
Started Oct 02 09:00:46 PM UTC 24
Finished Oct 02 09:00:57 PM UTC 24
Peak memory 215608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520502255 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same_csr_outstanding.1520502255
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/14.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_errors.3112976858
Short name T440
Test name
Test status
Simulation time 218263272 ps
CPU time 6.26 seconds
Started Oct 02 09:00:44 PM UTC 24
Finished Oct 02 09:00:51 PM UTC 24
Peak memory 225928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112976858 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.3112976858
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/14.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_intg_err.919268313
Short name T230
Test name
Test status
Simulation time 3600367203 ps
CPU time 21.21 seconds
Started Oct 02 09:00:45 PM UTC 24
Finished Oct 02 09:01:07 PM UTC 24
Peak memory 227960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919268313 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.919268313
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/14.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.614823140
Short name T441
Test name
Test status
Simulation time 246267484 ps
CPU time 1.96 seconds
Started Oct 02 09:00:49 PM UTC 24
Finished Oct 02 09:00:52 PM UTC 24
Peak memory 225288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=614823140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_r
and_reset.614823140
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_rw.2666779539
Short name T444
Test name
Test status
Simulation time 147493706 ps
CPU time 3.1 seconds
Started Oct 02 09:00:49 PM UTC 24
Finished Oct 02 09:00:53 PM UTC 24
Peak memory 229936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666779539 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.2666779539
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/15.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2261708744
Short name T467
Test name
Test status
Simulation time 27648873463 ps
CPU time 19 seconds
Started Oct 02 09:00:47 PM UTC 24
Finished Oct 02 09:01:07 PM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261708744 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_bit_bash.2261708744
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1972058310
Short name T472
Test name
Test status
Simulation time 4904287840 ps
CPU time 20.7 seconds
Started Oct 02 09:00:47 PM UTC 24
Finished Oct 02 09:01:09 PM UTC 24
Peak memory 215664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972058310 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.1972058310
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2129862647
Short name T437
Test name
Test status
Simulation time 353208491 ps
CPU time 2.08 seconds
Started Oct 02 09:00:47 PM UTC 24
Finished Oct 02 09:00:50 PM UTC 24
Peak memory 215372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129862647 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.2129862647
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1220572903
Short name T455
Test name
Test status
Simulation time 1242623230 ps
CPU time 9.65 seconds
Started Oct 02 09:00:49 PM UTC 24
Finished Oct 02 09:00:59 PM UTC 24
Peak memory 215616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220572903 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_csr_outstanding.1220572903
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/15.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_errors.3982673845
Short name T443
Test name
Test status
Simulation time 163288973 ps
CPU time 4.11 seconds
Started Oct 02 09:00:47 PM UTC 24
Finished Oct 02 09:00:53 PM UTC 24
Peak memory 226032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982673845 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.3982673845
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/15.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3251462624
Short name T474
Test name
Test status
Simulation time 1999376892 ps
CPU time 22.1 seconds
Started Oct 02 09:00:47 PM UTC 24
Finished Oct 02 09:01:11 PM UTC 24
Peak memory 228036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251462624 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.3251462624
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/15.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1492281446
Short name T448
Test name
Test status
Simulation time 218747647 ps
CPU time 4.14 seconds
Started Oct 02 09:00:51 PM UTC 24
Finished Oct 02 09:00:56 PM UTC 24
Peak memory 230176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=1492281446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_
rand_reset.1492281446
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.945916762
Short name T483
Test name
Test status
Simulation time 34368824781 ps
CPU time 106.37 seconds
Started Oct 02 09:00:49 PM UTC 24
Finished Oct 02 09:02:37 PM UTC 24
Peak memory 215532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945916762 -assert nopostpro
c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_bit_bash.945916762
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2409854879
Short name T442
Test name
Test status
Simulation time 1719164934 ps
CPU time 2.66 seconds
Started Oct 02 09:00:49 PM UTC 24
Finished Oct 02 09:00:52 PM UTC 24
Peak memory 215600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409854879 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.2409854879
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.4005653647
Short name T438
Test name
Test status
Simulation time 144087336 ps
CPU time 1.3 seconds
Started Oct 02 09:00:49 PM UTC 24
Finished Oct 02 09:00:51 PM UTC 24
Peak memory 215312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005653647 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.4005653647
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1079593563
Short name T450
Test name
Test status
Simulation time 192927182 ps
CPU time 5.66 seconds
Started Oct 02 09:00:50 PM UTC 24
Finished Oct 02 09:00:57 PM UTC 24
Peak memory 215636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079593563 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_csr_outstanding.1079593563
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/16.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_errors.1545010994
Short name T453
Test name
Test status
Simulation time 373412648 ps
CPU time 7.36 seconds
Started Oct 02 09:00:50 PM UTC 24
Finished Oct 02 09:00:58 PM UTC 24
Peak memory 225924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545010994 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.1545010994
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/16.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.4211490759
Short name T231
Test name
Test status
Simulation time 2260339821 ps
CPU time 25.7 seconds
Started Oct 02 09:00:50 PM UTC 24
Finished Oct 02 09:01:17 PM UTC 24
Peak memory 232764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211490759 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.4211490759
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/16.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.425285306
Short name T110
Test name
Test status
Simulation time 137418050 ps
CPU time 4.5 seconds
Started Oct 02 09:00:54 PM UTC 24
Finished Oct 02 09:00:59 PM UTC 24
Peak memory 232420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=425285306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_r
and_reset.425285306
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_rw.3916287528
Short name T452
Test name
Test status
Simulation time 602452603 ps
CPU time 2.71 seconds
Started Oct 02 09:00:54 PM UTC 24
Finished Oct 02 09:00:57 PM UTC 24
Peak memory 225904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916287528 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.3916287528
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/17.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3683642604
Short name T482
Test name
Test status
Simulation time 66438072928 ps
CPU time 59.66 seconds
Started Oct 02 09:00:52 PM UTC 24
Finished Oct 02 09:01:54 PM UTC 24
Peak memory 215700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683642604 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_bit_bash.3683642604
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2449779508
Short name T461
Test name
Test status
Simulation time 3420122714 ps
CPU time 8.76 seconds
Started Oct 02 09:00:52 PM UTC 24
Finished Oct 02 09:01:02 PM UTC 24
Peak memory 215616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449779508 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.2449779508
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.4057118040
Short name T445
Test name
Test status
Simulation time 308874342 ps
CPU time 1.9 seconds
Started Oct 02 09:00:51 PM UTC 24
Finished Oct 02 09:00:54 PM UTC 24
Peak memory 215312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057118040 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.4057118040
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1727155267
Short name T462
Test name
Test status
Simulation time 159110840 ps
CPU time 7.56 seconds
Started Oct 02 09:00:54 PM UTC 24
Finished Oct 02 09:01:02 PM UTC 24
Peak memory 215676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727155267 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same_csr_outstanding.1727155267
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/17.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_errors.1573953765
Short name T454
Test name
Test status
Simulation time 1347642362 ps
CPU time 5 seconds
Started Oct 02 09:00:52 PM UTC 24
Finished Oct 02 09:00:59 PM UTC 24
Peak memory 226032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573953765 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.1573953765
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/17.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.541645819
Short name T227
Test name
Test status
Simulation time 4740649330 ps
CPU time 19.72 seconds
Started Oct 02 09:00:53 PM UTC 24
Finished Oct 02 09:01:13 PM UTC 24
Peak memory 232624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541645819 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.541645819
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/17.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.580987375
Short name T460
Test name
Test status
Simulation time 128081412 ps
CPU time 2.81 seconds
Started Oct 02 09:00:58 PM UTC 24
Finished Oct 02 09:01:02 PM UTC 24
Peak memory 227988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=580987375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_r
and_reset.580987375
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_rw.2992073065
Short name T458
Test name
Test status
Simulation time 53810554 ps
CPU time 1.77 seconds
Started Oct 02 09:00:58 PM UTC 24
Finished Oct 02 09:01:01 PM UTC 24
Peak memory 225372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992073065 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.2992073065
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/18.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.3771046113
Short name T479
Test name
Test status
Simulation time 9190763202 ps
CPU time 33.26 seconds
Started Oct 02 09:00:55 PM UTC 24
Finished Oct 02 09:01:30 PM UTC 24
Peak memory 215612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771046113 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_bit_bash.3771046113
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1878824120
Short name T473
Test name
Test status
Simulation time 3092055105 ps
CPU time 14.62 seconds
Started Oct 02 09:00:55 PM UTC 24
Finished Oct 02 09:01:11 PM UTC 24
Peak memory 215604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878824120 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.1878824120
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3573361033
Short name T451
Test name
Test status
Simulation time 174794389 ps
CPU time 1.3 seconds
Started Oct 02 09:00:55 PM UTC 24
Finished Oct 02 09:00:57 PM UTC 24
Peak memory 215312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573361033 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.3573361033
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3738441321
Short name T465
Test name
Test status
Simulation time 1892653308 ps
CPU time 7.3 seconds
Started Oct 02 09:00:58 PM UTC 24
Finished Oct 02 09:01:07 PM UTC 24
Peak memory 215476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738441321 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same_csr_outstanding.3738441321
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/18.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_errors.4064447730
Short name T463
Test name
Test status
Simulation time 4073917710 ps
CPU time 6.83 seconds
Started Oct 02 09:00:56 PM UTC 24
Finished Oct 02 09:01:04 PM UTC 24
Peak memory 226160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064447730 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.4064447730
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/18.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.4003350821
Short name T466
Test name
Test status
Simulation time 89329496 ps
CPU time 4.72 seconds
Started Oct 02 09:01:01 PM UTC 24
Finished Oct 02 09:01:07 PM UTC 24
Peak memory 232640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=4003350821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_
rand_reset.4003350821
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_rw.3955524708
Short name T464
Test name
Test status
Simulation time 411640388 ps
CPU time 2.96 seconds
Started Oct 02 09:01:01 PM UTC 24
Finished Oct 02 09:01:05 PM UTC 24
Peak memory 232048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955524708 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.3955524708
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/19.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.712803324
Short name T480
Test name
Test status
Simulation time 17858290651 ps
CPU time 28.85 seconds
Started Oct 02 09:01:00 PM UTC 24
Finished Oct 02 09:01:30 PM UTC 24
Peak memory 215692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712803324 -assert nopostpro
c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_bit_bash.712803324
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1335174107
Short name T477
Test name
Test status
Simulation time 12359377658 ps
CPU time 13.19 seconds
Started Oct 02 09:01:00 PM UTC 24
Finished Oct 02 09:01:14 PM UTC 24
Peak memory 215692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335174107 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.1335174107
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2960974602
Short name T457
Test name
Test status
Simulation time 405869384 ps
CPU time 1.16 seconds
Started Oct 02 09:00:58 PM UTC 24
Finished Oct 02 09:01:01 PM UTC 24
Peak memory 215312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960974602 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.2960974602
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.985654065
Short name T470
Test name
Test status
Simulation time 341434737 ps
CPU time 7.05 seconds
Started Oct 02 09:01:01 PM UTC 24
Finished Oct 02 09:01:09 PM UTC 24
Peak memory 215536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985654065 -assert nopostproc +UV
M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_csr_outstanding.985654065
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/19.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_errors.1735517006
Short name T471
Test name
Test status
Simulation time 147582663 ps
CPU time 8.29 seconds
Started Oct 02 09:01:00 PM UTC 24
Finished Oct 02 09:01:09 PM UTC 24
Peak memory 225964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735517006 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.1735517006
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/19.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_aliasing.632112732
Short name T146
Test name
Test status
Simulation time 21616094972 ps
CPU time 88.52 seconds
Started Oct 02 08:59:12 PM UTC 24
Finished Oct 02 09:00:43 PM UTC 24
Peak memory 225904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632112732 -asse
rt nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_aliasing.632112732
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/2.rv_dm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.546748021
Short name T425
Test name
Test status
Simulation time 36409849706 ps
CPU time 80.86 seconds
Started Oct 02 08:59:22 PM UTC 24
Finished Oct 02 09:00:45 PM UTC 24
Peak memory 215704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546748021 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.546748021
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/2.rv_dm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1254672315
Short name T130
Test name
Test status
Simulation time 313063728 ps
CPU time 2.29 seconds
Started Oct 02 08:59:21 PM UTC 24
Finished Oct 02 08:59:25 PM UTC 24
Peak memory 225784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254672315 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.1254672315
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/2.rv_dm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3125690867
Short name T354
Test name
Test status
Simulation time 81593531 ps
CPU time 3.52 seconds
Started Oct 02 08:59:24 PM UTC 24
Finished Oct 02 08:59:28 PM UTC 24
Peak memory 230148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=3125690867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_r
and_reset.3125690867
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_rw.2805857961
Short name T131
Test name
Test status
Simulation time 112506534 ps
CPU time 2.46 seconds
Started Oct 02 08:59:21 PM UTC 24
Finished Oct 02 08:59:25 PM UTC 24
Peak memory 225876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805857961 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.2805857961
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/2.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2001159205
Short name T370
Test name
Test status
Simulation time 58808608519 ps
CPU time 35.32 seconds
Started Oct 02 08:59:18 PM UTC 24
Finished Oct 02 08:59:54 PM UTC 24
Peak memory 215608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001159205 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_aliasing.2001159205
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3896575428
Short name T364
Test name
Test status
Simulation time 7813016284 ps
CPU time 24.31 seconds
Started Oct 02 08:59:17 PM UTC 24
Finished Oct 02 08:59:42 PM UTC 24
Peak memory 215620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896575428 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_bit_bash.3896575428
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.268097541
Short name T138
Test name
Test status
Simulation time 11067516448 ps
CPU time 10.91 seconds
Started Oct 02 08:59:17 PM UTC 24
Finished Oct 02 08:59:29 PM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268097541 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_hw_reset.268097541
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1252502726
Short name T352
Test name
Test status
Simulation time 3129536275 ps
CPU time 6.84 seconds
Started Oct 02 08:59:17 PM UTC 24
Finished Oct 02 08:59:25 PM UTC 24
Peak memory 215604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252502726 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1252502726
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.4280799823
Short name T348
Test name
Test status
Simulation time 463999560 ps
CPU time 2.38 seconds
Started Oct 02 08:59:17 PM UTC 24
Finished Oct 02 08:59:20 PM UTC 24
Peak memory 215392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280799823 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_aliasing.4280799823
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3458159405
Short name T358
Test name
Test status
Simulation time 8874431843 ps
CPU time 16.41 seconds
Started Oct 02 08:59:13 PM UTC 24
Finished Oct 02 08:59:31 PM UTC 24
Peak memory 215540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458159405 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_bit_bash.3458159405
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1223553122
Short name T351
Test name
Test status
Simulation time 1404835076 ps
CPU time 7.7 seconds
Started Oct 02 08:59:13 PM UTC 24
Finished Oct 02 08:59:23 PM UTC 24
Peak memory 215392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223553122 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_hw_reset.1223553122
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3173182099
Short name T345
Test name
Test status
Simulation time 426748627 ps
CPU time 2.38 seconds
Started Oct 02 08:59:13 PM UTC 24
Finished Oct 02 08:59:17 PM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173182099 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.3173182099
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_partial_access.707367725
Short name T350
Test name
Test status
Simulation time 40087586 ps
CPU time 1.16 seconds
Started Oct 02 08:59:19 PM UTC 24
Finished Oct 02 08:59:21 PM UTC 24
Peak memory 215380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707367725 -assert nopostproc +UVM_
TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_partial_access.707367725
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/2.rv_dm_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_walk.3545644917
Short name T349
Test name
Test status
Simulation time 46170399 ps
CPU time 0.87 seconds
Started Oct 02 08:59:19 PM UTC 24
Finished Oct 02 08:59:21 PM UTC 24
Peak memory 214864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545644917 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.3545644917
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/2.rv_dm_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.122450576
Short name T132
Test name
Test status
Simulation time 607840569 ps
CPU time 7.64 seconds
Started Oct 02 08:59:22 PM UTC 24
Finished Oct 02 08:59:31 PM UTC 24
Peak memory 215732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122450576 -assert nopostproc +UV
M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_csr_outstanding.122450576
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/2.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.1165602605
Short name T105
Test name
Test status
Simulation time 7212098839 ps
CPU time 58.93 seconds
Started Oct 02 08:59:18 PM UTC 24
Finished Oct 02 09:00:18 PM UTC 24
Peak memory 232724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=1165602605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_re
set.1165602605
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_errors.1890177128
Short name T353
Test name
Test status
Simulation time 105577827 ps
CPU time 5.64 seconds
Started Oct 02 08:59:18 PM UTC 24
Finished Oct 02 08:59:25 PM UTC 24
Peak memory 225980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890177128 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.1890177128
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/2.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1027842951
Short name T182
Test name
Test status
Simulation time 4257891354 ps
CPU time 21 seconds
Started Oct 02 08:59:19 PM UTC 24
Finished Oct 02 08:59:41 PM UTC 24
Peak memory 227756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027842951 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.1027842951
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/2.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1299125287
Short name T155
Test name
Test status
Simulation time 4370709228 ps
CPU time 72.34 seconds
Started Oct 02 08:59:26 PM UTC 24
Finished Oct 02 09:00:40 PM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299125287 -ass
ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_aliasing.1299125287
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/3.rv_dm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3515585366
Short name T392
Test name
Test status
Simulation time 5839504352 ps
CPU time 40.79 seconds
Started Oct 02 08:59:35 PM UTC 24
Finished Oct 02 09:00:17 PM UTC 24
Peak memory 225868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515585366 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.3515585366
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/3.rv_dm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3261825676
Short name T149
Test name
Test status
Simulation time 555078630 ps
CPU time 3.83 seconds
Started Oct 02 08:59:35 PM UTC 24
Finished Oct 02 08:59:40 PM UTC 24
Peak memory 225872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261825676 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.3261825676
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/3.rv_dm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.4286026597
Short name T367
Test name
Test status
Simulation time 61937583 ps
CPU time 5.35 seconds
Started Oct 02 08:59:36 PM UTC 24
Finished Oct 02 08:59:42 PM UTC 24
Peak memory 230176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=4286026597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_r
and_reset.4286026597
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_rw.3992603383
Short name T133
Test name
Test status
Simulation time 211794664 ps
CPU time 2.44 seconds
Started Oct 02 08:59:35 PM UTC 24
Finished Oct 02 08:59:38 PM UTC 24
Peak memory 225724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992603383 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.3992603383
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/3.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3556834495
Short name T365
Test name
Test status
Simulation time 22045534609 ps
CPU time 23.96 seconds
Started Oct 02 08:59:29 PM UTC 24
Finished Oct 02 08:59:54 PM UTC 24
Peak memory 215536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556834495 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_aliasing.3556834495
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1599804697
Short name T381
Test name
Test status
Simulation time 46215782019 ps
CPU time 37.49 seconds
Started Oct 02 08:59:29 PM UTC 24
Finished Oct 02 09:00:08 PM UTC 24
Peak memory 215540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599804697 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_bit_bash.1599804697
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3633612407
Short name T361
Test name
Test status
Simulation time 2685864754 ps
CPU time 6.28 seconds
Started Oct 02 08:59:29 PM UTC 24
Finished Oct 02 08:59:36 PM UTC 24
Peak memory 215604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633612407 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.3633612407
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3750295198
Short name T356
Test name
Test status
Simulation time 971450551 ps
CPU time 2.01 seconds
Started Oct 02 08:59:26 PM UTC 24
Finished Oct 02 08:59:29 PM UTC 24
Peak memory 215320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750295198 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_aliasing.3750295198
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1838981848
Short name T362
Test name
Test status
Simulation time 4267020399 ps
CPU time 12.78 seconds
Started Oct 02 08:59:26 PM UTC 24
Finished Oct 02 08:59:40 PM UTC 24
Peak memory 215324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838981848 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_bit_bash.1838981848
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3239759369
Short name T355
Test name
Test status
Simulation time 667597848 ps
CPU time 2.02 seconds
Started Oct 02 08:59:26 PM UTC 24
Finished Oct 02 08:59:29 PM UTC 24
Peak memory 215392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239759369 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_hw_reset.3239759369
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1734633562
Short name T357
Test name
Test status
Simulation time 335907736 ps
CPU time 2.2 seconds
Started Oct 02 08:59:26 PM UTC 24
Finished Oct 02 08:59:29 PM UTC 24
Peak memory 215388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734633562 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.1734633562
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3654768690
Short name T359
Test name
Test status
Simulation time 97239189 ps
CPU time 1.09 seconds
Started Oct 02 08:59:32 PM UTC 24
Finished Oct 02 08:59:34 PM UTC 24
Peak memory 215376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654768690 -assert nopostproc +UVM
_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_partial_access.3654768690
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/3.rv_dm_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_walk.2611728217
Short name T360
Test name
Test status
Simulation time 47563527 ps
CPU time 1.13 seconds
Started Oct 02 08:59:32 PM UTC 24
Finished Oct 02 08:59:34 PM UTC 24
Peak memory 215316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611728217 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.2611728217
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/3.rv_dm_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2175119804
Short name T157
Test name
Test status
Simulation time 506147603 ps
CPU time 12.3 seconds
Started Oct 02 08:59:36 PM UTC 24
Finished Oct 02 08:59:49 PM UTC 24
Peak memory 215480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175119804 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_csr_outstanding.2175119804
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/3.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3940152088
Short name T430
Test name
Test status
Simulation time 2981216932 ps
CPU time 74.18 seconds
Started Oct 02 08:59:30 PM UTC 24
Finished Oct 02 09:00:46 PM UTC 24
Peak memory 226012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3940152088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_re
set.3940152088
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_errors.802361236
Short name T170
Test name
Test status
Simulation time 884939911 ps
CPU time 7.26 seconds
Started Oct 02 08:59:30 PM UTC 24
Finished Oct 02 08:59:39 PM UTC 24
Peak memory 225928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802361236 -assert nopostproc +UVM_TESTNAME=rv_dm_base
_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_d
m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.802361236
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/3.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2577158713
Short name T224
Test name
Test status
Simulation time 4756849358 ps
CPU time 20.4 seconds
Started Oct 02 08:59:31 PM UTC 24
Finished Oct 02 08:59:52 PM UTC 24
Peak memory 228084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577158713 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.2577158713
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/3.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_aliasing.903160248
Short name T153
Test name
Test status
Simulation time 18920206950 ps
CPU time 37.65 seconds
Started Oct 02 08:59:37 PM UTC 24
Finished Oct 02 09:00:16 PM UTC 24
Peak memory 215764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903160248 -asse
rt nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_aliasing.903160248
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/4.rv_dm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.837827183
Short name T406
Test name
Test status
Simulation time 14491254873 ps
CPU time 37.31 seconds
Started Oct 02 08:59:56 PM UTC 24
Finished Oct 02 09:00:34 PM UTC 24
Peak memory 215632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837827183 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.837827183
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/4.rv_dm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.823974131
Short name T150
Test name
Test status
Simulation time 227863342 ps
CPU time 3.47 seconds
Started Oct 02 08:59:53 PM UTC 24
Finished Oct 02 08:59:58 PM UTC 24
Peak memory 225880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823974131 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.823974131
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/4.rv_dm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.4249798030
Short name T376
Test name
Test status
Simulation time 199639136 ps
CPU time 5.4 seconds
Started Oct 02 08:59:57 PM UTC 24
Finished Oct 02 09:00:03 PM UTC 24
Peak memory 225848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=4249798030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_r
and_reset.4249798030
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_rw.1503737403
Short name T151
Test name
Test status
Simulation time 236434134 ps
CPU time 3.38 seconds
Started Oct 02 08:59:53 PM UTC 24
Finished Oct 02 08:59:58 PM UTC 24
Peak memory 225780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503737403 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.1503737403
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/4.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2678415353
Short name T456
Test name
Test status
Simulation time 43117765384 ps
CPU time 74.72 seconds
Started Oct 02 08:59:43 PM UTC 24
Finished Oct 02 09:01:00 PM UTC 24
Peak memory 215608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678415353 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_aliasing.2678415353
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.270505692
Short name T372
Test name
Test status
Simulation time 3320517589 ps
CPU time 11.36 seconds
Started Oct 02 08:59:43 PM UTC 24
Finished Oct 02 08:59:56 PM UTC 24
Peak memory 215616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270505692 -assert nopostpro
c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_bit_bash.270505692
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2494754950
Short name T140
Test name
Test status
Simulation time 9539533579 ps
CPU time 34.16 seconds
Started Oct 02 08:59:41 PM UTC 24
Finished Oct 02 09:00:16 PM UTC 24
Peak memory 215632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494754950 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_hw_reset.2494754950
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.4253668515
Short name T380
Test name
Test status
Simulation time 6865610327 ps
CPU time 21.64 seconds
Started Oct 02 08:59:43 PM UTC 24
Finished Oct 02 09:00:06 PM UTC 24
Peak memory 215532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253668515 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.4253668515
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1641564633
Short name T373
Test name
Test status
Simulation time 2542213212 ps
CPU time 15.13 seconds
Started Oct 02 08:59:41 PM UTC 24
Finished Oct 02 08:59:57 PM UTC 24
Peak memory 215444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641564633 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_aliasing.1641564633
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.390684942
Short name T416
Test name
Test status
Simulation time 17727454162 ps
CPU time 58.49 seconds
Started Oct 02 08:59:40 PM UTC 24
Finished Oct 02 09:00:41 PM UTC 24
Peak memory 215604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390684942 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_bit_bash.390684942
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3903362541
Short name T363
Test name
Test status
Simulation time 229421573 ps
CPU time 1.41 seconds
Started Oct 02 08:59:39 PM UTC 24
Finished Oct 02 08:59:42 PM UTC 24
Peak memory 215320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903362541 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_hw_reset.3903362541
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2350082656
Short name T366
Test name
Test status
Simulation time 754605829 ps
CPU time 1.73 seconds
Started Oct 02 08:59:39 PM UTC 24
Finished Oct 02 08:59:42 PM UTC 24
Peak memory 215316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350082656 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.2350082656
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1508408822
Short name T371
Test name
Test status
Simulation time 118209491 ps
CPU time 1.11 seconds
Started Oct 02 08:59:53 PM UTC 24
Finished Oct 02 08:59:55 PM UTC 24
Peak memory 215376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508408822 -assert nopostproc +UVM
_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_partial_access.1508408822
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/4.rv_dm_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_walk.3305334968
Short name T369
Test name
Test status
Simulation time 35110761 ps
CPU time 1.14 seconds
Started Oct 02 08:59:50 PM UTC 24
Finished Oct 02 08:59:52 PM UTC 24
Peak memory 215316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305334968 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.3305334968
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/4.rv_dm_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1833435412
Short name T158
Test name
Test status
Simulation time 826844556 ps
CPU time 5.74 seconds
Started Oct 02 08:59:56 PM UTC 24
Finished Oct 02 09:00:02 PM UTC 24
Peak memory 215472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833435412 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_csr_outstanding.1833435412
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/4.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3899319817
Short name T431
Test name
Test status
Simulation time 4505817995 ps
CPU time 61.3 seconds
Started Oct 02 08:59:43 PM UTC 24
Finished Oct 02 09:00:47 PM UTC 24
Peak memory 226096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3899319817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_re
set.3899319817
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_errors.1225232295
Short name T368
Test name
Test status
Simulation time 161071867 ps
CPU time 3.79 seconds
Started Oct 02 08:59:44 PM UTC 24
Finished Oct 02 08:59:50 PM UTC 24
Peak memory 225912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225232295 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.1225232295
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/4.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3354449006
Short name T223
Test name
Test status
Simulation time 2108336727 ps
CPU time 12.47 seconds
Started Oct 02 08:59:50 PM UTC 24
Finished Oct 02 09:00:04 PM UTC 24
Peak memory 232528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354449006 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.3354449006
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/4.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1017827617
Short name T385
Test name
Test status
Simulation time 99650770 ps
CPU time 4.61 seconds
Started Oct 02 09:00:06 PM UTC 24
Finished Oct 02 09:00:12 PM UTC 24
Peak memory 231956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=1017827617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_r
and_reset.1017827617
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_rw.2456752697
Short name T384
Test name
Test status
Simulation time 203496093 ps
CPU time 2.49 seconds
Started Oct 02 09:00:06 PM UTC 24
Finished Oct 02 09:00:10 PM UTC 24
Peak memory 225744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456752697 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.2456752697
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/5.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3770598255
Short name T383
Test name
Test status
Simulation time 3355415344 ps
CPU time 10.72 seconds
Started Oct 02 08:59:58 PM UTC 24
Finished Oct 02 09:00:10 PM UTC 24
Peak memory 215604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770598255 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_bit_bash.3770598255
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3556978059
Short name T375
Test name
Test status
Simulation time 6372980455 ps
CPU time 5.25 seconds
Started Oct 02 08:59:57 PM UTC 24
Finished Oct 02 09:00:03 PM UTC 24
Peak memory 215592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556978059 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.3556978059
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1376043008
Short name T374
Test name
Test status
Simulation time 115537379 ps
CPU time 1.1 seconds
Started Oct 02 08:59:57 PM UTC 24
Finished Oct 02 08:59:59 PM UTC 24
Peak memory 215316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376043008 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.1376043008
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.540199489
Short name T159
Test name
Test status
Simulation time 127385586 ps
CPU time 3.68 seconds
Started Oct 02 09:00:06 PM UTC 24
Finished Oct 02 09:00:11 PM UTC 24
Peak memory 215528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540199489 -assert nopostproc +UV
M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_csr_outstanding.540199489
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/5.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_errors.1121610066
Short name T377
Test name
Test status
Simulation time 678720329 ps
CPU time 3.61 seconds
Started Oct 02 08:59:59 PM UTC 24
Finished Oct 02 09:00:04 PM UTC 24
Peak memory 225912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121610066 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.1121610066
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/5.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1270542093
Short name T113
Test name
Test status
Simulation time 192886839 ps
CPU time 4 seconds
Started Oct 02 09:00:11 PM UTC 24
Finished Oct 02 09:00:16 PM UTC 24
Peak memory 225836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=1270542093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_r
and_reset.1270542093
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_rw.1894860339
Short name T152
Test name
Test status
Simulation time 276097808 ps
CPU time 2.6 seconds
Started Oct 02 09:00:09 PM UTC 24
Finished Oct 02 09:00:13 PM UTC 24
Peak memory 225756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894860339 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.1894860339
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/6.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3246798436
Short name T476
Test name
Test status
Simulation time 39354906285 ps
CPU time 65.24 seconds
Started Oct 02 09:00:07 PM UTC 24
Finished Oct 02 09:01:14 PM UTC 24
Peak memory 215756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246798436 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_bit_bash.3246798436
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1956505016
Short name T386
Test name
Test status
Simulation time 3255899996 ps
CPU time 4.59 seconds
Started Oct 02 09:00:07 PM UTC 24
Finished Oct 02 09:00:12 PM UTC 24
Peak memory 215756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956505016 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.1956505016
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.4053257531
Short name T382
Test name
Test status
Simulation time 97443820 ps
CPU time 1.31 seconds
Started Oct 02 09:00:06 PM UTC 24
Finished Oct 02 09:00:09 PM UTC 24
Peak memory 214512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053257531 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.4053257531
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2392757
Short name T160
Test name
Test status
Simulation time 242399750 ps
CPU time 6.18 seconds
Started Oct 02 09:00:10 PM UTC 24
Finished Oct 02 09:00:17 PM UTC 24
Peak memory 215604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392757 -assert nopostproc +UVM_
TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_csr_outstanding.2392757
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/6.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3246110640
Short name T179
Test name
Test status
Simulation time 586270365 ps
CPU time 12.33 seconds
Started Oct 02 09:00:08 PM UTC 24
Finished Oct 02 09:00:21 PM UTC 24
Peak memory 225888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3246110640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_re
set.3246110640
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_errors.23810022
Short name T389
Test name
Test status
Simulation time 3333513810 ps
CPU time 5.71 seconds
Started Oct 02 09:00:08 PM UTC 24
Finished Oct 02 09:00:14 PM UTC 24
Peak memory 226108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23810022 -assert nopostproc +UVM_TESTNAME=rv_dm_base_
test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.23810022
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/6.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_intg_err.170585807
Short name T222
Test name
Test status
Simulation time 6741181649 ps
CPU time 20.08 seconds
Started Oct 02 09:00:09 PM UTC 24
Finished Oct 02 09:00:30 PM UTC 24
Peak memory 232676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170585807 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.170585807
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/6.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1273628844
Short name T397
Test name
Test status
Simulation time 54593964 ps
CPU time 5.2 seconds
Started Oct 02 09:00:17 PM UTC 24
Finished Oct 02 09:00:23 PM UTC 24
Peak memory 232428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=1273628844 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_r
and_reset.1273628844
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_rw.3797212438
Short name T143
Test name
Test status
Simulation time 50616629 ps
CPU time 3.1 seconds
Started Oct 02 09:00:15 PM UTC 24
Finished Oct 02 09:00:19 PM UTC 24
Peak memory 231996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797212438 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.3797212438
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/7.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1978027389
Short name T481
Test name
Test status
Simulation time 37499348313 ps
CPU time 96.64 seconds
Started Oct 02 09:00:13 PM UTC 24
Finished Oct 02 09:01:52 PM UTC 24
Peak memory 215692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978027389 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_bit_bash.1978027389
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3768769792
Short name T391
Test name
Test status
Simulation time 1912266487 ps
CPU time 3.79 seconds
Started Oct 02 09:00:12 PM UTC 24
Finished Oct 02 09:00:17 PM UTC 24
Peak memory 215604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768769792 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.3768769792
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.776431220
Short name T388
Test name
Test status
Simulation time 162955943 ps
CPU time 1.66 seconds
Started Oct 02 09:00:11 PM UTC 24
Finished Oct 02 09:00:14 PM UTC 24
Peak memory 215320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776431220 -assert nopostproc +UVM_TESTNAME=rv_dm_b
ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.776431220
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2655196205
Short name T161
Test name
Test status
Simulation time 382236208 ps
CPU time 4.92 seconds
Started Oct 02 09:00:16 PM UTC 24
Finished Oct 02 09:00:22 PM UTC 24
Peak memory 215472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655196205 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_csr_outstanding.2655196205
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/7.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.3375288730
Short name T469
Test name
Test status
Simulation time 7054683238 ps
CPU time 52.87 seconds
Started Oct 02 09:00:13 PM UTC 24
Finished Oct 02 09:01:08 PM UTC 24
Peak memory 228076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3375288730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_re
set.3375288730
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_errors.1805853820
Short name T394
Test name
Test status
Simulation time 204462266 ps
CPU time 5.28 seconds
Started Oct 02 09:00:13 PM UTC 24
Finished Oct 02 09:00:20 PM UTC 24
Peak memory 225916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805853820 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.1805853820
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/7.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_intg_err.4256907110
Short name T220
Test name
Test status
Simulation time 2223846781 ps
CPU time 26.58 seconds
Started Oct 02 09:00:15 PM UTC 24
Finished Oct 02 09:00:42 PM UTC 24
Peak memory 232736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256907110 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.4256907110
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/7.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.126121424
Short name T180
Test name
Test status
Simulation time 186300342 ps
CPU time 4.99 seconds
Started Oct 02 09:00:20 PM UTC 24
Finished Oct 02 09:00:26 PM UTC 24
Peak memory 230040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=126121424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_ra
nd_reset.126121424
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_rw.2282182101
Short name T156
Test name
Test status
Simulation time 104121590 ps
CPU time 3.39 seconds
Started Oct 02 09:00:19 PM UTC 24
Finished Oct 02 09:00:24 PM UTC 24
Peak memory 229948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282182101 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.2282182101
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/8.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1326171489
Short name T402
Test name
Test status
Simulation time 10157585729 ps
CPU time 12.83 seconds
Started Oct 02 09:00:17 PM UTC 24
Finished Oct 02 09:00:31 PM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326171489 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_bit_bash.1326171489
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.2639302705
Short name T398
Test name
Test status
Simulation time 6078045365 ps
CPU time 10.98 seconds
Started Oct 02 09:00:17 PM UTC 24
Finished Oct 02 09:00:29 PM UTC 24
Peak memory 215632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639302705 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.2639302705
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2825087569
Short name T393
Test name
Test status
Simulation time 123109915 ps
CPU time 1.39 seconds
Started Oct 02 09:00:17 PM UTC 24
Finished Oct 02 09:00:19 PM UTC 24
Peak memory 215316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825087569 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.2825087569
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1184728137
Short name T144
Test name
Test status
Simulation time 663201464 ps
CPU time 5.03 seconds
Started Oct 02 09:00:19 PM UTC 24
Finished Oct 02 09:00:25 PM UTC 24
Peak memory 215508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184728137 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_csr_outstanding.1184728137
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/8.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1816132988
Short name T114
Test name
Test status
Simulation time 7214316973 ps
CPU time 42.39 seconds
Started Oct 02 09:00:18 PM UTC 24
Finished Oct 02 09:01:02 PM UTC 24
Peak memory 226160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=1816132988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_re
set.1816132988
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_errors.4002823719
Short name T395
Test name
Test status
Simulation time 202142262 ps
CPU time 3.51 seconds
Started Oct 02 09:00:18 PM UTC 24
Finished Oct 02 09:00:23 PM UTC 24
Peak memory 226128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002823719 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.4002823719
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/8.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1553005712
Short name T219
Test name
Test status
Simulation time 4544666917 ps
CPU time 15.8 seconds
Started Oct 02 09:00:18 PM UTC 24
Finished Oct 02 09:00:35 PM UTC 24
Peak memory 226192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553005712 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.1553005712
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/8.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1516695568
Short name T404
Test name
Test status
Simulation time 116930287 ps
CPU time 4.47 seconds
Started Oct 02 09:00:26 PM UTC 24
Finished Oct 02 09:00:32 PM UTC 24
Peak memory 228036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc
b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=1516695568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_r
and_reset.1516695568
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_rw.4281971684
Short name T400
Test name
Test status
Simulation time 1744664318 ps
CPU time 4.85 seconds
Started Oct 02 09:00:24 PM UTC 24
Finished Oct 02 09:00:30 PM UTC 24
Peak memory 225880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281971684 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.4281971684
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/9.rv_dm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2098816961
Short name T436
Test name
Test status
Simulation time 6721799806 ps
CPU time 25.87 seconds
Started Oct 02 09:00:23 PM UTC 24
Finished Oct 02 09:00:50 PM UTC 24
Peak memory 215536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098816961 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_bit_bash.2098816961
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3560150179
Short name T405
Test name
Test status
Simulation time 4511562473 ps
CPU time 8.56 seconds
Started Oct 02 09:00:23 PM UTC 24
Finished Oct 02 09:00:32 PM UTC 24
Peak memory 215532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560150179 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.3560150179
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2663349501
Short name T396
Test name
Test status
Simulation time 100798999 ps
CPU time 1.21 seconds
Started Oct 02 09:00:20 PM UTC 24
Finished Oct 02 09:00:23 PM UTC 24
Peak memory 215316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663349501 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.2663349501
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1918762149
Short name T145
Test name
Test status
Simulation time 10270834749 ps
CPU time 12.6 seconds
Started Oct 02 09:00:25 PM UTC 24
Finished Oct 02 09:00:39 PM UTC 24
Peak memory 215760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918762149 -assert nopostproc +U
VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_csr_outstanding.1918762149
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/9.rv_dm_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.352522757
Short name T106
Test name
Test status
Simulation time 7279480545 ps
CPU time 33.21 seconds
Started Oct 02 09:00:24 PM UTC 24
Finished Oct 02 09:00:58 PM UTC 24
Peak memory 228016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_
scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=352522757 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.352522757
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_errors.1128850660
Short name T399
Test name
Test status
Simulation time 161171018 ps
CPU time 4.4 seconds
Started Oct 02 09:00:24 PM UTC 24
Finished Oct 02 09:00:29 PM UTC 24
Peak memory 225696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128850660 -assert nopostproc +UVM_TESTNAME=rv_dm_bas
e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_
dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.1128850660
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/9.rv_dm_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1068298149
Short name T225
Test name
Test status
Simulation time 942792525 ps
CPU time 10.55 seconds
Started Oct 02 09:00:24 PM UTC 24
Finished Oct 02 09:00:35 PM UTC 24
Peak memory 226008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068298149 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.1068298149
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/9.rv_dm_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.617283171
Short name T45
Test name
Test status
Simulation time 508552752 ps
CPU time 3.16 seconds
Started Oct 02 09:01:12 PM UTC 24
Finished Oct 02 09:01:16 PM UTC 24
Peak memory 258136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617283171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_buffered_enable.617283171
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.645204246
Short name T12
Test name
Test status
Simulation time 202980034 ps
CPU time 1.45 seconds
Started Oct 02 09:01:06 PM UTC 24
Finished Oct 02 09:01:08 PM UTC 24
Peak memory 215336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645204246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_cmderr_exception_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.645204246
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_cmderr_exception/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.1937233552
Short name T41
Test name
Test status
Simulation time 414997219 ps
CPU time 1.85 seconds
Started Oct 02 09:01:08 PM UTC 24
Finished Oct 02 09:01:11 PM UTC 24
Peak memory 215332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937233552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.1937233552
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_cmderr_halt_resume/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.2282138041
Short name T2
Test name
Test status
Simulation time 149001483 ps
CPU time 1.1 seconds
Started Oct 02 09:01:04 PM UTC 24
Finished Oct 02 09:01:07 PM UTC 24
Peak memory 215332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282138041 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.2282138041
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_cmderr_not_supported/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_dataaddr_rw_access.1924167061
Short name T8
Test name
Test status
Simulation time 317362229 ps
CPU time 1.94 seconds
Started Oct 02 09:01:09 PM UTC 24
Finished Oct 02 09:01:12 PM UTC 24
Peak memory 215332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924167061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.1924167061
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_dataaddr_rw_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_debug_disabled.124362810
Short name T88
Test name
Test status
Simulation time 47657743 ps
CPU time 1.38 seconds
Started Oct 02 09:01:11 PM UTC 24
Finished Oct 02 09:01:13 PM UTC 24
Peak memory 237120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124362810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.124362810
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_debug_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.3720909665
Short name T46
Test name
Test status
Simulation time 449974366 ps
CPU time 1.39 seconds
Started Oct 02 09:01:09 PM UTC 24
Finished Oct 02 09:01:12 PM UTC 24
Peak memory 215328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720909665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.3720909665
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_halt_resume_whereto/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_hartsel_warl.1910468164
Short name T29
Test name
Test status
Simulation time 269141552 ps
CPU time 1.06 seconds
Started Oct 02 09:01:12 PM UTC 24
Finished Oct 02 09:01:14 PM UTC 24
Peak memory 215328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910468164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.1910468164
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_hartsel_warl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.353660194
Short name T7
Test name
Test status
Simulation time 820274471 ps
CPU time 1.38 seconds
Started Oct 02 09:01:09 PM UTC 24
Finished Oct 02 09:01:12 PM UTC 24
Peak memory 215336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353660194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.353660194
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1354671296
Short name T16
Test name
Test status
Simulation time 1105030265 ps
CPU time 4.68 seconds
Started Oct 02 09:01:09 PM UTC 24
Finished Oct 02 09:01:15 PM UTC 24
Peak memory 215468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354671296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.1354671296
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_hard_reset.3569168512
Short name T6
Test name
Test status
Simulation time 121291107 ps
CPU time 1.27 seconds
Started Oct 02 09:01:09 PM UTC 24
Finished Oct 02 09:01:12 PM UTC 24
Peak memory 215332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569168512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.3569168512
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_idle_hint.4030938044
Short name T25
Test name
Test status
Simulation time 238815373 ps
CPU time 1.39 seconds
Started Oct 02 09:01:09 PM UTC 24
Finished Oct 02 09:01:12 PM UTC 24
Peak memory 215332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030938044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.4030938044
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_halted.4023114287
Short name T13
Test name
Test status
Simulation time 626581101 ps
CPU time 1.51 seconds
Started Oct 02 09:01:06 PM UTC 24
Finished Oct 02 09:01:08 PM UTC 24
Peak memory 215332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023114287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.4023114287
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_halted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_resuming.3463243168
Short name T5
Test name
Test status
Simulation time 117044517 ps
CPU time 1.64 seconds
Started Oct 02 09:01:08 PM UTC 24
Finished Oct 02 09:01:11 PM UTC 24
Peak memory 215336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463243168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.3463243168
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.1998803133
Short name T62
Test name
Test status
Simulation time 228748666 ps
CPU time 1.9 seconds
Started Oct 02 09:01:11 PM UTC 24
Finished Oct 02 09:01:14 PM UTC 24
Peak memory 215336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998803133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_progbuf_read_write_execute_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_d
m-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.1998803133
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_tl_access.621589781
Short name T3
Test name
Test status
Simulation time 2098006931 ps
CPU time 4.13 seconds
Started Oct 02 09:01:02 PM UTC 24
Finished Oct 02 09:01:07 PM UTC 24
Peak memory 216044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621589781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.621589781
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_smoke.3634977572
Short name T1
Test name
Test status
Simulation time 627496084 ps
CPU time 1.97 seconds
Started Oct 02 09:01:02 PM UTC 24
Finished Oct 02 09:01:05 PM UTC 24
Peak memory 214876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634977572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.3634977572
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.2760639153
Short name T111
Test name
Test status
Simulation time 2392961462 ps
CPU time 63.23 seconds
Started Oct 02 09:01:13 PM UTC 24
Finished Oct 02 09:02:18 PM UTC 24
Peak memory 232932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=2760639153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stres
s_all_with_rand_reset.2760639153
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_abstractcmd_status.1528221982
Short name T65
Test name
Test status
Simulation time 77497615 ps
CPU time 1.17 seconds
Started Oct 02 09:01:18 PM UTC 24
Finished Oct 02 09:01:20 PM UTC 24
Peak memory 215332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528221982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_abstractcmd_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.1528221982
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_abstractcmd_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_alert_test.2544281509
Short name T52
Test name
Test status
Simulation time 35117193 ps
CPU time 1.27 seconds
Started Oct 02 09:01:19 PM UTC 24
Finished Oct 02 09:01:22 PM UTC 24
Peak memory 215204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544281509 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.2544281509
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_autoincr_sba_tl_access.2685870770
Short name T23
Test name
Test status
Simulation time 6054279028 ps
CPU time 14.2 seconds
Started Oct 02 09:01:15 PM UTC 24
Finished Oct 02 09:01:30 PM UTC 24
Peak memory 216028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685870770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.2685870770
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_buffered_enable.3070987922
Short name T84
Test name
Test status
Simulation time 124200221 ps
CPU time 1.26 seconds
Started Oct 02 09:01:19 PM UTC 24
Finished Oct 02 09:01:21 PM UTC 24
Peak memory 257140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070987922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_buffered_enable.3070987922
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_busy.99254630
Short name T9
Test name
Test status
Simulation time 191546392 ps
CPU time 1.66 seconds
Started Oct 02 09:01:15 PM UTC 24
Finished Oct 02 09:01:17 PM UTC 24
Peak memory 215340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99254630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv
_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.99254630
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_cmderr_busy/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_not_supported.1250145620
Short name T55
Test name
Test status
Simulation time 171571561 ps
CPU time 1.9 seconds
Started Oct 02 09:01:15 PM UTC 24
Finished Oct 02 09:01:18 PM UTC 24
Peak memory 215320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250145620 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.1250145620
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_cmderr_not_supported/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_dataaddr_rw_access.2957656031
Short name T42
Test name
Test status
Simulation time 172329883 ps
CPU time 1.21 seconds
Started Oct 02 09:01:15 PM UTC 24
Finished Oct 02 09:01:17 PM UTC 24
Peak memory 215332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957656031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.2957656031
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_dataaddr_rw_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_debug_disabled.3906174881
Short name T91
Test name
Test status
Simulation time 125132606 ps
CPU time 1.78 seconds
Started Oct 02 09:01:19 PM UTC 24
Finished Oct 02 09:01:22 PM UTC 24
Peak memory 236404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906174881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.3906174881
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_debug_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.594377223
Short name T87
Test name
Test status
Simulation time 4816804202 ps
CPU time 6.37 seconds
Started Oct 02 09:01:14 PM UTC 24
Finished Oct 02 09:01:21 PM UTC 24
Peak memory 226484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594377223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_tl_access.594377223
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.1624054176
Short name T75
Test name
Test status
Simulation time 327236505 ps
CPU time 1.32 seconds
Started Oct 02 09:01:19 PM UTC 24
Finished Oct 02 09:01:21 PM UTC 24
Peak memory 215340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624054176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.1624054176
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_dmi_failed_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_hart_unavail.3508279433
Short name T97
Test name
Test status
Simulation time 97582953 ps
CPU time 1.33 seconds
Started Oct 02 09:01:15 PM UTC 24
Finished Oct 02 09:01:17 PM UTC 24
Peak memory 215328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508279433 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.3508279433
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_hart_unavail/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.418650897
Short name T92
Test name
Test status
Simulation time 725924338 ps
CPU time 5.28 seconds
Started Oct 02 09:01:18 PM UTC 24
Finished Oct 02 09:01:24 PM UTC 24
Peak memory 215796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418650897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.418650897
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1129775419
Short name T266
Test name
Test status
Simulation time 898999593 ps
CPU time 2.03 seconds
Started Oct 02 09:01:16 PM UTC 24
Finished Oct 02 09:01:20 PM UTC 24
Peak memory 215656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129775419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.1129775419
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_idle_hint.215469692
Short name T78
Test name
Test status
Simulation time 265195616 ps
CPU time 0.94 seconds
Started Oct 02 09:01:16 PM UTC 24
Finished Oct 02 09:01:18 PM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215469692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.215469692
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_halted.3258899502
Short name T96
Test name
Test status
Simulation time 193834347 ps
CPU time 1.62 seconds
Started Oct 02 09:01:15 PM UTC 24
Finished Oct 02 09:01:17 PM UTC 24
Peak memory 215332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258899502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.3258899502
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_mem_tl_access_halted/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_resuming.4039384157
Short name T30
Test name
Test status
Simulation time 775904023 ps
CPU time 1.85 seconds
Started Oct 02 09:01:15 PM UTC 24
Finished Oct 02 09:01:18 PM UTC 24
Peak memory 215336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039384157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.4039384157
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_ndmreset_req.760847677
Short name T43
Test name
Test status
Simulation time 162999729 ps
CPU time 1.27 seconds
Started Oct 02 09:01:16 PM UTC 24
Finished Oct 02 09:01:19 PM UTC 24
Peak memory 225192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760847677 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.760847677
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_ndmreset_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_progbuf_read_write_execute.2507524800
Short name T63
Test name
Test status
Simulation time 183150650 ps
CPU time 1.67 seconds
Started Oct 02 09:01:19 PM UTC 24
Finished Oct 02 09:01:22 PM UTC 24
Peak memory 215336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507524800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_progbuf_read_write_execute_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_d
m-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.2507524800
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_rom_read_access.1488273019
Short name T67
Test name
Test status
Simulation time 85321834 ps
CPU time 1.31 seconds
Started Oct 02 09:01:19 PM UTC 24
Finished Oct 02 09:01:21 PM UTC 24
Peak memory 225132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488273019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_rom_read_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.1488273019
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_rom_read_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_debug_disabled.3497777248
Short name T166
Test name
Test status
Simulation time 3766562713 ps
CPU time 3.86 seconds
Started Oct 02 09:01:16 PM UTC 24
Finished Oct 02 09:01:21 PM UTC 24
Peak memory 215936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497777248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.3497777248
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_sba_debug_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_tl_access.314055456
Short name T251
Test name
Test status
Simulation time 7528008384 ps
CPU time 22.78 seconds
Started Oct 02 09:01:13 PM UTC 24
Finished Oct 02 09:01:38 PM UTC 24
Peak memory 216160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314055456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.314055456
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_sec_cm.3352044674
Short name T89
Test name
Test status
Simulation time 1185501408 ps
CPU time 3.5 seconds
Started Oct 02 09:01:19 PM UTC 24
Finished Oct 02 09:01:24 PM UTC 24
Peak memory 256132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352044674 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.3352044674
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_smoke.4172595462
Short name T80
Test name
Test status
Simulation time 1321461431 ps
CPU time 5.12 seconds
Started Oct 02 09:01:13 PM UTC 24
Finished Oct 02 09:01:20 PM UTC 24
Peak memory 215596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172595462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.4172595462
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.1553640266
Short name T54
Test name
Test status
Simulation time 320129313 ps
CPU time 1.27 seconds
Started Oct 02 09:01:19 PM UTC 24
Finished Oct 02 09:01:22 PM UTC 24
Peak memory 225192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553640266 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sparse_lc_gate_fsm.1553640266
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_sparse_lc_gate_fsm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.3941433775
Short name T93
Test name
Test status
Simulation time 3647008853 ps
CPU time 21.74 seconds
Started Oct 02 09:01:19 PM UTC 24
Finished Oct 02 09:01:42 PM UTC 24
Peak memory 216244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941433775 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.3941433775
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/1.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/10.rv_dm_alert_test.1084744531
Short name T235
Test name
Test status
Simulation time 169602345 ps
CPU time 1.11 seconds
Started Oct 02 09:01:47 PM UTC 24
Finished Oct 02 09:01:49 PM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084744531 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.1084744531
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/10.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/10.rv_dm_autoincr_sba_tl_access.574023095
Short name T247
Test name
Test status
Simulation time 2552363067 ps
CPU time 2.84 seconds
Started Oct 02 09:01:46 PM UTC 24
Finished Oct 02 09:01:50 PM UTC 24
Peak memory 226588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574023095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.574023095
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/10.rv_dm_bad_sba_tl_access.1139636480
Short name T218
Test name
Test status
Simulation time 4915150175 ps
CPU time 22.64 seconds
Started Oct 02 09:01:45 PM UTC 24
Finished Oct 02 09:02:08 PM UTC 24
Peak memory 226260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139636480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.1139636480
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/10.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.3519521324
Short name T238
Test name
Test status
Simulation time 6013261841 ps
CPU time 8.16 seconds
Started Oct 02 09:01:45 PM UTC 24
Finished Oct 02 09:01:54 PM UTC 24
Peak memory 226404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519521324 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_tl_access.3519521324
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/10.rv_dm_sba_tl_access.637486619
Short name T273
Test name
Test status
Simulation time 11407085356 ps
CPU time 11.68 seconds
Started Oct 02 09:01:45 PM UTC 24
Finished Oct 02 09:01:58 PM UTC 24
Peak memory 216224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637486619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.637486619
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/10.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/10.rv_dm_stress_all.3505799043
Short name T57
Test name
Test status
Simulation time 1351141572 ps
CPU time 3.56 seconds
Started Oct 02 09:01:47 PM UTC 24
Finished Oct 02 09:01:51 PM UTC 24
Peak memory 215864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505799043 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.3505799043
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/10.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/11.rv_dm_alert_test.4108921445
Short name T241
Test name
Test status
Simulation time 28928130 ps
CPU time 1.15 seconds
Started Oct 02 09:01:48 PM UTC 24
Finished Oct 02 09:01:51 PM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108921445 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.4108921445
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/11.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/11.rv_dm_bad_sba_tl_access.3303094965
Short name T254
Test name
Test status
Simulation time 3462920461 ps
CPU time 7.33 seconds
Started Oct 02 09:01:48 PM UTC 24
Finished Oct 02 09:01:57 PM UTC 24
Peak memory 216296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303094965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.3303094965
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/11.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.1127263693
Short name T264
Test name
Test status
Simulation time 4077725247 ps
CPU time 5.89 seconds
Started Oct 02 09:01:48 PM UTC 24
Finished Oct 02 09:01:55 PM UTC 24
Peak memory 226400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127263693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_tl_access.1127263693
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/11.rv_dm_sba_tl_access.1552514714
Short name T210
Test name
Test status
Simulation time 3327454491 ps
CPU time 5.16 seconds
Started Oct 02 09:01:48 PM UTC 24
Finished Oct 02 09:01:54 PM UTC 24
Peak memory 216168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552514714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.1552514714
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/11.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/12.rv_dm_alert_test.902450771
Short name T248
Test name
Test status
Simulation time 166008477 ps
CPU time 1.22 seconds
Started Oct 02 09:01:52 PM UTC 24
Finished Oct 02 09:01:54 PM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902450771 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.902450771
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/12.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/12.rv_dm_autoincr_sba_tl_access.724316718
Short name T330
Test name
Test status
Simulation time 60807270589 ps
CPU time 108.76 seconds
Started Oct 02 09:01:51 PM UTC 24
Finished Oct 02 09:03:42 PM UTC 24
Peak memory 226392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724316718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.724316718
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/12.rv_dm_bad_sba_tl_access.2198583774
Short name T303
Test name
Test status
Simulation time 14891297318 ps
CPU time 34.49 seconds
Started Oct 02 09:01:51 PM UTC 24
Finished Oct 02 09:02:27 PM UTC 24
Peak memory 226260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198583774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.2198583774
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/12.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.4268547298
Short name T212
Test name
Test status
Simulation time 1189501240 ps
CPU time 7.48 seconds
Started Oct 02 09:01:50 PM UTC 24
Finished Oct 02 09:01:58 PM UTC 24
Peak memory 216028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268547298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_tl_access.4268547298
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/12.rv_dm_sba_tl_access.3542553463
Short name T175
Test name
Test status
Simulation time 11318084919 ps
CPU time 26.61 seconds
Started Oct 02 09:01:50 PM UTC 24
Finished Oct 02 09:02:17 PM UTC 24
Peak memory 216360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542553463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.3542553463
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/12.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/13.rv_dm_alert_test.2607179475
Short name T260
Test name
Test status
Simulation time 90546161 ps
CPU time 1.48 seconds
Started Oct 02 09:01:56 PM UTC 24
Finished Oct 02 09:01:58 PM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607179475 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.2607179475
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/13.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.2292356480
Short name T119
Test name
Test status
Simulation time 8955288354 ps
CPU time 9.7 seconds
Started Oct 02 09:01:54 PM UTC 24
Finished Oct 02 09:02:05 PM UTC 24
Peak memory 216016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292356480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_tl_access.2292356480
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/14.rv_dm_alert_test.2873121362
Short name T239
Test name
Test status
Simulation time 109627198 ps
CPU time 1.12 seconds
Started Oct 02 09:01:59 PM UTC 24
Finished Oct 02 09:02:01 PM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873121362 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.2873121362
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/14.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/14.rv_dm_autoincr_sba_tl_access.3289960721
Short name T329
Test name
Test status
Simulation time 61206878794 ps
CPU time 73.87 seconds
Started Oct 02 09:01:58 PM UTC 24
Finished Oct 02 09:03:14 PM UTC 24
Peak memory 226340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289960721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.3289960721
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/14.rv_dm_bad_sba_tl_access.1334699795
Short name T276
Test name
Test status
Simulation time 4513132459 ps
CPU time 5.09 seconds
Started Oct 02 09:01:57 PM UTC 24
Finished Oct 02 09:02:03 PM UTC 24
Peak memory 226332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334699795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.1334699795
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/14.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.3216620810
Short name T178
Test name
Test status
Simulation time 4935187761 ps
CPU time 21.79 seconds
Started Oct 02 09:01:56 PM UTC 24
Finished Oct 02 09:02:19 PM UTC 24
Peak memory 216144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216620810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_tl_access.3216620810
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/14.rv_dm_sba_tl_access.2067600260
Short name T267
Test name
Test status
Simulation time 3354372458 ps
CPU time 11.29 seconds
Started Oct 02 09:01:56 PM UTC 24
Finished Oct 02 09:02:08 PM UTC 24
Peak memory 216032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067600260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.2067600260
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/14.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/15.rv_dm_alert_test.3560352023
Short name T117
Test name
Test status
Simulation time 133260527 ps
CPU time 1.33 seconds
Started Oct 02 09:02:02 PM UTC 24
Finished Oct 02 09:02:04 PM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560352023 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.3560352023
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/15.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/15.rv_dm_autoincr_sba_tl_access.2029160345
Short name T286
Test name
Test status
Simulation time 3846914569 ps
CPU time 18.1 seconds
Started Oct 02 09:02:01 PM UTC 24
Finished Oct 02 09:02:20 PM UTC 24
Peak memory 226340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029160345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.2029160345
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/15.rv_dm_bad_sba_tl_access.1159251781
Short name T278
Test name
Test status
Simulation time 4163991730 ps
CPU time 8.17 seconds
Started Oct 02 09:02:01 PM UTC 24
Finished Oct 02 09:02:10 PM UTC 24
Peak memory 216296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159251781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.1159251781
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/15.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2973761886
Short name T277
Test name
Test status
Simulation time 3519511780 ps
CPU time 9.11 seconds
Started Oct 02 09:01:59 PM UTC 24
Finished Oct 02 09:02:10 PM UTC 24
Peak memory 216088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973761886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_tl_access.2973761886
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/15.rv_dm_sba_tl_access.1654787511
Short name T118
Test name
Test status
Simulation time 3518176176 ps
CPU time 4.62 seconds
Started Oct 02 09:01:59 PM UTC 24
Finished Oct 02 09:02:05 PM UTC 24
Peak memory 216096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654787511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.1654787511
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/15.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/16.rv_dm_alert_test.3170825059
Short name T123
Test name
Test status
Simulation time 108551287 ps
CPU time 1.04 seconds
Started Oct 02 09:02:06 PM UTC 24
Finished Oct 02 09:02:08 PM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170825059 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.3170825059
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/16.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/16.rv_dm_autoincr_sba_tl_access.1127381235
Short name T292
Test name
Test status
Simulation time 5596816055 ps
CPU time 16.03 seconds
Started Oct 02 09:02:05 PM UTC 24
Finished Oct 02 09:02:22 PM UTC 24
Peak memory 226404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127381235 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.1127381235
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/16.rv_dm_bad_sba_tl_access.2267975865
Short name T206
Test name
Test status
Simulation time 9068506244 ps
CPU time 19.74 seconds
Started Oct 02 09:02:04 PM UTC 24
Finished Oct 02 09:02:25 PM UTC 24
Peak memory 226320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267975865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.2267975865
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/16.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.3055975499
Short name T279
Test name
Test status
Simulation time 905894208 ps
CPU time 5.35 seconds
Started Oct 02 09:02:04 PM UTC 24
Finished Oct 02 09:02:10 PM UTC 24
Peak memory 216216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055975499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_tl_access.3055975499
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/16.rv_dm_sba_tl_access.800162827
Short name T122
Test name
Test status
Simulation time 1460170851 ps
CPU time 3.49 seconds
Started Oct 02 09:02:02 PM UTC 24
Finished Oct 02 09:02:06 PM UTC 24
Peak memory 216168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800162827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.800162827
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/16.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/16.rv_dm_stress_all.3895510880
Short name T26
Test name
Test status
Simulation time 3443259464 ps
CPU time 13.14 seconds
Started Oct 02 09:02:05 PM UTC 24
Finished Oct 02 09:02:20 PM UTC 24
Peak memory 226440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895510880 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.3895510880
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/16.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/17.rv_dm_alert_test.2120985847
Short name T281
Test name
Test status
Simulation time 87378917 ps
CPU time 1.14 seconds
Started Oct 02 09:02:09 PM UTC 24
Finished Oct 02 09:02:11 PM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120985847 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.2120985847
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/17.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/17.rv_dm_autoincr_sba_tl_access.149484445
Short name T328
Test name
Test status
Simulation time 12424961961 ps
CPU time 45.07 seconds
Started Oct 02 09:02:08 PM UTC 24
Finished Oct 02 09:02:54 PM UTC 24
Peak memory 226512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149484445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.149484445
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/17.rv_dm_bad_sba_tl_access.1828469689
Short name T299
Test name
Test status
Simulation time 4147162096 ps
CPU time 17.58 seconds
Started Oct 02 09:02:07 PM UTC 24
Finished Oct 02 09:02:25 PM UTC 24
Peak memory 226336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828469689 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.1828469689
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/17.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.2184395972
Short name T282
Test name
Test status
Simulation time 2934067871 ps
CPU time 4.12 seconds
Started Oct 02 09:02:07 PM UTC 24
Finished Oct 02 09:02:12 PM UTC 24
Peak memory 216156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184395972 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_tl_access.2184395972
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/17.rv_dm_sba_tl_access.398836141
Short name T280
Test name
Test status
Simulation time 1564689553 ps
CPU time 2.86 seconds
Started Oct 02 09:02:07 PM UTC 24
Finished Oct 02 09:02:10 PM UTC 24
Peak memory 215972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398836141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.398836141
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/17.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/17.rv_dm_stress_all.2083007873
Short name T186
Test name
Test status
Simulation time 1914585144 ps
CPU time 6.67 seconds
Started Oct 02 09:02:08 PM UTC 24
Finished Oct 02 09:02:15 PM UTC 24
Peak memory 216000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083007873 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.2083007873
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/17.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/18.rv_dm_alert_test.3090765940
Short name T283
Test name
Test status
Simulation time 80054973 ps
CPU time 1.34 seconds
Started Oct 02 09:02:11 PM UTC 24
Finished Oct 02 09:02:14 PM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090765940 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.3090765940
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/18.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.1642662987
Short name T246
Test name
Test status
Simulation time 1284222379 ps
CPU time 3.16 seconds
Started Oct 02 09:02:09 PM UTC 24
Finished Oct 02 09:02:13 PM UTC 24
Peak memory 226276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642662987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_tl_access.1642662987
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/18.rv_dm_sba_tl_access.2411973090
Short name T311
Test name
Test status
Simulation time 4938377664 ps
CPU time 20.43 seconds
Started Oct 02 09:02:09 PM UTC 24
Finished Oct 02 09:02:31 PM UTC 24
Peak memory 216092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411973090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.2411973090
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/18.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/18.rv_dm_stress_all.2672511882
Short name T192
Test name
Test status
Simulation time 5102320128 ps
CPU time 18.6 seconds
Started Oct 02 09:02:10 PM UTC 24
Finished Oct 02 09:02:30 PM UTC 24
Peak memory 226236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672511882 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.2672511882
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/18.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/19.rv_dm_alert_test.3906720485
Short name T171
Test name
Test status
Simulation time 47865296 ps
CPU time 1.35 seconds
Started Oct 02 09:02:14 PM UTC 24
Finished Oct 02 09:02:16 PM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906720485 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.3906720485
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/19.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.970159826
Short name T215
Test name
Test status
Simulation time 14497804111 ps
CPU time 28.09 seconds
Started Oct 02 09:02:13 PM UTC 24
Finished Oct 02 09:02:42 PM UTC 24
Peak memory 226568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970159826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.970159826
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/19.rv_dm_bad_sba_tl_access.4085553862
Short name T323
Test name
Test status
Simulation time 8808046545 ps
CPU time 24.43 seconds
Started Oct 02 09:02:12 PM UTC 24
Finished Oct 02 09:02:37 PM UTC 24
Peak memory 226592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085553862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.4085553862
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/19.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2797244274
Short name T173
Test name
Test status
Simulation time 1126536571 ps
CPU time 3.79 seconds
Started Oct 02 09:02:12 PM UTC 24
Finished Oct 02 09:02:16 PM UTC 24
Peak memory 226404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797244274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_tl_access.2797244274
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/19.rv_dm_sba_tl_access.3233669874
Short name T217
Test name
Test status
Simulation time 5302744344 ps
CPU time 6.35 seconds
Started Oct 02 09:02:12 PM UTC 24
Finished Oct 02 09:02:19 PM UTC 24
Peak memory 216160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233669874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.3233669874
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/19.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.1268331442
Short name T199
Test name
Test status
Simulation time 3136952648 ps
CPU time 8.78 seconds
Started Oct 02 09:02:14 PM UTC 24
Finished Oct 02 09:02:24 PM UTC 24
Peak memory 216116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268331442 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.1268331442
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/19.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.2865945938
Short name T53
Test name
Test status
Simulation time 70338781 ps
CPU time 1.16 seconds
Started Oct 02 09:01:22 PM UTC 24
Finished Oct 02 09:01:25 PM UTC 24
Peak memory 215088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865945938 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.2865945938
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/2.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.1547169795
Short name T271
Test name
Test status
Simulation time 6506821883 ps
CPU time 25.1 seconds
Started Oct 02 09:01:21 PM UTC 24
Finished Oct 02 09:01:47 PM UTC 24
Peak memory 216084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547169795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.1547169795
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.1449508939
Short name T115
Test name
Test status
Simulation time 1992053586 ps
CPU time 9.78 seconds
Started Oct 02 09:01:21 PM UTC 24
Finished Oct 02 09:01:32 PM UTC 24
Peak memory 216232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449508939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.1449508939
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/2.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.2103647731
Short name T275
Test name
Test status
Simulation time 11344939309 ps
CPU time 38.71 seconds
Started Oct 02 09:01:21 PM UTC 24
Finished Oct 02 09:02:01 PM UTC 24
Peak memory 216156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103647731 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_tl_access.2103647731
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.4294519712
Short name T59
Test name
Test status
Simulation time 230466367 ps
CPU time 1.47 seconds
Started Oct 02 09:01:21 PM UTC 24
Finished Oct 02 09:01:23 PM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294519712 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_halt_resume_whereto.4294519712
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/2.rv_dm_halt_resume_whereto/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.872351877
Short name T141
Test name
Test status
Simulation time 85235513 ps
CPU time 1.16 seconds
Started Oct 02 09:01:21 PM UTC 24
Finished Oct 02 09:01:23 PM UTC 24
Peak memory 215332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872351877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.872351877
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/2.rv_dm_hart_unavail/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.1181031943
Short name T100
Test name
Test status
Simulation time 11406519035 ps
CPU time 10.2 seconds
Started Oct 02 09:01:19 PM UTC 24
Finished Oct 02 09:01:31 PM UTC 24
Peak memory 226596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181031943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.1181031943
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/2.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.838660093
Short name T90
Test name
Test status
Simulation time 2706959853 ps
CPU time 5.71 seconds
Started Oct 02 09:01:22 PM UTC 24
Finished Oct 02 09:01:29 PM UTC 24
Peak memory 254472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838660093 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.838660093
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/2.rv_dm_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_sparse_lc_gate_fsm.2111135103
Short name T83
Test name
Test status
Simulation time 63216197 ps
CPU time 1.2 seconds
Started Oct 02 09:01:22 PM UTC 24
Finished Oct 02 09:01:24 PM UTC 24
Peak memory 225192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111135103 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sparse_lc_gate_fsm.2111135103
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/2.rv_dm_sparse_lc_gate_fsm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.1144792356
Short name T82
Test name
Test status
Simulation time 3931802217 ps
CPU time 99.51 seconds
Started Oct 02 09:01:22 PM UTC 24
Finished Oct 02 09:03:04 PM UTC 24
Peak memory 232872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=1144792356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stres
s_all_with_rand_reset.1144792356
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/20.rv_dm_alert_test.2415805596
Short name T177
Test name
Test status
Simulation time 34695371 ps
CPU time 1.05 seconds
Started Oct 02 09:02:16 PM UTC 24
Finished Oct 02 09:02:18 PM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415805596 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.2415805596
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/20.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/21.rv_dm_alert_test.1985567207
Short name T287
Test name
Test status
Simulation time 145274495 ps
CPU time 1.73 seconds
Started Oct 02 09:02:17 PM UTC 24
Finished Oct 02 09:02:20 PM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985567207 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.1985567207
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/21.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/21.rv_dm_stress_all.3398472689
Short name T34
Test name
Test status
Simulation time 2486609407 ps
CPU time 3.45 seconds
Started Oct 02 09:02:16 PM UTC 24
Finished Oct 02 09:02:21 PM UTC 24
Peak memory 215928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398472689 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.3398472689
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/21.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/22.rv_dm_alert_test.3621156860
Short name T284
Test name
Test status
Simulation time 134450411 ps
CPU time 0.99 seconds
Started Oct 02 09:02:18 PM UTC 24
Finished Oct 02 09:02:19 PM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621156860 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.3621156860
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/22.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.2400979446
Short name T58
Test name
Test status
Simulation time 4418508322 ps
CPU time 11.28 seconds
Started Oct 02 09:02:17 PM UTC 24
Finished Oct 02 09:02:30 PM UTC 24
Peak memory 216184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400979446 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.2400979446
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/22.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/23.rv_dm_alert_test.398846200
Short name T288
Test name
Test status
Simulation time 83739887 ps
CPU time 1.31 seconds
Started Oct 02 09:02:19 PM UTC 24
Finished Oct 02 09:02:21 PM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398846200 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.398846200
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/23.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/23.rv_dm_stress_all.3087587689
Short name T315
Test name
Test status
Simulation time 6710466193 ps
CPU time 11.96 seconds
Started Oct 02 09:02:19 PM UTC 24
Finished Oct 02 09:02:32 PM UTC 24
Peak memory 215988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087587689 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.3087587689
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/23.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/24.rv_dm_alert_test.2896465968
Short name T289
Test name
Test status
Simulation time 78404368 ps
CPU time 1.1 seconds
Started Oct 02 09:02:19 PM UTC 24
Finished Oct 02 09:02:21 PM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896465968 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.2896465968
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/24.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/24.rv_dm_stress_all.1269810712
Short name T188
Test name
Test status
Simulation time 2007229155 ps
CPU time 4.79 seconds
Started Oct 02 09:02:19 PM UTC 24
Finished Oct 02 09:02:25 PM UTC 24
Peak memory 226120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269810712 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.1269810712
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/24.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/25.rv_dm_alert_test.1415703980
Short name T290
Test name
Test status
Simulation time 59848140 ps
CPU time 1.05 seconds
Started Oct 02 09:02:20 PM UTC 24
Finished Oct 02 09:02:22 PM UTC 24
Peak memory 215264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415703980 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.1415703980
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/25.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.1161692976
Short name T202
Test name
Test status
Simulation time 1888995980 ps
CPU time 7.51 seconds
Started Oct 02 09:02:19 PM UTC 24
Finished Oct 02 09:02:28 PM UTC 24
Peak memory 226184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161692976 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.1161692976
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/25.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/26.rv_dm_alert_test.2001405853
Short name T291
Test name
Test status
Simulation time 75857064 ps
CPU time 1.02 seconds
Started Oct 02 09:02:20 PM UTC 24
Finished Oct 02 09:02:22 PM UTC 24
Peak memory 215260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001405853 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.2001405853
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/26.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/27.rv_dm_alert_test.1412325685
Short name T293
Test name
Test status
Simulation time 57529023 ps
CPU time 1.02 seconds
Started Oct 02 09:02:20 PM UTC 24
Finished Oct 02 09:02:22 PM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412325685 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.1412325685
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/27.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.1252398626
Short name T201
Test name
Test status
Simulation time 7919031009 ps
CPU time 24.07 seconds
Started Oct 02 09:02:20 PM UTC 24
Finished Oct 02 09:02:46 PM UTC 24
Peak memory 215936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252398626 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.1252398626
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/27.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/28.rv_dm_alert_test.979304724
Short name T294
Test name
Test status
Simulation time 71490137 ps
CPU time 1.1 seconds
Started Oct 02 09:02:21 PM UTC 24
Finished Oct 02 09:02:23 PM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979304724 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.979304724
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/28.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/29.rv_dm_alert_test.118062557
Short name T295
Test name
Test status
Simulation time 30183935 ps
CPU time 1.15 seconds
Started Oct 02 09:02:22 PM UTC 24
Finished Oct 02 09:02:24 PM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118062557 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.118062557
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/29.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/29.rv_dm_stress_all.830224547
Short name T194
Test name
Test status
Simulation time 713772289 ps
CPU time 4.71 seconds
Started Oct 02 09:02:21 PM UTC 24
Finished Oct 02 09:02:26 PM UTC 24
Peak memory 226048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830224547 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.830224547
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/29.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.258738182
Short name T99
Test name
Test status
Simulation time 97848181 ps
CPU time 1.47 seconds
Started Oct 02 09:01:26 PM UTC 24
Finished Oct 02 09:01:29 PM UTC 24
Peak memory 215264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258738182 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.258738182
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/3.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.2104607706
Short name T24
Test name
Test status
Simulation time 6041751091 ps
CPU time 7.13 seconds
Started Oct 02 09:01:23 PM UTC 24
Finished Oct 02 09:01:32 PM UTC 24
Peak memory 216412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104607706 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.2104607706
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.178962650
Short name T167
Test name
Test status
Simulation time 1775648925 ps
CPU time 6.92 seconds
Started Oct 02 09:01:23 PM UTC 24
Finished Oct 02 09:01:32 PM UTC 24
Peak memory 226268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178962650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.178962650
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/3.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.3415665785
Short name T165
Test name
Test status
Simulation time 175904188 ps
CPU time 1.33 seconds
Started Oct 02 09:01:25 PM UTC 24
Finished Oct 02 09:01:27 PM UTC 24
Peak memory 250896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415665785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_buffered_enable.3415665785
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/3.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1945173249
Short name T98
Test name
Test status
Simulation time 1177882376 ps
CPU time 4.86 seconds
Started Oct 02 09:01:22 PM UTC 24
Finished Oct 02 09:01:28 PM UTC 24
Peak memory 215972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945173249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_tl_access.1945173249
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.1784558580
Short name T60
Test name
Test status
Simulation time 528519841 ps
CPU time 1.77 seconds
Started Oct 02 09:01:25 PM UTC 24
Finished Oct 02 09:01:28 PM UTC 24
Peak memory 215332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784558580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_halt_resume_whereto.1784558580
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/3.rv_dm_halt_resume_whereto/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_hart_unavail.566102143
Short name T198
Test name
Test status
Simulation time 65818048 ps
CPU time 1.42 seconds
Started Oct 02 09:01:25 PM UTC 24
Finished Oct 02 09:01:27 PM UTC 24
Peak memory 215332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566102143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.566102143
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/3.rv_dm_hart_unavail/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_sec_cm.969873188
Short name T94
Test name
Test status
Simulation time 1270757701 ps
CPU time 2.45 seconds
Started Oct 02 09:01:26 PM UTC 24
Finished Oct 02 09:01:30 PM UTC 24
Peak memory 254216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969873188 -assert nopostproc +UVM_TESTNAME=rv_dm_
base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.969873188
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/3.rv_dm_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/30.rv_dm_alert_test.1116919347
Short name T297
Test name
Test status
Simulation time 49814072 ps
CPU time 1.22 seconds
Started Oct 02 09:02:22 PM UTC 24
Finished Oct 02 09:02:24 PM UTC 24
Peak memory 215160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116919347 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.1116919347
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/30.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/31.rv_dm_alert_test.3279915966
Short name T296
Test name
Test status
Simulation time 95427628 ps
CPU time 1.06 seconds
Started Oct 02 09:02:22 PM UTC 24
Finished Oct 02 09:02:24 PM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279915966 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.3279915966
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/31.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/31.rv_dm_stress_all.1974610556
Short name T322
Test name
Test status
Simulation time 2679742187 ps
CPU time 12.53 seconds
Started Oct 02 09:02:22 PM UTC 24
Finished Oct 02 09:02:36 PM UTC 24
Peak memory 216116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974610556 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.1974610556
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/31.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/32.rv_dm_alert_test.3458492249
Short name T298
Test name
Test status
Simulation time 118032689 ps
CPU time 1.63 seconds
Started Oct 02 09:02:22 PM UTC 24
Finished Oct 02 09:02:25 PM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458492249 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.3458492249
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/32.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/32.rv_dm_stress_all.2115020056
Short name T203
Test name
Test status
Simulation time 2462144390 ps
CPU time 6.3 seconds
Started Oct 02 09:02:22 PM UTC 24
Finished Oct 02 09:02:30 PM UTC 24
Peak memory 226152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115020056 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.2115020056
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/32.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/33.rv_dm_alert_test.1332956483
Short name T300
Test name
Test status
Simulation time 33861487 ps
CPU time 1.18 seconds
Started Oct 02 09:02:24 PM UTC 24
Finished Oct 02 09:02:26 PM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332956483 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.1332956483
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/33.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/34.rv_dm_alert_test.374746245
Short name T302
Test name
Test status
Simulation time 44578198 ps
CPU time 1.14 seconds
Started Oct 02 09:02:24 PM UTC 24
Finished Oct 02 09:02:26 PM UTC 24
Peak memory 215204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374746245 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.374746245
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/34.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/34.rv_dm_stress_all.362471448
Short name T324
Test name
Test status
Simulation time 10895876911 ps
CPU time 13.36 seconds
Started Oct 02 09:02:24 PM UTC 24
Finished Oct 02 09:02:39 PM UTC 24
Peak memory 226436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362471448 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.362471448
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/34.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/35.rv_dm_alert_test.352199105
Short name T301
Test name
Test status
Simulation time 117161734 ps
CPU time 0.96 seconds
Started Oct 02 09:02:24 PM UTC 24
Finished Oct 02 09:02:26 PM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352199105 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.352199105
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/35.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/35.rv_dm_stress_all.1888588325
Short name T19
Test name
Test status
Simulation time 4375007112 ps
CPU time 3.87 seconds
Started Oct 02 09:02:24 PM UTC 24
Finished Oct 02 09:02:29 PM UTC 24
Peak memory 215924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888588325 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.1888588325
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/35.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/36.rv_dm_alert_test.4045246004
Short name T305
Test name
Test status
Simulation time 80603418 ps
CPU time 1.14 seconds
Started Oct 02 09:02:26 PM UTC 24
Finished Oct 02 09:02:28 PM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045246004 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.4045246004
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/36.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/37.rv_dm_alert_test.3543052013
Short name T306
Test name
Test status
Simulation time 38800696 ps
CPU time 1.19 seconds
Started Oct 02 09:02:26 PM UTC 24
Finished Oct 02 09:02:28 PM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543052013 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.3543052013
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/37.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/37.rv_dm_stress_all.3556234004
Short name T304
Test name
Test status
Simulation time 2376406055 ps
CPU time 5.19 seconds
Started Oct 02 09:02:26 PM UTC 24
Finished Oct 02 09:02:32 PM UTC 24
Peak memory 215772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556234004 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.3556234004
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/37.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/38.rv_dm_alert_test.3857945407
Short name T307
Test name
Test status
Simulation time 74026468 ps
CPU time 1.17 seconds
Started Oct 02 09:02:26 PM UTC 24
Finished Oct 02 09:02:28 PM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857945407 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.3857945407
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/38.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/39.rv_dm_alert_test.605623546
Short name T237
Test name
Test status
Simulation time 137346895 ps
CPU time 1.25 seconds
Started Oct 02 09:02:26 PM UTC 24
Finished Oct 02 09:02:28 PM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605623546 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.605623546
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/39.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/39.rv_dm_stress_all.815548208
Short name T316
Test name
Test status
Simulation time 2886112167 ps
CPU time 5.89 seconds
Started Oct 02 09:02:26 PM UTC 24
Finished Oct 02 09:02:33 PM UTC 24
Peak memory 216196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815548208 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.815548208
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/39.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_alert_test.559828422
Short name T162
Test name
Test status
Simulation time 118327916 ps
CPU time 0.93 seconds
Started Oct 02 09:01:31 PM UTC 24
Finished Oct 02 09:01:33 PM UTC 24
Peak memory 215264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559828422 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.559828422
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/4.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_autoincr_sba_tl_access.3555752994
Short name T285
Test name
Test status
Simulation time 15960913404 ps
CPU time 49.39 seconds
Started Oct 02 09:01:28 PM UTC 24
Finished Oct 02 09:02:20 PM UTC 24
Peak memory 226332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555752994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.3555752994
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_bad_sba_tl_access.914092397
Short name T244
Test name
Test status
Simulation time 2920514663 ps
CPU time 8.59 seconds
Started Oct 02 09:01:28 PM UTC 24
Finished Oct 02 09:01:38 PM UTC 24
Peak memory 232968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914092397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.914092397
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/4.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_buffered_enable.2379914608
Short name T208
Test name
Test status
Simulation time 461747738 ps
CPU time 1.84 seconds
Started Oct 02 09:01:30 PM UTC 24
Finished Oct 02 09:01:33 PM UTC 24
Peak memory 244276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379914608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_buffered_enable.2379914608
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/4.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.1674229581
Short name T263
Test name
Test status
Simulation time 594467017 ps
CPU time 2.52 seconds
Started Oct 02 09:01:28 PM UTC 24
Finished Oct 02 09:01:32 PM UTC 24
Peak memory 215872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674229581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_tl_access.1674229581
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.3177766452
Short name T61
Test name
Test status
Simulation time 516381493 ps
CPU time 3.06 seconds
Started Oct 02 09:01:29 PM UTC 24
Finished Oct 02 09:01:33 PM UTC 24
Peak memory 215536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177766452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_halt_resume_whereto.3177766452
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/4.rv_dm_halt_resume_whereto/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.4178330350
Short name T101
Test name
Test status
Simulation time 268648842 ps
CPU time 1.24 seconds
Started Oct 02 09:01:28 PM UTC 24
Finished Oct 02 09:01:31 PM UTC 24
Peak memory 215284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178330350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.4178330350
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/4.rv_dm_hart_unavail/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_sba_tl_access.2337268435
Short name T134
Test name
Test status
Simulation time 991504119 ps
CPU time 3.57 seconds
Started Oct 02 09:01:26 PM UTC 24
Finished Oct 02 09:01:31 PM UTC 24
Peak memory 216228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337268435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.2337268435
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/4.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_sec_cm.1677284121
Short name T95
Test name
Test status
Simulation time 1219617985 ps
CPU time 2.78 seconds
Started Oct 02 09:01:30 PM UTC 24
Finished Oct 02 09:01:34 PM UTC 24
Peak memory 254352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677284121 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.1677284121
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/4.rv_dm_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.3434015843
Short name T70
Test name
Test status
Simulation time 3988396892 ps
CPU time 17.29 seconds
Started Oct 02 09:01:30 PM UTC 24
Finished Oct 02 09:01:48 PM UTC 24
Peak memory 226428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434015843 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.3434015843
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/4.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/40.rv_dm_alert_test.2251972863
Short name T308
Test name
Test status
Simulation time 72010887 ps
CPU time 1.04 seconds
Started Oct 02 09:02:27 PM UTC 24
Finished Oct 02 09:02:29 PM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251972863 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.2251972863
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/40.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/40.rv_dm_stress_all.2289097511
Short name T200
Test name
Test status
Simulation time 3986337811 ps
CPU time 9.28 seconds
Started Oct 02 09:02:26 PM UTC 24
Finished Oct 02 09:02:36 PM UTC 24
Peak memory 216184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289097511 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.2289097511
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/40.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/41.rv_dm_alert_test.2982387235
Short name T310
Test name
Test status
Simulation time 134991290 ps
CPU time 1.42 seconds
Started Oct 02 09:02:27 PM UTC 24
Finished Oct 02 09:02:30 PM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982387235 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.2982387235
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/41.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/41.rv_dm_stress_all.530850249
Short name T326
Test name
Test status
Simulation time 3095509328 ps
CPU time 11.42 seconds
Started Oct 02 09:02:27 PM UTC 24
Finished Oct 02 09:02:40 PM UTC 24
Peak memory 226436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530850249 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.530850249
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/41.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/42.rv_dm_alert_test.3737849614
Short name T309
Test name
Test status
Simulation time 34801156 ps
CPU time 1.12 seconds
Started Oct 02 09:02:28 PM UTC 24
Finished Oct 02 09:02:30 PM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737849614 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.3737849614
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/42.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/42.rv_dm_stress_all.4293480585
Short name T38
Test name
Test status
Simulation time 5548703885 ps
CPU time 3.4 seconds
Started Oct 02 09:02:27 PM UTC 24
Finished Oct 02 09:02:32 PM UTC 24
Peak memory 215936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293480585 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.4293480585
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/42.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/43.rv_dm_alert_test.3782543604
Short name T312
Test name
Test status
Simulation time 70534635 ps
CPU time 1.05 seconds
Started Oct 02 09:02:29 PM UTC 24
Finished Oct 02 09:02:31 PM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782543604 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.3782543604
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/43.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/43.rv_dm_stress_all.3623523087
Short name T321
Test name
Test status
Simulation time 4511661466 ps
CPU time 5.66 seconds
Started Oct 02 09:02:29 PM UTC 24
Finished Oct 02 09:02:36 PM UTC 24
Peak memory 226376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623523087 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.3623523087
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/43.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/44.rv_dm_alert_test.2230469739
Short name T313
Test name
Test status
Simulation time 25650333 ps
CPU time 0.98 seconds
Started Oct 02 09:02:29 PM UTC 24
Finished Oct 02 09:02:31 PM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230469739 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.2230469739
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/44.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.1461054329
Short name T320
Test name
Test status
Simulation time 3036576057 ps
CPU time 4.57 seconds
Started Oct 02 09:02:29 PM UTC 24
Finished Oct 02 09:02:35 PM UTC 24
Peak memory 215928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461054329 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.1461054329
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/44.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/45.rv_dm_alert_test.176663126
Short name T252
Test name
Test status
Simulation time 138938822 ps
CPU time 1.32 seconds
Started Oct 02 09:02:29 PM UTC 24
Finished Oct 02 09:02:31 PM UTC 24
Peak memory 215244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176663126 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.176663126
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/45.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/45.rv_dm_stress_all.1557580298
Short name T327
Test name
Test status
Simulation time 4817049765 ps
CPU time 16.23 seconds
Started Oct 02 09:02:29 PM UTC 24
Finished Oct 02 09:02:47 PM UTC 24
Peak memory 216000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557580298 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.1557580298
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/45.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/46.rv_dm_alert_test.134975309
Short name T314
Test name
Test status
Simulation time 79211224 ps
CPU time 1.08 seconds
Started Oct 02 09:02:29 PM UTC 24
Finished Oct 02 09:02:31 PM UTC 24
Peak memory 215240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134975309 -assert nopostproc +UVM_TESTNAME=rv_dm
_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.134975309
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/46.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.3664229046
Short name T204
Test name
Test status
Simulation time 2116056634 ps
CPU time 3.77 seconds
Started Oct 02 09:02:29 PM UTC 24
Finished Oct 02 09:02:34 PM UTC 24
Peak memory 215816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664229046 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.3664229046
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/46.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/47.rv_dm_alert_test.1358157695
Short name T317
Test name
Test status
Simulation time 78825505 ps
CPU time 1.13 seconds
Started Oct 02 09:02:31 PM UTC 24
Finished Oct 02 09:02:33 PM UTC 24
Peak memory 215264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358157695 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.1358157695
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/47.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/47.rv_dm_stress_all.4281831456
Short name T189
Test name
Test status
Simulation time 7539154484 ps
CPU time 9.65 seconds
Started Oct 02 09:02:31 PM UTC 24
Finished Oct 02 09:02:42 PM UTC 24
Peak memory 216184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281831456 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.4281831456
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/47.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/48.rv_dm_alert_test.2122536450
Short name T318
Test name
Test status
Simulation time 131441376 ps
CPU time 1.11 seconds
Started Oct 02 09:02:31 PM UTC 24
Finished Oct 02 09:02:33 PM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122536450 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.2122536450
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/48.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/48.rv_dm_stress_all.2298333996
Short name T197
Test name
Test status
Simulation time 1493635956 ps
CPU time 3.63 seconds
Started Oct 02 09:02:31 PM UTC 24
Finished Oct 02 09:02:36 PM UTC 24
Peak memory 215804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298333996 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.2298333996
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/48.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/49.rv_dm_alert_test.3654812240
Short name T319
Test name
Test status
Simulation time 73970138 ps
CPU time 1.19 seconds
Started Oct 02 09:02:31 PM UTC 24
Finished Oct 02 09:02:33 PM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654812240 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.3654812240
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/49.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/49.rv_dm_stress_all.3445670608
Short name T325
Test name
Test status
Simulation time 2210438331 ps
CPU time 6.45 seconds
Started Oct 02 09:02:31 PM UTC 24
Finished Oct 02 09:02:39 PM UTC 24
Peak memory 226504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445670608 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.3445670608
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/49.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/5.rv_dm_alert_test.1557677702
Short name T163
Test name
Test status
Simulation time 110565161 ps
CPU time 1.04 seconds
Started Oct 02 09:01:33 PM UTC 24
Finished Oct 02 09:01:35 PM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557677702 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.1557677702
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/5.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.2812013982
Short name T183
Test name
Test status
Simulation time 28762119944 ps
CPU time 21.86 seconds
Started Oct 02 09:01:31 PM UTC 24
Finished Oct 02 09:01:54 PM UTC 24
Peak memory 226328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812013982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.2812013982
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.2933016158
Short name T236
Test name
Test status
Simulation time 4736907506 ps
CPU time 10.28 seconds
Started Oct 02 09:01:31 PM UTC 24
Finished Oct 02 09:01:42 PM UTC 24
Peak memory 226600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933016158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.2933016158
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/5.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/5.rv_dm_buffered_enable.67515386
Short name T233
Test name
Test status
Simulation time 154281387 ps
CPU time 1.25 seconds
Started Oct 02 09:01:32 PM UTC 24
Finished Oct 02 09:01:35 PM UTC 24
Peak memory 250892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67515386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv
_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_buffered_enable.67515386
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/5.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.3659167590
Short name T256
Test name
Test status
Simulation time 1333610945 ps
CPU time 5.04 seconds
Started Oct 02 09:01:31 PM UTC 24
Finished Oct 02 09:01:37 PM UTC 24
Peak memory 215960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659167590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl_access.3659167590
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/5.rv_dm_halt_resume_whereto.2969645385
Short name T68
Test name
Test status
Simulation time 348494688 ps
CPU time 1.68 seconds
Started Oct 02 09:01:32 PM UTC 24
Finished Oct 02 09:01:35 PM UTC 24
Peak memory 215176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969645385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_halt_resume_whereto.2969645385
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/5.rv_dm_halt_resume_whereto/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/5.rv_dm_sba_tl_access.3489439774
Short name T268
Test name
Test status
Simulation time 990850195 ps
CPU time 2.97 seconds
Started Oct 02 09:01:31 PM UTC 24
Finished Oct 02 09:01:35 PM UTC 24
Peak memory 216020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489439774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.3489439774
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/5.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.780596968
Short name T35
Test name
Test status
Simulation time 5000127628 ps
CPU time 8.63 seconds
Started Oct 02 09:01:32 PM UTC 24
Finished Oct 02 09:01:42 PM UTC 24
Peak memory 226248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780596968 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.780596968
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/5.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/6.rv_dm_alert_test.4284049576
Short name T164
Test name
Test status
Simulation time 39477889 ps
CPU time 0.96 seconds
Started Oct 02 09:01:35 PM UTC 24
Finished Oct 02 09:01:37 PM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284049576 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.4284049576
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/6.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/6.rv_dm_autoincr_sba_tl_access.4206406450
Short name T269
Test name
Test status
Simulation time 2092152588 ps
CPU time 5.91 seconds
Started Oct 02 09:01:34 PM UTC 24
Finished Oct 02 09:01:41 PM UTC 24
Peak memory 226504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206406450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.4206406450
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/6.rv_dm_bad_sba_tl_access.2585669282
Short name T211
Test name
Test status
Simulation time 969636090 ps
CPU time 4.25 seconds
Started Oct 02 09:01:34 PM UTC 24
Finished Oct 02 09:01:39 PM UTC 24
Peak memory 215900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585669282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.2585669282
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/6.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/6.rv_dm_buffered_enable.2131932310
Short name T234
Test name
Test status
Simulation time 671798294 ps
CPU time 2.17 seconds
Started Oct 02 09:01:34 PM UTC 24
Finished Oct 02 09:01:37 PM UTC 24
Peak memory 245816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131932310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_buffered_enable.2131932310
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/6.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.2094404581
Short name T240
Test name
Test status
Simulation time 1369600163 ps
CPU time 5.49 seconds
Started Oct 02 09:01:34 PM UTC 24
Finished Oct 02 09:01:40 PM UTC 24
Peak memory 216036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094404581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_tl_access.2094404581
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/6.rv_dm_halt_resume_whereto.3888392662
Short name T72
Test name
Test status
Simulation time 448900945 ps
CPU time 1.3 seconds
Started Oct 02 09:01:34 PM UTC 24
Finished Oct 02 09:01:36 PM UTC 24
Peak memory 215332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888392662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_halt_resume_whereto.3888392662
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/6.rv_dm_halt_resume_whereto/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/6.rv_dm_sba_tl_access.2167460920
Short name T249
Test name
Test status
Simulation time 1617662091 ps
CPU time 2.54 seconds
Started Oct 02 09:01:33 PM UTC 24
Finished Oct 02 09:01:36 PM UTC 24
Peak memory 216092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167460920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.2167460920
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/6.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all.2690407964
Short name T195
Test name
Test status
Simulation time 4016183673 ps
CPU time 22.57 seconds
Started Oct 02 09:01:34 PM UTC 24
Finished Oct 02 09:01:58 PM UTC 24
Peak memory 226180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690407964 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.2690407964
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/6.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/7.rv_dm_alert_test.1820092124
Short name T242
Test name
Test status
Simulation time 54720346 ps
CPU time 1.33 seconds
Started Oct 02 09:01:38 PM UTC 24
Finished Oct 02 09:01:40 PM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820092124 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.1820092124
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/7.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.1288440212
Short name T274
Test name
Test status
Simulation time 12238021368 ps
CPU time 22.57 seconds
Started Oct 02 09:01:37 PM UTC 24
Finished Oct 02 09:02:00 PM UTC 24
Peak memory 216092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288440212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.1288440212
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.2554043041
Short name T257
Test name
Test status
Simulation time 3204378942 ps
CPU time 5.15 seconds
Started Oct 02 09:01:35 PM UTC 24
Finished Oct 02 09:01:42 PM UTC 24
Peak memory 226580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554043041 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.2554043041
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/7.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/7.rv_dm_buffered_enable.1911471085
Short name T135
Test name
Test status
Simulation time 478029868 ps
CPU time 3.69 seconds
Started Oct 02 09:01:37 PM UTC 24
Finished Oct 02 09:01:41 PM UTC 24
Peak memory 252304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911471085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_buffered_enable.1911471085
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/7.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.94054421
Short name T216
Test name
Test status
Simulation time 8725222335 ps
CPU time 7.23 seconds
Started Oct 02 09:01:35 PM UTC 24
Finished Oct 02 09:01:44 PM UTC 24
Peak memory 216344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94054421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_tl_access.94054421
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.134337317
Short name T209
Test name
Test status
Simulation time 532662821 ps
CPU time 1.79 seconds
Started Oct 02 09:01:37 PM UTC 24
Finished Oct 02 09:01:39 PM UTC 24
Peak memory 215392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134337317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_halt_resume_whereto.134337317
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/7.rv_dm_halt_resume_whereto/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/7.rv_dm_sba_tl_access.3641470095
Short name T261
Test name
Test status
Simulation time 2510712406 ps
CPU time 5.95 seconds
Started Oct 02 09:01:35 PM UTC 24
Finished Oct 02 09:01:42 PM UTC 24
Peak memory 233048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641470095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.3641470095
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/7.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all.283322055
Short name T32
Test name
Test status
Simulation time 5746543089 ps
CPU time 25.98 seconds
Started Oct 02 09:01:37 PM UTC 24
Finished Oct 02 09:02:04 PM UTC 24
Peak memory 226112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283322055 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.283322055
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/7.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.707401568
Short name T107
Test name
Test status
Simulation time 4592482541 ps
CPU time 74.43 seconds
Started Oct 02 09:01:38 PM UTC 24
Finished Oct 02 09:02:54 PM UTC 24
Peak memory 232960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=707401568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress
_all_with_rand_reset.707401568
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/8.rv_dm_alert_test.1639561656
Short name T250
Test name
Test status
Simulation time 259246961 ps
CPU time 1.25 seconds
Started Oct 02 09:01:42 PM UTC 24
Finished Oct 02 09:01:44 PM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639561656 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.1639561656
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/8.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.1808608988
Short name T259
Test name
Test status
Simulation time 3770147569 ps
CPU time 6.93 seconds
Started Oct 02 09:01:39 PM UTC 24
Finished Oct 02 09:01:47 PM UTC 24
Peak memory 216220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808608988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.1808608988
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/8.rv_dm_bad_sba_tl_access.1992403335
Short name T265
Test name
Test status
Simulation time 8970141823 ps
CPU time 7.22 seconds
Started Oct 02 09:01:39 PM UTC 24
Finished Oct 02 09:01:47 PM UTC 24
Peak memory 226400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992403335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.1992403335
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/8.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/8.rv_dm_buffered_enable.204392657
Short name T232
Test name
Test status
Simulation time 134673668 ps
CPU time 1.43 seconds
Started Oct 02 09:01:40 PM UTC 24
Finished Oct 02 09:01:43 PM UTC 24
Peak memory 251016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204392657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_buffered_enable.204392657
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/8.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.817067720
Short name T270
Test name
Test status
Simulation time 3902583947 ps
CPU time 5.92 seconds
Started Oct 02 09:01:39 PM UTC 24
Finished Oct 02 09:01:46 PM UTC 24
Peak memory 216332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817067720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl_access.817067720
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/8.rv_dm_sba_tl_access.1262171881
Short name T262
Test name
Test status
Simulation time 2597793817 ps
CPU time 5.5 seconds
Started Oct 02 09:01:38 PM UTC 24
Finished Oct 02 09:01:45 PM UTC 24
Peak memory 216424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262171881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.1262171881
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/8.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.857358883
Short name T193
Test name
Test status
Simulation time 3274640642 ps
CPU time 5.54 seconds
Started Oct 02 09:01:41 PM UTC 24
Finished Oct 02 09:01:47 PM UTC 24
Peak memory 216000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857358883 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.857358883
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/8.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.1598452496
Short name T243
Test name
Test status
Simulation time 60386582 ps
CPU time 1.21 seconds
Started Oct 02 09:01:43 PM UTC 24
Finished Oct 02 09:01:46 PM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598452496 -assert nopostproc +UVM_TESTNAME=rv_d
m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.1598452496
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/9.rv_dm_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/9.rv_dm_autoincr_sba_tl_access.3001019520
Short name T253
Test name
Test status
Simulation time 7474030318 ps
CPU time 23.63 seconds
Started Oct 02 09:01:43 PM UTC 24
Finished Oct 02 09:02:08 PM UTC 24
Peak memory 216092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001019520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.3001019520
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.1544541580
Short name T255
Test name
Test status
Simulation time 10153622944 ps
CPU time 15.62 seconds
Started Oct 02 09:01:43 PM UTC 24
Finished Oct 02 09:02:00 PM UTC 24
Peak memory 226656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544541580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.1544541580
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/9.rv_dm_bad_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/9.rv_dm_buffered_enable.3435686961
Short name T245
Test name
Test status
Simulation time 262183416 ps
CPU time 2.69 seconds
Started Oct 02 09:01:43 PM UTC 24
Finished Oct 02 09:01:47 PM UTC 24
Peak memory 258176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435686961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_buffered_enable.3435686961
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/9.rv_dm_buffered_enable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.2968612932
Short name T272
Test name
Test status
Simulation time 1376336271 ps
CPU time 3.44 seconds
Started Oct 02 09:01:43 PM UTC 24
Finished Oct 02 09:01:48 PM UTC 24
Peak memory 215888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968612932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test
+UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_tl_access.2968612932
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.2192847245
Short name T258
Test name
Test status
Simulation time 3984666907 ps
CPU time 16.79 seconds
Started Oct 02 09:01:42 PM UTC 24
Finished Oct 02 09:02:00 PM UTC 24
Peak memory 216304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192847245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.2192847245
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/9.rv_dm_sba_tl_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.36351390
Short name T36
Test name
Test status
Simulation time 2488181581 ps
CPU time 5.99 seconds
Started Oct 02 09:01:43 PM UTC 24
Finished Oct 02 09:01:50 PM UTC 24
Peak memory 216176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36351390 -assert nopostproc +UVM_TESTNAME=rv_
dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.36351390
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/9.rv_dm_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.2984507246
Short name T17
Test name
Test status
Simulation time 2569781044 ps
CPU time 30.84 seconds
Started Oct 02 09:01:43 PM UTC 24
Finished Oct 02 09:02:16 PM UTC 24
Peak memory 233104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=
rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.
tcl +ntb_random_seed=2984507246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stres
s_all_with_rand_reset.2984507246
Directory /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest