| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 88.49 | 96.34 | 89.82 | 92.10 | 94.67 | 90.27 | 98.74 | 57.49 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 52.33 | 52.33 | 83.90 | 83.90 | 47.67 | 47.67 | 32.44 | 32.44 | 44.00 | 44.00 | 63.19 | 63.19 | 93.07 | 93.07 | 2.05 | 2.05 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.270717177 |
| 61.59 | 9.26 | 85.55 | 1.65 | 56.29 | 8.63 | 35.13 | 2.69 | 49.33 | 5.33 | 68.50 | 5.31 | 94.33 | 1.26 | 42.03 | 39.98 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.3223897393 |
| 69.54 | 7.94 | 87.56 | 2.01 | 67.89 | 11.60 | 67.56 | 32.44 | 50.67 | 1.33 | 72.92 | 4.42 | 95.59 | 1.26 | 44.57 | 2.54 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.759580240 |
| 73.98 | 4.44 | 90.92 | 3.35 | 72.14 | 4.24 | 71.68 | 4.12 | 62.67 | 12.00 | 79.12 | 6.19 | 95.90 | 0.32 | 45.41 | 0.85 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all.625481385 |
| 76.31 | 2.33 | 91.95 | 1.03 | 76.66 | 4.53 | 72.14 | 0.46 | 70.67 | 8.00 | 81.06 | 1.95 | 95.90 | 0.00 | 45.77 | 0.36 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_busy.4213525611 |
| 78.42 | 2.11 | 92.93 | 0.98 | 78.36 | 1.70 | 77.31 | 5.17 | 74.67 | 4.00 | 83.19 | 2.12 | 96.11 | 0.21 | 46.38 | 0.60 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.2180336319 |
| 79.96 | 1.54 | 92.98 | 0.05 | 78.78 | 0.42 | 87.35 | 10.04 | 74.67 | 0.00 | 83.36 | 0.18 | 96.22 | 0.11 | 46.38 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_halt_resume_whereto.1459341293 |
| 80.82 | 0.86 | 93.09 | 0.10 | 80.34 | 1.56 | 88.03 | 0.67 | 74.67 | 0.00 | 83.89 | 0.53 | 96.22 | 0.00 | 49.52 | 3.14 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3703437226 |
| 81.63 | 0.81 | 93.14 | 0.05 | 81.19 | 0.85 | 88.15 | 0.13 | 78.67 | 4.00 | 84.42 | 0.53 | 96.22 | 0.00 | 49.64 | 0.12 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.4229835236 |
| 82.40 | 0.77 | 93.14 | 0.00 | 81.19 | 0.00 | 88.19 | 0.04 | 84.00 | 5.33 | 84.42 | 0.00 | 96.22 | 0.00 | 49.64 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.2378684372 |
| 83.08 | 0.68 | 93.81 | 0.67 | 83.03 | 1.84 | 88.19 | 0.00 | 85.33 | 1.33 | 85.31 | 0.88 | 96.22 | 0.00 | 49.64 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.2086849617 |
| 83.73 | 0.66 | 94.32 | 0.52 | 84.16 | 1.13 | 88.74 | 0.55 | 86.67 | 1.33 | 86.37 | 1.06 | 96.22 | 0.00 | 49.64 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.80797109 |
| 84.23 | 0.50 | 94.74 | 0.41 | 84.72 | 0.57 | 89.37 | 0.63 | 88.00 | 1.33 | 86.90 | 0.53 | 96.22 | 0.00 | 49.64 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.3636382525 |
| 84.65 | 0.42 | 95.20 | 0.46 | 85.57 | 0.85 | 90.13 | 0.76 | 88.00 | 0.00 | 87.43 | 0.53 | 96.22 | 0.00 | 50.00 | 0.36 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.101283481 |
| 85.03 | 0.38 | 95.20 | 0.00 | 85.57 | 0.00 | 90.13 | 0.00 | 90.67 | 2.67 | 87.43 | 0.00 | 96.22 | 0.00 | 50.00 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2046897656 |
| 85.40 | 0.36 | 95.30 | 0.10 | 86.00 | 0.42 | 90.46 | 0.34 | 92.00 | 1.33 | 87.79 | 0.35 | 96.22 | 0.00 | 50.00 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all_with_rand_reset.767430930 |
| 85.74 | 0.35 | 95.30 | 0.00 | 88.26 | 2.26 | 90.50 | 0.04 | 92.00 | 0.00 | 87.79 | 0.00 | 96.22 | 0.00 | 50.12 | 0.12 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.3524649269 |
| 85.98 | 0.24 | 95.30 | 0.00 | 88.26 | 0.00 | 90.50 | 0.00 | 92.00 | 0.00 | 87.79 | 0.00 | 97.90 | 1.68 | 50.12 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.466739983 |
| 86.18 | 0.20 | 95.30 | 0.00 | 88.26 | 0.00 | 90.55 | 0.04 | 93.33 | 1.33 | 87.79 | 0.00 | 97.90 | 0.00 | 50.12 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.730571388 |
| 86.37 | 0.19 | 95.30 | 0.00 | 88.26 | 0.00 | 90.55 | 0.00 | 94.67 | 1.33 | 87.79 | 0.00 | 97.90 | 0.00 | 50.12 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.450554767 |
| 86.55 | 0.19 | 95.51 | 0.21 | 88.40 | 0.14 | 90.71 | 0.17 | 94.67 | 0.00 | 87.96 | 0.18 | 97.90 | 0.00 | 50.72 | 0.60 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/26.rv_dm_stress_all.2421440998 |
| 86.73 | 0.17 | 95.72 | 0.21 | 88.54 | 0.14 | 90.76 | 0.04 | 94.67 | 0.00 | 88.67 | 0.71 | 97.90 | 0.00 | 50.85 | 0.12 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.4053242213 |
| 86.87 | 0.15 | 95.98 | 0.26 | 88.83 | 0.28 | 90.76 | 0.00 | 94.67 | 0.00 | 89.03 | 0.35 | 97.90 | 0.00 | 50.97 | 0.12 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/15.rv_dm_stress_all.1321561341 |
| 87.01 | 0.14 | 96.03 | 0.05 | 88.83 | 0.00 | 90.88 | 0.13 | 94.67 | 0.00 | 89.20 | 0.18 | 97.90 | 0.00 | 51.57 | 0.60 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.3986098699 |
| 87.14 | 0.13 | 96.03 | 0.00 | 89.25 | 0.42 | 91.05 | 0.17 | 94.67 | 0.00 | 89.20 | 0.00 | 98.00 | 0.11 | 51.81 | 0.24 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.1186131254 |
| 87.26 | 0.12 | 96.03 | 0.00 | 89.25 | 0.00 | 91.39 | 0.34 | 94.67 | 0.00 | 89.20 | 0.00 | 98.00 | 0.00 | 52.29 | 0.48 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2130256846 |
| 87.38 | 0.12 | 96.03 | 0.00 | 89.25 | 0.00 | 91.47 | 0.08 | 94.67 | 0.00 | 89.20 | 0.00 | 98.00 | 0.00 | 53.02 | 0.72 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/13.rv_dm_autoincr_sba_tl_access.2974442448 |
| 87.46 | 0.09 | 96.23 | 0.21 | 89.25 | 0.00 | 91.51 | 0.04 | 94.67 | 0.00 | 89.56 | 0.35 | 98.00 | 0.00 | 53.02 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.2067613534 |
| 87.54 | 0.08 | 96.28 | 0.05 | 89.39 | 0.14 | 91.51 | 0.00 | 94.67 | 0.00 | 89.91 | 0.35 | 98.00 | 0.00 | 53.02 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.3777482386 |
| 87.61 | 0.06 | 96.28 | 0.00 | 89.39 | 0.00 | 91.60 | 0.08 | 94.67 | 0.00 | 89.91 | 0.00 | 98.00 | 0.00 | 53.38 | 0.36 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3777767983 |
| 87.67 | 0.06 | 96.28 | 0.00 | 89.39 | 0.00 | 91.68 | 0.08 | 94.67 | 0.00 | 89.91 | 0.00 | 98.00 | 0.00 | 53.74 | 0.36 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/18.rv_dm_autoincr_sba_tl_access.1756614506 |
| 87.73 | 0.06 | 96.28 | 0.00 | 89.53 | 0.14 | 91.68 | 0.00 | 94.67 | 0.00 | 90.09 | 0.18 | 98.00 | 0.00 | 53.86 | 0.12 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.1563429154 |
| 87.79 | 0.06 | 96.28 | 0.00 | 89.53 | 0.00 | 91.85 | 0.17 | 94.67 | 0.00 | 90.09 | 0.00 | 98.00 | 0.00 | 54.11 | 0.24 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/13.rv_dm_bad_sba_tl_access.960252200 |
| 87.84 | 0.05 | 96.28 | 0.00 | 89.53 | 0.00 | 91.85 | 0.00 | 94.67 | 0.00 | 90.09 | 0.00 | 98.00 | 0.00 | 54.47 | 0.36 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/28.rv_dm_stress_all.460121276 |
| 87.89 | 0.05 | 96.28 | 0.00 | 89.53 | 0.00 | 91.85 | 0.00 | 94.67 | 0.00 | 90.09 | 0.00 | 98.00 | 0.00 | 54.83 | 0.36 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.2389385950 |
| 87.94 | 0.05 | 96.28 | 0.00 | 89.53 | 0.00 | 91.97 | 0.13 | 94.67 | 0.00 | 90.09 | 0.00 | 98.11 | 0.11 | 54.95 | 0.12 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.1859491024 |
| 87.99 | 0.04 | 96.28 | 0.00 | 89.53 | 0.00 | 92.06 | 0.08 | 94.67 | 0.00 | 90.09 | 0.00 | 98.32 | 0.21 | 54.95 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3708990179 |
| 88.02 | 0.03 | 96.28 | 0.00 | 89.53 | 0.00 | 92.06 | 0.00 | 94.67 | 0.00 | 90.09 | 0.00 | 98.32 | 0.00 | 55.19 | 0.24 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.478535879 |
| 88.06 | 0.03 | 96.28 | 0.00 | 89.53 | 0.00 | 92.06 | 0.00 | 94.67 | 0.00 | 90.09 | 0.00 | 98.32 | 0.00 | 55.43 | 0.24 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.2934799504 |
| 88.09 | 0.03 | 96.34 | 0.05 | 89.53 | 0.00 | 92.06 | 0.00 | 94.67 | 0.00 | 90.27 | 0.18 | 98.32 | 0.00 | 55.43 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3318272337 |
| 88.12 | 0.03 | 96.34 | 0.00 | 89.53 | 0.00 | 92.06 | 0.00 | 94.67 | 0.00 | 90.27 | 0.00 | 98.53 | 0.21 | 55.43 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1032707583 |
| 88.14 | 0.03 | 96.34 | 0.00 | 89.67 | 0.14 | 92.10 | 0.04 | 94.67 | 0.00 | 90.27 | 0.00 | 98.53 | 0.00 | 55.43 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.30370962 |
| 88.16 | 0.02 | 96.34 | 0.00 | 89.82 | 0.14 | 92.10 | 0.00 | 94.67 | 0.00 | 90.27 | 0.00 | 98.53 | 0.00 | 55.43 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.1211377807 |
| 88.18 | 0.02 | 96.34 | 0.00 | 89.82 | 0.00 | 92.10 | 0.00 | 94.67 | 0.00 | 90.27 | 0.00 | 98.53 | 0.00 | 55.56 | 0.12 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2971854135 |
| 88.20 | 0.02 | 96.34 | 0.00 | 89.82 | 0.00 | 92.10 | 0.00 | 94.67 | 0.00 | 90.27 | 0.00 | 98.53 | 0.00 | 55.68 | 0.12 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_intg_err.4019504875 |
| 88.22 | 0.02 | 96.34 | 0.00 | 89.82 | 0.00 | 92.10 | 0.00 | 94.67 | 0.00 | 90.27 | 0.00 | 98.53 | 0.00 | 55.80 | 0.12 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_hart_unavail.3628463297 |
| 88.23 | 0.02 | 96.34 | 0.00 | 89.82 | 0.00 | 92.10 | 0.00 | 94.67 | 0.00 | 90.27 | 0.00 | 98.53 | 0.00 | 55.92 | 0.12 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.4011395699 |
| 88.25 | 0.02 | 96.34 | 0.00 | 89.82 | 0.00 | 92.10 | 0.00 | 94.67 | 0.00 | 90.27 | 0.00 | 98.53 | 0.00 | 56.04 | 0.12 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_bad_sba_tl_access.3329490997 |
| 88.27 | 0.02 | 96.34 | 0.00 | 89.82 | 0.00 | 92.10 | 0.00 | 94.67 | 0.00 | 90.27 | 0.00 | 98.53 | 0.00 | 56.16 | 0.12 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3999088903 |
| 88.29 | 0.02 | 96.34 | 0.00 | 89.82 | 0.00 | 92.10 | 0.00 | 94.67 | 0.00 | 90.27 | 0.00 | 98.53 | 0.00 | 56.28 | 0.12 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/11.rv_dm_autoincr_sba_tl_access.1530762951 |
| 88.30 | 0.02 | 96.34 | 0.00 | 89.82 | 0.00 | 92.10 | 0.00 | 94.67 | 0.00 | 90.27 | 0.00 | 98.53 | 0.00 | 56.40 | 0.12 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/11.rv_dm_stress_all.238458297 |
| 88.32 | 0.02 | 96.34 | 0.00 | 89.82 | 0.00 | 92.10 | 0.00 | 94.67 | 0.00 | 90.27 | 0.00 | 98.53 | 0.00 | 56.52 | 0.12 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/12.rv_dm_stress_all.1723960590 |
| 88.34 | 0.02 | 96.34 | 0.00 | 89.82 | 0.00 | 92.10 | 0.00 | 94.67 | 0.00 | 90.27 | 0.00 | 98.53 | 0.00 | 56.64 | 0.12 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/13.rv_dm_sba_tl_access.1382947153 |
| 88.35 | 0.02 | 96.34 | 0.00 | 89.82 | 0.00 | 92.10 | 0.00 | 94.67 | 0.00 | 90.27 | 0.00 | 98.53 | 0.00 | 56.76 | 0.12 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/13.rv_dm_stress_all.1951521606 |
| 88.37 | 0.02 | 96.34 | 0.00 | 89.82 | 0.00 | 92.10 | 0.00 | 94.67 | 0.00 | 90.27 | 0.00 | 98.53 | 0.00 | 56.88 | 0.12 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/14.rv_dm_stress_all.1968014591 |
| 88.39 | 0.02 | 96.34 | 0.00 | 89.82 | 0.00 | 92.10 | 0.00 | 94.67 | 0.00 | 90.27 | 0.00 | 98.53 | 0.00 | 57.00 | 0.12 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/18.rv_dm_bad_sba_tl_access.1598919154 |
| 88.41 | 0.02 | 96.34 | 0.00 | 89.82 | 0.00 | 92.10 | 0.00 | 94.67 | 0.00 | 90.27 | 0.00 | 98.53 | 0.00 | 57.13 | 0.12 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.1169255270 |
| 88.42 | 0.02 | 96.34 | 0.00 | 89.82 | 0.00 | 92.10 | 0.00 | 94.67 | 0.00 | 90.27 | 0.00 | 98.53 | 0.00 | 57.25 | 0.12 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.1479934986 |
| 88.44 | 0.02 | 96.34 | 0.00 | 89.82 | 0.00 | 92.10 | 0.00 | 94.67 | 0.00 | 90.27 | 0.00 | 98.53 | 0.00 | 57.37 | 0.12 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/36.rv_dm_stress_all.126361944 |
| 88.46 | 0.02 | 96.34 | 0.00 | 89.82 | 0.00 | 92.10 | 0.00 | 94.67 | 0.00 | 90.27 | 0.00 | 98.53 | 0.00 | 57.49 | 0.12 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/38.rv_dm_stress_all.2248067642 |
| 88.47 | 0.02 | 96.34 | 0.00 | 89.82 | 0.00 | 92.10 | 0.00 | 94.67 | 0.00 | 90.27 | 0.00 | 98.63 | 0.11 | 57.49 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_rw.984064467 |
| 88.49 | 0.02 | 96.34 | 0.00 | 89.82 | 0.00 | 92.10 | 0.00 | 94.67 | 0.00 | 90.27 | 0.00 | 98.74 | 0.11 | 57.49 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.2930526603 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1759210381 |
| /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.4086489300 |
| /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.675028227 |
| /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2916885071 |
| /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1936931227 |
| /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1784094195 |
| /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.973053532 |
| /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2896351022 |
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| /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.1544541580 |
| /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/9.rv_dm_buffered_enable.3435686961 |
| /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.2968612932 |
| /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.2192847245 |
| /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.36351390 |
| /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.2984507246 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_smoke.3634977572 | Oct 02 09:01:02 PM UTC 24 | Oct 02 09:01:05 PM UTC 24 | 627496084 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.2282138041 | Oct 02 09:01:04 PM UTC 24 | Oct 02 09:01:07 PM UTC 24 | 149001483 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_tl_access.621589781 | Oct 02 09:01:02 PM UTC 24 | Oct 02 09:01:07 PM UTC 24 | 2098006931 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.270717177 | Oct 02 09:01:03 PM UTC 24 | Oct 02 09:01:08 PM UTC 24 | 1606348849 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.645204246 | Oct 02 09:01:06 PM UTC 24 | Oct 02 09:01:08 PM UTC 24 | 202980034 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_halted.4023114287 | Oct 02 09:01:06 PM UTC 24 | Oct 02 09:01:08 PM UTC 24 | 626581101 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_busy.4213525611 | Oct 02 09:01:03 PM UTC 24 | Oct 02 09:01:09 PM UTC 24 | 1101477830 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_hart_unavail.3628463297 | Oct 02 09:01:08 PM UTC 24 | Oct 02 09:01:10 PM UTC 24 | 152564475 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_resuming.3463243168 | Oct 02 09:01:08 PM UTC 24 | Oct 02 09:01:11 PM UTC 24 | 117044517 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.1563429154 | Oct 02 09:01:09 PM UTC 24 | Oct 02 09:01:27 PM UTC 24 | 4977120276 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.1937233552 | Oct 02 09:01:08 PM UTC 24 | Oct 02 09:01:11 PM UTC 24 | 414997219 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.759580240 | Oct 02 09:01:09 PM UTC 24 | Oct 02 09:01:12 PM UTC 24 | 97974814 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.3720909665 | Oct 02 09:01:09 PM UTC 24 | Oct 02 09:01:12 PM UTC 24 | 449974366 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_hard_reset.3569168512 | Oct 02 09:01:09 PM UTC 24 | Oct 02 09:01:12 PM UTC 24 | 121291107 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_idle_hint.4030938044 | Oct 02 09:01:09 PM UTC 24 | Oct 02 09:01:12 PM UTC 24 | 238815373 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.353660194 | Oct 02 09:01:09 PM UTC 24 | Oct 02 09:01:12 PM UTC 24 | 820274471 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_dataaddr_rw_access.1924167061 | Oct 02 09:01:09 PM UTC 24 | Oct 02 09:01:12 PM UTC 24 | 317362229 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.3777482386 | Oct 02 09:01:11 PM UTC 24 | Oct 02 09:01:13 PM UTC 24 | 43304190 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.2067613534 | Oct 02 09:01:09 PM UTC 24 | Oct 02 09:01:13 PM UTC 24 | 639499411 ps | ||
| T88 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_debug_disabled.124362810 | Oct 02 09:01:11 PM UTC 24 | Oct 02 09:01:13 PM UTC 24 | 47657743 ps | ||
| T77 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.3524649269 | Oct 02 09:01:12 PM UTC 24 | Oct 02 09:01:14 PM UTC 24 | 42765350 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.1998803133 | Oct 02 09:01:11 PM UTC 24 | Oct 02 09:01:14 PM UTC 24 | 228748666 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_hartsel_warl.1910468164 | Oct 02 09:01:12 PM UTC 24 | Oct 02 09:01:14 PM UTC 24 | 269141552 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.1859491024 | Oct 02 09:01:12 PM UTC 24 | Oct 02 09:01:14 PM UTC 24 | 79919859 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.2180336319 | Oct 02 09:01:03 PM UTC 24 | Oct 02 09:01:14 PM UTC 24 | 9970174094 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.3636382525 | Oct 02 09:01:12 PM UTC 24 | Oct 02 09:01:15 PM UTC 24 | 241137015 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1354671296 | Oct 02 09:01:09 PM UTC 24 | Oct 02 09:01:15 PM UTC 24 | 1105030265 ps | ||
| T51 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.101283481 | Oct 02 09:01:13 PM UTC 24 | Oct 02 09:01:16 PM UTC 24 | 91490441 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.617283171 | Oct 02 09:01:12 PM UTC 24 | Oct 02 09:01:16 PM UTC 24 | 508552752 ps | ||
| T97 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_hart_unavail.3508279433 | Oct 02 09:01:15 PM UTC 24 | Oct 02 09:01:17 PM UTC 24 | 97582953 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.1186131254 | Oct 02 09:01:13 PM UTC 24 | Oct 02 09:01:17 PM UTC 24 | 428544805 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_dataaddr_rw_access.2957656031 | Oct 02 09:01:15 PM UTC 24 | Oct 02 09:01:17 PM UTC 24 | 172329883 ps | ||
| T96 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_halted.3258899502 | Oct 02 09:01:15 PM UTC 24 | Oct 02 09:01:17 PM UTC 24 | 193834347 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.4053242213 | Oct 02 09:01:15 PM UTC 24 | Oct 02 09:01:17 PM UTC 24 | 372186018 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_busy.99254630 | Oct 02 09:01:15 PM UTC 24 | Oct 02 09:01:17 PM UTC 24 | 191546392 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_halt_resume_whereto.1459341293 | Oct 02 09:01:15 PM UTC 24 | Oct 02 09:01:17 PM UTC 24 | 249794840 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_not_supported.1250145620 | Oct 02 09:01:15 PM UTC 24 | Oct 02 09:01:18 PM UTC 24 | 171571561 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.30370962 | Oct 02 09:01:15 PM UTC 24 | Oct 02 09:01:18 PM UTC 24 | 469739580 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_resuming.4039384157 | Oct 02 09:01:15 PM UTC 24 | Oct 02 09:01:18 PM UTC 24 | 775904023 ps | ||
| T78 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_idle_hint.215469692 | Oct 02 09:01:16 PM UTC 24 | Oct 02 09:01:18 PM UTC 24 | 265195616 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_ndmreset_req.760847677 | Oct 02 09:01:16 PM UTC 24 | Oct 02 09:01:19 PM UTC 24 | 162999729 ps | ||
| T266 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1129775419 | Oct 02 09:01:16 PM UTC 24 | Oct 02 09:01:20 PM UTC 24 | 898999593 ps | ||
| T80 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_smoke.4172595462 | Oct 02 09:01:13 PM UTC 24 | Oct 02 09:01:20 PM UTC 24 | 1321461431 ps | ||
| T76 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3999088903 | Oct 02 09:01:18 PM UTC 24 | Oct 02 09:01:20 PM UTC 24 | 445894102 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_abstractcmd_status.1528221982 | Oct 02 09:01:18 PM UTC 24 | Oct 02 09:01:20 PM UTC 24 | 77497615 ps | ||
| T87 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.594377223 | Oct 02 09:01:14 PM UTC 24 | Oct 02 09:01:21 PM UTC 24 | 4816804202 ps | ||
| T115 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.1449508939 | Oct 02 09:01:21 PM UTC 24 | Oct 02 09:01:32 PM UTC 24 | 1992053586 ps | ||
| T166 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_debug_disabled.3497777248 | Oct 02 09:01:16 PM UTC 24 | Oct 02 09:01:21 PM UTC 24 | 3766562713 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_rom_read_access.1488273019 | Oct 02 09:01:19 PM UTC 24 | Oct 02 09:01:21 PM UTC 24 | 85321834 ps | ||
| T84 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_buffered_enable.3070987922 | Oct 02 09:01:19 PM UTC 24 | Oct 02 09:01:21 PM UTC 24 | 124200221 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.1624054176 | Oct 02 09:01:19 PM UTC 24 | Oct 02 09:01:21 PM UTC 24 | 327236505 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.1553640266 | Oct 02 09:01:19 PM UTC 24 | Oct 02 09:01:22 PM UTC 24 | 320129313 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_progbuf_read_write_execute.2507524800 | Oct 02 09:01:19 PM UTC 24 | Oct 02 09:01:22 PM UTC 24 | 183150650 ps | ||
| T52 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_alert_test.2544281509 | Oct 02 09:01:19 PM UTC 24 | Oct 02 09:01:22 PM UTC 24 | 35117193 ps | ||
| T91 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_debug_disabled.3906174881 | Oct 02 09:01:19 PM UTC 24 | Oct 02 09:01:22 PM UTC 24 | 125132606 ps | ||
| T141 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.872351877 | Oct 02 09:01:21 PM UTC 24 | Oct 02 09:01:23 PM UTC 24 | 85235513 ps | ||
| T59 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.4294519712 | Oct 02 09:01:21 PM UTC 24 | Oct 02 09:01:23 PM UTC 24 | 230466367 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.4011395699 | Oct 02 09:01:13 PM UTC 24 | Oct 02 09:01:24 PM UTC 24 | 2580330022 ps | ||
| T92 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.418650897 | Oct 02 09:01:18 PM UTC 24 | Oct 02 09:01:24 PM UTC 24 | 725924338 ps | ||
| T198 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_hart_unavail.566102143 | Oct 02 09:01:25 PM UTC 24 | Oct 02 09:01:27 PM UTC 24 | 65818048 ps | ||
| T89 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_sec_cm.3352044674 | Oct 02 09:01:19 PM UTC 24 | Oct 02 09:01:24 PM UTC 24 | 1185501408 ps | ||
| T83 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_sparse_lc_gate_fsm.2111135103 | Oct 02 09:01:22 PM UTC 24 | Oct 02 09:01:24 PM UTC 24 | 63216197 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.2865945938 | Oct 02 09:01:22 PM UTC 24 | Oct 02 09:01:25 PM UTC 24 | 70338781 ps | ||
| T116 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_bad_sba_tl_access.3329490997 | Oct 02 09:01:14 PM UTC 24 | Oct 02 09:01:25 PM UTC 24 | 3933050001 ps | ||
| T86 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.2086849617 | Oct 02 09:01:21 PM UTC 24 | Oct 02 09:01:25 PM UTC 24 | 566393482 ps | ||
| T165 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.3415665785 | Oct 02 09:01:25 PM UTC 24 | Oct 02 09:01:27 PM UTC 24 | 175904188 ps | ||
| T85 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.2930526603 | Oct 02 09:01:25 PM UTC 24 | Oct 02 09:01:27 PM UTC 24 | 99026035 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.1784558580 | Oct 02 09:01:25 PM UTC 24 | Oct 02 09:01:28 PM UTC 24 | 528519841 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all.625481385 | Oct 02 09:01:22 PM UTC 24 | Oct 02 09:01:28 PM UTC 24 | 5006714876 ps | ||
| T98 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1945173249 | Oct 02 09:01:22 PM UTC 24 | Oct 02 09:01:28 PM UTC 24 | 1177882376 ps | ||
| T90 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.838660093 | Oct 02 09:01:22 PM UTC 24 | Oct 02 09:01:29 PM UTC 24 | 2706959853 ps | ||
| T99 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.258738182 | Oct 02 09:01:26 PM UTC 24 | Oct 02 09:01:29 PM UTC 24 | 97848181 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_autoincr_sba_tl_access.2685870770 | Oct 02 09:01:15 PM UTC 24 | Oct 02 09:01:30 PM UTC 24 | 6054279028 ps | ||
| T94 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_sec_cm.969873188 | Oct 02 09:01:26 PM UTC 24 | Oct 02 09:01:30 PM UTC 24 | 1270757701 ps | ||
| T100 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.1181031943 | Oct 02 09:01:19 PM UTC 24 | Oct 02 09:01:31 PM UTC 24 | 11406519035 ps | ||
| T101 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.4178330350 | Oct 02 09:01:28 PM UTC 24 | Oct 02 09:01:31 PM UTC 24 | 268648842 ps | ||
| T134 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_sba_tl_access.2337268435 | Oct 02 09:01:26 PM UTC 24 | Oct 02 09:01:31 PM UTC 24 | 991504119 ps | ||
| T167 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.178962650 | Oct 02 09:01:23 PM UTC 24 | Oct 02 09:01:32 PM UTC 24 | 1775648925 ps | ||
| T81 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.4229835236 | Oct 02 09:01:02 PM UTC 24 | Oct 02 09:01:33 PM UTC 24 | 6742510756 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.2104607706 | Oct 02 09:01:23 PM UTC 24 | Oct 02 09:01:32 PM UTC 24 | 6041751091 ps | ||
| T207 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.3986098699 | Oct 02 09:01:03 PM UTC 24 | Oct 02 09:01:32 PM UTC 24 | 8818824889 ps | ||
| T263 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.1674229581 | Oct 02 09:01:28 PM UTC 24 | Oct 02 09:01:32 PM UTC 24 | 594467017 ps | ||
| T267 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/14.rv_dm_sba_tl_access.2067600260 | Oct 02 09:01:56 PM UTC 24 | Oct 02 09:02:08 PM UTC 24 | 3354372458 ps | ||
| T208 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_buffered_enable.2379914608 | Oct 02 09:01:30 PM UTC 24 | Oct 02 09:01:33 PM UTC 24 | 461747738 ps | ||
| T214 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.1169255270 | Oct 02 09:01:22 PM UTC 24 | Oct 02 09:01:33 PM UTC 24 | 4326813674 ps | ||
| T162 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_alert_test.559828422 | Oct 02 09:01:31 PM UTC 24 | Oct 02 09:01:33 PM UTC 24 | 118327916 ps | ||
| T61 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.3177766452 | Oct 02 09:01:29 PM UTC 24 | Oct 02 09:01:33 PM UTC 24 | 516381493 ps | ||
| T95 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_sec_cm.1677284121 | Oct 02 09:01:30 PM UTC 24 | Oct 02 09:01:34 PM UTC 24 | 1219617985 ps | ||
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| T111 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.2760639153 | Oct 02 09:01:13 PM UTC 24 | Oct 02 09:02:18 PM UTC 24 | 2392961462 ps | ||
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