Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.49 96.34 89.82 92.10 94.67 90.27 98.74 57.49


Total tests in report: 483
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
52.33 52.33 83.90 83.90 47.67 47.67 32.44 32.44 44.00 44.00 63.19 63.19 93.07 93.07 2.05 2.05 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.270717177
61.59 9.26 85.55 1.65 56.29 8.63 35.13 2.69 49.33 5.33 68.50 5.31 94.33 1.26 42.03 39.98 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.3223897393
69.54 7.94 87.56 2.01 67.89 11.60 67.56 32.44 50.67 1.33 72.92 4.42 95.59 1.26 44.57 2.54 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.759580240
73.98 4.44 90.92 3.35 72.14 4.24 71.68 4.12 62.67 12.00 79.12 6.19 95.90 0.32 45.41 0.85 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all.625481385
76.31 2.33 91.95 1.03 76.66 4.53 72.14 0.46 70.67 8.00 81.06 1.95 95.90 0.00 45.77 0.36 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_busy.4213525611
78.42 2.11 92.93 0.98 78.36 1.70 77.31 5.17 74.67 4.00 83.19 2.12 96.11 0.21 46.38 0.60 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.2180336319
79.96 1.54 92.98 0.05 78.78 0.42 87.35 10.04 74.67 0.00 83.36 0.18 96.22 0.11 46.38 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_halt_resume_whereto.1459341293
80.82 0.86 93.09 0.10 80.34 1.56 88.03 0.67 74.67 0.00 83.89 0.53 96.22 0.00 49.52 3.14 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3703437226
81.63 0.81 93.14 0.05 81.19 0.85 88.15 0.13 78.67 4.00 84.42 0.53 96.22 0.00 49.64 0.12 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.4229835236
82.40 0.77 93.14 0.00 81.19 0.00 88.19 0.04 84.00 5.33 84.42 0.00 96.22 0.00 49.64 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.2378684372
83.08 0.68 93.81 0.67 83.03 1.84 88.19 0.00 85.33 1.33 85.31 0.88 96.22 0.00 49.64 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.2086849617
83.73 0.66 94.32 0.52 84.16 1.13 88.74 0.55 86.67 1.33 86.37 1.06 96.22 0.00 49.64 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.80797109
84.23 0.50 94.74 0.41 84.72 0.57 89.37 0.63 88.00 1.33 86.90 0.53 96.22 0.00 49.64 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.3636382525
84.65 0.42 95.20 0.46 85.57 0.85 90.13 0.76 88.00 0.00 87.43 0.53 96.22 0.00 50.00 0.36 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.101283481
85.03 0.38 95.20 0.00 85.57 0.00 90.13 0.00 90.67 2.67 87.43 0.00 96.22 0.00 50.00 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2046897656
85.40 0.36 95.30 0.10 86.00 0.42 90.46 0.34 92.00 1.33 87.79 0.35 96.22 0.00 50.00 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all_with_rand_reset.767430930
85.74 0.35 95.30 0.00 88.26 2.26 90.50 0.04 92.00 0.00 87.79 0.00 96.22 0.00 50.12 0.12 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.3524649269
85.98 0.24 95.30 0.00 88.26 0.00 90.50 0.00 92.00 0.00 87.79 0.00 97.90 1.68 50.12 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.466739983
86.18 0.20 95.30 0.00 88.26 0.00 90.55 0.04 93.33 1.33 87.79 0.00 97.90 0.00 50.12 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.730571388
86.37 0.19 95.30 0.00 88.26 0.00 90.55 0.00 94.67 1.33 87.79 0.00 97.90 0.00 50.12 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.450554767
86.55 0.19 95.51 0.21 88.40 0.14 90.71 0.17 94.67 0.00 87.96 0.18 97.90 0.00 50.72 0.60 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/26.rv_dm_stress_all.2421440998
86.73 0.17 95.72 0.21 88.54 0.14 90.76 0.04 94.67 0.00 88.67 0.71 97.90 0.00 50.85 0.12 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.4053242213
86.87 0.15 95.98 0.26 88.83 0.28 90.76 0.00 94.67 0.00 89.03 0.35 97.90 0.00 50.97 0.12 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/15.rv_dm_stress_all.1321561341
87.01 0.14 96.03 0.05 88.83 0.00 90.88 0.13 94.67 0.00 89.20 0.18 97.90 0.00 51.57 0.60 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.3986098699
87.14 0.13 96.03 0.00 89.25 0.42 91.05 0.17 94.67 0.00 89.20 0.00 98.00 0.11 51.81 0.24 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.1186131254
87.26 0.12 96.03 0.00 89.25 0.00 91.39 0.34 94.67 0.00 89.20 0.00 98.00 0.00 52.29 0.48 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2130256846
87.38 0.12 96.03 0.00 89.25 0.00 91.47 0.08 94.67 0.00 89.20 0.00 98.00 0.00 53.02 0.72 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/13.rv_dm_autoincr_sba_tl_access.2974442448
87.46 0.09 96.23 0.21 89.25 0.00 91.51 0.04 94.67 0.00 89.56 0.35 98.00 0.00 53.02 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.2067613534
87.54 0.08 96.28 0.05 89.39 0.14 91.51 0.00 94.67 0.00 89.91 0.35 98.00 0.00 53.02 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.3777482386
87.61 0.06 96.28 0.00 89.39 0.00 91.60 0.08 94.67 0.00 89.91 0.00 98.00 0.00 53.38 0.36 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3777767983
87.67 0.06 96.28 0.00 89.39 0.00 91.68 0.08 94.67 0.00 89.91 0.00 98.00 0.00 53.74 0.36 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/18.rv_dm_autoincr_sba_tl_access.1756614506
87.73 0.06 96.28 0.00 89.53 0.14 91.68 0.00 94.67 0.00 90.09 0.18 98.00 0.00 53.86 0.12 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.1563429154
87.79 0.06 96.28 0.00 89.53 0.00 91.85 0.17 94.67 0.00 90.09 0.00 98.00 0.00 54.11 0.24 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/13.rv_dm_bad_sba_tl_access.960252200
87.84 0.05 96.28 0.00 89.53 0.00 91.85 0.00 94.67 0.00 90.09 0.00 98.00 0.00 54.47 0.36 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/28.rv_dm_stress_all.460121276
87.89 0.05 96.28 0.00 89.53 0.00 91.85 0.00 94.67 0.00 90.09 0.00 98.00 0.00 54.83 0.36 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.2389385950
87.94 0.05 96.28 0.00 89.53 0.00 91.97 0.13 94.67 0.00 90.09 0.00 98.11 0.11 54.95 0.12 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.1859491024
87.99 0.04 96.28 0.00 89.53 0.00 92.06 0.08 94.67 0.00 90.09 0.00 98.32 0.21 54.95 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3708990179
88.02 0.03 96.28 0.00 89.53 0.00 92.06 0.00 94.67 0.00 90.09 0.00 98.32 0.00 55.19 0.24 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.478535879
88.06 0.03 96.28 0.00 89.53 0.00 92.06 0.00 94.67 0.00 90.09 0.00 98.32 0.00 55.43 0.24 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.2934799504
88.09 0.03 96.34 0.05 89.53 0.00 92.06 0.00 94.67 0.00 90.27 0.18 98.32 0.00 55.43 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3318272337
88.12 0.03 96.34 0.00 89.53 0.00 92.06 0.00 94.67 0.00 90.27 0.00 98.53 0.21 55.43 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1032707583
88.14 0.03 96.34 0.00 89.67 0.14 92.10 0.04 94.67 0.00 90.27 0.00 98.53 0.00 55.43 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.30370962
88.16 0.02 96.34 0.00 89.82 0.14 92.10 0.00 94.67 0.00 90.27 0.00 98.53 0.00 55.43 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.1211377807
88.18 0.02 96.34 0.00 89.82 0.00 92.10 0.00 94.67 0.00 90.27 0.00 98.53 0.00 55.56 0.12 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2971854135
88.20 0.02 96.34 0.00 89.82 0.00 92.10 0.00 94.67 0.00 90.27 0.00 98.53 0.00 55.68 0.12 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_intg_err.4019504875
88.22 0.02 96.34 0.00 89.82 0.00 92.10 0.00 94.67 0.00 90.27 0.00 98.53 0.00 55.80 0.12 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_hart_unavail.3628463297
88.23 0.02 96.34 0.00 89.82 0.00 92.10 0.00 94.67 0.00 90.27 0.00 98.53 0.00 55.92 0.12 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.4011395699
88.25 0.02 96.34 0.00 89.82 0.00 92.10 0.00 94.67 0.00 90.27 0.00 98.53 0.00 56.04 0.12 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_bad_sba_tl_access.3329490997
88.27 0.02 96.34 0.00 89.82 0.00 92.10 0.00 94.67 0.00 90.27 0.00 98.53 0.00 56.16 0.12 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3999088903
88.29 0.02 96.34 0.00 89.82 0.00 92.10 0.00 94.67 0.00 90.27 0.00 98.53 0.00 56.28 0.12 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/11.rv_dm_autoincr_sba_tl_access.1530762951
88.30 0.02 96.34 0.00 89.82 0.00 92.10 0.00 94.67 0.00 90.27 0.00 98.53 0.00 56.40 0.12 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/11.rv_dm_stress_all.238458297
88.32 0.02 96.34 0.00 89.82 0.00 92.10 0.00 94.67 0.00 90.27 0.00 98.53 0.00 56.52 0.12 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/12.rv_dm_stress_all.1723960590
88.34 0.02 96.34 0.00 89.82 0.00 92.10 0.00 94.67 0.00 90.27 0.00 98.53 0.00 56.64 0.12 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/13.rv_dm_sba_tl_access.1382947153
88.35 0.02 96.34 0.00 89.82 0.00 92.10 0.00 94.67 0.00 90.27 0.00 98.53 0.00 56.76 0.12 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/13.rv_dm_stress_all.1951521606
88.37 0.02 96.34 0.00 89.82 0.00 92.10 0.00 94.67 0.00 90.27 0.00 98.53 0.00 56.88 0.12 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/14.rv_dm_stress_all.1968014591
88.39 0.02 96.34 0.00 89.82 0.00 92.10 0.00 94.67 0.00 90.27 0.00 98.53 0.00 57.00 0.12 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/18.rv_dm_bad_sba_tl_access.1598919154
88.41 0.02 96.34 0.00 89.82 0.00 92.10 0.00 94.67 0.00 90.27 0.00 98.53 0.00 57.13 0.12 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.1169255270
88.42 0.02 96.34 0.00 89.82 0.00 92.10 0.00 94.67 0.00 90.27 0.00 98.53 0.00 57.25 0.12 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.1479934986
88.44 0.02 96.34 0.00 89.82 0.00 92.10 0.00 94.67 0.00 90.27 0.00 98.53 0.00 57.37 0.12 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/36.rv_dm_stress_all.126361944
88.46 0.02 96.34 0.00 89.82 0.00 92.10 0.00 94.67 0.00 90.27 0.00 98.53 0.00 57.49 0.12 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/38.rv_dm_stress_all.2248067642
88.47 0.02 96.34 0.00 89.82 0.00 92.10 0.00 94.67 0.00 90.27 0.00 98.63 0.11 57.49 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_rw.984064467
88.49 0.02 96.34 0.00 89.82 0.00 92.10 0.00 94.67 0.00 90.27 0.00 98.74 0.11 57.49 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.2930526603

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1759210381
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.4086489300
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.675028227
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2916885071
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1936931227
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1784094195
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.973053532
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2896351022
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1480764802
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.4245157626
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2927235294
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.4076012118
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.113155025
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.2029940391
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1599445191
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1922798719
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.22256140
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2042285293
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.2138284292
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.493638234
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2246999753
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1039428652
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2417479787
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.852788335
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2254340795
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1822972136
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.982044297
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.4287932458
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.490991227
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3328304546
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3261767291
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.4219915122
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2675197568
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1939008408
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.1029663685
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2748878016
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3912207501
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1354648531
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.324057403
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.1897328891
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1854830421
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1199633788
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_rw.1044649332
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1805776427
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1009622931
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1924274401
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3408973651
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_errors.2418874012
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.315491905
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_rw.398071852
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2042982575
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.152151234
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.4252560167
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3048182445
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_errors.1408959645
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1658202328
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1455597243
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_rw.757257017
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.3468466494
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3205912195
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2886840144
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2895824559
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_errors.1747945580
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3184730057
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3836119386
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_rw.3879131341
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.2605683497
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2013561726
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1682351515
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1520502255
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_errors.3112976858
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_intg_err.919268313
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.614823140
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_rw.2666779539
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2261708744
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1972058310
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2129862647
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1220572903
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_errors.3982673845
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3251462624
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1492281446
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.945916762
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2409854879
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.4005653647
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1079593563
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_errors.1545010994
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.4211490759
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.425285306
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_rw.3916287528
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3683642604
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2449779508
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.4057118040
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1727155267
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_errors.1573953765
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.541645819
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.580987375
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_rw.2992073065
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.3771046113
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1878824120
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3573361033
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3738441321
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_errors.4064447730
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.4003350821
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_rw.3955524708
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.712803324
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1335174107
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2960974602
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.985654065
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_errors.1735517006
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_aliasing.632112732
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.546748021
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1254672315
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3125690867
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_rw.2805857961
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2001159205
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3896575428
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.268097541
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1252502726
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.4280799823
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3458159405
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1223553122
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3173182099
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_partial_access.707367725
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_walk.3545644917
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.122450576
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.1165602605
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_errors.1890177128
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1027842951
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1299125287
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3515585366
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3261825676
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.4286026597
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_rw.3992603383
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3556834495
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1599804697
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3633612407
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3750295198
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1838981848
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3239759369
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1734633562
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3654768690
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_walk.2611728217
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2175119804
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3940152088
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_errors.802361236
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2577158713
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_aliasing.903160248
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.837827183
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.823974131
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.4249798030
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_rw.1503737403
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2678415353
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.270505692
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2494754950
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.4253668515
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1641564633
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.390684942
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3903362541
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2350082656
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1508408822
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_walk.3305334968
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1833435412
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3899319817
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_errors.1225232295
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3354449006
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1017827617
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_rw.2456752697
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3770598255
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3556978059
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1376043008
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.540199489
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_errors.1121610066
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1270542093
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_rw.1894860339
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3246798436
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1956505016
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.4053257531
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2392757
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3246110640
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_errors.23810022
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_intg_err.170585807
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1273628844
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_rw.3797212438
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1978027389
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3768769792
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.776431220
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2655196205
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.3375288730
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_errors.1805853820
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_intg_err.4256907110
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.126121424
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_rw.2282182101
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1326171489
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.2639302705
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2825087569
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1184728137
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1816132988
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_errors.4002823719
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1553005712
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1516695568
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_rw.4281971684
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2098816961
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3560150179
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2663349501
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1918762149
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.352522757
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_errors.1128850660
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1068298149
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.617283171
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.645204246
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.1937233552
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.2282138041
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_dataaddr_rw_access.1924167061
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_debug_disabled.124362810
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.3720909665
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_hartsel_warl.1910468164
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.353660194
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1354671296
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_hard_reset.3569168512
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_idle_hint.4030938044
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_halted.4023114287
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_resuming.3463243168
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.1998803133
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_tl_access.621589781
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_smoke.3634977572
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.2760639153
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_abstractcmd_status.1528221982
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_alert_test.2544281509
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_autoincr_sba_tl_access.2685870770
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_buffered_enable.3070987922
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_busy.99254630
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_not_supported.1250145620
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_dataaddr_rw_access.2957656031
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_debug_disabled.3906174881
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.594377223
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.1624054176
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_hart_unavail.3508279433
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.418650897
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1129775419
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_idle_hint.215469692
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_halted.3258899502
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_resuming.4039384157
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_ndmreset_req.760847677
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_progbuf_read_write_execute.2507524800
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_rom_read_access.1488273019
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_debug_disabled.3497777248
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_tl_access.314055456
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_sec_cm.3352044674
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_smoke.4172595462
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.1553640266
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.3941433775
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/10.rv_dm_alert_test.1084744531
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/10.rv_dm_autoincr_sba_tl_access.574023095
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/10.rv_dm_bad_sba_tl_access.1139636480
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.3519521324
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/10.rv_dm_sba_tl_access.637486619
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/10.rv_dm_stress_all.3505799043
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/11.rv_dm_alert_test.4108921445
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/11.rv_dm_bad_sba_tl_access.3303094965
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.1127263693
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/11.rv_dm_sba_tl_access.1552514714
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/12.rv_dm_alert_test.902450771
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/12.rv_dm_autoincr_sba_tl_access.724316718
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/12.rv_dm_bad_sba_tl_access.2198583774
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.4268547298
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/12.rv_dm_sba_tl_access.3542553463
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/13.rv_dm_alert_test.2607179475
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.2292356480
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/14.rv_dm_alert_test.2873121362
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/14.rv_dm_autoincr_sba_tl_access.3289960721
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/14.rv_dm_bad_sba_tl_access.1334699795
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.3216620810
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/14.rv_dm_sba_tl_access.2067600260
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/15.rv_dm_alert_test.3560352023
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/15.rv_dm_autoincr_sba_tl_access.2029160345
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/15.rv_dm_bad_sba_tl_access.1159251781
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2973761886
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/15.rv_dm_sba_tl_access.1654787511
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/16.rv_dm_alert_test.3170825059
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/16.rv_dm_autoincr_sba_tl_access.1127381235
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/16.rv_dm_bad_sba_tl_access.2267975865
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.3055975499
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/16.rv_dm_sba_tl_access.800162827
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/16.rv_dm_stress_all.3895510880
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/17.rv_dm_alert_test.2120985847
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/17.rv_dm_autoincr_sba_tl_access.149484445
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/17.rv_dm_bad_sba_tl_access.1828469689
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.2184395972
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/17.rv_dm_sba_tl_access.398836141
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/17.rv_dm_stress_all.2083007873
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/18.rv_dm_alert_test.3090765940
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.1642662987
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/18.rv_dm_sba_tl_access.2411973090
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/18.rv_dm_stress_all.2672511882
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/19.rv_dm_alert_test.3906720485
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.970159826
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/19.rv_dm_bad_sba_tl_access.4085553862
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2797244274
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/19.rv_dm_sba_tl_access.3233669874
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.1268331442
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.2865945938
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.1547169795
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.1449508939
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.2103647731
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.4294519712
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.872351877
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.1181031943
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.838660093
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_sparse_lc_gate_fsm.2111135103
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.1144792356
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/20.rv_dm_alert_test.2415805596
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/21.rv_dm_alert_test.1985567207
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/21.rv_dm_stress_all.3398472689
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/22.rv_dm_alert_test.3621156860
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.2400979446
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/23.rv_dm_alert_test.398846200
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/23.rv_dm_stress_all.3087587689
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/24.rv_dm_alert_test.2896465968
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/24.rv_dm_stress_all.1269810712
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/25.rv_dm_alert_test.1415703980
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.1161692976
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/26.rv_dm_alert_test.2001405853
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/27.rv_dm_alert_test.1412325685
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.1252398626
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/28.rv_dm_alert_test.979304724
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/29.rv_dm_alert_test.118062557
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/29.rv_dm_stress_all.830224547
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.258738182
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.2104607706
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.178962650
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.3415665785
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1945173249
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.1784558580
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_hart_unavail.566102143
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_sec_cm.969873188
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/30.rv_dm_alert_test.1116919347
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/31.rv_dm_alert_test.3279915966
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/31.rv_dm_stress_all.1974610556
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/32.rv_dm_alert_test.3458492249
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/32.rv_dm_stress_all.2115020056
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/33.rv_dm_alert_test.1332956483
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/34.rv_dm_alert_test.374746245
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/34.rv_dm_stress_all.362471448
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/35.rv_dm_alert_test.352199105
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/35.rv_dm_stress_all.1888588325
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/36.rv_dm_alert_test.4045246004
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/37.rv_dm_alert_test.3543052013
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/37.rv_dm_stress_all.3556234004
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/38.rv_dm_alert_test.3857945407
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/39.rv_dm_alert_test.605623546
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/39.rv_dm_stress_all.815548208
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_alert_test.559828422
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_autoincr_sba_tl_access.3555752994
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_bad_sba_tl_access.914092397
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_buffered_enable.2379914608
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.1674229581
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.3177766452
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.4178330350
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_sba_tl_access.2337268435
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_sec_cm.1677284121
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.3434015843
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/40.rv_dm_alert_test.2251972863
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/40.rv_dm_stress_all.2289097511
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/41.rv_dm_alert_test.2982387235
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/41.rv_dm_stress_all.530850249
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/42.rv_dm_alert_test.3737849614
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/42.rv_dm_stress_all.4293480585
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/43.rv_dm_alert_test.3782543604
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/43.rv_dm_stress_all.3623523087
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/44.rv_dm_alert_test.2230469739
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.1461054329
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/45.rv_dm_alert_test.176663126
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/45.rv_dm_stress_all.1557580298
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/46.rv_dm_alert_test.134975309
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.3664229046
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/47.rv_dm_alert_test.1358157695
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/47.rv_dm_stress_all.4281831456
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/48.rv_dm_alert_test.2122536450
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/48.rv_dm_stress_all.2298333996
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/49.rv_dm_alert_test.3654812240
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/49.rv_dm_stress_all.3445670608
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/5.rv_dm_alert_test.1557677702
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.2812013982
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.2933016158
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/5.rv_dm_buffered_enable.67515386
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.3659167590
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/5.rv_dm_halt_resume_whereto.2969645385
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/5.rv_dm_sba_tl_access.3489439774
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.780596968
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/6.rv_dm_alert_test.4284049576
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/6.rv_dm_autoincr_sba_tl_access.4206406450
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/6.rv_dm_bad_sba_tl_access.2585669282
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/6.rv_dm_buffered_enable.2131932310
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.2094404581
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/6.rv_dm_halt_resume_whereto.3888392662
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/6.rv_dm_sba_tl_access.2167460920
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all.2690407964
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/7.rv_dm_alert_test.1820092124
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.1288440212
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.2554043041
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/7.rv_dm_buffered_enable.1911471085
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.94054421
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.134337317
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/7.rv_dm_sba_tl_access.3641470095
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all.283322055
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.707401568
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/8.rv_dm_alert_test.1639561656
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.1808608988
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/8.rv_dm_bad_sba_tl_access.1992403335
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/8.rv_dm_buffered_enable.204392657
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.817067720
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/8.rv_dm_sba_tl_access.1262171881
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.857358883
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.1598452496
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/9.rv_dm_autoincr_sba_tl_access.3001019520
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.1544541580
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/9.rv_dm_buffered_enable.3435686961
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.2968612932
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.2192847245
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.36351390
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.2984507246



Total test records in report: 483
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_smoke.3634977572 Oct 02 09:01:02 PM UTC 24 Oct 02 09:01:05 PM UTC 24 627496084 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.2282138041 Oct 02 09:01:04 PM UTC 24 Oct 02 09:01:07 PM UTC 24 149001483 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_tl_access.621589781 Oct 02 09:01:02 PM UTC 24 Oct 02 09:01:07 PM UTC 24 2098006931 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.270717177 Oct 02 09:01:03 PM UTC 24 Oct 02 09:01:08 PM UTC 24 1606348849 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.645204246 Oct 02 09:01:06 PM UTC 24 Oct 02 09:01:08 PM UTC 24 202980034 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_halted.4023114287 Oct 02 09:01:06 PM UTC 24 Oct 02 09:01:08 PM UTC 24 626581101 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_busy.4213525611 Oct 02 09:01:03 PM UTC 24 Oct 02 09:01:09 PM UTC 24 1101477830 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_hart_unavail.3628463297 Oct 02 09:01:08 PM UTC 24 Oct 02 09:01:10 PM UTC 24 152564475 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_resuming.3463243168 Oct 02 09:01:08 PM UTC 24 Oct 02 09:01:11 PM UTC 24 117044517 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.1563429154 Oct 02 09:01:09 PM UTC 24 Oct 02 09:01:27 PM UTC 24 4977120276 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.1937233552 Oct 02 09:01:08 PM UTC 24 Oct 02 09:01:11 PM UTC 24 414997219 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.759580240 Oct 02 09:01:09 PM UTC 24 Oct 02 09:01:12 PM UTC 24 97974814 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.3720909665 Oct 02 09:01:09 PM UTC 24 Oct 02 09:01:12 PM UTC 24 449974366 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_hard_reset.3569168512 Oct 02 09:01:09 PM UTC 24 Oct 02 09:01:12 PM UTC 24 121291107 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_idle_hint.4030938044 Oct 02 09:01:09 PM UTC 24 Oct 02 09:01:12 PM UTC 24 238815373 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.353660194 Oct 02 09:01:09 PM UTC 24 Oct 02 09:01:12 PM UTC 24 820274471 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_dataaddr_rw_access.1924167061 Oct 02 09:01:09 PM UTC 24 Oct 02 09:01:12 PM UTC 24 317362229 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.3777482386 Oct 02 09:01:11 PM UTC 24 Oct 02 09:01:13 PM UTC 24 43304190 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.2067613534 Oct 02 09:01:09 PM UTC 24 Oct 02 09:01:13 PM UTC 24 639499411 ps
T88 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_debug_disabled.124362810 Oct 02 09:01:11 PM UTC 24 Oct 02 09:01:13 PM UTC 24 47657743 ps
T77 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.3524649269 Oct 02 09:01:12 PM UTC 24 Oct 02 09:01:14 PM UTC 24 42765350 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.1998803133 Oct 02 09:01:11 PM UTC 24 Oct 02 09:01:14 PM UTC 24 228748666 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_hartsel_warl.1910468164 Oct 02 09:01:12 PM UTC 24 Oct 02 09:01:14 PM UTC 24 269141552 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.1859491024 Oct 02 09:01:12 PM UTC 24 Oct 02 09:01:14 PM UTC 24 79919859 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.2180336319 Oct 02 09:01:03 PM UTC 24 Oct 02 09:01:14 PM UTC 24 9970174094 ps
T74 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.3636382525 Oct 02 09:01:12 PM UTC 24 Oct 02 09:01:15 PM UTC 24 241137015 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1354671296 Oct 02 09:01:09 PM UTC 24 Oct 02 09:01:15 PM UTC 24 1105030265 ps
T51 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.101283481 Oct 02 09:01:13 PM UTC 24 Oct 02 09:01:16 PM UTC 24 91490441 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.617283171 Oct 02 09:01:12 PM UTC 24 Oct 02 09:01:16 PM UTC 24 508552752 ps
T97 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_hart_unavail.3508279433 Oct 02 09:01:15 PM UTC 24 Oct 02 09:01:17 PM UTC 24 97582953 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.1186131254 Oct 02 09:01:13 PM UTC 24 Oct 02 09:01:17 PM UTC 24 428544805 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_dataaddr_rw_access.2957656031 Oct 02 09:01:15 PM UTC 24 Oct 02 09:01:17 PM UTC 24 172329883 ps
T96 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_halted.3258899502 Oct 02 09:01:15 PM UTC 24 Oct 02 09:01:17 PM UTC 24 193834347 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.4053242213 Oct 02 09:01:15 PM UTC 24 Oct 02 09:01:17 PM UTC 24 372186018 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_busy.99254630 Oct 02 09:01:15 PM UTC 24 Oct 02 09:01:17 PM UTC 24 191546392 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_halt_resume_whereto.1459341293 Oct 02 09:01:15 PM UTC 24 Oct 02 09:01:17 PM UTC 24 249794840 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_not_supported.1250145620 Oct 02 09:01:15 PM UTC 24 Oct 02 09:01:18 PM UTC 24 171571561 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.30370962 Oct 02 09:01:15 PM UTC 24 Oct 02 09:01:18 PM UTC 24 469739580 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_resuming.4039384157 Oct 02 09:01:15 PM UTC 24 Oct 02 09:01:18 PM UTC 24 775904023 ps
T78 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_idle_hint.215469692 Oct 02 09:01:16 PM UTC 24 Oct 02 09:01:18 PM UTC 24 265195616 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_ndmreset_req.760847677 Oct 02 09:01:16 PM UTC 24 Oct 02 09:01:19 PM UTC 24 162999729 ps
T266 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1129775419 Oct 02 09:01:16 PM UTC 24 Oct 02 09:01:20 PM UTC 24 898999593 ps
T80 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_smoke.4172595462 Oct 02 09:01:13 PM UTC 24 Oct 02 09:01:20 PM UTC 24 1321461431 ps
T76 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3999088903 Oct 02 09:01:18 PM UTC 24 Oct 02 09:01:20 PM UTC 24 445894102 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_abstractcmd_status.1528221982 Oct 02 09:01:18 PM UTC 24 Oct 02 09:01:20 PM UTC 24 77497615 ps
T87 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.594377223 Oct 02 09:01:14 PM UTC 24 Oct 02 09:01:21 PM UTC 24 4816804202 ps
T115 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.1449508939 Oct 02 09:01:21 PM UTC 24 Oct 02 09:01:32 PM UTC 24 1992053586 ps
T166 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_debug_disabled.3497777248 Oct 02 09:01:16 PM UTC 24 Oct 02 09:01:21 PM UTC 24 3766562713 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_rom_read_access.1488273019 Oct 02 09:01:19 PM UTC 24 Oct 02 09:01:21 PM UTC 24 85321834 ps
T84 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_buffered_enable.3070987922 Oct 02 09:01:19 PM UTC 24 Oct 02 09:01:21 PM UTC 24 124200221 ps
T75 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.1624054176 Oct 02 09:01:19 PM UTC 24 Oct 02 09:01:21 PM UTC 24 327236505 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.1553640266 Oct 02 09:01:19 PM UTC 24 Oct 02 09:01:22 PM UTC 24 320129313 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_progbuf_read_write_execute.2507524800 Oct 02 09:01:19 PM UTC 24 Oct 02 09:01:22 PM UTC 24 183150650 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_alert_test.2544281509 Oct 02 09:01:19 PM UTC 24 Oct 02 09:01:22 PM UTC 24 35117193 ps
T91 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_debug_disabled.3906174881 Oct 02 09:01:19 PM UTC 24 Oct 02 09:01:22 PM UTC 24 125132606 ps
T141 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.872351877 Oct 02 09:01:21 PM UTC 24 Oct 02 09:01:23 PM UTC 24 85235513 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.4294519712 Oct 02 09:01:21 PM UTC 24 Oct 02 09:01:23 PM UTC 24 230466367 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.4011395699 Oct 02 09:01:13 PM UTC 24 Oct 02 09:01:24 PM UTC 24 2580330022 ps
T92 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.418650897 Oct 02 09:01:18 PM UTC 24 Oct 02 09:01:24 PM UTC 24 725924338 ps
T198 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_hart_unavail.566102143 Oct 02 09:01:25 PM UTC 24 Oct 02 09:01:27 PM UTC 24 65818048 ps
T89 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_sec_cm.3352044674 Oct 02 09:01:19 PM UTC 24 Oct 02 09:01:24 PM UTC 24 1185501408 ps
T83 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_sparse_lc_gate_fsm.2111135103 Oct 02 09:01:22 PM UTC 24 Oct 02 09:01:24 PM UTC 24 63216197 ps
T53 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.2865945938 Oct 02 09:01:22 PM UTC 24 Oct 02 09:01:25 PM UTC 24 70338781 ps
T116 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_bad_sba_tl_access.3329490997 Oct 02 09:01:14 PM UTC 24 Oct 02 09:01:25 PM UTC 24 3933050001 ps
T86 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.2086849617 Oct 02 09:01:21 PM UTC 24 Oct 02 09:01:25 PM UTC 24 566393482 ps
T165 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.3415665785 Oct 02 09:01:25 PM UTC 24 Oct 02 09:01:27 PM UTC 24 175904188 ps
T85 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.2930526603 Oct 02 09:01:25 PM UTC 24 Oct 02 09:01:27 PM UTC 24 99026035 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.1784558580 Oct 02 09:01:25 PM UTC 24 Oct 02 09:01:28 PM UTC 24 528519841 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all.625481385 Oct 02 09:01:22 PM UTC 24 Oct 02 09:01:28 PM UTC 24 5006714876 ps
T98 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1945173249 Oct 02 09:01:22 PM UTC 24 Oct 02 09:01:28 PM UTC 24 1177882376 ps
T90 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.838660093 Oct 02 09:01:22 PM UTC 24 Oct 02 09:01:29 PM UTC 24 2706959853 ps
T99 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.258738182 Oct 02 09:01:26 PM UTC 24 Oct 02 09:01:29 PM UTC 24 97848181 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_autoincr_sba_tl_access.2685870770 Oct 02 09:01:15 PM UTC 24 Oct 02 09:01:30 PM UTC 24 6054279028 ps
T94 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_sec_cm.969873188 Oct 02 09:01:26 PM UTC 24 Oct 02 09:01:30 PM UTC 24 1270757701 ps
T100 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.1181031943 Oct 02 09:01:19 PM UTC 24 Oct 02 09:01:31 PM UTC 24 11406519035 ps
T101 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.4178330350 Oct 02 09:01:28 PM UTC 24 Oct 02 09:01:31 PM UTC 24 268648842 ps
T134 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_sba_tl_access.2337268435 Oct 02 09:01:26 PM UTC 24 Oct 02 09:01:31 PM UTC 24 991504119 ps
T167 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.178962650 Oct 02 09:01:23 PM UTC 24 Oct 02 09:01:32 PM UTC 24 1775648925 ps
T81 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.4229835236 Oct 02 09:01:02 PM UTC 24 Oct 02 09:01:33 PM UTC 24 6742510756 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.2104607706 Oct 02 09:01:23 PM UTC 24 Oct 02 09:01:32 PM UTC 24 6041751091 ps
T207 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.3986098699 Oct 02 09:01:03 PM UTC 24 Oct 02 09:01:32 PM UTC 24 8818824889 ps
T263 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.1674229581 Oct 02 09:01:28 PM UTC 24 Oct 02 09:01:32 PM UTC 24 594467017 ps
T267 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/14.rv_dm_sba_tl_access.2067600260 Oct 02 09:01:56 PM UTC 24 Oct 02 09:02:08 PM UTC 24 3354372458 ps
T208 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_buffered_enable.2379914608 Oct 02 09:01:30 PM UTC 24 Oct 02 09:01:33 PM UTC 24 461747738 ps
T214 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.1169255270 Oct 02 09:01:22 PM UTC 24 Oct 02 09:01:33 PM UTC 24 4326813674 ps
T162 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_alert_test.559828422 Oct 02 09:01:31 PM UTC 24 Oct 02 09:01:33 PM UTC 24 118327916 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.3177766452 Oct 02 09:01:29 PM UTC 24 Oct 02 09:01:33 PM UTC 24 516381493 ps
T95 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_sec_cm.1677284121 Oct 02 09:01:30 PM UTC 24 Oct 02 09:01:34 PM UTC 24 1219617985 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.2934799504 Oct 02 09:01:25 PM UTC 24 Oct 02 09:01:34 PM UTC 24 2309742753 ps
T233 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/5.rv_dm_buffered_enable.67515386 Oct 02 09:01:32 PM UTC 24 Oct 02 09:01:35 PM UTC 24 154281387 ps
T163 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/5.rv_dm_alert_test.1557677702 Oct 02 09:01:33 PM UTC 24 Oct 02 09:01:35 PM UTC 24 110565161 ps
T268 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/5.rv_dm_sba_tl_access.3489439774 Oct 02 09:01:31 PM UTC 24 Oct 02 09:01:35 PM UTC 24 990850195 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/5.rv_dm_halt_resume_whereto.2969645385 Oct 02 09:01:32 PM UTC 24 Oct 02 09:01:35 PM UTC 24 348494688 ps
T72 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/6.rv_dm_halt_resume_whereto.3888392662 Oct 02 09:01:34 PM UTC 24 Oct 02 09:01:36 PM UTC 24 448900945 ps
T249 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/6.rv_dm_sba_tl_access.2167460920 Oct 02 09:01:33 PM UTC 24 Oct 02 09:01:36 PM UTC 24 1617662091 ps
T256 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.3659167590 Oct 02 09:01:31 PM UTC 24 Oct 02 09:01:37 PM UTC 24 1333610945 ps
T234 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/6.rv_dm_buffered_enable.2131932310 Oct 02 09:01:34 PM UTC 24 Oct 02 09:01:37 PM UTC 24 671798294 ps
T164 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/6.rv_dm_alert_test.4284049576 Oct 02 09:01:35 PM UTC 24 Oct 02 09:01:37 PM UTC 24 39477889 ps
T251 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_tl_access.314055456 Oct 02 09:01:13 PM UTC 24 Oct 02 09:01:38 PM UTC 24 7528008384 ps
T244 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_bad_sba_tl_access.914092397 Oct 02 09:01:28 PM UTC 24 Oct 02 09:01:38 PM UTC 24 2920514663 ps
T211 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/6.rv_dm_bad_sba_tl_access.2585669282 Oct 02 09:01:34 PM UTC 24 Oct 02 09:01:39 PM UTC 24 969636090 ps
T209 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.134337317 Oct 02 09:01:37 PM UTC 24 Oct 02 09:01:39 PM UTC 24 532662821 ps
T242 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/7.rv_dm_alert_test.1820092124 Oct 02 09:01:38 PM UTC 24 Oct 02 09:01:40 PM UTC 24 54720346 ps
T240 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.2094404581 Oct 02 09:01:34 PM UTC 24 Oct 02 09:01:40 PM UTC 24 1369600163 ps
T253 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/9.rv_dm_autoincr_sba_tl_access.3001019520 Oct 02 09:01:43 PM UTC 24 Oct 02 09:02:08 PM UTC 24 7474030318 ps
T269 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/6.rv_dm_autoincr_sba_tl_access.4206406450 Oct 02 09:01:34 PM UTC 24 Oct 02 09:01:41 PM UTC 24 2092152588 ps
T135 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/7.rv_dm_buffered_enable.1911471085 Oct 02 09:01:37 PM UTC 24 Oct 02 09:01:41 PM UTC 24 478029868 ps
T257 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.2554043041 Oct 02 09:01:35 PM UTC 24 Oct 02 09:01:42 PM UTC 24 3204378942 ps
T93 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.3941433775 Oct 02 09:01:19 PM UTC 24 Oct 02 09:01:42 PM UTC 24 3647008853 ps
T261 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/7.rv_dm_sba_tl_access.3641470095 Oct 02 09:01:35 PM UTC 24 Oct 02 09:01:42 PM UTC 24 2510712406 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.780596968 Oct 02 09:01:32 PM UTC 24 Oct 02 09:01:42 PM UTC 24 5000127628 ps
T236 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.2933016158 Oct 02 09:01:31 PM UTC 24 Oct 02 09:01:42 PM UTC 24 4736907506 ps
T232 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/8.rv_dm_buffered_enable.204392657 Oct 02 09:01:40 PM UTC 24 Oct 02 09:01:43 PM UTC 24 134673668 ps
T216 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.94054421 Oct 02 09:01:35 PM UTC 24 Oct 02 09:01:44 PM UTC 24 8725222335 ps
T250 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/8.rv_dm_alert_test.1639561656 Oct 02 09:01:42 PM UTC 24 Oct 02 09:01:44 PM UTC 24 259246961 ps
T262 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/8.rv_dm_sba_tl_access.1262171881 Oct 02 09:01:38 PM UTC 24 Oct 02 09:01:45 PM UTC 24 2597793817 ps
T243 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.1598452496 Oct 02 09:01:43 PM UTC 24 Oct 02 09:01:46 PM UTC 24 60386582 ps
T270 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.817067720 Oct 02 09:01:39 PM UTC 24 Oct 02 09:01:46 PM UTC 24 3902583947 ps
T193 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.857358883 Oct 02 09:01:41 PM UTC 24 Oct 02 09:01:47 PM UTC 24 3274640642 ps
T245 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/9.rv_dm_buffered_enable.3435686961 Oct 02 09:01:43 PM UTC 24 Oct 02 09:01:47 PM UTC 24 262183416 ps
T259 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.1808608988 Oct 02 09:01:39 PM UTC 24 Oct 02 09:01:47 PM UTC 24 3770147569 ps
T271 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.1547169795 Oct 02 09:01:21 PM UTC 24 Oct 02 09:01:47 PM UTC 24 6506821883 ps
T265 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/8.rv_dm_bad_sba_tl_access.1992403335 Oct 02 09:01:39 PM UTC 24 Oct 02 09:01:47 PM UTC 24 8970141823 ps
T272 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.2968612932 Oct 02 09:01:43 PM UTC 24 Oct 02 09:01:48 PM UTC 24 1376336271 ps
T70 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.3434015843 Oct 02 09:01:30 PM UTC 24 Oct 02 09:01:48 PM UTC 24 3988396892 ps
T235 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/10.rv_dm_alert_test.1084744531 Oct 02 09:01:47 PM UTC 24 Oct 02 09:01:49 PM UTC 24 169602345 ps
T247 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/10.rv_dm_autoincr_sba_tl_access.574023095 Oct 02 09:01:46 PM UTC 24 Oct 02 09:01:50 PM UTC 24 2552363067 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.36351390 Oct 02 09:01:43 PM UTC 24 Oct 02 09:01:50 PM UTC 24 2488181581 ps
T241 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/11.rv_dm_alert_test.4108921445 Oct 02 09:01:48 PM UTC 24 Oct 02 09:01:51 PM UTC 24 28928130 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/10.rv_dm_stress_all.3505799043 Oct 02 09:01:47 PM UTC 24 Oct 02 09:01:51 PM UTC 24 1351141572 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/11.rv_dm_stress_all.238458297 Oct 02 09:01:48 PM UTC 24 Oct 02 09:01:53 PM UTC 24 1904330791 ps
T238 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.3519521324 Oct 02 09:01:45 PM UTC 24 Oct 02 09:01:54 PM UTC 24 6013261841 ps
T248 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/12.rv_dm_alert_test.902450771 Oct 02 09:01:52 PM UTC 24 Oct 02 09:01:54 PM UTC 24 166008477 ps
T183 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.2812013982 Oct 02 09:01:31 PM UTC 24 Oct 02 09:01:54 PM UTC 24 28762119944 ps
T210 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/11.rv_dm_sba_tl_access.1552514714 Oct 02 09:01:48 PM UTC 24 Oct 02 09:01:54 PM UTC 24 3327454491 ps
T264 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.1127263693 Oct 02 09:01:48 PM UTC 24 Oct 02 09:01:55 PM UTC 24 4077725247 ps
T254 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/11.rv_dm_bad_sba_tl_access.3303094965 Oct 02 09:01:48 PM UTC 24 Oct 02 09:01:57 PM UTC 24 3462920461 ps
T273 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/10.rv_dm_sba_tl_access.637486619 Oct 02 09:01:45 PM UTC 24 Oct 02 09:01:58 PM UTC 24 11407085356 ps
T196 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/12.rv_dm_stress_all.1723960590 Oct 02 09:01:52 PM UTC 24 Oct 02 09:01:58 PM UTC 24 3537053786 ps
T195 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all.2690407964 Oct 02 09:01:34 PM UTC 24 Oct 02 09:01:58 PM UTC 24 4016183673 ps
T260 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/13.rv_dm_alert_test.2607179475 Oct 02 09:01:56 PM UTC 24 Oct 02 09:01:58 PM UTC 24 90546161 ps
T212 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.4268547298 Oct 02 09:01:50 PM UTC 24 Oct 02 09:01:58 PM UTC 24 1189501240 ps
T258 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.2192847245 Oct 02 09:01:42 PM UTC 24 Oct 02 09:02:00 PM UTC 24 3984666907 ps
T255 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.1544541580 Oct 02 09:01:43 PM UTC 24 Oct 02 09:02:00 PM UTC 24 10153622944 ps
T274 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.1288440212 Oct 02 09:01:37 PM UTC 24 Oct 02 09:02:00 PM UTC 24 12238021368 ps
T275 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.2103647731 Oct 02 09:01:21 PM UTC 24 Oct 02 09:02:01 PM UTC 24 11344939309 ps
T239 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/14.rv_dm_alert_test.2873121362 Oct 02 09:01:59 PM UTC 24 Oct 02 09:02:01 PM UTC 24 109627198 ps
T276 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/14.rv_dm_bad_sba_tl_access.1334699795 Oct 02 09:01:57 PM UTC 24 Oct 02 09:02:03 PM UTC 24 4513132459 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.730571388 Oct 02 09:01:19 PM UTC 24 Oct 02 09:02:03 PM UTC 24 1817676211 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all.283322055 Oct 02 09:01:37 PM UTC 24 Oct 02 09:02:04 PM UTC 24 5746543089 ps
T117 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/15.rv_dm_alert_test.3560352023 Oct 02 09:02:02 PM UTC 24 Oct 02 09:02:04 PM UTC 24 133260527 ps
T118 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/15.rv_dm_sba_tl_access.1654787511 Oct 02 09:01:59 PM UTC 24 Oct 02 09:02:05 PM UTC 24 3518176176 ps
T119 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.2292356480 Oct 02 09:01:54 PM UTC 24 Oct 02 09:02:05 PM UTC 24 8955288354 ps
T120 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/13.rv_dm_sba_tl_access.1382947153 Oct 02 09:01:53 PM UTC 24 Oct 02 09:02:05 PM UTC 24 5968394732 ps
T121 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/13.rv_dm_stress_all.1951521606 Oct 02 09:01:56 PM UTC 24 Oct 02 09:02:06 PM UTC 24 3068745601 ps
T122 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/16.rv_dm_sba_tl_access.800162827 Oct 02 09:02:02 PM UTC 24 Oct 02 09:02:06 PM UTC 24 1460170851 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/15.rv_dm_stress_all.1321561341 Oct 02 09:02:02 PM UTC 24 Oct 02 09:02:07 PM UTC 24 2381385390 ps
T123 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/16.rv_dm_alert_test.3170825059 Oct 02 09:02:06 PM UTC 24 Oct 02 09:02:08 PM UTC 24 108551287 ps
T218 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/10.rv_dm_bad_sba_tl_access.1139636480 Oct 02 09:01:45 PM UTC 24 Oct 02 09:02:08 PM UTC 24 4915150175 ps
T277 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2973761886 Oct 02 09:01:59 PM UTC 24 Oct 02 09:02:10 PM UTC 24 3519511780 ps
T278 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/15.rv_dm_bad_sba_tl_access.1159251781 Oct 02 09:02:01 PM UTC 24 Oct 02 09:02:10 PM UTC 24 4163991730 ps
T279 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.3055975499 Oct 02 09:02:04 PM UTC 24 Oct 02 09:02:10 PM UTC 24 905894208 ps
T280 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/17.rv_dm_sba_tl_access.398836141 Oct 02 09:02:07 PM UTC 24 Oct 02 09:02:10 PM UTC 24 1564689553 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all_with_rand_reset.767430930 Oct 02 09:01:34 PM UTC 24 Oct 02 09:02:11 PM UTC 24 7211355530 ps
T281 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/17.rv_dm_alert_test.2120985847 Oct 02 09:02:09 PM UTC 24 Oct 02 09:02:11 PM UTC 24 87378917 ps
T282 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.2184395972 Oct 02 09:02:07 PM UTC 24 Oct 02 09:02:12 PM UTC 24 2934067871 ps
T205 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/13.rv_dm_autoincr_sba_tl_access.2974442448 Oct 02 09:01:54 PM UTC 24 Oct 02 09:02:13 PM UTC 24 13214589300 ps
T252 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/45.rv_dm_alert_test.176663126 Oct 02 09:02:29 PM UTC 24 Oct 02 09:02:31 PM UTC 24 138938822 ps
T246 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.1642662987 Oct 02 09:02:09 PM UTC 24 Oct 02 09:02:13 PM UTC 24 1284222379 ps
T283 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/18.rv_dm_alert_test.3090765940 Oct 02 09:02:11 PM UTC 24 Oct 02 09:02:14 PM UTC 24 80054973 ps
T186 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/17.rv_dm_stress_all.2083007873 Oct 02 09:02:08 PM UTC 24 Oct 02 09:02:15 PM UTC 24 1914585144 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.2984507246 Oct 02 09:01:43 PM UTC 24 Oct 02 09:02:16 PM UTC 24 2569781044 ps
T171 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/19.rv_dm_alert_test.3906720485 Oct 02 09:02:14 PM UTC 24 Oct 02 09:02:16 PM UTC 24 47865296 ps
T172 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/13.rv_dm_bad_sba_tl_access.960252200 Oct 02 09:01:54 PM UTC 24 Oct 02 09:02:16 PM UTC 24 4871431646 ps
T173 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2797244274 Oct 02 09:02:12 PM UTC 24 Oct 02 09:02:16 PM UTC 24 1126536571 ps
T174 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/18.rv_dm_bad_sba_tl_access.1598919154 Oct 02 09:02:09 PM UTC 24 Oct 02 09:02:17 PM UTC 24 2116865749 ps
T175 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/12.rv_dm_sba_tl_access.3542553463 Oct 02 09:01:50 PM UTC 24 Oct 02 09:02:17 PM UTC 24 11318084919 ps
T176 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/11.rv_dm_autoincr_sba_tl_access.1530762951 Oct 02 09:01:48 PM UTC 24 Oct 02 09:02:18 PM UTC 24 6769858025 ps
T177 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/20.rv_dm_alert_test.2415805596 Oct 02 09:02:16 PM UTC 24 Oct 02 09:02:18 PM UTC 24 34695371 ps
T111 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.2760639153 Oct 02 09:01:13 PM UTC 24 Oct 02 09:02:18 PM UTC 24 2392961462 ps
T178 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.3216620810 Oct 02 09:01:56 PM UTC 24 Oct 02 09:02:19 PM UTC 24 4935187761 ps
T217 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/19.rv_dm_sba_tl_access.3233669874 Oct 02 09:02:12 PM UTC 24 Oct 02 09:02:19 PM UTC 24 5302744344 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.3223897393 Oct 02 09:01:30 PM UTC 24 Oct 02 09:02:19 PM UTC 24 9362711145 ps
T284 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/22.rv_dm_alert_test.3621156860 Oct 02 09:02:18 PM UTC 24 Oct 02 09:02:19 PM UTC 24 134450411 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/16.rv_dm_stress_all.3895510880 Oct 02 09:02:05 PM UTC 24 Oct 02 09:02:20 PM UTC 24 3443259464 ps
T191 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/14.rv_dm_stress_all.1968014591 Oct 02 09:01:59 PM UTC 24 Oct 02 09:02:20 PM UTC 24 3388656653 ps
T285 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/4.rv_dm_autoincr_sba_tl_access.3555752994 Oct 02 09:01:28 PM UTC 24 Oct 02 09:02:20 PM UTC 24 15960913404 ps
T286 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/15.rv_dm_autoincr_sba_tl_access.2029160345 Oct 02 09:02:01 PM UTC 24 Oct 02 09:02:20 PM UTC 24 3846914569 ps
T287 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/21.rv_dm_alert_test.1985567207 Oct 02 09:02:17 PM UTC 24 Oct 02 09:02:20 PM UTC 24 145274495 ps
T71 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.478535879 Oct 02 09:02:15 PM UTC 24 Oct 02 09:02:20 PM UTC 24 4785082431 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/42.rv_dm_stress_all.4293480585 Oct 02 09:02:27 PM UTC 24 Oct 02 09:02:32 PM UTC 24 5548703885 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/21.rv_dm_stress_all.3398472689 Oct 02 09:02:16 PM UTC 24 Oct 02 09:02:21 PM UTC 24 2486609407 ps
T288 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/23.rv_dm_alert_test.398846200 Oct 02 09:02:19 PM UTC 24 Oct 02 09:02:21 PM UTC 24 83739887 ps
T289 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/24.rv_dm_alert_test.2896465968 Oct 02 09:02:19 PM UTC 24 Oct 02 09:02:21 PM UTC 24 78404368 ps
T290 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/25.rv_dm_alert_test.1415703980 Oct 02 09:02:20 PM UTC 24 Oct 02 09:02:22 PM UTC 24 59848140 ps
T291 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/26.rv_dm_alert_test.2001405853 Oct 02 09:02:20 PM UTC 24 Oct 02 09:02:22 PM UTC 24 75857064 ps
T292 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/16.rv_dm_autoincr_sba_tl_access.1127381235 Oct 02 09:02:05 PM UTC 24 Oct 02 09:02:22 PM UTC 24 5596816055 ps
T213 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/18.rv_dm_autoincr_sba_tl_access.1756614506 Oct 02 09:02:10 PM UTC 24 Oct 02 09:02:22 PM UTC 24 6964980224 ps
T293 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/27.rv_dm_alert_test.1412325685 Oct 02 09:02:20 PM UTC 24 Oct 02 09:02:22 PM UTC 24 57529023 ps
T294 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/28.rv_dm_alert_test.979304724 Oct 02 09:02:21 PM UTC 24 Oct 02 09:02:23 PM UTC 24 71490137 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.1211377807 Oct 02 09:01:42 PM UTC 24 Oct 02 09:02:23 PM UTC 24 16657481553 ps
T199 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.1268331442 Oct 02 09:02:14 PM UTC 24 Oct 02 09:02:24 PM UTC 24 3136952648 ps
T295 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/29.rv_dm_alert_test.118062557 Oct 02 09:02:22 PM UTC 24 Oct 02 09:02:24 PM UTC 24 30183935 ps
T296 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/31.rv_dm_alert_test.3279915966 Oct 02 09:02:22 PM UTC 24 Oct 02 09:02:24 PM UTC 24 95427628 ps
T297 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/30.rv_dm_alert_test.1116919347 Oct 02 09:02:22 PM UTC 24 Oct 02 09:02:24 PM UTC 24 49814072 ps
T188 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/24.rv_dm_stress_all.1269810712 Oct 02 09:02:19 PM UTC 24 Oct 02 09:02:25 PM UTC 24 2007229155 ps
T206 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/16.rv_dm_bad_sba_tl_access.2267975865 Oct 02 09:02:04 PM UTC 24 Oct 02 09:02:25 PM UTC 24 9068506244 ps
T298 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/32.rv_dm_alert_test.3458492249 Oct 02 09:02:22 PM UTC 24 Oct 02 09:02:25 PM UTC 24 118032689 ps
T299 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/17.rv_dm_bad_sba_tl_access.1828469689 Oct 02 09:02:07 PM UTC 24 Oct 02 09:02:25 PM UTC 24 4147162096 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/33.rv_dm_alert_test.1332956483 Oct 02 09:02:24 PM UTC 24 Oct 02 09:02:26 PM UTC 24 33861487 ps
T301 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/35.rv_dm_alert_test.352199105 Oct 02 09:02:24 PM UTC 24 Oct 02 09:02:26 PM UTC 24 117161734 ps
T302 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/34.rv_dm_alert_test.374746245 Oct 02 09:02:24 PM UTC 24 Oct 02 09:02:26 PM UTC 24 44578198 ps
T194 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/29.rv_dm_stress_all.830224547 Oct 02 09:02:21 PM UTC 24 Oct 02 09:02:26 PM UTC 24 713772289 ps
T303 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/12.rv_dm_bad_sba_tl_access.2198583774 Oct 02 09:01:51 PM UTC 24 Oct 02 09:02:27 PM UTC 24 14891297318 ps
T304 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/37.rv_dm_stress_all.3556234004 Oct 02 09:02:26 PM UTC 24 Oct 02 09:02:32 PM UTC 24 2376406055 ps
T202 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.1161692976 Oct 02 09:02:19 PM UTC 24 Oct 02 09:02:28 PM UTC 24 1888995980 ps
T305 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/36.rv_dm_alert_test.4045246004 Oct 02 09:02:26 PM UTC 24 Oct 02 09:02:28 PM UTC 24 80603418 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/26.rv_dm_stress_all.2421440998 Oct 02 09:02:20 PM UTC 24 Oct 02 09:02:28 PM UTC 24 3425356938 ps
T306 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/37.rv_dm_alert_test.3543052013 Oct 02 09:02:26 PM UTC 24 Oct 02 09:02:28 PM UTC 24 38800696 ps
T307 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/38.rv_dm_alert_test.3857945407 Oct 02 09:02:26 PM UTC 24 Oct 02 09:02:28 PM UTC 24 74026468 ps
T185 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/36.rv_dm_stress_all.126361944 Oct 02 09:02:24 PM UTC 24 Oct 02 09:02:28 PM UTC 24 1493828689 ps
T237 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/39.rv_dm_alert_test.605623546 Oct 02 09:02:26 PM UTC 24 Oct 02 09:02:28 PM UTC 24 137346895 ps
T184 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/28.rv_dm_stress_all.460121276 Oct 02 09:02:21 PM UTC 24 Oct 02 09:02:29 PM UTC 24 1892539330 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.1479934986 Oct 02 09:02:22 PM UTC 24 Oct 02 09:02:29 PM UTC 24 3790406641 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/35.rv_dm_stress_all.1888588325 Oct 02 09:02:24 PM UTC 24 Oct 02 09:02:29 PM UTC 24 4375007112 ps
T308 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/40.rv_dm_alert_test.2251972863 Oct 02 09:02:27 PM UTC 24 Oct 02 09:02:29 PM UTC 24 72010887 ps
T309 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/42.rv_dm_alert_test.3737849614 Oct 02 09:02:28 PM UTC 24 Oct 02 09:02:30 PM UTC 24 34801156 ps
T203 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/32.rv_dm_stress_all.2115020056 Oct 02 09:02:22 PM UTC 24 Oct 02 09:02:30 PM UTC 24 2462144390 ps
T310 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/41.rv_dm_alert_test.2982387235 Oct 02 09:02:27 PM UTC 24 Oct 02 09:02:30 PM UTC 24 134991290 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.2400979446 Oct 02 09:02:17 PM UTC 24 Oct 02 09:02:30 PM UTC 24 4418508322 ps
T192 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/18.rv_dm_stress_all.2672511882 Oct 02 09:02:10 PM UTC 24 Oct 02 09:02:30 PM UTC 24 5102320128 ps
T311 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/18.rv_dm_sba_tl_access.2411973090 Oct 02 09:02:09 PM UTC 24 Oct 02 09:02:31 PM UTC 24 4938377664 ps
T312 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/43.rv_dm_alert_test.3782543604 Oct 02 09:02:29 PM UTC 24 Oct 02 09:02:31 PM UTC 24 70534635 ps
T313 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/44.rv_dm_alert_test.2230469739 Oct 02 09:02:29 PM UTC 24 Oct 02 09:02:31 PM UTC 24 25650333 ps
T314 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/46.rv_dm_alert_test.134975309 Oct 02 09:02:29 PM UTC 24 Oct 02 09:02:31 PM UTC 24 79211224 ps
T315 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/23.rv_dm_stress_all.3087587689 Oct 02 09:02:19 PM UTC 24 Oct 02 09:02:32 PM UTC 24 6710466193 ps
T316 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/39.rv_dm_stress_all.815548208 Oct 02 09:02:26 PM UTC 24 Oct 02 09:02:33 PM UTC 24 2886112167 ps
T317 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/47.rv_dm_alert_test.1358157695 Oct 02 09:02:31 PM UTC 24 Oct 02 09:02:33 PM UTC 24 78825505 ps
T318 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/48.rv_dm_alert_test.2122536450 Oct 02 09:02:31 PM UTC 24 Oct 02 09:02:33 PM UTC 24 131441376 ps
T319 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/49.rv_dm_alert_test.3654812240 Oct 02 09:02:31 PM UTC 24 Oct 02 09:02:33 PM UTC 24 73970138 ps
T204 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.3664229046 Oct 02 09:02:29 PM UTC 24 Oct 02 09:02:34 PM UTC 24 2116056634 ps
T320 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.1461054329 Oct 02 09:02:29 PM UTC 24 Oct 02 09:02:35 PM UTC 24 3036576057 ps
T73 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.450554767 Oct 02 09:01:26 PM UTC 24 Oct 02 09:02:35 PM UTC 24 16258832183 ps
T187 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.2389385950 Oct 02 09:02:24 PM UTC 24 Oct 02 09:02:35 PM UTC 24 4949694108 ps
T197 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/48.rv_dm_stress_all.2298333996 Oct 02 09:02:31 PM UTC 24 Oct 02 09:02:36 PM UTC 24 1493635956 ps
T321 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/43.rv_dm_stress_all.3623523087 Oct 02 09:02:29 PM UTC 24 Oct 02 09:02:36 PM UTC 24 4511661466 ps
T322 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/31.rv_dm_stress_all.1974610556 Oct 02 09:02:22 PM UTC 24 Oct 02 09:02:36 PM UTC 24 2679742187 ps
T200 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/40.rv_dm_stress_all.2289097511 Oct 02 09:02:26 PM UTC 24 Oct 02 09:02:36 PM UTC 24 3986337811 ps
T323 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/19.rv_dm_bad_sba_tl_access.4085553862 Oct 02 09:02:12 PM UTC 24 Oct 02 09:02:37 PM UTC 24 8808046545 ps
T324 /workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/coverage/default/34.rv_dm_stress_all.362471448 Oct 02 09:02:24 PM UTC 24 Oct 02 09:02:39 PM UTC 24 10895876911 ps
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