| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 88.98 | 96.64 | 90.52 | 92.10 | 93.33 | 90.44 | 98.74 | 61.10 |
| T323 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/37.rv_dm_stress_all.813424238 | Oct 09 10:50:26 PM UTC 24 | Oct 09 10:50:48 PM UTC 24 | 6723665434 ps | ||
| T85 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all_with_rand_reset.1769036947 | Oct 09 10:49:45 PM UTC 24 | Oct 09 10:50:50 PM UTC 24 | 63575261690 ps | ||
| T140 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/31.rv_dm_stress_all.3823114834 | Oct 09 10:50:22 PM UTC 24 | Oct 09 10:50:50 PM UTC 24 | 9713377547 ps | ||
| T83 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.3233571472 | Oct 09 10:49:35 PM UTC 24 | Oct 09 10:50:52 PM UTC 24 | 6879489947 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.3724805895 | Oct 09 10:49:47 PM UTC 24 | Oct 09 10:51:10 PM UTC 24 | 7080604638 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.3486499253 | Oct 09 10:49:52 PM UTC 24 | Oct 09 10:51:15 PM UTC 24 | 4874415043 ps | ||
| T324 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/16.rv_dm_autoincr_sba_tl_access.3156715053 | Oct 09 10:50:07 PM UTC 24 | Oct 09 10:51:25 PM UTC 24 | 20920529999 ps | ||
| T325 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.1400605963 | Oct 09 10:50:12 PM UTC 24 | Oct 09 10:51:43 PM UTC 24 | 21729673400 ps | ||
| T326 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.2838293786 | Oct 09 10:49:24 PM UTC 24 | Oct 09 10:53:44 PM UTC 24 | 70158260466 ps | ||
| T327 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/12.rv_dm_autoincr_sba_tl_access.1353993989 | Oct 09 10:49:57 PM UTC 24 | Oct 09 10:53:49 PM UTC 24 | 59246206253 ps | ||
| T106 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.678135807 | Oct 09 10:42:01 PM UTC 24 | Oct 09 10:42:03 PM UTC 24 | 230426217 ps | ||
| T107 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2312344375 | Oct 09 10:42:01 PM UTC 24 | Oct 09 10:42:04 PM UTC 24 | 264454656 ps | ||
| T108 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1653405528 | Oct 09 10:42:02 PM UTC 24 | Oct 09 10:42:08 PM UTC 24 | 1291429722 ps | ||
| T328 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2240142498 | Oct 09 10:42:02 PM UTC 24 | Oct 09 10:42:10 PM UTC 24 | 3128029516 ps | ||
| T124 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.2378490583 | Oct 09 10:42:05 PM UTC 24 | Oct 09 10:42:10 PM UTC 24 | 159149408 ps | ||
| T144 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1074637716 | Oct 09 10:42:02 PM UTC 24 | Oct 09 10:42:12 PM UTC 24 | 4986648660 ps | ||
| T329 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1394364935 | Oct 09 10:42:11 PM UTC 24 | Oct 09 10:42:13 PM UTC 24 | 188244139 ps | ||
| T330 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.2593987184 | Oct 09 10:42:11 PM UTC 24 | Oct 09 10:42:13 PM UTC 24 | 164199970 ps | ||
| T129 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2441584588 | Oct 09 10:42:13 PM UTC 24 | Oct 09 10:42:18 PM UTC 24 | 375416490 ps | ||
| T130 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.1473657562 | Oct 09 10:42:14 PM UTC 24 | Oct 09 10:42:18 PM UTC 24 | 84330196 ps | ||
| T331 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1270355644 | Oct 09 10:42:18 PM UTC 24 | Oct 09 10:42:25 PM UTC 24 | 326663633 ps | ||
| T131 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2036462680 | Oct 09 10:42:17 PM UTC 24 | Oct 09 10:42:28 PM UTC 24 | 166785585 ps | ||
| T332 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.559109714 | Oct 09 10:42:25 PM UTC 24 | Oct 09 10:42:33 PM UTC 24 | 848148111 ps | ||
| T333 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2303793663 | Oct 09 10:42:28 PM UTC 24 | Oct 09 10:42:35 PM UTC 24 | 667994701 ps | ||
| T174 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.4214058001 | Oct 09 10:42:09 PM UTC 24 | Oct 09 10:42:39 PM UTC 24 | 3671036274 ps | ||
| T334 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3584250852 | Oct 09 10:42:34 PM UTC 24 | Oct 09 10:42:39 PM UTC 24 | 1949817138 ps | ||
| T335 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3248840619 | Oct 09 10:42:30 PM UTC 24 | Oct 09 10:42:40 PM UTC 24 | 15937423600 ps | ||
| T148 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1427216148 | Oct 09 10:42:01 PM UTC 24 | Oct 09 10:42:41 PM UTC 24 | 7699197303 ps | ||
| T336 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.837665430 | Oct 09 10:42:36 PM UTC 24 | Oct 09 10:42:43 PM UTC 24 | 2924943414 ps | ||
| T337 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1696023149 | Oct 09 10:42:34 PM UTC 24 | Oct 09 10:42:44 PM UTC 24 | 2385131578 ps | ||
| T338 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.351171127 | Oct 09 10:42:45 PM UTC 24 | Oct 09 10:42:48 PM UTC 24 | 57614739 ps | ||
| T339 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.2967512814 | Oct 09 10:42:42 PM UTC 24 | Oct 09 10:42:50 PM UTC 24 | 802323195 ps | ||
| T340 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1796870264 | Oct 09 10:42:48 PM UTC 24 | Oct 09 10:42:51 PM UTC 24 | 105667809 ps | ||
| T132 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.428917055 | Oct 09 10:42:52 PM UTC 24 | Oct 09 10:42:56 PM UTC 24 | 120080355 ps | ||
| T176 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.412466814 | Oct 09 10:42:05 PM UTC 24 | Oct 09 10:42:56 PM UTC 24 | 2807389882 ps | ||
| T133 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2621293157 | Oct 09 10:42:52 PM UTC 24 | Oct 09 10:42:57 PM UTC 24 | 629610779 ps | ||
| T341 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3292723662 | Oct 09 10:42:40 PM UTC 24 | Oct 09 10:42:58 PM UTC 24 | 9801179111 ps | ||
| T208 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3734888864 | Oct 09 10:42:43 PM UTC 24 | Oct 09 10:42:58 PM UTC 24 | 1758706633 ps | ||
| T342 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3039869270 | Oct 09 10:42:59 PM UTC 24 | Oct 09 10:43:02 PM UTC 24 | 212869882 ps | ||
| T134 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2705948911 | Oct 09 10:42:58 PM UTC 24 | Oct 09 10:43:03 PM UTC 24 | 993368643 ps | ||
| T343 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.236754288 | Oct 09 10:42:58 PM UTC 24 | Oct 09 10:43:05 PM UTC 24 | 128432365 ps | ||
| T344 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2506790913 | Oct 09 10:43:03 PM UTC 24 | Oct 09 10:43:06 PM UTC 24 | 265386764 ps | ||
| T345 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.962347151 | Oct 09 10:43:05 PM UTC 24 | Oct 09 10:43:08 PM UTC 24 | 743950542 ps | ||
| T346 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3420178635 | Oct 09 10:43:06 PM UTC 24 | Oct 09 10:43:11 PM UTC 24 | 1925879697 ps | ||
| T347 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1092744369 | Oct 09 10:43:04 PM UTC 24 | Oct 09 10:43:13 PM UTC 24 | 3735695031 ps | ||
| T348 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1034363827 | Oct 09 10:43:06 PM UTC 24 | Oct 09 10:43:18 PM UTC 24 | 7956577873 ps | ||
| T135 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2932020576 | Oct 09 10:42:14 PM UTC 24 | Oct 09 10:43:19 PM UTC 24 | 2899845326 ps | ||
| T349 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_errors.1584276216 | Oct 09 10:43:15 PM UTC 24 | Oct 09 10:43:21 PM UTC 24 | 354752128 ps | ||
| T350 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_walk.4071833988 | Oct 09 10:43:20 PM UTC 24 | Oct 09 10:43:22 PM UTC 24 | 61121584 ps | ||
| T351 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1828544024 | Oct 09 10:43:22 PM UTC 24 | Oct 09 10:43:25 PM UTC 24 | 146785570 ps | ||
| T136 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3450523024 | Oct 09 10:43:23 PM UTC 24 | Oct 09 10:43:28 PM UTC 24 | 199975189 ps | ||
| T137 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_rw.2304833151 | Oct 09 10:43:25 PM UTC 24 | Oct 09 10:43:30 PM UTC 24 | 331442813 ps | ||
| T352 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1145262009 | Oct 09 10:42:03 PM UTC 24 | Oct 09 10:43:30 PM UTC 24 | 11959123207 ps | ||
| T206 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3274418042 | Oct 09 10:43:19 PM UTC 24 | Oct 09 10:43:31 PM UTC 24 | 1227328182 ps | ||
| T353 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1008107109 | Oct 09 10:43:32 PM UTC 24 | Oct 09 10:43:34 PM UTC 24 | 106902222 ps | ||
| T354 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1139668097 | Oct 09 10:43:32 PM UTC 24 | Oct 09 10:43:34 PM UTC 24 | 116419524 ps | ||
| T120 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1723386122 | Oct 09 10:43:31 PM UTC 24 | Oct 09 10:43:35 PM UTC 24 | 150852143 ps | ||
| T138 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4052788368 | Oct 09 10:42:57 PM UTC 24 | Oct 09 10:43:35 PM UTC 24 | 7373878766 ps | ||
| T355 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1633537613 | Oct 09 10:43:35 PM UTC 24 | Oct 09 10:43:37 PM UTC 24 | 340567064 ps | ||
| T356 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2567657226 | Oct 09 10:42:02 PM UTC 24 | Oct 09 10:43:39 PM UTC 24 | 14815727633 ps | ||
| T357 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3413860965 | Oct 09 10:43:38 PM UTC 24 | Oct 09 10:43:40 PM UTC 24 | 83593483 ps | ||
| T358 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2552326333 | Oct 09 10:44:06 PM UTC 24 | Oct 09 10:44:09 PM UTC 24 | 1463193704 ps | ||
| T166 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1777671219 | Oct 09 10:43:28 PM UTC 24 | Oct 09 10:43:42 PM UTC 24 | 2221709562 ps | ||
| T170 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3263742276 | Oct 09 10:42:19 PM UTC 24 | Oct 09 10:43:42 PM UTC 24 | 3777367403 ps | ||
| T149 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_aliasing.180900199 | Oct 09 10:42:59 PM UTC 24 | Oct 09 10:43:46 PM UTC 24 | 1646707387 ps | ||
| T359 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_walk.2009849671 | Oct 09 10:43:44 PM UTC 24 | Oct 09 10:43:46 PM UTC 24 | 76585790 ps | ||
| T360 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_partial_access.4251644626 | Oct 09 10:43:47 PM UTC 24 | Oct 09 10:43:49 PM UTC 24 | 55312404 ps | ||
| T361 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_errors.2485773396 | Oct 09 10:43:41 PM UTC 24 | Oct 09 10:43:50 PM UTC 24 | 405189633 ps | ||
| T157 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.21090236 | Oct 09 10:43:47 PM UTC 24 | Oct 09 10:43:52 PM UTC 24 | 314841056 ps | ||
| T362 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_rw.1728943429 | Oct 09 10:43:50 PM UTC 24 | Oct 09 10:43:55 PM UTC 24 | 331171695 ps | ||
| T150 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2556145185 | Oct 09 10:43:53 PM UTC 24 | Oct 09 10:43:59 PM UTC 24 | 94029126 ps | ||
| T116 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.1810116039 | Oct 09 10:43:14 PM UTC 24 | Oct 09 10:43:59 PM UTC 24 | 7477910546 ps | ||
| T363 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1108377940 | Oct 09 10:43:36 PM UTC 24 | Oct 09 10:43:59 PM UTC 24 | 7692470190 ps | ||
| T112 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.677062714 | Oct 09 10:43:56 PM UTC 24 | Oct 09 10:44:03 PM UTC 24 | 165593746 ps | ||
| T364 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3550428877 | Oct 09 10:43:59 PM UTC 24 | Oct 09 10:44:03 PM UTC 24 | 384979609 ps | ||
| T365 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1981023394 | Oct 09 10:43:59 PM UTC 24 | Oct 09 10:44:05 PM UTC 24 | 574476015 ps | ||
| T366 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.323256791 | Oct 09 10:44:03 PM UTC 24 | Oct 09 10:44:06 PM UTC 24 | 219237392 ps | ||
| T145 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1849027433 | Oct 09 10:44:04 PM UTC 24 | Oct 09 10:44:10 PM UTC 24 | 3890509907 ps | ||
| T109 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2073317886 | Oct 09 10:42:41 PM UTC 24 | Oct 09 10:44:11 PM UTC 24 | 9228449340 ps | ||
| T207 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3855066645 | Oct 09 10:43:42 PM UTC 24 | Oct 09 10:44:13 PM UTC 24 | 7904049286 ps | ||
| T367 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.29896480 | Oct 09 10:43:35 PM UTC 24 | Oct 09 10:44:14 PM UTC 24 | 11192004462 ps | ||
| T368 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_errors.2786781874 | Oct 09 10:44:12 PM UTC 24 | Oct 09 10:44:16 PM UTC 24 | 181498741 ps | ||
| T369 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.166389455 | Oct 09 10:43:09 PM UTC 24 | Oct 09 10:44:18 PM UTC 24 | 19269458822 ps | ||
| T370 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_walk.384493100 | Oct 09 10:44:15 PM UTC 24 | Oct 09 10:44:18 PM UTC 24 | 129810668 ps | ||
| T158 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.672434201 | Oct 09 10:43:27 PM UTC 24 | Oct 09 10:44:19 PM UTC 24 | 3103356551 ps | ||
| T146 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1509646219 | Oct 09 10:43:36 PM UTC 24 | Oct 09 10:44:20 PM UTC 24 | 10801197002 ps | ||
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| T372 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3815343888 | Oct 09 10:44:00 PM UTC 24 | Oct 09 10:44:24 PM UTC 24 | 3569282034 ps | ||
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| T374 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3231050525 | Oct 09 10:44:07 PM UTC 24 | Oct 09 10:44:25 PM UTC 24 | 10163574237 ps | ||
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| T376 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_errors.3500332740 | Oct 09 10:44:26 PM UTC 24 | Oct 09 10:44:33 PM UTC 24 | 987603317 ps | ||
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| T380 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.239339589 | Oct 09 10:43:12 PM UTC 24 | Oct 09 10:44:42 PM UTC 24 | 155035953690 ps | ||
| T381 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_errors.1347790961 | Oct 09 10:44:37 PM UTC 24 | Oct 09 10:44:43 PM UTC 24 | 143266914 ps | ||
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| T382 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.983891252 | Oct 09 10:44:43 PM UTC 24 | Oct 09 10:44:46 PM UTC 24 | 75504999 ps | ||
| T210 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2569949656 | Oct 09 10:44:26 PM UTC 24 | Oct 09 10:44:46 PM UTC 24 | 2232349871 ps | ||
| T383 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.895723335 | Oct 09 10:44:44 PM UTC 24 | Oct 09 10:44:46 PM UTC 24 | 217070641 ps | ||
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| T387 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_errors.3560270577 | Oct 09 10:44:48 PM UTC 24 | Oct 09 10:44:52 PM UTC 24 | 103300386 ps | ||
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| T390 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1288144164 | Oct 09 10:44:45 PM UTC 24 | Oct 09 10:44:57 PM UTC 24 | 2449023534 ps | ||
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| T154 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.577885719 | Oct 09 10:45:11 PM UTC 24 | Oct 09 10:45:21 PM UTC 24 | 1831733286 ps | ||
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| T426 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_errors.1591293603 | Oct 09 10:45:38 PM UTC 24 | Oct 09 10:45:43 PM UTC 24 | 400118759 ps | ||
| T427 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2489962649 | Oct 09 10:45:06 PM UTC 24 | Oct 09 10:45:43 PM UTC 24 | 5218776615 ps | ||
| T428 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_errors.3243535818 | Oct 09 10:45:34 PM UTC 24 | Oct 09 10:45:44 PM UTC 24 | 998526437 ps | ||
| T217 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3453671401 | Oct 09 10:45:23 PM UTC 24 | Oct 09 10:45:44 PM UTC 24 | 2311973300 ps | ||
| T429 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_rw.2057701906 | Oct 09 10:45:40 PM UTC 24 | Oct 09 10:45:45 PM UTC 24 | 332466166 ps | ||
| T430 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1786078353 | Oct 09 10:45:22 PM UTC 24 | Oct 09 10:45:45 PM UTC 24 | 8566070237 ps | ||
| T431 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3047390765 | Oct 09 10:45:42 PM UTC 24 | Oct 09 10:45:45 PM UTC 24 | 92682809 ps | ||
| T432 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.811826137 | Oct 09 10:45:38 PM UTC 24 | Oct 09 10:45:47 PM UTC 24 | 3553365662 ps | ||
| T156 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_rw.3903253543 | Oct 09 10:45:45 PM UTC 24 | Oct 09 10:45:48 PM UTC 24 | 84731514 ps | ||
| T433 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3838133248 | Oct 09 10:45:46 PM UTC 24 | Oct 09 10:45:49 PM UTC 24 | 84487184 ps | ||
| T434 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1995599925 | Oct 09 10:45:40 PM UTC 24 | Oct 09 10:45:49 PM UTC 24 | 389137288 ps | ||
| T118 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2418156368 | Oct 09 10:44:11 PM UTC 24 | Oct 09 10:45:49 PM UTC 24 | 8892322105 ps | ||
| T435 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2493178825 | Oct 09 10:45:42 PM UTC 24 | Oct 09 10:45:49 PM UTC 24 | 160506353 ps | ||
| T436 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2876975631 | Oct 09 10:45:46 PM UTC 24 | Oct 09 10:45:50 PM UTC 24 | 59658601 ps | ||
| T437 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.2925332268 | Oct 09 10:45:38 PM UTC 24 | Oct 09 10:45:51 PM UTC 24 | 4665443810 ps | ||
| T438 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_errors.2604387542 | Oct 09 10:45:45 PM UTC 24 | Oct 09 10:45:52 PM UTC 24 | 736607726 ps | ||
| T439 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2038985683 | Oct 09 10:45:46 PM UTC 24 | Oct 09 10:45:52 PM UTC 24 | 208548302 ps | ||
| T440 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.931812372 | Oct 09 10:45:46 PM UTC 24 | Oct 09 10:45:53 PM UTC 24 | 859330126 ps | ||
| T441 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3500608099 | Oct 09 10:45:51 PM UTC 24 | Oct 09 10:45:53 PM UTC 24 | 788499870 ps | ||
| T442 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_rw.318399835 | Oct 09 10:45:49 PM UTC 24 | Oct 09 10:45:55 PM UTC 24 | 1313253913 ps | ||
| T443 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.679694132 | Oct 09 10:45:51 PM UTC 24 | Oct 09 10:45:56 PM UTC 24 | 301767612 ps | ||
| T444 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_errors.3202330351 | Oct 09 10:45:49 PM UTC 24 | Oct 09 10:45:56 PM UTC 24 | 261082686 ps | ||
| T445 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_rw.4060344080 | Oct 09 10:45:54 PM UTC 24 | Oct 09 10:45:57 PM UTC 24 | 137481352 ps | ||
| T446 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.4154886917 | Oct 09 10:45:52 PM UTC 24 | Oct 09 10:45:58 PM UTC 24 | 1218339022 ps | ||
| T447 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1546930933 | Oct 09 10:45:35 PM UTC 24 | Oct 09 10:45:58 PM UTC 24 | 4052995616 ps | ||
| T448 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.418134501 | Oct 09 10:45:57 PM UTC 24 | Oct 09 10:46:00 PM UTC 24 | 134737870 ps | ||
| T449 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_errors.201906568 | Oct 09 10:45:53 PM UTC 24 | Oct 09 10:46:00 PM UTC 24 | 224021256 ps | ||
| T450 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1587257944 | Oct 09 10:45:49 PM UTC 24 | Oct 09 10:46:01 PM UTC 24 | 435778318 ps | ||
| T451 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.359655009 | Oct 09 10:45:27 PM UTC 24 | Oct 09 10:46:01 PM UTC 24 | 10483454553 ps | ||
| T452 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.526698259 | Oct 09 10:45:44 PM UTC 24 | Oct 09 10:46:01 PM UTC 24 | 16180693469 ps | ||
| T453 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1973704954 | Oct 09 10:45:53 PM UTC 24 | Oct 09 10:46:01 PM UTC 24 | 1919805272 ps | ||
| T454 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2945953845 | Oct 09 10:45:57 PM UTC 24 | Oct 09 10:46:01 PM UTC 24 | 48686632 ps | ||
| T455 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2855575333 | Oct 09 10:45:55 PM UTC 24 | Oct 09 10:46:03 PM UTC 24 | 255829624 ps | ||
| T213 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.4077385741 | Oct 09 10:45:49 PM UTC 24 | Oct 09 10:46:04 PM UTC 24 | 1862925097 ps | ||
| T456 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.2841465752 | Oct 09 10:44:36 PM UTC 24 | Oct 09 10:46:04 PM UTC 24 | 16474435452 ps | ||
| T457 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2885331924 | Oct 09 10:46:02 PM UTC 24 | Oct 09 10:46:06 PM UTC 24 | 51511849 ps | ||
| T458 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_rw.3254129423 | Oct 09 10:46:02 PM UTC 24 | Oct 09 10:46:06 PM UTC 24 | 255051971 ps | ||
| T459 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1296808441 | Oct 09 10:45:58 PM UTC 24 | Oct 09 10:46:07 PM UTC 24 | 5813415706 ps | ||
| T460 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.3083450131 | Oct 09 10:46:02 PM UTC 24 | Oct 09 10:46:08 PM UTC 24 | 1876194476 ps | ||
| T461 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_errors.784014667 | Oct 09 10:45:59 PM UTC 24 | Oct 09 10:46:08 PM UTC 24 | 223091284 ps | ||
| T462 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2779996817 | Oct 09 10:46:02 PM UTC 24 | Oct 09 10:46:08 PM UTC 24 | 605907335 ps | ||
| T463 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2109006539 | Oct 09 10:46:02 PM UTC 24 | Oct 09 10:46:09 PM UTC 24 | 1445945873 ps | ||
| T464 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_rw.4015504218 | Oct 09 10:46:05 PM UTC 24 | Oct 09 10:46:09 PM UTC 24 | 430476854 ps | ||
| T218 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_intg_err.788357987 | Oct 09 10:45:39 PM UTC 24 | Oct 09 10:46:10 PM UTC 24 | 2421890430 ps | ||
| T465 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2643176793 | Oct 09 10:45:58 PM UTC 24 | Oct 09 10:46:10 PM UTC 24 | 4680612343 ps | ||
| T466 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_errors.1945332163 | Oct 09 10:46:04 PM UTC 24 | Oct 09 10:46:11 PM UTC 24 | 306985417 ps | ||
| T467 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2641946218 | Oct 09 10:46:07 PM UTC 24 | Oct 09 10:46:11 PM UTC 24 | 66668198 ps | ||
| T468 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1366045426 | Oct 09 10:46:02 PM UTC 24 | Oct 09 10:46:13 PM UTC 24 | 11756980827 ps | ||
| T214 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3773763777 | Oct 09 10:45:45 PM UTC 24 | Oct 09 10:46:14 PM UTC 24 | 12913090066 ps | ||
| T469 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3530080367 | Oct 09 10:46:01 PM UTC 24 | Oct 09 10:46:15 PM UTC 24 | 1611182406 ps | ||
| T470 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2941061070 | Oct 09 10:45:44 PM UTC 24 | Oct 09 10:46:18 PM UTC 24 | 6377991289 ps | ||
| T471 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2964493641 | Oct 09 10:46:06 PM UTC 24 | Oct 09 10:46:18 PM UTC 24 | 2068809338 ps | ||
| T472 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3847493990 | Oct 09 10:45:54 PM UTC 24 | Oct 09 10:46:25 PM UTC 24 | 5054894892 ps | ||
| T473 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1572205951 | Oct 09 10:46:05 PM UTC 24 | Oct 09 10:46:27 PM UTC 24 | 2694382610 ps | ||
| T474 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.16489929 | Oct 09 10:42:03 PM UTC 24 | Oct 09 10:46:33 PM UTC 24 | 64185720268 ps | ||
| T475 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.393562976 | Oct 09 10:45:32 PM UTC 24 | Oct 09 10:46:34 PM UTC 24 | 18032700448 ps | ||
| T476 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.3176739450 | Oct 09 10:45:48 PM UTC 24 | Oct 09 10:46:48 PM UTC 24 | 19153358832 ps | ||
| T477 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2099073073 | Oct 09 10:45:22 PM UTC 24 | Oct 09 10:47:01 PM UTC 24 | 26207179192 ps | ||
| T478 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3914015785 | Oct 09 10:43:40 PM UTC 24 | Oct 09 10:48:16 PM UTC 24 | 70788367319 ps | ||
| T479 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2697434050 | Oct 09 10:44:10 PM UTC 24 | Oct 09 10:48:19 PM UTC 24 | 82312752048 ps | ||
| T480 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2817729240 | Oct 09 10:42:40 PM UTC 24 | Oct 09 10:49:21 PM UTC 24 | 219934675114 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.3431660494 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 3089767013 ps |
| CPU time | 4.05 seconds |
| Started | Oct 09 10:49:24 PM UTC 24 |
| Finished | Oct 09 10:49:30 PM UTC 24 |
| Peak memory | 233012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431660494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.3431660494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.2699549530 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 6208729582 ps |
| CPU time | 26.52 seconds |
| Started | Oct 09 10:49:37 PM UTC 24 |
| Finished | Oct 09 10:50:05 PM UTC 24 |
| Peak memory | 233108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2699549530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stres s_all_with_rand_reset.2699549530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_busy.1335677411 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1384272707 ps |
| CPU time | 2.77 seconds |
| Started | Oct 09 10:49:24 PM UTC 24 |
| Finished | Oct 09 10:49:28 PM UTC 24 |
| Peak memory | 215608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335677411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.1335677411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_cmderr_busy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.3058991066 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 3273456493 ps |
| CPU time | 5.18 seconds |
| Started | Oct 09 10:49:35 PM UTC 24 |
| Finished | Oct 09 10:49:42 PM UTC 24 |
| Peak memory | 226316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058991066 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.3058991066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.4205326269 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 70242451 ps |
| CPU time | 1.12 seconds |
| Started | Oct 09 10:49:39 PM UTC 24 |
| Finished | Oct 09 10:49:41 PM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205326269 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.4205326269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/3.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all_with_rand_reset.1769036947 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 63575261690 ps |
| CPU time | 63.29 seconds |
| Started | Oct 09 10:49:45 PM UTC 24 |
| Finished | Oct 09 10:50:50 PM UTC 24 |
| Peak memory | 243388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1769036947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stres s_all_with_rand_reset.1769036947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.4214058001 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 3671036274 ps |
| CPU time | 28.75 seconds |
| Started | Oct 09 10:42:09 PM UTC 24 |
| Finished | Oct 09 10:42:39 PM UTC 24 |
| Peak memory | 226140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214058001 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.4214058001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.4059871779 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 454953614 ps |
| CPU time | 1.66 seconds |
| Started | Oct 09 10:49:29 PM UTC 24 |
| Finished | Oct 09 10:49:32 PM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059871779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_abstractcmd_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.4059871779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_abstractcmd_status/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.2772393775 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 2201821596 ps |
| CPU time | 48.53 seconds |
| Started | Oct 09 10:43:41 PM UTC 24 |
| Finished | Oct 09 10:44:32 PM UTC 24 |
| Peak memory | 232764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2772393775 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_re set.2772393775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/3.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.133075098 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 697611443 ps |
| CPU time | 2.08 seconds |
| Started | Oct 09 10:49:31 PM UTC 24 |
| Finished | Oct 09 10:49:34 PM UTC 24 |
| Peak memory | 254488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133075098 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.133075098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.3251655814 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 264455302 ps |
| CPU time | 1.36 seconds |
| Started | Oct 09 10:49:36 PM UTC 24 |
| Finished | Oct 09 10:49:39 PM UTC 24 |
| Peak memory | 257336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251655814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_buffered_enable.3251655814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/2.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.3830749014 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 1873713400 ps |
| CPU time | 57.56 seconds |
| Started | Oct 09 10:44:26 PM UTC 24 |
| Finished | Oct 09 10:45:25 PM UTC 24 |
| Peak memory | 227972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3830749014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_re set.3830749014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/5.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/12.rv_dm_stress_all.2794121099 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 807440737 ps |
| CPU time | 4.37 seconds |
| Started | Oct 09 10:49:57 PM UTC 24 |
| Finished | Oct 09 10:50:03 PM UTC 24 |
| Peak memory | 226380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794121099 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.2794121099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/12.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.2264319204 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 2253642284 ps |
| CPU time | 34.21 seconds |
| Started | Oct 09 10:49:38 PM UTC 24 |
| Finished | Oct 09 10:50:14 PM UTC 24 |
| Peak memory | 228488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2264319204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stres s_all_with_rand_reset.2264319204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.2811599321 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1589311207 ps |
| CPU time | 3.77 seconds |
| Started | Oct 09 10:49:29 PM UTC 24 |
| Finished | Oct 09 10:49:34 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811599321 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.2811599321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/11.rv_dm_autoincr_sba_tl_access.3929064234 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 5235229133 ps |
| CPU time | 18.9 seconds |
| Started | Oct 09 10:49:55 PM UTC 24 |
| Finished | Oct 09 10:50:16 PM UTC 24 |
| Peak memory | 226368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929064234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.3929064234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/11.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2073317886 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 9228449340 ps |
| CPU time | 87.3 seconds |
| Started | Oct 09 10:42:41 PM UTC 24 |
| Finished | Oct 09 10:44:11 PM UTC 24 |
| Peak memory | 232668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2073317886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_re set.2073317886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.428917055 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 120080355 ps |
| CPU time | 3.5 seconds |
| Started | Oct 09 10:42:52 PM UTC 24 |
| Finished | Oct 09 10:42:56 PM UTC 24 |
| Peak memory | 225976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428917055 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.428917055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.3486499253 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 4874415043 ps |
| CPU time | 80.32 seconds |
| Started | Oct 09 10:49:52 PM UTC 24 |
| Finished | Oct 09 10:51:15 PM UTC 24 |
| Peak memory | 233112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3486499253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stres s_all_with_rand_reset.3486499253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.4106353817 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 122835012 ps |
| CPU time | 0.98 seconds |
| Started | Oct 09 10:49:29 PM UTC 24 |
| Finished | Oct 09 10:49:32 PM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106353817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.4106353817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_dmi_failed_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/21.rv_dm_stress_all.1445873403 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 4191587999 ps |
| CPU time | 7.91 seconds |
| Started | Oct 09 10:50:17 PM UTC 24 |
| Finished | Oct 09 10:50:26 PM UTC 24 |
| Peak memory | 215996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445873403 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.1445873403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/21.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/15.rv_dm_autoincr_sba_tl_access.2903234474 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 13145293534 ps |
| CPU time | 20.57 seconds |
| Started | Oct 09 10:50:03 PM UTC 24 |
| Finished | Oct 09 10:50:25 PM UTC 24 |
| Peak memory | 226192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903234474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.2903234474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/15.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.2228440018 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 519312944 ps |
| CPU time | 0.89 seconds |
| Started | Oct 09 10:49:32 PM UTC 24 |
| Finished | Oct 09 10:49:34 PM UTC 24 |
| Peak memory | 215404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228440018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.2228440018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_cmderr_exception/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_rom_read_access.2922304141 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 57264631 ps |
| CPU time | 0.96 seconds |
| Started | Oct 09 10:49:34 PM UTC 24 |
| Finished | Oct 09 10:49:37 PM UTC 24 |
| Peak memory | 225268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922304141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_rom_read_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.2922304141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_rom_read_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/14.rv_dm_autoincr_sba_tl_access.1287467000 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 1512095478 ps |
| CPU time | 2.78 seconds |
| Started | Oct 09 10:50:02 PM UTC 24 |
| Finished | Oct 09 10:50:07 PM UTC 24 |
| Peak memory | 226212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287467000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.1287467000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/14.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3855066645 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 7904049286 ps |
| CPU time | 29.15 seconds |
| Started | Oct 09 10:43:42 PM UTC 24 |
| Finished | Oct 09 10:44:13 PM UTC 24 |
| Peak memory | 225916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855066645 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.3855066645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/3.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.3144841231 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 7062953339 ps |
| CPU time | 11.14 seconds |
| Started | Oct 09 10:49:40 PM UTC 24 |
| Finished | Oct 09 10:49:53 PM UTC 24 |
| Peak memory | 226636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144841231 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.3144841231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/4.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/12.rv_dm_autoincr_sba_tl_access.1353993989 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 59246206253 ps |
| CPU time | 227.99 seconds |
| Started | Oct 09 10:49:57 PM UTC 24 |
| Finished | Oct 09 10:53:49 PM UTC 24 |
| Peak memory | 226384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353993989 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.1353993989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/12.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/15.rv_dm_stress_all.3665495201 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 2331420217 ps |
| CPU time | 11.55 seconds |
| Started | Oct 09 10:50:05 PM UTC 24 |
| Finished | Oct 09 10:50:17 PM UTC 24 |
| Peak memory | 226308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665495201 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.3665495201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/15.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.2624769551 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 715724060 ps |
| CPU time | 2.53 seconds |
| Started | Oct 09 10:49:29 PM UTC 24 |
| Finished | Oct 09 10:49:33 PM UTC 24 |
| Peak memory | 216136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624769551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.2624769551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_sba_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.3233571472 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 6879489947 ps |
| CPU time | 73.69 seconds |
| Started | Oct 09 10:49:35 PM UTC 24 |
| Finished | Oct 09 10:50:52 PM UTC 24 |
| Peak memory | 232840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3233571472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stres s_all_with_rand_reset.3233571472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.1442563592 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 5399053263 ps |
| CPU time | 6.26 seconds |
| Started | Oct 09 10:50:17 PM UTC 24 |
| Finished | Oct 09 10:50:24 PM UTC 24 |
| Peak memory | 226428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442563592 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.1442563592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/22.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_intg_err.788357987 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 2421890430 ps |
| CPU time | 28.5 seconds |
| Started | Oct 09 10:45:39 PM UTC 24 |
| Finished | Oct 09 10:46:10 PM UTC 24 |
| Peak memory | 225952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788357987 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.788357987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/14.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/15.rv_dm_bad_sba_tl_access.1623105532 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 3790687316 ps |
| CPU time | 6.86 seconds |
| Started | Oct 09 10:50:03 PM UTC 24 |
| Finished | Oct 09 10:50:11 PM UTC 24 |
| Peak memory | 226436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623105532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.1623105532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/15.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/45.rv_dm_stress_all.3194403923 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 7255539768 ps |
| CPU time | 12.4 seconds |
| Started | Oct 09 10:50:31 PM UTC 24 |
| Finished | Oct 09 10:50:45 PM UTC 24 |
| Peak memory | 216064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194403923 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.3194403923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/45.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1653405528 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 1291429722 ps |
| CPU time | 3.34 seconds |
| Started | Oct 09 10:42:02 PM UTC 24 |
| Finished | Oct 09 10:42:08 PM UTC 24 |
| Peak memory | 215332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653405528 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_aliasing.1653405528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1074637716 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 4986648660 ps |
| CPU time | 7.47 seconds |
| Started | Oct 09 10:42:02 PM UTC 24 |
| Finished | Oct 09 10:42:12 PM UTC 24 |
| Peak memory | 215812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074637716 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_hw_reset.1074637716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2036462680 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 166785585 ps |
| CPU time | 9.8 seconds |
| Started | Oct 09 10:42:17 PM UTC 24 |
| Finished | Oct 09 10:42:28 PM UTC 24 |
| Peak memory | 215896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036462680 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_csr_outstanding.2036462680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_aliasing.180900199 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 1646707387 ps |
| CPU time | 44.99 seconds |
| Started | Oct 09 10:42:59 PM UTC 24 |
| Finished | Oct 09 10:43:46 PM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180900199 -asse rt nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_aliasing.180900199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/2.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.49000722 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 162593380 ps |
| CPU time | 1.33 seconds |
| Started | Oct 09 10:49:29 PM UTC 24 |
| Finished | Oct 09 10:49:32 PM UTC 24 |
| Peak memory | 225328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49000722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv _dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sparse_lc_gate_fsm.49000722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_sparse_lc_gate_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.1970149722 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 161798318 ps |
| CPU time | 1.35 seconds |
| Started | Oct 09 10:49:26 PM UTC 24 |
| Finished | Oct 09 10:49:29 PM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970149722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.1970149722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_cmderr_halt_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/17.rv_dm_stress_all.899501675 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 2902870123 ps |
| CPU time | 12.68 seconds |
| Started | Oct 09 10:50:10 PM UTC 24 |
| Finished | Oct 09 10:50:23 PM UTC 24 |
| Peak memory | 216140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899501675 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.899501675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/17.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3773763777 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 12913090066 ps |
| CPU time | 27.32 seconds |
| Started | Oct 09 10:45:45 PM UTC 24 |
| Finished | Oct 09 10:46:14 PM UTC 24 |
| Peak memory | 225932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773763777 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.3773763777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/15.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.4051267925 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 120291177 ps |
| CPU time | 1.05 seconds |
| Started | Oct 09 10:49:35 PM UTC 24 |
| Finished | Oct 09 10:49:38 PM UTC 24 |
| Peak memory | 225328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051267925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sparse_lc_gate_fsm.4051267925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_sparse_lc_gate_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1427216148 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 7699197303 ps |
| CPU time | 39.21 seconds |
| Started | Oct 09 10:42:01 PM UTC 24 |
| Finished | Oct 09 10:42:41 PM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427216148 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_aliasing.1427216148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2932020576 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 2899845326 ps |
| CPU time | 63.38 seconds |
| Started | Oct 09 10:42:14 PM UTC 24 |
| Finished | Oct 09 10:43:19 PM UTC 24 |
| Peak memory | 215528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932020576 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.2932020576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2441584588 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 375416490 ps |
| CPU time | 3.71 seconds |
| Started | Oct 09 10:42:13 PM UTC 24 |
| Finished | Oct 09 10:42:18 PM UTC 24 |
| Peak memory | 225816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441584588 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.2441584588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1270355644 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 326663633 ps |
| CPU time | 4.97 seconds |
| Started | Oct 09 10:42:18 PM UTC 24 |
| Finished | Oct 09 10:42:25 PM UTC 24 |
| Peak memory | 232376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1270355644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_r and_reset.1270355644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.1473657562 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 84330196 ps |
| CPU time | 3.1 seconds |
| Started | Oct 09 10:42:14 PM UTC 24 |
| Finished | Oct 09 10:42:18 PM UTC 24 |
| Peak memory | 226048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473657562 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.1473657562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.16489929 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 64185720268 ps |
| CPU time | 265.36 seconds |
| Started | Oct 09 10:42:03 PM UTC 24 |
| Finished | Oct 09 10:46:33 PM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16489929 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_aliasing.16489929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1145262009 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 11959123207 ps |
| CPU time | 84.16 seconds |
| Started | Oct 09 10:42:03 PM UTC 24 |
| Finished | Oct 09 10:43:30 PM UTC 24 |
| Peak memory | 215492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145262009 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_bit_bash.1145262009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2240142498 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 3128029516 ps |
| CPU time | 5.41 seconds |
| Started | Oct 09 10:42:02 PM UTC 24 |
| Finished | Oct 09 10:42:10 PM UTC 24 |
| Peak memory | 215576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240142498 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.2240142498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2567657226 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 14815727633 ps |
| CPU time | 93.72 seconds |
| Started | Oct 09 10:42:02 PM UTC 24 |
| Finished | Oct 09 10:43:39 PM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567657226 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_bit_bash.2567657226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2312344375 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 264454656 ps |
| CPU time | 2.14 seconds |
| Started | Oct 09 10:42:01 PM UTC 24 |
| Finished | Oct 09 10:42:04 PM UTC 24 |
| Peak memory | 215328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312344375 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_hw_reset.2312344375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.678135807 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 230426217 ps |
| CPU time | 1.17 seconds |
| Started | Oct 09 10:42:01 PM UTC 24 |
| Finished | Oct 09 10:42:03 PM UTC 24 |
| Peak memory | 214612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678135807 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.678135807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1394364935 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 188244139 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 10:42:11 PM UTC 24 |
| Finished | Oct 09 10:42:13 PM UTC 24 |
| Peak memory | 215128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394364935 -assert nopostproc +UVM _TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_partial_access.1394364935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.2593987184 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 164199970 ps |
| CPU time | 1.25 seconds |
| Started | Oct 09 10:42:11 PM UTC 24 |
| Finished | Oct 09 10:42:13 PM UTC 24 |
| Peak memory | 215128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593987184 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.2593987184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.412466814 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 2807389882 ps |
| CPU time | 49.6 seconds |
| Started | Oct 09 10:42:05 PM UTC 24 |
| Finished | Oct 09 10:42:56 PM UTC 24 |
| Peak memory | 228036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=412466814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.412466814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.2378490583 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 159149408 ps |
| CPU time | 3.89 seconds |
| Started | Oct 09 10:42:05 PM UTC 24 |
| Finished | Oct 09 10:42:10 PM UTC 24 |
| Peak memory | 225852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378490583 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.2378490583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3263742276 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 3777367403 ps |
| CPU time | 80.6 seconds |
| Started | Oct 09 10:42:19 PM UTC 24 |
| Finished | Oct 09 10:43:42 PM UTC 24 |
| Peak memory | 226012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263742276 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_aliasing.3263742276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4052788368 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 7373878766 ps |
| CPU time | 36.97 seconds |
| Started | Oct 09 10:42:57 PM UTC 24 |
| Finished | Oct 09 10:43:35 PM UTC 24 |
| Peak memory | 226012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052788368 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.4052788368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2621293157 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 629610779 ps |
| CPU time | 4.58 seconds |
| Started | Oct 09 10:42:52 PM UTC 24 |
| Finished | Oct 09 10:42:57 PM UTC 24 |
| Peak memory | 225728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621293157 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2621293157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.236754288 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 128432365 ps |
| CPU time | 6.31 seconds |
| Started | Oct 09 10:42:58 PM UTC 24 |
| Finished | Oct 09 10:43:05 PM UTC 24 |
| Peak memory | 230148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=236754288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_ra nd_reset.236754288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2817729240 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 219934675114 ps |
| CPU time | 396.29 seconds |
| Started | Oct 09 10:42:40 PM UTC 24 |
| Finished | Oct 09 10:49:21 PM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817729240 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_aliasing.2817729240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3292723662 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 9801179111 ps |
| CPU time | 16.76 seconds |
| Started | Oct 09 10:42:40 PM UTC 24 |
| Finished | Oct 09 10:42:58 PM UTC 24 |
| Peak memory | 215492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292723662 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_bit_bash.3292723662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3584250852 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 1949817138 ps |
| CPU time | 4.41 seconds |
| Started | Oct 09 10:42:34 PM UTC 24 |
| Finished | Oct 09 10:42:39 PM UTC 24 |
| Peak memory | 215612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584250852 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_hw_reset.3584250852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.837665430 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 2924943414 ps |
| CPU time | 5.5 seconds |
| Started | Oct 09 10:42:36 PM UTC 24 |
| Finished | Oct 09 10:42:43 PM UTC 24 |
| Peak memory | 215488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837665430 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.837665430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1696023149 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 2385131578 ps |
| CPU time | 8.97 seconds |
| Started | Oct 09 10:42:34 PM UTC 24 |
| Finished | Oct 09 10:42:44 PM UTC 24 |
| Peak memory | 215588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696023149 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_aliasing.1696023149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3248840619 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 15937423600 ps |
| CPU time | 9.43 seconds |
| Started | Oct 09 10:42:30 PM UTC 24 |
| Finished | Oct 09 10:42:40 PM UTC 24 |
| Peak memory | 215768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248840619 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_bit_bash.3248840619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.559109714 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 848148111 ps |
| CPU time | 6.29 seconds |
| Started | Oct 09 10:42:25 PM UTC 24 |
| Finished | Oct 09 10:42:33 PM UTC 24 |
| Peak memory | 215332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559109714 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_hw_reset.559109714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2303793663 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 667994701 ps |
| CPU time | 5.41 seconds |
| Started | Oct 09 10:42:28 PM UTC 24 |
| Finished | Oct 09 10:42:35 PM UTC 24 |
| Peak memory | 215520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303793663 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.2303793663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1796870264 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 105667809 ps |
| CPU time | 1.03 seconds |
| Started | Oct 09 10:42:48 PM UTC 24 |
| Finished | Oct 09 10:42:51 PM UTC 24 |
| Peak memory | 215188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796870264 -assert nopostproc +UVM _TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_partial_access.1796870264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.351171127 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 57614739 ps |
| CPU time | 1.17 seconds |
| Started | Oct 09 10:42:45 PM UTC 24 |
| Finished | Oct 09 10:42:48 PM UTC 24 |
| Peak memory | 215128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351171127 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.351171127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2705948911 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 993368643 ps |
| CPU time | 3.99 seconds |
| Started | Oct 09 10:42:58 PM UTC 24 |
| Finished | Oct 09 10:43:03 PM UTC 24 |
| Peak memory | 215640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705948911 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_csr_outstanding.2705948911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.2967512814 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 802323195 ps |
| CPU time | 7.05 seconds |
| Started | Oct 09 10:42:42 PM UTC 24 |
| Finished | Oct 09 10:42:50 PM UTC 24 |
| Peak memory | 226192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967512814 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.2967512814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3734888864 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 1758706633 ps |
| CPU time | 13.87 seconds |
| Started | Oct 09 10:42:43 PM UTC 24 |
| Finished | Oct 09 10:42:58 PM UTC 24 |
| Peak memory | 225852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734888864 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.3734888864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2451587450 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 97018889 ps |
| CPU time | 4.53 seconds |
| Started | Oct 09 10:45:18 PM UTC 24 |
| Finished | Oct 09 10:45:24 PM UTC 24 |
| Peak memory | 229964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2451587450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_ rand_reset.2451587450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/10.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.1329296330 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 210932957 ps |
| CPU time | 2.41 seconds |
| Started | Oct 09 10:45:18 PM UTC 24 |
| Finished | Oct 09 10:45:21 PM UTC 24 |
| Peak memory | 225780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329296330 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.1329296330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/10.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.1814163722 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 15475380111 ps |
| CPU time | 23.2 seconds |
| Started | Oct 09 10:45:15 PM UTC 24 |
| Finished | Oct 09 10:45:39 PM UTC 24 |
| Peak memory | 215492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814163722 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_bit_bash.1814163722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/10.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1205686492 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 2876051640 ps |
| CPU time | 15.4 seconds |
| Started | Oct 09 10:45:14 PM UTC 24 |
| Finished | Oct 09 10:45:31 PM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205686492 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.1205686492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/10.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2723686624 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 78859528 ps |
| CPU time | 1.44 seconds |
| Started | Oct 09 10:45:14 PM UTC 24 |
| Finished | Oct 09 10:45:17 PM UTC 24 |
| Peak memory | 215128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723686624 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.2723686624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/10.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2173893534 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 296041809 ps |
| CPU time | 6.55 seconds |
| Started | Oct 09 10:45:18 PM UTC 24 |
| Finished | Oct 09 10:45:26 PM UTC 24 |
| Peak memory | 215812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173893534 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_csr_outstanding.2173893534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/10.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.3201289817 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 590019659 ps |
| CPU time | 5.09 seconds |
| Started | Oct 09 10:45:16 PM UTC 24 |
| Finished | Oct 09 10:45:22 PM UTC 24 |
| Peak memory | 226100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201289817 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.3201289817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/10.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3099122797 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 3154962292 ps |
| CPU time | 10.68 seconds |
| Started | Oct 09 10:45:18 PM UTC 24 |
| Finished | Oct 09 10:45:30 PM UTC 24 |
| Peak memory | 225912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099122797 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.3099122797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/10.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3312798647 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 239669152 ps |
| CPU time | 4.65 seconds |
| Started | Oct 09 10:45:25 PM UTC 24 |
| Finished | Oct 09 10:45:30 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3312798647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_ rand_reset.3312798647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/11.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_rw.4239018807 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 143345498 ps |
| CPU time | 2.46 seconds |
| Started | Oct 09 10:45:23 PM UTC 24 |
| Finished | Oct 09 10:45:27 PM UTC 24 |
| Peak memory | 225780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239018807 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.4239018807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/11.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2099073073 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 26207179192 ps |
| CPU time | 96.57 seconds |
| Started | Oct 09 10:45:22 PM UTC 24 |
| Finished | Oct 09 10:47:01 PM UTC 24 |
| Peak memory | 215484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099073073 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_bit_bash.2099073073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/11.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1786078353 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 8566070237 ps |
| CPU time | 21.82 seconds |
| Started | Oct 09 10:45:22 PM UTC 24 |
| Finished | Oct 09 10:45:45 PM UTC 24 |
| Peak memory | 215484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786078353 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.1786078353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/11.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2562421666 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 306393211 ps |
| CPU time | 2.87 seconds |
| Started | Oct 09 10:45:19 PM UTC 24 |
| Finished | Oct 09 10:45:23 PM UTC 24 |
| Peak memory | 215332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562421666 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.2562421666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/11.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.712676233 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 307166467 ps |
| CPU time | 8.86 seconds |
| Started | Oct 09 10:45:24 PM UTC 24 |
| Finished | Oct 09 10:45:35 PM UTC 24 |
| Peak memory | 215648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712676233 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_csr_outstanding.712676233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/11.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_errors.983806995 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 301531327 ps |
| CPU time | 6.45 seconds |
| Started | Oct 09 10:45:22 PM UTC 24 |
| Finished | Oct 09 10:45:30 PM UTC 24 |
| Peak memory | 225936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983806995 -assert nopostproc +UVM_TESTNAME=rv_dm_base _test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.983806995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/11.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3453671401 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 2311973300 ps |
| CPU time | 19.82 seconds |
| Started | Oct 09 10:45:23 PM UTC 24 |
| Finished | Oct 09 10:45:44 PM UTC 24 |
| Peak memory | 225932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453671401 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.3453671401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/11.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.495630082 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 124729165 ps |
| CPU time | 4.29 seconds |
| Started | Oct 09 10:45:31 PM UTC 24 |
| Finished | Oct 09 10:45:37 PM UTC 24 |
| Peak memory | 227916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=495630082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_r and_reset.495630082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/12.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_rw.979308750 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 138088239 ps |
| CPU time | 2.62 seconds |
| Started | Oct 09 10:45:30 PM UTC 24 |
| Finished | Oct 09 10:45:34 PM UTC 24 |
| Peak memory | 225732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979308750 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.979308750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/12.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.359655009 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 10483454553 ps |
| CPU time | 32.51 seconds |
| Started | Oct 09 10:45:27 PM UTC 24 |
| Finished | Oct 09 10:46:01 PM UTC 24 |
| Peak memory | 215580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359655009 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_bit_bash.359655009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/12.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3126728302 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 2841306807 ps |
| CPU time | 6.33 seconds |
| Started | Oct 09 10:45:27 PM UTC 24 |
| Finished | Oct 09 10:45:34 PM UTC 24 |
| Peak memory | 215484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126728302 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.3126728302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/12.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2512470070 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 108766519 ps |
| CPU time | 1.19 seconds |
| Started | Oct 09 10:45:27 PM UTC 24 |
| Finished | Oct 09 10:45:29 PM UTC 24 |
| Peak memory | 215128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512470070 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.2512470070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/12.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.168957243 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 104494382 ps |
| CPU time | 5.63 seconds |
| Started | Oct 09 10:45:30 PM UTC 24 |
| Finished | Oct 09 10:45:37 PM UTC 24 |
| Peak memory | 215620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168957243 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same_csr_outstanding.168957243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/12.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_errors.2137455894 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 590835840 ps |
| CPU time | 4.5 seconds |
| Started | Oct 09 10:45:28 PM UTC 24 |
| Finished | Oct 09 10:45:33 PM UTC 24 |
| Peak memory | 226128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137455894 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.2137455894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/12.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3662516075 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 2988069582 ps |
| CPU time | 12.44 seconds |
| Started | Oct 09 10:45:29 PM UTC 24 |
| Finished | Oct 09 10:45:43 PM UTC 24 |
| Peak memory | 225932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662516075 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.3662516075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/12.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.4100623870 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 312379807 ps |
| CPU time | 4.57 seconds |
| Started | Oct 09 10:45:36 PM UTC 24 |
| Finished | Oct 09 10:45:42 PM UTC 24 |
| Peak memory | 230024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=4100623870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_ rand_reset.4100623870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/13.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_rw.1685657176 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 182388658 ps |
| CPU time | 2.31 seconds |
| Started | Oct 09 10:45:36 PM UTC 24 |
| Finished | Oct 09 10:45:39 PM UTC 24 |
| Peak memory | 225780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685657176 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.1685657176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/13.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.393562976 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 18032700448 ps |
| CPU time | 59.75 seconds |
| Started | Oct 09 10:45:32 PM UTC 24 |
| Finished | Oct 09 10:46:34 PM UTC 24 |
| Peak memory | 215492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393562976 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_bit_bash.393562976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/13.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1465901231 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 2626617343 ps |
| CPU time | 5.62 seconds |
| Started | Oct 09 10:45:31 PM UTC 24 |
| Finished | Oct 09 10:45:38 PM UTC 24 |
| Peak memory | 215572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465901231 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.1465901231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/13.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3232984036 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 158654499 ps |
| CPU time | 1.58 seconds |
| Started | Oct 09 10:45:31 PM UTC 24 |
| Finished | Oct 09 10:45:34 PM UTC 24 |
| Peak memory | 215188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232984036 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.3232984036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/13.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3267307236 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 362417539 ps |
| CPU time | 5.71 seconds |
| Started | Oct 09 10:45:36 PM UTC 24 |
| Finished | Oct 09 10:45:43 PM UTC 24 |
| Peak memory | 215844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267307236 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_csr_outstanding.3267307236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/13.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_errors.3243535818 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 998526437 ps |
| CPU time | 7.84 seconds |
| Started | Oct 09 10:45:34 PM UTC 24 |
| Finished | Oct 09 10:45:44 PM UTC 24 |
| Peak memory | 225908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243535818 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.3243535818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/13.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1546930933 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 4052995616 ps |
| CPU time | 21.87 seconds |
| Started | Oct 09 10:45:35 PM UTC 24 |
| Finished | Oct 09 10:45:58 PM UTC 24 |
| Peak memory | 225960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546930933 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.1546930933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/13.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2493178825 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 160506353 ps |
| CPU time | 4.91 seconds |
| Started | Oct 09 10:45:42 PM UTC 24 |
| Finished | Oct 09 10:45:49 PM UTC 24 |
| Peak memory | 229756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2493178825 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_ rand_reset.2493178825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/14.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_rw.2057701906 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 332466166 ps |
| CPU time | 3.14 seconds |
| Started | Oct 09 10:45:40 PM UTC 24 |
| Finished | Oct 09 10:45:45 PM UTC 24 |
| Peak memory | 225912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057701906 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.2057701906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/14.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.2925332268 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 4665443810 ps |
| CPU time | 11.59 seconds |
| Started | Oct 09 10:45:38 PM UTC 24 |
| Finished | Oct 09 10:45:51 PM UTC 24 |
| Peak memory | 215624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925332268 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_bit_bash.2925332268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/14.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.811826137 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 3553365662 ps |
| CPU time | 8.28 seconds |
| Started | Oct 09 10:45:38 PM UTC 24 |
| Finished | Oct 09 10:45:47 PM UTC 24 |
| Peak memory | 215640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811826137 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.811826137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/14.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.3383961860 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 972992083 ps |
| CPU time | 2.88 seconds |
| Started | Oct 09 10:45:37 PM UTC 24 |
| Finished | Oct 09 10:45:41 PM UTC 24 |
| Peak memory | 215588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383961860 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.3383961860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/14.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1995599925 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 389137288 ps |
| CPU time | 6.83 seconds |
| Started | Oct 09 10:45:40 PM UTC 24 |
| Finished | Oct 09 10:45:49 PM UTC 24 |
| Peak memory | 215564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995599925 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same_csr_outstanding.1995599925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/14.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_errors.1591293603 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 400118759 ps |
| CPU time | 3.92 seconds |
| Started | Oct 09 10:45:38 PM UTC 24 |
| Finished | Oct 09 10:45:43 PM UTC 24 |
| Peak memory | 225936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591293603 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.1591293603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/14.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2876975631 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 59658601 ps |
| CPU time | 2.36 seconds |
| Started | Oct 09 10:45:46 PM UTC 24 |
| Finished | Oct 09 10:45:50 PM UTC 24 |
| Peak memory | 230152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2876975631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_ rand_reset.2876975631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/15.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_rw.3903253543 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 84731514 ps |
| CPU time | 2.11 seconds |
| Started | Oct 09 10:45:45 PM UTC 24 |
| Finished | Oct 09 10:45:48 PM UTC 24 |
| Peak memory | 225784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903253543 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.3903253543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/15.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.526698259 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 16180693469 ps |
| CPU time | 15.88 seconds |
| Started | Oct 09 10:45:44 PM UTC 24 |
| Finished | Oct 09 10:46:01 PM UTC 24 |
| Peak memory | 215492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526698259 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_bit_bash.526698259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/15.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2941061070 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 6377991289 ps |
| CPU time | 32.29 seconds |
| Started | Oct 09 10:45:44 PM UTC 24 |
| Finished | Oct 09 10:46:18 PM UTC 24 |
| Peak memory | 215484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941061070 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.2941061070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/15.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3047390765 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 92682809 ps |
| CPU time | 1.42 seconds |
| Started | Oct 09 10:45:42 PM UTC 24 |
| Finished | Oct 09 10:45:45 PM UTC 24 |
| Peak memory | 214788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047390765 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.3047390765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/15.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2038985683 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 208548302 ps |
| CPU time | 4.78 seconds |
| Started | Oct 09 10:45:46 PM UTC 24 |
| Finished | Oct 09 10:45:52 PM UTC 24 |
| Peak memory | 215516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038985683 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_csr_outstanding.2038985683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/15.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_errors.2604387542 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 736607726 ps |
| CPU time | 5.77 seconds |
| Started | Oct 09 10:45:45 PM UTC 24 |
| Finished | Oct 09 10:45:52 PM UTC 24 |
| Peak memory | 226168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604387542 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.2604387542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/15.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.679694132 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 301767612 ps |
| CPU time | 4.3 seconds |
| Started | Oct 09 10:45:51 PM UTC 24 |
| Finished | Oct 09 10:45:56 PM UTC 24 |
| Peak memory | 227944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=679694132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_r and_reset.679694132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/16.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_rw.318399835 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 1313253913 ps |
| CPU time | 4.11 seconds |
| Started | Oct 09 10:45:49 PM UTC 24 |
| Finished | Oct 09 10:45:55 PM UTC 24 |
| Peak memory | 225916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318399835 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.318399835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/16.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.3176739450 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 19153358832 ps |
| CPU time | 57.59 seconds |
| Started | Oct 09 10:45:48 PM UTC 24 |
| Finished | Oct 09 10:46:48 PM UTC 24 |
| Peak memory | 215580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176739450 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_bit_bash.3176739450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/16.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.931812372 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 859330126 ps |
| CPU time | 5.76 seconds |
| Started | Oct 09 10:45:46 PM UTC 24 |
| Finished | Oct 09 10:45:53 PM UTC 24 |
| Peak memory | 215616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931812372 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.931812372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/16.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3838133248 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 84487184 ps |
| CPU time | 1.25 seconds |
| Started | Oct 09 10:45:46 PM UTC 24 |
| Finished | Oct 09 10:45:49 PM UTC 24 |
| Peak memory | 215128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838133248 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.3838133248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/16.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1587257944 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 435778318 ps |
| CPU time | 9.84 seconds |
| Started | Oct 09 10:45:49 PM UTC 24 |
| Finished | Oct 09 10:46:01 PM UTC 24 |
| Peak memory | 215620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587257944 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_csr_outstanding.1587257944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/16.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_errors.3202330351 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 261082686 ps |
| CPU time | 5.84 seconds |
| Started | Oct 09 10:45:49 PM UTC 24 |
| Finished | Oct 09 10:45:56 PM UTC 24 |
| Peak memory | 225852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202330351 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.3202330351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/16.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.4077385741 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 1862925097 ps |
| CPU time | 13.42 seconds |
| Started | Oct 09 10:45:49 PM UTC 24 |
| Finished | Oct 09 10:46:04 PM UTC 24 |
| Peak memory | 225808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077385741 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.4077385741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/16.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2945953845 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 48686632 ps |
| CPU time | 2.77 seconds |
| Started | Oct 09 10:45:57 PM UTC 24 |
| Finished | Oct 09 10:46:01 PM UTC 24 |
| Peak memory | 227920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2945953845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_ rand_reset.2945953845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/17.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_rw.4060344080 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 137481352 ps |
| CPU time | 2.4 seconds |
| Started | Oct 09 10:45:54 PM UTC 24 |
| Finished | Oct 09 10:45:57 PM UTC 24 |
| Peak memory | 225756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060344080 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.4060344080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/17.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1973704954 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 1919805272 ps |
| CPU time | 7.08 seconds |
| Started | Oct 09 10:45:53 PM UTC 24 |
| Finished | Oct 09 10:46:01 PM UTC 24 |
| Peak memory | 215516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973704954 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_bit_bash.1973704954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/17.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.4154886917 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 1218339022 ps |
| CPU time | 4.9 seconds |
| Started | Oct 09 10:45:52 PM UTC 24 |
| Finished | Oct 09 10:45:58 PM UTC 24 |
| Peak memory | 215508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154886917 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.4154886917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/17.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3500608099 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 788499870 ps |
| CPU time | 1.52 seconds |
| Started | Oct 09 10:45:51 PM UTC 24 |
| Finished | Oct 09 10:45:53 PM UTC 24 |
| Peak memory | 215128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500608099 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.3500608099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/17.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2855575333 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 255829624 ps |
| CPU time | 6.97 seconds |
| Started | Oct 09 10:45:55 PM UTC 24 |
| Finished | Oct 09 10:46:03 PM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855575333 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same_csr_outstanding.2855575333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/17.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_errors.201906568 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 224021256 ps |
| CPU time | 6.19 seconds |
| Started | Oct 09 10:45:53 PM UTC 24 |
| Finished | Oct 09 10:46:00 PM UTC 24 |
| Peak memory | 225908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201906568 -assert nopostproc +UVM_TESTNAME=rv_dm_base _test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.201906568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/17.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3847493990 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 5054894892 ps |
| CPU time | 29.94 seconds |
| Started | Oct 09 10:45:54 PM UTC 24 |
| Finished | Oct 09 10:46:25 PM UTC 24 |
| Peak memory | 225944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847493990 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.3847493990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/17.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2885331924 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 51511849 ps |
| CPU time | 2.67 seconds |
| Started | Oct 09 10:46:02 PM UTC 24 |
| Finished | Oct 09 10:46:06 PM UTC 24 |
| Peak memory | 227976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2885331924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_ rand_reset.2885331924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/18.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_rw.3254129423 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 255051971 ps |
| CPU time | 3.35 seconds |
| Started | Oct 09 10:46:02 PM UTC 24 |
| Finished | Oct 09 10:46:06 PM UTC 24 |
| Peak memory | 225912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254129423 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.3254129423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/18.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1296808441 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 5813415706 ps |
| CPU time | 7.81 seconds |
| Started | Oct 09 10:45:58 PM UTC 24 |
| Finished | Oct 09 10:46:07 PM UTC 24 |
| Peak memory | 215496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296808441 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_bit_bash.1296808441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/18.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2643176793 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 4680612343 ps |
| CPU time | 10.25 seconds |
| Started | Oct 09 10:45:58 PM UTC 24 |
| Finished | Oct 09 10:46:10 PM UTC 24 |
| Peak memory | 215572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643176793 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.2643176793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/18.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.418134501 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 134737870 ps |
| CPU time | 1.29 seconds |
| Started | Oct 09 10:45:57 PM UTC 24 |
| Finished | Oct 09 10:46:00 PM UTC 24 |
| Peak memory | 215192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418134501 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.418134501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/18.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2109006539 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 1445945873 ps |
| CPU time | 5.75 seconds |
| Started | Oct 09 10:46:02 PM UTC 24 |
| Finished | Oct 09 10:46:09 PM UTC 24 |
| Peak memory | 215652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109006539 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same_csr_outstanding.2109006539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/18.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_errors.784014667 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 223091284 ps |
| CPU time | 6.93 seconds |
| Started | Oct 09 10:45:59 PM UTC 24 |
| Finished | Oct 09 10:46:08 PM UTC 24 |
| Peak memory | 225936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784014667 -assert nopostproc +UVM_TESTNAME=rv_dm_base _test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.784014667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/18.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3530080367 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 1611182406 ps |
| CPU time | 13 seconds |
| Started | Oct 09 10:46:01 PM UTC 24 |
| Finished | Oct 09 10:46:15 PM UTC 24 |
| Peak memory | 225896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530080367 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3530080367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/18.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2641946218 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 66668198 ps |
| CPU time | 2.89 seconds |
| Started | Oct 09 10:46:07 PM UTC 24 |
| Finished | Oct 09 10:46:11 PM UTC 24 |
| Peak memory | 226088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2641946218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_ rand_reset.2641946218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/19.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_rw.4015504218 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 430476854 ps |
| CPU time | 2.79 seconds |
| Started | Oct 09 10:46:05 PM UTC 24 |
| Finished | Oct 09 10:46:09 PM UTC 24 |
| Peak memory | 225780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015504218 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.4015504218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/19.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.3083450131 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 1876194476 ps |
| CPU time | 4.4 seconds |
| Started | Oct 09 10:46:02 PM UTC 24 |
| Finished | Oct 09 10:46:08 PM UTC 24 |
| Peak memory | 215516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083450131 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_bit_bash.3083450131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/19.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1366045426 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 11756980827 ps |
| CPU time | 9.88 seconds |
| Started | Oct 09 10:46:02 PM UTC 24 |
| Finished | Oct 09 10:46:13 PM UTC 24 |
| Peak memory | 215572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366045426 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.1366045426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/19.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2779996817 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 605907335 ps |
| CPU time | 4.74 seconds |
| Started | Oct 09 10:46:02 PM UTC 24 |
| Finished | Oct 09 10:46:08 PM UTC 24 |
| Peak memory | 215332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779996817 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.2779996817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/19.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2964493641 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 2068809338 ps |
| CPU time | 10.95 seconds |
| Started | Oct 09 10:46:06 PM UTC 24 |
| Finished | Oct 09 10:46:18 PM UTC 24 |
| Peak memory | 215596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964493641 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_csr_outstanding.2964493641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/19.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_errors.1945332163 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 306985417 ps |
| CPU time | 5.36 seconds |
| Started | Oct 09 10:46:04 PM UTC 24 |
| Finished | Oct 09 10:46:11 PM UTC 24 |
| Peak memory | 225880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945332163 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.1945332163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/19.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1572205951 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 2694382610 ps |
| CPU time | 21.1 seconds |
| Started | Oct 09 10:46:05 PM UTC 24 |
| Finished | Oct 09 10:46:27 PM UTC 24 |
| Peak memory | 226124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572205951 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.1572205951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/19.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.672434201 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 3103356551 ps |
| CPU time | 50.14 seconds |
| Started | Oct 09 10:43:27 PM UTC 24 |
| Finished | Oct 09 10:44:19 PM UTC 24 |
| Peak memory | 215720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672434201 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.672434201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/2.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3450523024 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 199975189 ps |
| CPU time | 3.26 seconds |
| Started | Oct 09 10:43:23 PM UTC 24 |
| Finished | Oct 09 10:43:28 PM UTC 24 |
| Peak memory | 225816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450523024 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3450523024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/2.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1723386122 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 150852143 ps |
| CPU time | 3.01 seconds |
| Started | Oct 09 10:43:31 PM UTC 24 |
| Finished | Oct 09 10:43:35 PM UTC 24 |
| Peak memory | 225852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1723386122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_r and_reset.1723386122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/2.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_rw.2304833151 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 331442813 ps |
| CPU time | 3.58 seconds |
| Started | Oct 09 10:43:25 PM UTC 24 |
| Finished | Oct 09 10:43:30 PM UTC 24 |
| Peak memory | 225820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304833151 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.2304833151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/2.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.239339589 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 155035953690 ps |
| CPU time | 88.16 seconds |
| Started | Oct 09 10:43:12 PM UTC 24 |
| Finished | Oct 09 10:44:42 PM UTC 24 |
| Peak memory | 215552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239339589 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_aliasing.239339589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.166389455 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 19269458822 ps |
| CPU time | 66.32 seconds |
| Started | Oct 09 10:43:09 PM UTC 24 |
| Finished | Oct 09 10:44:18 PM UTC 24 |
| Peak memory | 215488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166389455 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_bit_bash.166389455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1034363827 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 7956577873 ps |
| CPU time | 10.44 seconds |
| Started | Oct 09 10:43:06 PM UTC 24 |
| Finished | Oct 09 10:43:18 PM UTC 24 |
| Peak memory | 215484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034363827 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_hw_reset.1034363827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3420178635 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 1925879697 ps |
| CPU time | 3.45 seconds |
| Started | Oct 09 10:43:06 PM UTC 24 |
| Finished | Oct 09 10:43:11 PM UTC 24 |
| Peak memory | 215576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420178635 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.3420178635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.962347151 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 743950542 ps |
| CPU time | 2.13 seconds |
| Started | Oct 09 10:43:05 PM UTC 24 |
| Finished | Oct 09 10:43:08 PM UTC 24 |
| Peak memory | 215464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962347151 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_aliasing.962347151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1092744369 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 3735695031 ps |
| CPU time | 7.95 seconds |
| Started | Oct 09 10:43:04 PM UTC 24 |
| Finished | Oct 09 10:43:13 PM UTC 24 |
| Peak memory | 215572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092744369 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_bit_bash.1092744369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3039869270 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 212869882 ps |
| CPU time | 1.84 seconds |
| Started | Oct 09 10:42:59 PM UTC 24 |
| Finished | Oct 09 10:43:02 PM UTC 24 |
| Peak memory | 215128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039869270 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_hw_reset.3039869270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2506790913 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 265386764 ps |
| CPU time | 1.43 seconds |
| Started | Oct 09 10:43:03 PM UTC 24 |
| Finished | Oct 09 10:43:06 PM UTC 24 |
| Peak memory | 215128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506790913 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.2506790913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1828544024 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 146785570 ps |
| CPU time | 1.24 seconds |
| Started | Oct 09 10:43:22 PM UTC 24 |
| Finished | Oct 09 10:43:25 PM UTC 24 |
| Peak memory | 215128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828544024 -assert nopostproc +UVM _TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_partial_access.1828544024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/2.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_walk.4071833988 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 61121584 ps |
| CPU time | 1.22 seconds |
| Started | Oct 09 10:43:20 PM UTC 24 |
| Finished | Oct 09 10:43:22 PM UTC 24 |
| Peak memory | 215188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071833988 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.4071833988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/2.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1777671219 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 2221709562 ps |
| CPU time | 12.38 seconds |
| Started | Oct 09 10:43:28 PM UTC 24 |
| Finished | Oct 09 10:43:42 PM UTC 24 |
| Peak memory | 215616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777671219 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_csr_outstanding.1777671219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/2.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.1810116039 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 7477910546 ps |
| CPU time | 43.68 seconds |
| Started | Oct 09 10:43:14 PM UTC 24 |
| Finished | Oct 09 10:43:59 PM UTC 24 |
| Peak memory | 232704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1810116039 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_re set.1810116039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/2.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_errors.1584276216 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 354752128 ps |
| CPU time | 4.98 seconds |
| Started | Oct 09 10:43:15 PM UTC 24 |
| Finished | Oct 09 10:43:21 PM UTC 24 |
| Peak memory | 225940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584276216 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.1584276216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/2.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3274418042 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 1227328182 ps |
| CPU time | 11.02 seconds |
| Started | Oct 09 10:43:19 PM UTC 24 |
| Finished | Oct 09 10:43:31 PM UTC 24 |
| Peak memory | 225832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274418042 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.3274418042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/2.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1061687764 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 13524644564 ps |
| CPU time | 101.34 seconds |
| Started | Oct 09 10:43:31 PM UTC 24 |
| Finished | Oct 09 10:45:14 PM UTC 24 |
| Peak memory | 225852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061687764 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_aliasing.1061687764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/3.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1188937940 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 20078342673 ps |
| CPU time | 72.7 seconds |
| Started | Oct 09 10:43:51 PM UTC 24 |
| Finished | Oct 09 10:45:06 PM UTC 24 |
| Peak memory | 215528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188937940 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.1188937940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/3.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.21090236 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 314841056 ps |
| CPU time | 4.07 seconds |
| Started | Oct 09 10:43:47 PM UTC 24 |
| Finished | Oct 09 10:43:52 PM UTC 24 |
| Peak memory | 225984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21090236 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.21090236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/3.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.677062714 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 165593746 ps |
| CPU time | 4.96 seconds |
| Started | Oct 09 10:43:56 PM UTC 24 |
| Finished | Oct 09 10:44:03 PM UTC 24 |
| Peak memory | 232668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=677062714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_ra nd_reset.677062714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/3.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_rw.1728943429 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 331171695 ps |
| CPU time | 3.54 seconds |
| Started | Oct 09 10:43:50 PM UTC 24 |
| Finished | Oct 09 10:43:55 PM UTC 24 |
| Peak memory | 226012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728943429 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.1728943429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/3.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3914015785 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 70788367319 ps |
| CPU time | 272.25 seconds |
| Started | Oct 09 10:43:40 PM UTC 24 |
| Finished | Oct 09 10:48:16 PM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914015785 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_aliasing.3914015785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3413860965 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 83593483 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 10:43:38 PM UTC 24 |
| Finished | Oct 09 10:43:40 PM UTC 24 |
| Peak memory | 215072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413860965 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_bit_bash.3413860965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1509646219 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 10801197002 ps |
| CPU time | 42.24 seconds |
| Started | Oct 09 10:43:36 PM UTC 24 |
| Finished | Oct 09 10:44:20 PM UTC 24 |
| Peak memory | 215580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509646219 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_hw_reset.1509646219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1108377940 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 7692470190 ps |
| CPU time | 21.94 seconds |
| Started | Oct 09 10:43:36 PM UTC 24 |
| Finished | Oct 09 10:43:59 PM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108377940 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.1108377940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1633537613 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 340567064 ps |
| CPU time | 1.4 seconds |
| Started | Oct 09 10:43:35 PM UTC 24 |
| Finished | Oct 09 10:43:37 PM UTC 24 |
| Peak memory | 215128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633537613 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_aliasing.1633537613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.29896480 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 11192004462 ps |
| CPU time | 37.78 seconds |
| Started | Oct 09 10:43:35 PM UTC 24 |
| Finished | Oct 09 10:44:14 PM UTC 24 |
| Peak memory | 215572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29896480 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_bit_bash.29896480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1008107109 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 106902222 ps |
| CPU time | 1.29 seconds |
| Started | Oct 09 10:43:32 PM UTC 24 |
| Finished | Oct 09 10:43:34 PM UTC 24 |
| Peak memory | 215128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008107109 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_hw_reset.1008107109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1139668097 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 116419524 ps |
| CPU time | 1.47 seconds |
| Started | Oct 09 10:43:32 PM UTC 24 |
| Finished | Oct 09 10:43:34 PM UTC 24 |
| Peak memory | 215128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139668097 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.1139668097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_partial_access.4251644626 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 55312404 ps |
| CPU time | 1.21 seconds |
| Started | Oct 09 10:43:47 PM UTC 24 |
| Finished | Oct 09 10:43:49 PM UTC 24 |
| Peak memory | 215128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251644626 -assert nopostproc +UVM _TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_partial_access.4251644626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/3.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_walk.2009849671 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 76585790 ps |
| CPU time | 1.44 seconds |
| Started | Oct 09 10:43:44 PM UTC 24 |
| Finished | Oct 09 10:43:46 PM UTC 24 |
| Peak memory | 215128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009849671 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.2009849671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/3.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2556145185 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 94029126 ps |
| CPU time | 4.64 seconds |
| Started | Oct 09 10:43:53 PM UTC 24 |
| Finished | Oct 09 10:43:59 PM UTC 24 |
| Peak memory | 215616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556145185 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_csr_outstanding.2556145185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/3.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_errors.2485773396 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 405189633 ps |
| CPU time | 7.17 seconds |
| Started | Oct 09 10:43:41 PM UTC 24 |
| Finished | Oct 09 10:43:50 PM UTC 24 |
| Peak memory | 225940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485773396 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.2485773396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/3.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1155126012 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 26989338839 ps |
| CPU time | 89.82 seconds |
| Started | Oct 09 10:43:56 PM UTC 24 |
| Finished | Oct 09 10:45:28 PM UTC 24 |
| Peak memory | 226048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155126012 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_aliasing.1155126012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/4.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.69871023 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 793750780 ps |
| CPU time | 30.45 seconds |
| Started | Oct 09 10:44:21 PM UTC 24 |
| Finished | Oct 09 10:44:52 PM UTC 24 |
| Peak memory | 215492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69871023 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.69871023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/4.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1160743787 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 388988717 ps |
| CPU time | 2.7 seconds |
| Started | Oct 09 10:44:18 PM UTC 24 |
| Finished | Oct 09 10:44:22 PM UTC 24 |
| Peak memory | 225792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160743787 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.1160743787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/4.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.917734245 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 166704715 ps |
| CPU time | 3.75 seconds |
| Started | Oct 09 10:44:21 PM UTC 24 |
| Finished | Oct 09 10:44:25 PM UTC 24 |
| Peak memory | 225820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=917734245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_ra nd_reset.917734245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/4.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_rw.2052398793 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 155264422 ps |
| CPU time | 2.48 seconds |
| Started | Oct 09 10:44:18 PM UTC 24 |
| Finished | Oct 09 10:44:22 PM UTC 24 |
| Peak memory | 225924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052398793 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.2052398793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/4.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2697434050 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 82312752048 ps |
| CPU time | 245.78 seconds |
| Started | Oct 09 10:44:10 PM UTC 24 |
| Finished | Oct 09 10:48:19 PM UTC 24 |
| Peak memory | 215484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697434050 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_aliasing.2697434050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3231050525 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 10163574237 ps |
| CPU time | 16.9 seconds |
| Started | Oct 09 10:44:07 PM UTC 24 |
| Finished | Oct 09 10:44:25 PM UTC 24 |
| Peak memory | 215556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231050525 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_bit_bash.3231050525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1849027433 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 3890509907 ps |
| CPU time | 5.15 seconds |
| Started | Oct 09 10:44:04 PM UTC 24 |
| Finished | Oct 09 10:44:10 PM UTC 24 |
| Peak memory | 215552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849027433 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_hw_reset.1849027433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2552326333 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 1463193704 ps |
| CPU time | 2.39 seconds |
| Started | Oct 09 10:44:06 PM UTC 24 |
| Finished | Oct 09 10:44:09 PM UTC 24 |
| Peak memory | 215616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552326333 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.2552326333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.323256791 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 219237392 ps |
| CPU time | 1.32 seconds |
| Started | Oct 09 10:44:03 PM UTC 24 |
| Finished | Oct 09 10:44:06 PM UTC 24 |
| Peak memory | 215068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323256791 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_aliasing.323256791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3815343888 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 3569282034 ps |
| CPU time | 21.63 seconds |
| Started | Oct 09 10:44:00 PM UTC 24 |
| Finished | Oct 09 10:44:24 PM UTC 24 |
| Peak memory | 215484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815343888 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_bit_bash.3815343888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1981023394 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 574476015 ps |
| CPU time | 4.75 seconds |
| Started | Oct 09 10:43:59 PM UTC 24 |
| Finished | Oct 09 10:44:05 PM UTC 24 |
| Peak memory | 215328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981023394 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_hw_reset.1981023394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3550428877 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 384979609 ps |
| CPU time | 2.48 seconds |
| Started | Oct 09 10:43:59 PM UTC 24 |
| Finished | Oct 09 10:44:03 PM UTC 24 |
| Peak memory | 215332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550428877 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.3550428877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3418580224 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 46728392 ps |
| CPU time | 1.25 seconds |
| Started | Oct 09 10:44:17 PM UTC 24 |
| Finished | Oct 09 10:44:20 PM UTC 24 |
| Peak memory | 215128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418580224 -assert nopostproc +UVM _TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_partial_access.3418580224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/4.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_walk.384493100 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 129810668 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 10:44:15 PM UTC 24 |
| Finished | Oct 09 10:44:18 PM UTC 24 |
| Peak memory | 215128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384493100 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.384493100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/4.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.369582644 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 213814841 ps |
| CPU time | 7.54 seconds |
| Started | Oct 09 10:44:21 PM UTC 24 |
| Finished | Oct 09 10:44:29 PM UTC 24 |
| Peak memory | 215644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369582644 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_csr_outstanding.369582644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/4.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2418156368 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 8892322105 ps |
| CPU time | 95.39 seconds |
| Started | Oct 09 10:44:11 PM UTC 24 |
| Finished | Oct 09 10:45:49 PM UTC 24 |
| Peak memory | 230084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2418156368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_re set.2418156368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/4.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_errors.2786781874 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 181498741 ps |
| CPU time | 2.93 seconds |
| Started | Oct 09 10:44:12 PM UTC 24 |
| Finished | Oct 09 10:44:16 PM UTC 24 |
| Peak memory | 225908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786781874 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2786781874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/4.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2645495407 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 2598733520 ps |
| CPU time | 28.79 seconds |
| Started | Oct 09 10:44:14 PM UTC 24 |
| Finished | Oct 09 10:44:45 PM UTC 24 |
| Peak memory | 225832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645495407 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.2645495407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/4.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1651591528 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 76883787 ps |
| CPU time | 2.47 seconds |
| Started | Oct 09 10:44:31 PM UTC 24 |
| Finished | Oct 09 10:44:35 PM UTC 24 |
| Peak memory | 228004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1651591528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_r and_reset.1651591528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/5.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_rw.2043615871 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 61003132 ps |
| CPU time | 2.19 seconds |
| Started | Oct 09 10:44:27 PM UTC 24 |
| Finished | Oct 09 10:44:30 PM UTC 24 |
| Peak memory | 225820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043615871 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.2043615871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/5.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.1948652805 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 3514844160 ps |
| CPU time | 23.42 seconds |
| Started | Oct 09 10:44:25 PM UTC 24 |
| Finished | Oct 09 10:44:50 PM UTC 24 |
| Peak memory | 215584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948652805 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_bit_bash.1948652805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/5.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1662865358 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 1795858143 ps |
| CPU time | 12.32 seconds |
| Started | Oct 09 10:44:23 PM UTC 24 |
| Finished | Oct 09 10:44:36 PM UTC 24 |
| Peak memory | 215420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662865358 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.1662865358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/5.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2867000415 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 204597079 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 10:44:23 PM UTC 24 |
| Finished | Oct 09 10:44:25 PM UTC 24 |
| Peak memory | 215128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867000415 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.2867000415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/5.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2013990873 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 644952504 ps |
| CPU time | 9.89 seconds |
| Started | Oct 09 10:44:30 PM UTC 24 |
| Finished | Oct 09 10:44:41 PM UTC 24 |
| Peak memory | 215612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013990873 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_csr_outstanding.2013990873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/5.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_errors.3500332740 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 987603317 ps |
| CPU time | 6.24 seconds |
| Started | Oct 09 10:44:26 PM UTC 24 |
| Finished | Oct 09 10:44:33 PM UTC 24 |
| Peak memory | 226040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500332740 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.3500332740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/5.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2569949656 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 2232349871 ps |
| CPU time | 18.96 seconds |
| Started | Oct 09 10:44:26 PM UTC 24 |
| Finished | Oct 09 10:44:46 PM UTC 24 |
| Peak memory | 225916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569949656 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.2569949656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/5.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.983891252 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 75504999 ps |
| CPU time | 1.9 seconds |
| Started | Oct 09 10:44:43 PM UTC 24 |
| Finished | Oct 09 10:44:46 PM UTC 24 |
| Peak memory | 227120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=983891252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_ra nd_reset.983891252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/6.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_rw.3622516419 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 89963212 ps |
| CPU time | 3.25 seconds |
| Started | Oct 09 10:44:40 PM UTC 24 |
| Finished | Oct 09 10:44:44 PM UTC 24 |
| Peak memory | 226012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622516419 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.3622516419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/6.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.846196996 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 38528240984 ps |
| CPU time | 44.59 seconds |
| Started | Oct 09 10:44:36 PM UTC 24 |
| Finished | Oct 09 10:45:22 PM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846196996 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_bit_bash.846196996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/6.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2366596610 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 5608254442 ps |
| CPU time | 21.86 seconds |
| Started | Oct 09 10:44:35 PM UTC 24 |
| Finished | Oct 09 10:44:58 PM UTC 24 |
| Peak memory | 215572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366596610 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.2366596610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/6.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.4150768997 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 345754298 ps |
| CPU time | 1.35 seconds |
| Started | Oct 09 10:44:32 PM UTC 24 |
| Finished | Oct 09 10:44:35 PM UTC 24 |
| Peak memory | 215128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150768997 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.4150768997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/6.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2316035448 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 556552967 ps |
| CPU time | 6.28 seconds |
| Started | Oct 09 10:44:42 PM UTC 24 |
| Finished | Oct 09 10:44:49 PM UTC 24 |
| Peak memory | 215640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316035448 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_csr_outstanding.2316035448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/6.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.2841465752 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 16474435452 ps |
| CPU time | 86.3 seconds |
| Started | Oct 09 10:44:36 PM UTC 24 |
| Finished | Oct 09 10:46:04 PM UTC 24 |
| Peak memory | 232544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2841465752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_re set.2841465752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/6.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_errors.1347790961 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 143266914 ps |
| CPU time | 5.29 seconds |
| Started | Oct 09 10:44:37 PM UTC 24 |
| Finished | Oct 09 10:44:43 PM UTC 24 |
| Peak memory | 226108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347790961 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.1347790961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/6.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_intg_err.4071884683 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 5599510792 ps |
| CPU time | 23.5 seconds |
| Started | Oct 09 10:44:38 PM UTC 24 |
| Finished | Oct 09 10:45:03 PM UTC 24 |
| Peak memory | 225856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071884683 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.4071884683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/6.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.352742239 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 104294988 ps |
| CPU time | 5.03 seconds |
| Started | Oct 09 10:44:51 PM UTC 24 |
| Finished | Oct 09 10:44:57 PM UTC 24 |
| Peak memory | 232484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=352742239 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_ra nd_reset.352742239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/7.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_rw.568172175 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 204772036 ps |
| CPU time | 2.39 seconds |
| Started | Oct 09 10:44:51 PM UTC 24 |
| Finished | Oct 09 10:44:54 PM UTC 24 |
| Peak memory | 225916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568172175 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.568172175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/7.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1288144164 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 2449023534 ps |
| CPU time | 10.58 seconds |
| Started | Oct 09 10:44:45 PM UTC 24 |
| Finished | Oct 09 10:44:57 PM UTC 24 |
| Peak memory | 215620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288144164 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_bit_bash.1288144164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/7.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.4178219259 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 995500416 ps |
| CPU time | 3.32 seconds |
| Started | Oct 09 10:44:45 PM UTC 24 |
| Finished | Oct 09 10:44:50 PM UTC 24 |
| Peak memory | 215424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178219259 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.4178219259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/7.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.895723335 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 217070641 ps |
| CPU time | 1.19 seconds |
| Started | Oct 09 10:44:44 PM UTC 24 |
| Finished | Oct 09 10:44:46 PM UTC 24 |
| Peak memory | 215128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895723335 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.895723335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/7.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2085115610 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 291152318 ps |
| CPU time | 9.76 seconds |
| Started | Oct 09 10:44:51 PM UTC 24 |
| Finished | Oct 09 10:45:02 PM UTC 24 |
| Peak memory | 215612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085115610 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_csr_outstanding.2085115610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/7.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.975539531 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 22895928802 ps |
| CPU time | 41.32 seconds |
| Started | Oct 09 10:44:46 PM UTC 24 |
| Finished | Oct 09 10:45:29 PM UTC 24 |
| Peak memory | 232388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=975539531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.975539531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/7.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_errors.3560270577 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 103300386 ps |
| CPU time | 3.89 seconds |
| Started | Oct 09 10:44:48 PM UTC 24 |
| Finished | Oct 09 10:44:52 PM UTC 24 |
| Peak memory | 228148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560270577 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.3560270577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/7.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3452952727 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 3238993324 ps |
| CPU time | 27.48 seconds |
| Started | Oct 09 10:44:48 PM UTC 24 |
| Finished | Oct 09 10:45:16 PM UTC 24 |
| Peak memory | 228124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452952727 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.3452952727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/7.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1272025380 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 99165799 ps |
| CPU time | 2.89 seconds |
| Started | Oct 09 10:45:02 PM UTC 24 |
| Finished | Oct 09 10:45:06 PM UTC 24 |
| Peak memory | 225896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1272025380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_r and_reset.1272025380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/8.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_rw.972888227 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 140205201 ps |
| CPU time | 3.35 seconds |
| Started | Oct 09 10:44:58 PM UTC 24 |
| Finished | Oct 09 10:45:03 PM UTC 24 |
| Peak memory | 225852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972888227 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.972888227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/8.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1098470624 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 26053390182 ps |
| CPU time | 26.56 seconds |
| Started | Oct 09 10:44:55 PM UTC 24 |
| Finished | Oct 09 10:45:23 PM UTC 24 |
| Peak memory | 215684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098470624 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_bit_bash.1098470624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/8.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.532217315 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 993362126 ps |
| CPU time | 7.22 seconds |
| Started | Oct 09 10:44:53 PM UTC 24 |
| Finished | Oct 09 10:45:01 PM UTC 24 |
| Peak memory | 215484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532217315 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.532217315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/8.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.811137763 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 168002965 ps |
| CPU time | 1.9 seconds |
| Started | Oct 09 10:44:53 PM UTC 24 |
| Finished | Oct 09 10:44:56 PM UTC 24 |
| Peak memory | 215068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811137763 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.811137763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/8.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3491763337 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 1668657252 ps |
| CPU time | 6.02 seconds |
| Started | Oct 09 10:45:02 PM UTC 24 |
| Finished | Oct 09 10:45:10 PM UTC 24 |
| Peak memory | 215612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491763337 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_csr_outstanding.3491763337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/8.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.67805669 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 9088684062 ps |
| CPU time | 38.86 seconds |
| Started | Oct 09 10:44:57 PM UTC 24 |
| Finished | Oct 09 10:45:37 PM UTC 24 |
| Peak memory | 232708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=67805669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.67805669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/8.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_errors.2749730322 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 560905254 ps |
| CPU time | 2.66 seconds |
| Started | Oct 09 10:44:58 PM UTC 24 |
| Finished | Oct 09 10:45:02 PM UTC 24 |
| Peak memory | 225936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749730322 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.2749730322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/8.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1783239448 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 2627186165 ps |
| CPU time | 14.43 seconds |
| Started | Oct 09 10:44:58 PM UTC 24 |
| Finished | Oct 09 10:45:14 PM UTC 24 |
| Peak memory | 225920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783239448 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.1783239448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/8.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3673821222 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 148751182 ps |
| CPU time | 3.67 seconds |
| Started | Oct 09 10:45:12 PM UTC 24 |
| Finished | Oct 09 10:45:17 PM UTC 24 |
| Peak memory | 232612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3673821222 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_r and_reset.3673821222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/9.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_rw.2793968038 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 114181889 ps |
| CPU time | 2.27 seconds |
| Started | Oct 09 10:45:10 PM UTC 24 |
| Finished | Oct 09 10:45:13 PM UTC 24 |
| Peak memory | 226016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793968038 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.2793968038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/9.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3001106261 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 13252257555 ps |
| CPU time | 21.05 seconds |
| Started | Oct 09 10:45:04 PM UTC 24 |
| Finished | Oct 09 10:45:26 PM UTC 24 |
| Peak memory | 215620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001106261 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_bit_bash.3001106261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/9.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.4176515675 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 7182363930 ps |
| CPU time | 13.49 seconds |
| Started | Oct 09 10:45:04 PM UTC 24 |
| Finished | Oct 09 10:45:18 PM UTC 24 |
| Peak memory | 215484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176515675 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.4176515675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/9.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2443438004 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 584997124 ps |
| CPU time | 1.72 seconds |
| Started | Oct 09 10:45:03 PM UTC 24 |
| Finished | Oct 09 10:45:05 PM UTC 24 |
| Peak memory | 215188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443438004 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.2443438004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/9.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.577885719 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 1831733286 ps |
| CPU time | 8.49 seconds |
| Started | Oct 09 10:45:11 PM UTC 24 |
| Finished | Oct 09 10:45:21 PM UTC 24 |
| Peak memory | 215556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577885719 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_csr_outstanding.577885719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/9.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2489962649 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 5218776615 ps |
| CPU time | 36.17 seconds |
| Started | Oct 09 10:45:06 PM UTC 24 |
| Finished | Oct 09 10:45:43 PM UTC 24 |
| Peak memory | 225900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2489962649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_re set.2489962649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/9.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_errors.3988841646 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 133152549 ps |
| CPU time | 3.38 seconds |
| Started | Oct 09 10:45:07 PM UTC 24 |
| Finished | Oct 09 10:45:11 PM UTC 24 |
| Peak memory | 226128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988841646 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.3988841646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/9.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_intg_err.389066909 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 10590281629 ps |
| CPU time | 27.02 seconds |
| Started | Oct 09 10:45:07 PM UTC 24 |
| Finished | Oct 09 10:45:35 PM UTC 24 |
| Peak memory | 225884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389066909 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.389066909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/9.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.1728814406 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 125766281 ps |
| CPU time | 1.11 seconds |
| Started | Oct 09 10:49:31 PM UTC 24 |
| Finished | Oct 09 10:49:33 PM UTC 24 |
| Peak memory | 215028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728814406 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.1728814406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.2838293786 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 70158260466 ps |
| CPU time | 255.8 seconds |
| Started | Oct 09 10:49:24 PM UTC 24 |
| Finished | Oct 09 10:53:44 PM UTC 24 |
| Peak memory | 226400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838293786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.2838293786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.3141398067 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 102078613 ps |
| CPU time | 1.09 seconds |
| Started | Oct 09 10:49:29 PM UTC 24 |
| Finished | Oct 09 10:49:32 PM UTC 24 |
| Peak memory | 250944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141398067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_buffered_enable.3141398067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.1483633765 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 859342678 ps |
| CPU time | 2.09 seconds |
| Started | Oct 09 10:49:26 PM UTC 24 |
| Finished | Oct 09 10:49:30 PM UTC 24 |
| Peak memory | 215608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483633765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.1483633765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_cmderr_exception/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.4129896559 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 373264398 ps |
| CPU time | 1.22 seconds |
| Started | Oct 09 10:49:26 PM UTC 24 |
| Finished | Oct 09 10:49:28 PM UTC 24 |
| Peak memory | 214952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129896559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.4129896559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_cmderr_not_supported/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_dataaddr_rw_access.1325414755 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 135488025 ps |
| CPU time | 0.86 seconds |
| Started | Oct 09 10:49:29 PM UTC 24 |
| Finished | Oct 09 10:49:31 PM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325414755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.1325414755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_dataaddr_rw_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_debug_disabled.4067381902 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 51374685 ps |
| CPU time | 0.98 seconds |
| Started | Oct 09 10:49:29 PM UTC 24 |
| Finished | Oct 09 10:49:31 PM UTC 24 |
| Peak memory | 237076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067381902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.4067381902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.3024998929 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 7239247523 ps |
| CPU time | 16.61 seconds |
| Started | Oct 09 10:49:24 PM UTC 24 |
| Finished | Oct 09 10:49:42 PM UTC 24 |
| Peak memory | 226400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024998929 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_tl_access.3024998929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.378961795 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1410552784 ps |
| CPU time | 2.02 seconds |
| Started | Oct 09 10:49:29 PM UTC 24 |
| Finished | Oct 09 10:49:32 PM UTC 24 |
| Peak memory | 215860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378961795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.378961795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_hart_unavail.2017581750 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 350813117 ps |
| CPU time | 1.76 seconds |
| Started | Oct 09 10:49:26 PM UTC 24 |
| Finished | Oct 09 10:49:29 PM UTC 24 |
| Peak memory | 215464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017581750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.2017581750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_hartsel_warl.4222426398 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 56983700 ps |
| CPU time | 0.94 seconds |
| Started | Oct 09 10:49:29 PM UTC 24 |
| Finished | Oct 09 10:49:31 PM UTC 24 |
| Peak memory | 215464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222426398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.4222426398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_hartsel_warl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.4213610972 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 109461082 ps |
| CPU time | 1.04 seconds |
| Started | Oct 09 10:49:29 PM UTC 24 |
| Finished | Oct 09 10:49:31 PM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213610972 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.4213610972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.858791431 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 609960694 ps |
| CPU time | 2.51 seconds |
| Started | Oct 09 10:49:29 PM UTC 24 |
| Finished | Oct 09 10:49:33 PM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858791431 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.858791431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_dm_inactive/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2214128652 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 687135743 ps |
| CPU time | 1.83 seconds |
| Started | Oct 09 10:49:29 PM UTC 24 |
| Finished | Oct 09 10:49:32 PM UTC 24 |
| Peak memory | 215528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214128652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.2214128652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_hard_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_idle_hint.300621531 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 592762288 ps |
| CPU time | 0.82 seconds |
| Started | Oct 09 10:49:29 PM UTC 24 |
| Finished | Oct 09 10:49:31 PM UTC 24 |
| Peak memory | 215408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300621531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.300621531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_idle_hint/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_halted.2405750608 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 497147868 ps |
| CPU time | 1.31 seconds |
| Started | Oct 09 10:49:26 PM UTC 24 |
| Finished | Oct 09 10:49:29 PM UTC 24 |
| Peak memory | 215408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405750608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.2405750608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_halted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_resuming.2141736886 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 260438028 ps |
| CPU time | 1.26 seconds |
| Started | Oct 09 10:49:26 PM UTC 24 |
| Finished | Oct 09 10:49:29 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141736886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.2141736886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_resuming/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.183520138 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 340176700 ps |
| CPU time | 1.26 seconds |
| Started | Oct 09 10:49:29 PM UTC 24 |
| Finished | Oct 09 10:49:31 PM UTC 24 |
| Peak memory | 225268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183520138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.183520138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_ndmreset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.1554806547 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 954224337 ps |
| CPU time | 1.75 seconds |
| Started | Oct 09 10:49:29 PM UTC 24 |
| Finished | Oct 09 10:49:32 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554806547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_progbuf_read_write_execute_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_d m-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.1554806547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_progbuf_read_write_execute/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.3402252554 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 137539415 ps |
| CPU time | 0.93 seconds |
| Started | Oct 09 10:49:29 PM UTC 24 |
| Finished | Oct 09 10:49:31 PM UTC 24 |
| Peak memory | 225216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402252554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_rom_read_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.3402252554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_rom_read_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_tl_access.1289487643 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 6801445449 ps |
| CPU time | 10.63 seconds |
| Started | Oct 09 10:49:24 PM UTC 24 |
| Finished | Oct 09 10:49:36 PM UTC 24 |
| Peak memory | 216100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289487643 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.1289487643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.2899563120 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 22556844 ps |
| CPU time | 0.75 seconds |
| Started | Oct 09 10:49:29 PM UTC 24 |
| Finished | Oct 09 10:49:31 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899563120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_scanmode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 0.rv_dm_scanmode.2899563120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_scanmode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.974895095 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 2447042991 ps |
| CPU time | 10.83 seconds |
| Started | Oct 09 10:49:31 PM UTC 24 |
| Finished | Oct 09 10:49:43 PM UTC 24 |
| Peak memory | 228196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=974895095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress _all_with_rand_reset.974895095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_abstractcmd_status.1767820901 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 127810364 ps |
| CPU time | 1.05 seconds |
| Started | Oct 09 10:49:34 PM UTC 24 |
| Finished | Oct 09 10:49:37 PM UTC 24 |
| Peak memory | 215452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767820901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_abstractcmd_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.1767820901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_abstractcmd_status/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_alert_test.1395544135 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 50914628 ps |
| CPU time | 0.71 seconds |
| Started | Oct 09 10:49:35 PM UTC 24 |
| Finished | Oct 09 10:49:38 PM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395544135 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.1395544135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_autoincr_sba_tl_access.3910034659 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 3564453379 ps |
| CPU time | 10.67 seconds |
| Started | Oct 09 10:49:31 PM UTC 24 |
| Finished | Oct 09 10:49:43 PM UTC 24 |
| Peak memory | 216280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910034659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.3910034659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_bad_sba_tl_access.1511470870 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 3085082591 ps |
| CPU time | 5.23 seconds |
| Started | Oct 09 10:49:31 PM UTC 24 |
| Finished | Oct 09 10:49:37 PM UTC 24 |
| Peak memory | 216164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511470870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.1511470870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_buffered_enable.2539137558 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 88412600 ps |
| CPU time | 0.97 seconds |
| Started | Oct 09 10:49:34 PM UTC 24 |
| Finished | Oct 09 10:49:37 PM UTC 24 |
| Peak memory | 256704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539137558 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_buffered_enable.2539137558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_busy.352792758 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 432809609 ps |
| CPU time | 1.33 seconds |
| Started | Oct 09 10:49:31 PM UTC 24 |
| Finished | Oct 09 10:49:33 PM UTC 24 |
| Peak memory | 215408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352792758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.352792758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_cmderr_busy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.982426051 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1747864777 ps |
| CPU time | 2.08 seconds |
| Started | Oct 09 10:49:32 PM UTC 24 |
| Finished | Oct 09 10:49:36 PM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982426051 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_cmderr_halt_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.982426051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_cmderr_halt_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_not_supported.187613528 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 860048634 ps |
| CPU time | 1.59 seconds |
| Started | Oct 09 10:49:32 PM UTC 24 |
| Finished | Oct 09 10:49:35 PM UTC 24 |
| Peak memory | 215532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187613528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.187613528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_cmderr_not_supported/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_dataaddr_rw_access.278291530 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 129556195 ps |
| CPU time | 1.43 seconds |
| Started | Oct 09 10:49:32 PM UTC 24 |
| Finished | Oct 09 10:49:35 PM UTC 24 |
| Peak memory | 215408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278291530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_dataaddr_rw_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.278291530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_dataaddr_rw_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_debug_disabled.3341018402 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 47408862 ps |
| CPU time | 1.04 seconds |
| Started | Oct 09 10:49:34 PM UTC 24 |
| Finished | Oct 09 10:49:37 PM UTC 24 |
| Peak memory | 237316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341018402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.3341018402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.1953480246 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 11941892663 ps |
| CPU time | 11.48 seconds |
| Started | Oct 09 10:49:31 PM UTC 24 |
| Finished | Oct 09 10:49:44 PM UTC 24 |
| Peak memory | 226472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953480246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_tl_access.1953480246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.1930394100 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 123879535 ps |
| CPU time | 0.95 seconds |
| Started | Oct 09 10:49:34 PM UTC 24 |
| Finished | Oct 09 10:49:37 PM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930394100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.1930394100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_dmi_failed_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_halt_resume_whereto.929828807 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 666662568 ps |
| CPU time | 1.8 seconds |
| Started | Oct 09 10:49:32 PM UTC 24 |
| Finished | Oct 09 10:49:35 PM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929828807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.929828807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_hart_unavail.826818143 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 76906726 ps |
| CPU time | 1.32 seconds |
| Started | Oct 09 10:49:32 PM UTC 24 |
| Finished | Oct 09 10:49:35 PM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826818143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.826818143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.4101299355 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 533622633 ps |
| CPU time | 1.01 seconds |
| Started | Oct 09 10:49:34 PM UTC 24 |
| Finished | Oct 09 10:49:37 PM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101299355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.4101299355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.3014572821 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 1551644968 ps |
| CPU time | 1.42 seconds |
| Started | Oct 09 10:49:34 PM UTC 24 |
| Finished | Oct 09 10:49:37 PM UTC 24 |
| Peak memory | 215408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014572821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.3014572821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_dm_inactive/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_hard_reset.2275590547 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 198011351 ps |
| CPU time | 0.88 seconds |
| Started | Oct 09 10:49:34 PM UTC 24 |
| Finished | Oct 09 10:49:36 PM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275590547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.2275590547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_hard_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_idle_hint.885090140 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 314170114 ps |
| CPU time | 1.97 seconds |
| Started | Oct 09 10:49:32 PM UTC 24 |
| Finished | Oct 09 10:49:36 PM UTC 24 |
| Peak memory | 215408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885090140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.885090140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_idle_hint/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_halted.2768277110 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 223267025 ps |
| CPU time | 0.82 seconds |
| Started | Oct 09 10:49:32 PM UTC 24 |
| Finished | Oct 09 10:49:34 PM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768277110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.2768277110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_mem_tl_access_halted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_resuming.615197822 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 507009366 ps |
| CPU time | 1.74 seconds |
| Started | Oct 09 10:49:32 PM UTC 24 |
| Finished | Oct 09 10:49:35 PM UTC 24 |
| Peak memory | 215408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615197822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.615197822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_mem_tl_access_resuming/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_ndmreset_req.3186400943 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 345199557 ps |
| CPU time | 1.44 seconds |
| Started | Oct 09 10:49:32 PM UTC 24 |
| Finished | Oct 09 10:49:35 PM UTC 24 |
| Peak memory | 225264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186400943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.3186400943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_ndmreset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_progbuf_read_write_execute.133234138 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 409878608 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 10:49:34 PM UTC 24 |
| Finished | Oct 09 10:49:37 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133234138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_progbuf_read_write_execute_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.133234138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_progbuf_read_write_execute/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_debug_disabled.803446943 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 1088761658 ps |
| CPU time | 4.17 seconds |
| Started | Oct 09 10:49:32 PM UTC 24 |
| Finished | Oct 09 10:49:38 PM UTC 24 |
| Peak memory | 215888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803446943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sba_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.803446943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_sba_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_tl_access.2957597346 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 2542214371 ps |
| CPU time | 3.27 seconds |
| Started | Oct 09 10:49:31 PM UTC 24 |
| Finished | Oct 09 10:49:35 PM UTC 24 |
| Peak memory | 216496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957597346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.2957597346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_sec_cm.3463226935 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 575948428 ps |
| CPU time | 1.72 seconds |
| Started | Oct 09 10:49:35 PM UTC 24 |
| Finished | Oct 09 10:49:39 PM UTC 24 |
| Peak memory | 255292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463226935 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.3463226935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_smoke.266046063 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1892302874 ps |
| CPU time | 2.29 seconds |
| Started | Oct 09 10:49:31 PM UTC 24 |
| Finished | Oct 09 10:49:34 PM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266046063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.266046063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/1.rv_dm_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/10.rv_dm_alert_test.309177830 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 157061424 ps |
| CPU time | 1.7 seconds |
| Started | Oct 09 10:49:55 PM UTC 24 |
| Finished | Oct 09 10:49:58 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309177830 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.309177830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/10.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/10.rv_dm_autoincr_sba_tl_access.3955886098 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 6395818198 ps |
| CPU time | 18.61 seconds |
| Started | Oct 09 10:49:55 PM UTC 24 |
| Finished | Oct 09 10:50:15 PM UTC 24 |
| Peak memory | 226636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955886098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.3955886098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/10.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/10.rv_dm_bad_sba_tl_access.113578460 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 2353590328 ps |
| CPU time | 10.61 seconds |
| Started | Oct 09 10:49:55 PM UTC 24 |
| Finished | Oct 09 10:50:07 PM UTC 24 |
| Peak memory | 226404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113578460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.113578460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/10.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.3832958346 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 4367911450 ps |
| CPU time | 5.73 seconds |
| Started | Oct 09 10:49:52 PM UTC 24 |
| Finished | Oct 09 10:49:59 PM UTC 24 |
| Peak memory | 226412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832958346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_tl_access.3832958346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/10.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/10.rv_dm_sba_tl_access.3636877225 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 1667618311 ps |
| CPU time | 6.51 seconds |
| Started | Oct 09 10:49:52 PM UTC 24 |
| Finished | Oct 09 10:50:00 PM UTC 24 |
| Peak memory | 216032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636877225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.3636877225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/10.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/10.rv_dm_stress_all.3029410230 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 3221531017 ps |
| CPU time | 2.97 seconds |
| Started | Oct 09 10:49:55 PM UTC 24 |
| Finished | Oct 09 10:49:59 PM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029410230 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.3029410230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/10.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/11.rv_dm_alert_test.768817219 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 67772838 ps |
| CPU time | 1.35 seconds |
| Started | Oct 09 10:49:57 PM UTC 24 |
| Finished | Oct 09 10:50:00 PM UTC 24 |
| Peak memory | 215220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768817219 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.768817219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/11.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/11.rv_dm_bad_sba_tl_access.3901704575 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 1617794641 ps |
| CPU time | 4.51 seconds |
| Started | Oct 09 10:49:55 PM UTC 24 |
| Finished | Oct 09 10:50:01 PM UTC 24 |
| Peak memory | 216296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901704575 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.3901704575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/11.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.4045050041 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 5548418167 ps |
| CPU time | 13.26 seconds |
| Started | Oct 09 10:49:55 PM UTC 24 |
| Finished | Oct 09 10:50:10 PM UTC 24 |
| Peak memory | 226476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045050041 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_tl_access.4045050041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/11.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/11.rv_dm_sba_tl_access.534357688 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 6830257392 ps |
| CPU time | 17.9 seconds |
| Started | Oct 09 10:49:55 PM UTC 24 |
| Finished | Oct 09 10:50:14 PM UTC 24 |
| Peak memory | 216092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534357688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.534357688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/11.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/11.rv_dm_stress_all.1944067238 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 4246618354 ps |
| CPU time | 17.59 seconds |
| Started | Oct 09 10:49:55 PM UTC 24 |
| Finished | Oct 09 10:50:15 PM UTC 24 |
| Peak memory | 216164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944067238 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.1944067238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/11.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/12.rv_dm_alert_test.3476480760 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 124586719 ps |
| CPU time | 1.43 seconds |
| Started | Oct 09 10:49:58 PM UTC 24 |
| Finished | Oct 09 10:50:00 PM UTC 24 |
| Peak memory | 215296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476480760 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.3476480760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/12.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/12.rv_dm_bad_sba_tl_access.504987242 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 1164575715 ps |
| CPU time | 3.03 seconds |
| Started | Oct 09 10:49:57 PM UTC 24 |
| Finished | Oct 09 10:50:02 PM UTC 24 |
| Peak memory | 215952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504987242 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.504987242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/12.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.2757855592 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 5203510654 ps |
| CPU time | 5.99 seconds |
| Started | Oct 09 10:49:57 PM UTC 24 |
| Finished | Oct 09 10:50:05 PM UTC 24 |
| Peak memory | 216420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757855592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_tl_access.2757855592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/12.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/12.rv_dm_sba_tl_access.1230666218 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 1523504458 ps |
| CPU time | 2.73 seconds |
| Started | Oct 09 10:49:57 PM UTC 24 |
| Finished | Oct 09 10:50:01 PM UTC 24 |
| Peak memory | 215968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230666218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.1230666218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/12.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/13.rv_dm_alert_test.889618954 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 52886806 ps |
| CPU time | 1.21 seconds |
| Started | Oct 09 10:50:02 PM UTC 24 |
| Finished | Oct 09 10:50:05 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889618954 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.889618954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/13.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/13.rv_dm_autoincr_sba_tl_access.2160367890 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 18539948370 ps |
| CPU time | 19.18 seconds |
| Started | Oct 09 10:50:00 PM UTC 24 |
| Finished | Oct 09 10:50:20 PM UTC 24 |
| Peak memory | 228440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160367890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.2160367890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/13.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/13.rv_dm_bad_sba_tl_access.2895628364 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 8948982008 ps |
| CPU time | 8.52 seconds |
| Started | Oct 09 10:50:00 PM UTC 24 |
| Finished | Oct 09 10:50:09 PM UTC 24 |
| Peak memory | 216424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895628364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.2895628364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/13.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.3703888890 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 4180953114 ps |
| CPU time | 7.24 seconds |
| Started | Oct 09 10:50:00 PM UTC 24 |
| Finished | Oct 09 10:50:08 PM UTC 24 |
| Peak memory | 216492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703888890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_tl_access.3703888890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/13.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/13.rv_dm_sba_tl_access.1604937456 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 1329686528 ps |
| CPU time | 2.21 seconds |
| Started | Oct 09 10:49:58 PM UTC 24 |
| Finished | Oct 09 10:50:01 PM UTC 24 |
| Peak memory | 216180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604937456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.1604937456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/13.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/13.rv_dm_stress_all.1467645965 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 2433484657 ps |
| CPU time | 4.64 seconds |
| Started | Oct 09 10:50:00 PM UTC 24 |
| Finished | Oct 09 10:50:06 PM UTC 24 |
| Peak memory | 215996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467645965 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.1467645965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/13.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/14.rv_dm_alert_test.3607064781 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 53750918 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 10:50:02 PM UTC 24 |
| Finished | Oct 09 10:50:05 PM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607064781 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.3607064781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/14.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/14.rv_dm_bad_sba_tl_access.1836546259 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 3156277970 ps |
| CPU time | 11.5 seconds |
| Started | Oct 09 10:50:02 PM UTC 24 |
| Finished | Oct 09 10:50:15 PM UTC 24 |
| Peak memory | 226400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836546259 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.1836546259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/14.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.3672548867 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 4166782215 ps |
| CPU time | 4.8 seconds |
| Started | Oct 09 10:50:02 PM UTC 24 |
| Finished | Oct 09 10:50:08 PM UTC 24 |
| Peak memory | 216172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672548867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_tl_access.3672548867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/14.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/14.rv_dm_sba_tl_access.1738655905 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 4991207243 ps |
| CPU time | 4.89 seconds |
| Started | Oct 09 10:50:02 PM UTC 24 |
| Finished | Oct 09 10:50:09 PM UTC 24 |
| Peak memory | 216160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738655905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.1738655905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/14.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/14.rv_dm_stress_all.3782237788 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 1835385390 ps |
| CPU time | 7.1 seconds |
| Started | Oct 09 10:50:02 PM UTC 24 |
| Finished | Oct 09 10:50:11 PM UTC 24 |
| Peak memory | 215860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782237788 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.3782237788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/14.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/15.rv_dm_alert_test.969452034 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 82236448 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 10:50:05 PM UTC 24 |
| Finished | Oct 09 10:50:07 PM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969452034 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.969452034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/15.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2237468185 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 2633218018 ps |
| CPU time | 12.68 seconds |
| Started | Oct 09 10:50:03 PM UTC 24 |
| Finished | Oct 09 10:50:17 PM UTC 24 |
| Peak memory | 216236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237468185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_tl_access.2237468185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/15.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/15.rv_dm_sba_tl_access.770881744 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 7198114398 ps |
| CPU time | 21.81 seconds |
| Started | Oct 09 10:50:02 PM UTC 24 |
| Finished | Oct 09 10:50:26 PM UTC 24 |
| Peak memory | 226672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770881744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.770881744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/15.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/16.rv_dm_alert_test.2486601193 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 69455120 ps |
| CPU time | 1.11 seconds |
| Started | Oct 09 10:50:07 PM UTC 24 |
| Finished | Oct 09 10:50:09 PM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486601193 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.2486601193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/16.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/16.rv_dm_autoincr_sba_tl_access.3156715053 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 20920529999 ps |
| CPU time | 75.55 seconds |
| Started | Oct 09 10:50:07 PM UTC 24 |
| Finished | Oct 09 10:51:25 PM UTC 24 |
| Peak memory | 226468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156715053 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.3156715053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/16.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/16.rv_dm_bad_sba_tl_access.2225203859 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 10719720109 ps |
| CPU time | 30.29 seconds |
| Started | Oct 09 10:50:07 PM UTC 24 |
| Finished | Oct 09 10:50:39 PM UTC 24 |
| Peak memory | 226736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225203859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.2225203859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/16.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.3658075510 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 4713314602 ps |
| CPU time | 16.82 seconds |
| Started | Oct 09 10:50:05 PM UTC 24 |
| Finished | Oct 09 10:50:23 PM UTC 24 |
| Peak memory | 216428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658075510 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_tl_access.3658075510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/16.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/16.rv_dm_sba_tl_access.1196997897 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 1204387230 ps |
| CPU time | 4.35 seconds |
| Started | Oct 09 10:50:05 PM UTC 24 |
| Finished | Oct 09 10:50:10 PM UTC 24 |
| Peak memory | 216104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196997897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.1196997897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/16.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/16.rv_dm_stress_all.3505421335 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 888889985 ps |
| CPU time | 4.48 seconds |
| Started | Oct 09 10:50:07 PM UTC 24 |
| Finished | Oct 09 10:50:13 PM UTC 24 |
| Peak memory | 226320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505421335 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.3505421335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/16.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/17.rv_dm_alert_test.2805250790 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 35803040 ps |
| CPU time | 1.22 seconds |
| Started | Oct 09 10:50:10 PM UTC 24 |
| Finished | Oct 09 10:50:12 PM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805250790 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.2805250790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/17.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/17.rv_dm_autoincr_sba_tl_access.1090999011 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 5925271304 ps |
| CPU time | 20.77 seconds |
| Started | Oct 09 10:50:10 PM UTC 24 |
| Finished | Oct 09 10:50:32 PM UTC 24 |
| Peak memory | 226464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090999011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.1090999011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/17.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/17.rv_dm_bad_sba_tl_access.4073092553 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 5343633540 ps |
| CPU time | 12.57 seconds |
| Started | Oct 09 10:50:07 PM UTC 24 |
| Finished | Oct 09 10:50:21 PM UTC 24 |
| Peak memory | 226416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073092553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.4073092553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/17.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.178733577 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 1724938832 ps |
| CPU time | 3.19 seconds |
| Started | Oct 09 10:50:07 PM UTC 24 |
| Finished | Oct 09 10:50:12 PM UTC 24 |
| Peak memory | 226472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178733577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_tl_access.178733577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/17.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/17.rv_dm_sba_tl_access.4143561040 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 1917962463 ps |
| CPU time | 4.35 seconds |
| Started | Oct 09 10:50:07 PM UTC 24 |
| Finished | Oct 09 10:50:13 PM UTC 24 |
| Peak memory | 216036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143561040 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.4143561040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/17.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/18.rv_dm_alert_test.486973866 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 31606376 ps |
| CPU time | 1.17 seconds |
| Started | Oct 09 10:50:12 PM UTC 24 |
| Finished | Oct 09 10:50:14 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486973866 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.486973866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/18.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/18.rv_dm_autoincr_sba_tl_access.1346772155 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 17943173888 ps |
| CPU time | 31.23 seconds |
| Started | Oct 09 10:50:12 PM UTC 24 |
| Finished | Oct 09 10:50:45 PM UTC 24 |
| Peak memory | 216216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346772155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.1346772155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/18.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/18.rv_dm_bad_sba_tl_access.2425290055 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 5755080772 ps |
| CPU time | 5.31 seconds |
| Started | Oct 09 10:50:10 PM UTC 24 |
| Finished | Oct 09 10:50:16 PM UTC 24 |
| Peak memory | 226396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425290055 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.2425290055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/18.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.2115379561 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 8764401426 ps |
| CPU time | 22.13 seconds |
| Started | Oct 09 10:50:10 PM UTC 24 |
| Finished | Oct 09 10:50:33 PM UTC 24 |
| Peak memory | 216428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115379561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_tl_access.2115379561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/18.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/18.rv_dm_sba_tl_access.1758657506 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 2699673248 ps |
| CPU time | 9.73 seconds |
| Started | Oct 09 10:50:10 PM UTC 24 |
| Finished | Oct 09 10:50:21 PM UTC 24 |
| Peak memory | 216232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758657506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.1758657506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/18.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/18.rv_dm_stress_all.2161115303 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 1372956668 ps |
| CPU time | 3.31 seconds |
| Started | Oct 09 10:50:12 PM UTC 24 |
| Finished | Oct 09 10:50:16 PM UTC 24 |
| Peak memory | 226180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161115303 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.2161115303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/18.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/19.rv_dm_alert_test.771612515 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 82714804 ps |
| CPU time | 0.94 seconds |
| Started | Oct 09 10:50:15 PM UTC 24 |
| Finished | Oct 09 10:50:17 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771612515 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.771612515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/19.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.1400605963 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 21729673400 ps |
| CPU time | 88.14 seconds |
| Started | Oct 09 10:50:12 PM UTC 24 |
| Finished | Oct 09 10:51:43 PM UTC 24 |
| Peak memory | 228708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400605963 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.1400605963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/19.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/19.rv_dm_bad_sba_tl_access.481378552 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 15469985862 ps |
| CPU time | 25.76 seconds |
| Started | Oct 09 10:50:12 PM UTC 24 |
| Finished | Oct 09 10:50:39 PM UTC 24 |
| Peak memory | 226472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481378552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.481378552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/19.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.748275767 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 1558996378 ps |
| CPU time | 6.43 seconds |
| Started | Oct 09 10:50:12 PM UTC 24 |
| Finished | Oct 09 10:50:20 PM UTC 24 |
| Peak memory | 216020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748275767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_tl_access.748275767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/19.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/19.rv_dm_sba_tl_access.2163014714 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 2179814821 ps |
| CPU time | 4.13 seconds |
| Started | Oct 09 10:50:12 PM UTC 24 |
| Finished | Oct 09 10:50:17 PM UTC 24 |
| Peak memory | 216236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163014714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.2163014714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/19.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.85028671 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4702317526 ps |
| CPU time | 7.67 seconds |
| Started | Oct 09 10:50:14 PM UTC 24 |
| Finished | Oct 09 10:50:23 PM UTC 24 |
| Peak memory | 226508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85028671 -assert nopostproc +UVM_TESTNAME=rv_ dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.85028671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/19.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.2598090611 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 106935640 ps |
| CPU time | 0.88 seconds |
| Started | Oct 09 10:49:37 PM UTC 24 |
| Finished | Oct 09 10:49:39 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598090611 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.2598090611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/2.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.1428670808 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 6316415659 ps |
| CPU time | 5.06 seconds |
| Started | Oct 09 10:49:36 PM UTC 24 |
| Finished | Oct 09 10:49:42 PM UTC 24 |
| Peak memory | 226344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428670808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.1428670808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/2.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.2749529184 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 10092739196 ps |
| CPU time | 31.07 seconds |
| Started | Oct 09 10:49:36 PM UTC 24 |
| Finished | Oct 09 10:50:09 PM UTC 24 |
| Peak memory | 226412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749529184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.2749529184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/2.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.1807534780 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 3068225213 ps |
| CPU time | 2.54 seconds |
| Started | Oct 09 10:49:36 PM UTC 24 |
| Finished | Oct 09 10:49:40 PM UTC 24 |
| Peak memory | 216420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807534780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_tl_access.1807534780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/2.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.518681226 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 667287538 ps |
| CPU time | 1.45 seconds |
| Started | Oct 09 10:49:36 PM UTC 24 |
| Finished | Oct 09 10:49:39 PM UTC 24 |
| Peak memory | 215368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518681226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_halt_resume_whereto.518681226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/2.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.3115683373 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 82260856 ps |
| CPU time | 0.94 seconds |
| Started | Oct 09 10:49:36 PM UTC 24 |
| Finished | Oct 09 10:49:38 PM UTC 24 |
| Peak memory | 215376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115683373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.3115683373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/2.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.2844833052 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 2262891643 ps |
| CPU time | 5.25 seconds |
| Started | Oct 09 10:49:35 PM UTC 24 |
| Finished | Oct 09 10:49:42 PM UTC 24 |
| Peak memory | 216168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844833052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.2844833052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/2.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.966039906 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 572449270 ps |
| CPU time | 1.83 seconds |
| Started | Oct 09 10:49:37 PM UTC 24 |
| Finished | Oct 09 10:49:40 PM UTC 24 |
| Peak memory | 251628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966039906 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.966039906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/2.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_sparse_lc_gate_fsm.3335750074 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 56053122 ps |
| CPU time | 0.98 seconds |
| Started | Oct 09 10:49:37 PM UTC 24 |
| Finished | Oct 09 10:49:39 PM UTC 24 |
| Peak memory | 225328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335750074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sparse_lc_gate_fsm.3335750074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/2.rv_dm_sparse_lc_gate_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all.3787575169 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 2877613119 ps |
| CPU time | 7.55 seconds |
| Started | Oct 09 10:49:37 PM UTC 24 |
| Finished | Oct 09 10:49:46 PM UTC 24 |
| Peak memory | 216016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787575169 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.3787575169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/2.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/20.rv_dm_alert_test.3132786082 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 52993639 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 10:50:17 PM UTC 24 |
| Finished | Oct 09 10:50:19 PM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132786082 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.3132786082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/20.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.3633084171 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 3789496668 ps |
| CPU time | 14.96 seconds |
| Started | Oct 09 10:50:15 PM UTC 24 |
| Finished | Oct 09 10:50:31 PM UTC 24 |
| Peak memory | 232996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633084171 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.3633084171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/20.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/21.rv_dm_alert_test.1235712816 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 65497070 ps |
| CPU time | 1.08 seconds |
| Started | Oct 09 10:50:17 PM UTC 24 |
| Finished | Oct 09 10:50:19 PM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235712816 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.1235712816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/21.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/22.rv_dm_alert_test.309817671 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 47064952 ps |
| CPU time | 1.22 seconds |
| Started | Oct 09 10:50:17 PM UTC 24 |
| Finished | Oct 09 10:50:19 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309817671 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.309817671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/22.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/23.rv_dm_alert_test.1502326218 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 99303373 ps |
| CPU time | 1.06 seconds |
| Started | Oct 09 10:50:17 PM UTC 24 |
| Finished | Oct 09 10:50:19 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502326218 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.1502326218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/23.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/23.rv_dm_stress_all.4234828298 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 2514667235 ps |
| CPU time | 9.69 seconds |
| Started | Oct 09 10:50:17 PM UTC 24 |
| Finished | Oct 09 10:50:28 PM UTC 24 |
| Peak memory | 226308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234828298 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.4234828298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/23.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/24.rv_dm_alert_test.3862175082 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 44227778 ps |
| CPU time | 1.04 seconds |
| Started | Oct 09 10:50:17 PM UTC 24 |
| Finished | Oct 09 10:50:19 PM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862175082 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.3862175082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/24.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/24.rv_dm_stress_all.2174680518 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 4562264801 ps |
| CPU time | 14.78 seconds |
| Started | Oct 09 10:50:17 PM UTC 24 |
| Finished | Oct 09 10:50:33 PM UTC 24 |
| Peak memory | 216256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174680518 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.2174680518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/24.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/25.rv_dm_alert_test.497941705 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 52284435 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 10:50:19 PM UTC 24 |
| Finished | Oct 09 10:50:22 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497941705 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.497941705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/25.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.141661652 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 1564827846 ps |
| CPU time | 8.52 seconds |
| Started | Oct 09 10:50:17 PM UTC 24 |
| Finished | Oct 09 10:50:27 PM UTC 24 |
| Peak memory | 226040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141661652 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.141661652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/25.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/26.rv_dm_alert_test.314870552 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 45942851 ps |
| CPU time | 1.05 seconds |
| Started | Oct 09 10:50:19 PM UTC 24 |
| Finished | Oct 09 10:50:22 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314870552 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.314870552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/26.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/26.rv_dm_stress_all.4178216192 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 6896777169 ps |
| CPU time | 6.66 seconds |
| Started | Oct 09 10:50:19 PM UTC 24 |
| Finished | Oct 09 10:50:27 PM UTC 24 |
| Peak memory | 216256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178216192 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.4178216192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/26.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/27.rv_dm_alert_test.2548037490 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 60253058 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 10:50:20 PM UTC 24 |
| Finished | Oct 09 10:50:22 PM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548037490 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.2548037490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/27.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.3928526195 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 8163911950 ps |
| CPU time | 8.52 seconds |
| Started | Oct 09 10:50:20 PM UTC 24 |
| Finished | Oct 09 10:50:29 PM UTC 24 |
| Peak memory | 216008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928526195 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.3928526195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/27.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/28.rv_dm_alert_test.2762066220 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 54161182 ps |
| CPU time | 1.23 seconds |
| Started | Oct 09 10:50:22 PM UTC 24 |
| Finished | Oct 09 10:50:24 PM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762066220 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.2762066220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/28.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/28.rv_dm_stress_all.3707606707 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 4306365215 ps |
| CPU time | 8.66 seconds |
| Started | Oct 09 10:50:21 PM UTC 24 |
| Finished | Oct 09 10:50:31 PM UTC 24 |
| Peak memory | 226512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707606707 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.3707606707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/28.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/29.rv_dm_alert_test.3152816035 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 89195111 ps |
| CPU time | 1.19 seconds |
| Started | Oct 09 10:50:22 PM UTC 24 |
| Finished | Oct 09 10:50:24 PM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152816035 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.3152816035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/29.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/29.rv_dm_stress_all.910601288 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 1968512016 ps |
| CPU time | 6.92 seconds |
| Started | Oct 09 10:50:22 PM UTC 24 |
| Finished | Oct 09 10:50:30 PM UTC 24 |
| Peak memory | 226108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910601288 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.910601288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/29.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.150906194 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 6083957337 ps |
| CPU time | 19.93 seconds |
| Started | Oct 09 10:49:37 PM UTC 24 |
| Finished | Oct 09 10:49:59 PM UTC 24 |
| Peak memory | 226444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150906194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.150906194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/3.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.1932564277 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 3121794653 ps |
| CPU time | 4.62 seconds |
| Started | Oct 09 10:49:37 PM UTC 24 |
| Finished | Oct 09 10:49:43 PM UTC 24 |
| Peak memory | 226532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932564277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.1932564277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/3.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.2416860136 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 109407893 ps |
| CPU time | 1.33 seconds |
| Started | Oct 09 10:49:38 PM UTC 24 |
| Finished | Oct 09 10:49:41 PM UTC 24 |
| Peak memory | 250996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416860136 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_buffered_enable.2416860136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/3.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.4030767855 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 7587091812 ps |
| CPU time | 12.88 seconds |
| Started | Oct 09 10:49:37 PM UTC 24 |
| Finished | Oct 09 10:49:52 PM UTC 24 |
| Peak memory | 216160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030767855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_tl_access.4030767855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/3.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.3137009147 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 467429755 ps |
| CPU time | 2.12 seconds |
| Started | Oct 09 10:49:38 PM UTC 24 |
| Finished | Oct 09 10:49:42 PM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137009147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_halt_resume_whereto.3137009147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/3.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_hart_unavail.1623490824 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 297148302 ps |
| CPU time | 1.56 seconds |
| Started | Oct 09 10:49:38 PM UTC 24 |
| Finished | Oct 09 10:49:41 PM UTC 24 |
| Peak memory | 215464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623490824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.1623490824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/3.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.1352964050 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 5929793616 ps |
| CPU time | 16.4 seconds |
| Started | Oct 09 10:49:37 PM UTC 24 |
| Finished | Oct 09 10:49:55 PM UTC 24 |
| Peak memory | 216168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352964050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.1352964050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/3.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_sec_cm.4119802628 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 1071131075 ps |
| CPU time | 1.93 seconds |
| Started | Oct 09 10:49:39 PM UTC 24 |
| Finished | Oct 09 10:49:42 PM UTC 24 |
| Peak memory | 251040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119802628 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.4119802628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/3.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.2060903518 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 273464945 ps |
| CPU time | 1.76 seconds |
| Started | Oct 09 10:49:38 PM UTC 24 |
| Finished | Oct 09 10:49:41 PM UTC 24 |
| Peak memory | 225328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060903518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sparse_lc_gate_fsm.2060903518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/3.rv_dm_sparse_lc_gate_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.2028181341 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 2896795950 ps |
| CPU time | 5.92 seconds |
| Started | Oct 09 10:49:38 PM UTC 24 |
| Finished | Oct 09 10:49:46 PM UTC 24 |
| Peak memory | 215992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028181341 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.2028181341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/3.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/30.rv_dm_alert_test.2909113240 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 99337942 ps |
| CPU time | 0.98 seconds |
| Started | Oct 09 10:50:22 PM UTC 24 |
| Finished | Oct 09 10:50:24 PM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909113240 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.2909113240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/30.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.3513322056 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1735704612 ps |
| CPU time | 9.57 seconds |
| Started | Oct 09 10:50:22 PM UTC 24 |
| Finished | Oct 09 10:50:33 PM UTC 24 |
| Peak memory | 215844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513322056 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.3513322056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/30.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/31.rv_dm_alert_test.3835440453 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 90616664 ps |
| CPU time | 1.35 seconds |
| Started | Oct 09 10:50:23 PM UTC 24 |
| Finished | Oct 09 10:50:26 PM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835440453 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.3835440453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/31.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/31.rv_dm_stress_all.3823114834 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 9713377547 ps |
| CPU time | 27.12 seconds |
| Started | Oct 09 10:50:22 PM UTC 24 |
| Finished | Oct 09 10:50:50 PM UTC 24 |
| Peak memory | 216120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823114834 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.3823114834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/31.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/32.rv_dm_alert_test.1980703654 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 115219811 ps |
| CPU time | 1.21 seconds |
| Started | Oct 09 10:50:23 PM UTC 24 |
| Finished | Oct 09 10:50:26 PM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980703654 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.1980703654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/32.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/32.rv_dm_stress_all.3292457660 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 2912143839 ps |
| CPU time | 3.47 seconds |
| Started | Oct 09 10:50:23 PM UTC 24 |
| Finished | Oct 09 10:50:28 PM UTC 24 |
| Peak memory | 216192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292457660 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.3292457660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/32.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/33.rv_dm_alert_test.1609564863 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 66030726 ps |
| CPU time | 1.38 seconds |
| Started | Oct 09 10:50:23 PM UTC 24 |
| Finished | Oct 09 10:50:26 PM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609564863 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.1609564863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/33.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.2552596974 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 2809523256 ps |
| CPU time | 2.54 seconds |
| Started | Oct 09 10:50:23 PM UTC 24 |
| Finished | Oct 09 10:50:27 PM UTC 24 |
| Peak memory | 226236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552596974 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.2552596974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/33.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/34.rv_dm_alert_test.3808796897 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 32779613 ps |
| CPU time | 1 seconds |
| Started | Oct 09 10:50:26 PM UTC 24 |
| Finished | Oct 09 10:50:28 PM UTC 24 |
| Peak memory | 215320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808796897 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.3808796897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/34.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/34.rv_dm_stress_all.1557800334 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 1962896277 ps |
| CPU time | 7.14 seconds |
| Started | Oct 09 10:50:23 PM UTC 24 |
| Finished | Oct 09 10:50:32 PM UTC 24 |
| Peak memory | 226308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557800334 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.1557800334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/34.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/35.rv_dm_alert_test.2044322304 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 84698072 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 10:50:26 PM UTC 24 |
| Finished | Oct 09 10:50:28 PM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044322304 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.2044322304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/35.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/35.rv_dm_stress_all.381155734 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 2619150943 ps |
| CPU time | 3.98 seconds |
| Started | Oct 09 10:50:26 PM UTC 24 |
| Finished | Oct 09 10:50:31 PM UTC 24 |
| Peak memory | 226440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381155734 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.381155734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/35.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/36.rv_dm_alert_test.774106615 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 58225103 ps |
| CPU time | 0.94 seconds |
| Started | Oct 09 10:50:26 PM UTC 24 |
| Finished | Oct 09 10:50:28 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774106615 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.774106615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/36.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/36.rv_dm_stress_all.2446551592 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 9240401999 ps |
| CPU time | 10.89 seconds |
| Started | Oct 09 10:50:26 PM UTC 24 |
| Finished | Oct 09 10:50:38 PM UTC 24 |
| Peak memory | 216044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446551592 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.2446551592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/36.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/37.rv_dm_alert_test.4111115435 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 134151513 ps |
| CPU time | 1.46 seconds |
| Started | Oct 09 10:50:26 PM UTC 24 |
| Finished | Oct 09 10:50:29 PM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111115435 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.4111115435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/37.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/37.rv_dm_stress_all.813424238 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 6723665434 ps |
| CPU time | 20.32 seconds |
| Started | Oct 09 10:50:26 PM UTC 24 |
| Finished | Oct 09 10:50:48 PM UTC 24 |
| Peak memory | 216268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813424238 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.813424238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/37.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/38.rv_dm_alert_test.4155099391 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 154002132 ps |
| CPU time | 1.02 seconds |
| Started | Oct 09 10:50:28 PM UTC 24 |
| Finished | Oct 09 10:50:30 PM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155099391 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.4155099391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/38.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/38.rv_dm_stress_all.2229800547 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 1547559654 ps |
| CPU time | 3.58 seconds |
| Started | Oct 09 10:50:26 PM UTC 24 |
| Finished | Oct 09 10:50:31 PM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229800547 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.2229800547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/38.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/39.rv_dm_alert_test.2911506233 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 63049298 ps |
| CPU time | 1.12 seconds |
| Started | Oct 09 10:50:28 PM UTC 24 |
| Finished | Oct 09 10:50:31 PM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911506233 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.2911506233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/39.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/39.rv_dm_stress_all.1364599088 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 5081564697 ps |
| CPU time | 5.12 seconds |
| Started | Oct 09 10:50:28 PM UTC 24 |
| Finished | Oct 09 10:50:34 PM UTC 24 |
| Peak memory | 216256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364599088 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.1364599088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/39.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_alert_test.4184016783 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 136736467 ps |
| CPU time | 0.8 seconds |
| Started | Oct 09 10:49:42 PM UTC 24 |
| Finished | Oct 09 10:49:44 PM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184016783 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.4184016783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/4.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_autoincr_sba_tl_access.3400181348 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 6259710398 ps |
| CPU time | 11.1 seconds |
| Started | Oct 09 10:49:40 PM UTC 24 |
| Finished | Oct 09 10:49:53 PM UTC 24 |
| Peak memory | 226476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400181348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.3400181348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/4.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_bad_sba_tl_access.307467123 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 6480646188 ps |
| CPU time | 24.43 seconds |
| Started | Oct 09 10:49:40 PM UTC 24 |
| Finished | Oct 09 10:50:06 PM UTC 24 |
| Peak memory | 226592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307467123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.307467123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/4.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_buffered_enable.1739345121 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 407184002 ps |
| CPU time | 2.14 seconds |
| Started | Oct 09 10:49:40 PM UTC 24 |
| Finished | Oct 09 10:49:44 PM UTC 24 |
| Peak memory | 252292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739345121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_buffered_enable.1739345121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/4.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3412023417 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 8154911780 ps |
| CPU time | 15.38 seconds |
| Started | Oct 09 10:49:39 PM UTC 24 |
| Finished | Oct 09 10:49:55 PM UTC 24 |
| Peak memory | 216356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412023417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_tl_access.3412023417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/4.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.3076040457 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 393342341 ps |
| CPU time | 1.76 seconds |
| Started | Oct 09 10:49:40 PM UTC 24 |
| Finished | Oct 09 10:49:43 PM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076040457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_halt_resume_whereto.3076040457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/4.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.2276795775 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 295311278 ps |
| CPU time | 1.58 seconds |
| Started | Oct 09 10:49:40 PM UTC 24 |
| Finished | Oct 09 10:49:43 PM UTC 24 |
| Peak memory | 215464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276795775 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.2276795775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/4.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_sba_tl_access.2974094497 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 940591687 ps |
| CPU time | 3.19 seconds |
| Started | Oct 09 10:49:39 PM UTC 24 |
| Finished | Oct 09 10:49:43 PM UTC 24 |
| Peak memory | 216304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974094497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.2974094497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/4.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_sec_cm.4123272355 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 2613148387 ps |
| CPU time | 2.81 seconds |
| Started | Oct 09 10:49:40 PM UTC 24 |
| Finished | Oct 09 10:49:45 PM UTC 24 |
| Peak memory | 254764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123272355 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.4123272355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/4.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.692005783 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 2559397916 ps |
| CPU time | 38.29 seconds |
| Started | Oct 09 10:49:40 PM UTC 24 |
| Finished | Oct 09 10:50:20 PM UTC 24 |
| Peak memory | 243472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=692005783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress _all_with_rand_reset.692005783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/40.rv_dm_alert_test.1835844519 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 68005337 ps |
| CPU time | 1.38 seconds |
| Started | Oct 09 10:50:28 PM UTC 24 |
| Finished | Oct 09 10:50:31 PM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835844519 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.1835844519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/40.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/40.rv_dm_stress_all.1552654556 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 809628089 ps |
| CPU time | 4.57 seconds |
| Started | Oct 09 10:50:28 PM UTC 24 |
| Finished | Oct 09 10:50:34 PM UTC 24 |
| Peak memory | 226364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552654556 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.1552654556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/40.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/41.rv_dm_alert_test.2238663252 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 70179377 ps |
| CPU time | 1.16 seconds |
| Started | Oct 09 10:50:28 PM UTC 24 |
| Finished | Oct 09 10:50:31 PM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238663252 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.2238663252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/41.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/41.rv_dm_stress_all.850144963 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 2073065198 ps |
| CPU time | 4 seconds |
| Started | Oct 09 10:50:28 PM UTC 24 |
| Finished | Oct 09 10:50:33 PM UTC 24 |
| Peak memory | 216064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850144963 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.850144963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/41.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/42.rv_dm_alert_test.3812014707 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 73205436 ps |
| CPU time | 1.23 seconds |
| Started | Oct 09 10:50:29 PM UTC 24 |
| Finished | Oct 09 10:50:31 PM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812014707 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.3812014707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/42.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/42.rv_dm_stress_all.3111124273 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 1296923624 ps |
| CPU time | 3.05 seconds |
| Started | Oct 09 10:50:29 PM UTC 24 |
| Finished | Oct 09 10:50:33 PM UTC 24 |
| Peak memory | 215860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111124273 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.3111124273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/42.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/43.rv_dm_alert_test.221162838 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 32012173 ps |
| CPU time | 0.86 seconds |
| Started | Oct 09 10:50:31 PM UTC 24 |
| Finished | Oct 09 10:50:33 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221162838 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.221162838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/43.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/43.rv_dm_stress_all.4069899595 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 2275076064 ps |
| CPU time | 2.87 seconds |
| Started | Oct 09 10:50:31 PM UTC 24 |
| Finished | Oct 09 10:50:35 PM UTC 24 |
| Peak memory | 226632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069899595 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.4069899595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/43.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/44.rv_dm_alert_test.840282494 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 44629285 ps |
| CPU time | 0.92 seconds |
| Started | Oct 09 10:50:31 PM UTC 24 |
| Finished | Oct 09 10:50:33 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840282494 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.840282494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/44.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.27614277 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 3616278680 ps |
| CPU time | 3.55 seconds |
| Started | Oct 09 10:50:31 PM UTC 24 |
| Finished | Oct 09 10:50:36 PM UTC 24 |
| Peak memory | 216340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27614277 -assert nopostproc +UVM_TESTNAME=rv_ dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.27614277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/44.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/45.rv_dm_alert_test.14720154 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 172363401 ps |
| CPU time | 1.34 seconds |
| Started | Oct 09 10:50:31 PM UTC 24 |
| Finished | Oct 09 10:50:33 PM UTC 24 |
| Peak memory | 215340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14720154 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.14720154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/45.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/46.rv_dm_alert_test.1714831254 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 44994310 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 10:50:31 PM UTC 24 |
| Finished | Oct 09 10:50:33 PM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714831254 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.1714831254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/46.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.3688963634 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 1375576748 ps |
| CPU time | 8.12 seconds |
| Started | Oct 09 10:50:31 PM UTC 24 |
| Finished | Oct 09 10:50:40 PM UTC 24 |
| Peak memory | 216056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688963634 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.3688963634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/46.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/47.rv_dm_alert_test.4225737938 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 30746695 ps |
| CPU time | 0.89 seconds |
| Started | Oct 09 10:50:33 PM UTC 24 |
| Finished | Oct 09 10:50:35 PM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225737938 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.4225737938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/47.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/47.rv_dm_stress_all.489266857 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 2228292693 ps |
| CPU time | 7.12 seconds |
| Started | Oct 09 10:50:33 PM UTC 24 |
| Finished | Oct 09 10:50:42 PM UTC 24 |
| Peak memory | 216136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489266857 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.489266857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/47.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/48.rv_dm_alert_test.4076323643 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 65808308 ps |
| CPU time | 0.99 seconds |
| Started | Oct 09 10:50:33 PM UTC 24 |
| Finished | Oct 09 10:50:36 PM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076323643 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.4076323643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/48.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/48.rv_dm_stress_all.2968425482 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 5668545946 ps |
| CPU time | 5.28 seconds |
| Started | Oct 09 10:50:33 PM UTC 24 |
| Finished | Oct 09 10:50:40 PM UTC 24 |
| Peak memory | 216064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968425482 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.2968425482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/48.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/49.rv_dm_alert_test.635316253 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 148506145 ps |
| CPU time | 0.96 seconds |
| Started | Oct 09 10:50:34 PM UTC 24 |
| Finished | Oct 09 10:50:36 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635316253 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.635316253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/49.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/49.rv_dm_stress_all.1083740387 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 708226926 ps |
| CPU time | 3.75 seconds |
| Started | Oct 09 10:50:33 PM UTC 24 |
| Finished | Oct 09 10:50:38 PM UTC 24 |
| Peak memory | 226320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083740387 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.1083740387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/49.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_alert_test.1872128663 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 96958293 ps |
| CPU time | 0.89 seconds |
| Started | Oct 09 10:49:44 PM UTC 24 |
| Finished | Oct 09 10:49:46 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872128663 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.1872128663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/5.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.328296032 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1162665758 ps |
| CPU time | 2.94 seconds |
| Started | Oct 09 10:49:43 PM UTC 24 |
| Finished | Oct 09 10:49:47 PM UTC 24 |
| Peak memory | 226476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328296032 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.328296032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/5.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.3558059104 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 781801528 ps |
| CPU time | 2.02 seconds |
| Started | Oct 09 10:49:43 PM UTC 24 |
| Finished | Oct 09 10:49:46 PM UTC 24 |
| Peak memory | 216116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558059104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.3558059104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/5.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_buffered_enable.933267112 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 163916082 ps |
| CPU time | 1.21 seconds |
| Started | Oct 09 10:49:44 PM UTC 24 |
| Finished | Oct 09 10:49:46 PM UTC 24 |
| Peak memory | 250644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933267112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_buffered_enable.933267112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/5.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.3560470912 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 1877778550 ps |
| CPU time | 3.54 seconds |
| Started | Oct 09 10:49:43 PM UTC 24 |
| Finished | Oct 09 10:49:48 PM UTC 24 |
| Peak memory | 216016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560470912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl_access.3560470912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/5.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_halt_resume_whereto.3853292444 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 262366666 ps |
| CPU time | 1.42 seconds |
| Started | Oct 09 10:49:43 PM UTC 24 |
| Finished | Oct 09 10:49:45 PM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853292444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_halt_resume_whereto.3853292444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/5.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_sba_tl_access.3217437432 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 1204644705 ps |
| CPU time | 4.45 seconds |
| Started | Oct 09 10:49:43 PM UTC 24 |
| Finished | Oct 09 10:49:48 PM UTC 24 |
| Peak memory | 216044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217437432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.3217437432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/5.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.2864024341 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 2830887194 ps |
| CPU time | 9.49 seconds |
| Started | Oct 09 10:49:44 PM UTC 24 |
| Finished | Oct 09 10:49:55 PM UTC 24 |
| Peak memory | 216240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864024341 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.2864024341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/5.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_alert_test.4271133395 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 35699631 ps |
| CPU time | 1.17 seconds |
| Started | Oct 09 10:49:45 PM UTC 24 |
| Finished | Oct 09 10:49:47 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271133395 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.4271133395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/6.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_autoincr_sba_tl_access.1455496663 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 5402128169 ps |
| CPU time | 2.15 seconds |
| Started | Oct 09 10:49:44 PM UTC 24 |
| Finished | Oct 09 10:49:48 PM UTC 24 |
| Peak memory | 226668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455496663 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.1455496663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/6.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_bad_sba_tl_access.3850722184 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 1409158553 ps |
| CPU time | 8.29 seconds |
| Started | Oct 09 10:49:44 PM UTC 24 |
| Finished | Oct 09 10:49:54 PM UTC 24 |
| Peak memory | 216104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850722184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.3850722184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/6.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_buffered_enable.1407418704 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 185333287 ps |
| CPU time | 1.8 seconds |
| Started | Oct 09 10:49:44 PM UTC 24 |
| Finished | Oct 09 10:49:47 PM UTC 24 |
| Peak memory | 250696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407418704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_buffered_enable.1407418704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/6.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.2297809037 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 1699515129 ps |
| CPU time | 2.52 seconds |
| Started | Oct 09 10:49:44 PM UTC 24 |
| Finished | Oct 09 10:49:48 PM UTC 24 |
| Peak memory | 216152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297809037 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_tl_access.2297809037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/6.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_halt_resume_whereto.2385740206 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 292510585 ps |
| CPU time | 1.77 seconds |
| Started | Oct 09 10:49:44 PM UTC 24 |
| Finished | Oct 09 10:49:47 PM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385740206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_halt_resume_whereto.2385740206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/6.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_sba_tl_access.733312762 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 9967537429 ps |
| CPU time | 17.66 seconds |
| Started | Oct 09 10:49:44 PM UTC 24 |
| Finished | Oct 09 10:50:03 PM UTC 24 |
| Peak memory | 216300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733312762 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.733312762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/6.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all.1297341996 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 3279305201 ps |
| CPU time | 2.99 seconds |
| Started | Oct 09 10:49:45 PM UTC 24 |
| Finished | Oct 09 10:49:49 PM UTC 24 |
| Peak memory | 226424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297341996 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.1297341996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/6.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_alert_test.344525555 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 165827928 ps |
| CPU time | 1.26 seconds |
| Started | Oct 09 10:49:47 PM UTC 24 |
| Finished | Oct 09 10:49:50 PM UTC 24 |
| Peak memory | 215340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344525555 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.344525555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/7.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.2147667488 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 1977900876 ps |
| CPU time | 5.76 seconds |
| Started | Oct 09 10:49:45 PM UTC 24 |
| Finished | Oct 09 10:49:52 PM UTC 24 |
| Peak memory | 226476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147667488 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.2147667488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/7.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.3920759738 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 941955536 ps |
| CPU time | 2.08 seconds |
| Started | Oct 09 10:49:45 PM UTC 24 |
| Finished | Oct 09 10:49:48 PM UTC 24 |
| Peak memory | 226268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920759738 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.3920759738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/7.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_buffered_enable.3650037063 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 405642194 ps |
| CPU time | 2.07 seconds |
| Started | Oct 09 10:49:47 PM UTC 24 |
| Finished | Oct 09 10:49:50 PM UTC 24 |
| Peak memory | 252280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650037063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_buffered_enable.3650037063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/7.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3692971583 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 6074872362 ps |
| CPU time | 14.2 seconds |
| Started | Oct 09 10:49:45 PM UTC 24 |
| Finished | Oct 09 10:50:00 PM UTC 24 |
| Peak memory | 226532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692971583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_tl_access.3692971583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/7.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.1165093819 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 703530772 ps |
| CPU time | 2.25 seconds |
| Started | Oct 09 10:49:47 PM UTC 24 |
| Finished | Oct 09 10:49:50 PM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165093819 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_halt_resume_whereto.1165093819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/7.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_sba_tl_access.4270476064 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 872351098 ps |
| CPU time | 2.35 seconds |
| Started | Oct 09 10:49:45 PM UTC 24 |
| Finished | Oct 09 10:49:48 PM UTC 24 |
| Peak memory | 216112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270476064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.4270476064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/7.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all.4149502343 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 3018821729 ps |
| CPU time | 5.28 seconds |
| Started | Oct 09 10:49:47 PM UTC 24 |
| Finished | Oct 09 10:49:54 PM UTC 24 |
| Peak memory | 215920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149502343 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.4149502343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/7.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.3724805895 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 7080604638 ps |
| CPU time | 81.02 seconds |
| Started | Oct 09 10:49:47 PM UTC 24 |
| Finished | Oct 09 10:51:10 PM UTC 24 |
| Peak memory | 232944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3724805895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stres s_all_with_rand_reset.3724805895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_alert_test.306838374 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 60822817 ps |
| CPU time | 1.05 seconds |
| Started | Oct 09 10:49:50 PM UTC 24 |
| Finished | Oct 09 10:49:52 PM UTC 24 |
| Peak memory | 215340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306838374 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.306838374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/8.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.1803826384 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 3070290366 ps |
| CPU time | 11.69 seconds |
| Started | Oct 09 10:49:50 PM UTC 24 |
| Finished | Oct 09 10:50:03 PM UTC 24 |
| Peak memory | 216352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803826384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.1803826384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/8.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_bad_sba_tl_access.4143760077 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 8760165886 ps |
| CPU time | 7.54 seconds |
| Started | Oct 09 10:49:47 PM UTC 24 |
| Finished | Oct 09 10:49:56 PM UTC 24 |
| Peak memory | 226736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143760077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.4143760077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/8.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_buffered_enable.718162032 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 279283379 ps |
| CPU time | 1.57 seconds |
| Started | Oct 09 10:49:50 PM UTC 24 |
| Finished | Oct 09 10:49:52 PM UTC 24 |
| Peak memory | 250404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718162032 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_buffered_enable.718162032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/8.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.3492860126 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 1356046920 ps |
| CPU time | 6.08 seconds |
| Started | Oct 09 10:49:47 PM UTC 24 |
| Finished | Oct 09 10:49:55 PM UTC 24 |
| Peak memory | 226272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492860126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl_access.3492860126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/8.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_sba_tl_access.3290174511 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 1748832881 ps |
| CPU time | 6.89 seconds |
| Started | Oct 09 10:49:47 PM UTC 24 |
| Finished | Oct 09 10:49:55 PM UTC 24 |
| Peak memory | 216248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290174511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.3290174511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/8.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.4146398939 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 5134646290 ps |
| CPU time | 3.86 seconds |
| Started | Oct 09 10:49:50 PM UTC 24 |
| Finished | Oct 09 10:49:55 PM UTC 24 |
| Peak memory | 226512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146398939 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.4146398939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/8.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.2971450600 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 15466572666 ps |
| CPU time | 46.11 seconds |
| Started | Oct 09 10:49:50 PM UTC 24 |
| Finished | Oct 09 10:50:37 PM UTC 24 |
| Peak memory | 243280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2971450600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stres s_all_with_rand_reset.2971450600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.4187997218 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 44932655 ps |
| CPU time | 1.22 seconds |
| Started | Oct 09 10:49:52 PM UTC 24 |
| Finished | Oct 09 10:49:55 PM UTC 24 |
| Peak memory | 215348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187997218 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.4187997218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/9.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_autoincr_sba_tl_access.2272121445 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 10812918807 ps |
| CPU time | 9.25 seconds |
| Started | Oct 09 10:49:50 PM UTC 24 |
| Finished | Oct 09 10:50:01 PM UTC 24 |
| Peak memory | 226468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272121445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.2272121445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/9.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.3162153153 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 1359763481 ps |
| CPU time | 6.82 seconds |
| Started | Oct 09 10:49:50 PM UTC 24 |
| Finished | Oct 09 10:49:58 PM UTC 24 |
| Peak memory | 216240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162153153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.3162153153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/9.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_buffered_enable.4095402481 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 109853429 ps |
| CPU time | 1.9 seconds |
| Started | Oct 09 10:49:50 PM UTC 24 |
| Finished | Oct 09 10:49:53 PM UTC 24 |
| Peak memory | 251032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095402481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_buffered_enable.4095402481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/9.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.4255794942 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 7479498891 ps |
| CPU time | 25.9 seconds |
| Started | Oct 09 10:49:50 PM UTC 24 |
| Finished | Oct 09 10:50:17 PM UTC 24 |
| Peak memory | 226468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255794942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_tl_access.4255794942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/9.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.3130000370 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 9982176300 ps |
| CPU time | 8.96 seconds |
| Started | Oct 09 10:49:50 PM UTC 24 |
| Finished | Oct 09 10:50:00 PM UTC 24 |
| Peak memory | 226424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130000370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.3130000370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/9.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.3904216290 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 3037998862 ps |
| CPU time | 9.05 seconds |
| Started | Oct 09 10:49:50 PM UTC 24 |
| Finished | Oct 09 10:50:00 PM UTC 24 |
| Peak memory | 226168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904216290 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.3904216290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/9.rv_dm_stress_all/latest |
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