| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 88.98 | 96.64 | 90.52 | 92.10 | 93.33 | 90.44 | 98.74 | 61.10 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 57.96 | 57.96 | 85.21 | 85.21 | 52.05 | 52.05 | 53.30 | 53.30 | 53.33 | 53.33 | 65.49 | 65.49 | 93.59 | 93.59 | 2.74 | 2.74 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.3431660494 |
| 68.08 | 10.12 | 86.30 | 1.09 | 62.38 | 10.33 | 56.59 | 3.30 | 60.00 | 6.67 | 70.27 | 4.78 | 94.85 | 1.26 | 46.16 | 43.42 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.2699549530 |
| 75.14 | 7.06 | 89.09 | 2.79 | 72.14 | 9.76 | 77.87 | 21.28 | 66.67 | 6.67 | 75.93 | 5.66 | 95.90 | 1.05 | 48.36 | 2.19 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_busy.1335677411 |
| 79.22 | 4.09 | 92.45 | 3.36 | 77.93 | 5.80 | 79.33 | 1.46 | 77.33 | 10.67 | 82.83 | 6.90 | 95.90 | 0.00 | 48.77 | 0.41 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.3058991066 |
| 81.01 | 1.79 | 92.92 | 0.47 | 81.47 | 3.54 | 86.82 | 7.49 | 77.33 | 0.00 | 83.36 | 0.53 | 96.01 | 0.11 | 49.18 | 0.41 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.4205326269 |
| 82.10 | 1.09 | 93.54 | 0.62 | 82.46 | 0.99 | 87.38 | 0.56 | 80.00 | 2.67 | 84.25 | 0.88 | 96.01 | 0.00 | 51.10 | 1.92 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all_with_rand_reset.1769036947 |
| 83.14 | 1.04 | 93.64 | 0.10 | 84.02 | 1.56 | 88.75 | 1.37 | 80.00 | 0.00 | 84.78 | 0.53 | 96.01 | 0.00 | 54.79 | 3.70 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.4214058001 |
| 84.14 | 1.00 | 94.31 | 0.67 | 86.14 | 2.12 | 90.35 | 1.60 | 80.00 | 0.00 | 86.19 | 1.42 | 96.22 | 0.21 | 55.75 | 0.96 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.4059871779 |
| 84.73 | 0.59 | 94.31 | 0.00 | 86.14 | 0.00 | 90.49 | 0.14 | 84.00 | 4.00 | 86.19 | 0.00 | 96.22 | 0.00 | 55.75 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.2772393775 |
| 85.27 | 0.54 | 94.36 | 0.05 | 86.70 | 0.57 | 93.08 | 2.59 | 84.00 | 0.00 | 86.37 | 0.18 | 96.32 | 0.11 | 56.03 | 0.27 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.133075098 |
| 85.69 | 0.43 | 94.78 | 0.41 | 87.13 | 0.42 | 93.36 | 0.28 | 85.33 | 1.33 | 86.90 | 0.53 | 96.32 | 0.00 | 56.03 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.3251655814 |
| 86.09 | 0.40 | 94.78 | 0.00 | 87.13 | 0.00 | 93.50 | 0.14 | 88.00 | 2.67 | 86.90 | 0.00 | 96.32 | 0.00 | 56.03 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.3830749014 |
| 86.47 | 0.37 | 95.24 | 0.47 | 88.26 | 1.13 | 93.74 | 0.24 | 88.00 | 0.00 | 87.26 | 0.35 | 96.32 | 0.00 | 56.44 | 0.41 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/12.rv_dm_stress_all.2794121099 |
| 86.82 | 0.35 | 95.24 | 0.00 | 88.26 | 0.00 | 94.87 | 1.13 | 89.33 | 1.33 | 87.26 | 0.00 | 96.32 | 0.00 | 56.44 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.2264319204 |
| 87.16 | 0.34 | 95.97 | 0.72 | 88.54 | 0.28 | 95.10 | 0.24 | 89.33 | 0.00 | 88.14 | 0.88 | 96.32 | 0.00 | 56.71 | 0.27 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.2811599321 |
| 87.42 | 0.26 | 96.02 | 0.05 | 88.54 | 0.00 | 95.72 | 0.61 | 89.33 | 0.00 | 88.32 | 0.18 | 96.32 | 0.00 | 57.67 | 0.96 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/11.rv_dm_autoincr_sba_tl_access.3929064234 |
| 87.65 | 0.24 | 96.02 | 0.00 | 88.68 | 0.14 | 95.72 | 0.00 | 90.67 | 1.33 | 88.50 | 0.18 | 96.32 | 0.00 | 57.67 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2073317886 |
| 87.88 | 0.23 | 96.02 | 0.00 | 88.68 | 0.00 | 95.72 | 0.00 | 90.67 | 0.00 | 88.50 | 0.00 | 97.90 | 1.58 | 57.67 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.428917055 |
| 88.10 | 0.22 | 96.07 | 0.05 | 88.68 | 0.00 | 95.72 | 0.00 | 92.00 | 1.33 | 88.67 | 0.18 | 97.90 | 0.00 | 57.67 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.3486499253 |
| 88.30 | 0.20 | 96.12 | 0.05 | 88.68 | 0.00 | 95.72 | 0.00 | 93.33 | 1.33 | 88.67 | 0.00 | 97.90 | 0.00 | 57.67 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.4106353817 |
| 88.46 | 0.16 | 96.38 | 0.26 | 88.83 | 0.14 | 95.81 | 0.09 | 93.33 | 0.00 | 89.03 | 0.35 | 97.90 | 0.00 | 57.95 | 0.27 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/21.rv_dm_stress_all.1445873403 |
| 88.61 | 0.15 | 96.38 | 0.00 | 88.83 | 0.00 | 96.89 | 1.08 | 93.33 | 0.00 | 89.03 | 0.00 | 97.90 | 0.00 | 57.95 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/15.rv_dm_autoincr_sba_tl_access.2903234474 |
| 88.75 | 0.14 | 96.54 | 0.16 | 88.97 | 0.14 | 96.89 | 0.00 | 93.33 | 0.00 | 89.56 | 0.53 | 97.90 | 0.00 | 58.08 | 0.14 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.2228440018 |
| 88.86 | 0.10 | 96.59 | 0.05 | 89.11 | 0.14 | 96.94 | 0.05 | 93.33 | 0.00 | 89.91 | 0.35 | 97.90 | 0.00 | 58.22 | 0.14 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_rom_read_access.2922304141 |
| 88.96 | 0.10 | 96.59 | 0.00 | 89.25 | 0.14 | 96.94 | 0.00 | 93.33 | 0.00 | 90.09 | 0.18 | 97.90 | 0.00 | 58.63 | 0.41 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/14.rv_dm_autoincr_sba_tl_access.1287467000 |
| 89.06 | 0.10 | 96.59 | 0.00 | 89.25 | 0.00 | 96.94 | 0.00 | 93.33 | 0.00 | 90.09 | 0.00 | 97.90 | 0.00 | 59.32 | 0.68 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3855066645 |
| 89.15 | 0.09 | 96.59 | 0.00 | 89.39 | 0.14 | 97.13 | 0.19 | 93.33 | 0.00 | 90.09 | 0.00 | 97.90 | 0.00 | 59.59 | 0.27 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.3144841231 |
| 89.20 | 0.06 | 96.59 | 0.00 | 89.39 | 0.00 | 97.13 | 0.00 | 93.33 | 0.00 | 90.09 | 0.00 | 97.90 | 0.00 | 60.00 | 0.41 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/12.rv_dm_autoincr_sba_tl_access.1353993989 |
| 89.26 | 0.05 | 96.59 | 0.00 | 89.67 | 0.28 | 97.22 | 0.09 | 93.33 | 0.00 | 90.09 | 0.00 | 97.90 | 0.00 | 60.00 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/15.rv_dm_stress_all.3665495201 |
| 89.30 | 0.05 | 96.59 | 0.00 | 89.82 | 0.14 | 97.22 | 0.00 | 93.33 | 0.00 | 90.27 | 0.18 | 97.90 | 0.00 | 60.00 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.2624769551 |
| 89.34 | 0.04 | 96.59 | 0.00 | 90.10 | 0.28 | 97.22 | 0.00 | 93.33 | 0.00 | 90.27 | 0.00 | 97.90 | 0.00 | 60.00 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.3233571472 |
| 89.38 | 0.04 | 96.59 | 0.00 | 90.24 | 0.14 | 97.22 | 0.00 | 93.33 | 0.00 | 90.27 | 0.00 | 97.90 | 0.00 | 60.14 | 0.14 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.1442563592 |
| 89.42 | 0.04 | 96.59 | 0.00 | 90.24 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 90.27 | 0.00 | 97.90 | 0.00 | 60.41 | 0.27 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_intg_err.788357987 |
| 89.46 | 0.04 | 96.59 | 0.00 | 90.24 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 90.27 | 0.00 | 97.90 | 0.00 | 60.68 | 0.27 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/15.rv_dm_bad_sba_tl_access.1623105532 |
| 89.50 | 0.04 | 96.59 | 0.00 | 90.24 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 90.27 | 0.00 | 97.90 | 0.00 | 60.96 | 0.27 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/45.rv_dm_stress_all.3194403923 |
| 89.53 | 0.03 | 96.64 | 0.05 | 90.24 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 90.44 | 0.18 | 97.90 | 0.00 | 60.96 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1653405528 |
| 89.56 | 0.03 | 96.64 | 0.00 | 90.24 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 98.11 | 0.21 | 60.96 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1074637716 |
| 89.59 | 0.03 | 96.64 | 0.00 | 90.24 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 98.32 | 0.21 | 60.96 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2036462680 |
| 89.62 | 0.03 | 96.64 | 0.00 | 90.24 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 98.53 | 0.21 | 60.96 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_aliasing.180900199 |
| 89.65 | 0.02 | 96.64 | 0.00 | 90.24 | 0.00 | 97.27 | 0.05 | 93.33 | 0.00 | 90.44 | 0.00 | 98.63 | 0.11 | 60.96 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.49000722 |
| 89.67 | 0.02 | 96.64 | 0.00 | 90.38 | 0.14 | 97.27 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 98.63 | 0.00 | 60.96 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.1970149722 |
| 89.69 | 0.02 | 96.64 | 0.00 | 90.52 | 0.14 | 97.27 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 98.63 | 0.00 | 60.96 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/17.rv_dm_stress_all.899501675 |
| 89.71 | 0.02 | 96.64 | 0.00 | 90.52 | 0.00 | 97.27 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 98.63 | 0.00 | 61.10 | 0.14 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3773763777 |
| 89.72 | 0.02 | 96.64 | 0.00 | 90.52 | 0.00 | 97.27 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 98.74 | 0.11 | 61.10 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.4051267925 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1427216148 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2932020576 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2441584588 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1270355644 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.1473657562 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.16489929 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1145262009 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2240142498 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2567657226 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2312344375 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.678135807 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1394364935 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.2593987184 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.412466814 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.2378490583 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3263742276 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4052788368 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2621293157 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.236754288 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2817729240 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3292723662 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3584250852 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.837665430 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1696023149 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3248840619 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.559109714 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2303793663 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1796870264 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.351171127 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2705948911 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.2967512814 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3734888864 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2451587450 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.1329296330 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.1814163722 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1205686492 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2723686624 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2173893534 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.3201289817 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3099122797 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3312798647 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_rw.4239018807 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2099073073 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1786078353 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2562421666 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.712676233 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_errors.983806995 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3453671401 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.495630082 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_rw.979308750 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.359655009 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3126728302 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2512470070 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.168957243 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_errors.2137455894 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3662516075 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.4100623870 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_rw.1685657176 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.393562976 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1465901231 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3232984036 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3267307236 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_errors.3243535818 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1546930933 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2493178825 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_rw.2057701906 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.2925332268 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.811826137 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.3383961860 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1995599925 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_errors.1591293603 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2876975631 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_rw.3903253543 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.526698259 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2941061070 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3047390765 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2038985683 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_errors.2604387542 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.679694132 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_rw.318399835 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.3176739450 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.931812372 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3838133248 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1587257944 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_errors.3202330351 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.4077385741 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2945953845 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_rw.4060344080 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1973704954 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.4154886917 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3500608099 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2855575333 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_errors.201906568 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3847493990 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2885331924 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_rw.3254129423 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1296808441 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2643176793 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.418134501 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2109006539 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_errors.784014667 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3530080367 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2641946218 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_rw.4015504218 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.3083450131 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1366045426 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2779996817 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2964493641 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_errors.1945332163 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1572205951 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.672434201 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3450523024 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1723386122 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_rw.2304833151 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.239339589 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.166389455 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1034363827 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3420178635 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.962347151 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1092744369 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3039869270 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2506790913 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1828544024 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_walk.4071833988 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1777671219 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.1810116039 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_errors.1584276216 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3274418042 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1061687764 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1188937940 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.21090236 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.677062714 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_rw.1728943429 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3914015785 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3413860965 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1509646219 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1108377940 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1633537613 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.29896480 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1008107109 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1139668097 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_partial_access.4251644626 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_walk.2009849671 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2556145185 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_errors.2485773396 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1155126012 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.69871023 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1160743787 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.917734245 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_rw.2052398793 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2697434050 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3231050525 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1849027433 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2552326333 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.323256791 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3815343888 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1981023394 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3550428877 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3418580224 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_walk.384493100 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.369582644 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2418156368 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_errors.2786781874 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2645495407 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1651591528 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_rw.2043615871 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.1948652805 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1662865358 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2867000415 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2013990873 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_errors.3500332740 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2569949656 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.983891252 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_rw.3622516419 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.846196996 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2366596610 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.4150768997 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2316035448 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.2841465752 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_errors.1347790961 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_intg_err.4071884683 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.352742239 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_rw.568172175 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1288144164 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.4178219259 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.895723335 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2085115610 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.975539531 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_errors.3560270577 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3452952727 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1272025380 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_rw.972888227 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1098470624 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.532217315 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.811137763 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3491763337 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.67805669 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_errors.2749730322 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1783239448 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3673821222 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_rw.2793968038 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3001106261 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.4176515675 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2443438004 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.577885719 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2489962649 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_errors.3988841646 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_intg_err.389066909 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.1728814406 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.2838293786 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.3141398067 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.1483633765 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.4129896559 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_dataaddr_rw_access.1325414755 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_debug_disabled.4067381902 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.3024998929 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.378961795 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_hart_unavail.2017581750 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_hartsel_warl.4222426398 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.4213610972 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.858791431 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2214128652 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_idle_hint.300621531 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_halted.2405750608 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_resuming.2141736886 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.183520138 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.1554806547 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.3402252554 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_tl_access.1289487643 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.2899563120 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.974895095 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_abstractcmd_status.1767820901 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_alert_test.1395544135 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_autoincr_sba_tl_access.3910034659 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_bad_sba_tl_access.1511470870 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_buffered_enable.2539137558 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_busy.352792758 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.982426051 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_not_supported.187613528 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_dataaddr_rw_access.278291530 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_debug_disabled.3341018402 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.1953480246 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.1930394100 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_halt_resume_whereto.929828807 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_hart_unavail.826818143 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.4101299355 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.3014572821 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_hard_reset.2275590547 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_idle_hint.885090140 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_halted.2768277110 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_resuming.615197822 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_ndmreset_req.3186400943 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_progbuf_read_write_execute.133234138 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_debug_disabled.803446943 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_tl_access.2957597346 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_sec_cm.3463226935 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_smoke.266046063 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/10.rv_dm_alert_test.309177830 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/10.rv_dm_autoincr_sba_tl_access.3955886098 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/10.rv_dm_bad_sba_tl_access.113578460 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.3832958346 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/10.rv_dm_sba_tl_access.3636877225 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/10.rv_dm_stress_all.3029410230 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/11.rv_dm_alert_test.768817219 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/11.rv_dm_bad_sba_tl_access.3901704575 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.4045050041 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/11.rv_dm_sba_tl_access.534357688 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/11.rv_dm_stress_all.1944067238 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/12.rv_dm_alert_test.3476480760 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/12.rv_dm_bad_sba_tl_access.504987242 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.2757855592 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/12.rv_dm_sba_tl_access.1230666218 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/13.rv_dm_alert_test.889618954 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/13.rv_dm_autoincr_sba_tl_access.2160367890 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/13.rv_dm_bad_sba_tl_access.2895628364 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.3703888890 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/13.rv_dm_sba_tl_access.1604937456 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/13.rv_dm_stress_all.1467645965 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/14.rv_dm_alert_test.3607064781 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/14.rv_dm_bad_sba_tl_access.1836546259 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.3672548867 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/14.rv_dm_sba_tl_access.1738655905 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/14.rv_dm_stress_all.3782237788 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/15.rv_dm_alert_test.969452034 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2237468185 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/15.rv_dm_sba_tl_access.770881744 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/16.rv_dm_alert_test.2486601193 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/16.rv_dm_autoincr_sba_tl_access.3156715053 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/16.rv_dm_bad_sba_tl_access.2225203859 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.3658075510 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/16.rv_dm_sba_tl_access.1196997897 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/16.rv_dm_stress_all.3505421335 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/17.rv_dm_alert_test.2805250790 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/17.rv_dm_autoincr_sba_tl_access.1090999011 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/17.rv_dm_bad_sba_tl_access.4073092553 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.178733577 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/17.rv_dm_sba_tl_access.4143561040 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/18.rv_dm_alert_test.486973866 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/18.rv_dm_autoincr_sba_tl_access.1346772155 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/18.rv_dm_bad_sba_tl_access.2425290055 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.2115379561 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/18.rv_dm_sba_tl_access.1758657506 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/18.rv_dm_stress_all.2161115303 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/19.rv_dm_alert_test.771612515 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.1400605963 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/19.rv_dm_bad_sba_tl_access.481378552 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.748275767 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/19.rv_dm_sba_tl_access.2163014714 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.85028671 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.2598090611 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.1428670808 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.2749529184 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.1807534780 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.518681226 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.3115683373 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.2844833052 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.966039906 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_sparse_lc_gate_fsm.3335750074 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all.3787575169 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/20.rv_dm_alert_test.3132786082 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.3633084171 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/21.rv_dm_alert_test.1235712816 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/22.rv_dm_alert_test.309817671 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/23.rv_dm_alert_test.1502326218 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/23.rv_dm_stress_all.4234828298 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/24.rv_dm_alert_test.3862175082 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/24.rv_dm_stress_all.2174680518 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/25.rv_dm_alert_test.497941705 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.141661652 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/26.rv_dm_alert_test.314870552 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/26.rv_dm_stress_all.4178216192 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/27.rv_dm_alert_test.2548037490 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.3928526195 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/28.rv_dm_alert_test.2762066220 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/28.rv_dm_stress_all.3707606707 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/29.rv_dm_alert_test.3152816035 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/29.rv_dm_stress_all.910601288 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.150906194 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.1932564277 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.2416860136 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.4030767855 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.3137009147 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_hart_unavail.1623490824 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.1352964050 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_sec_cm.4119802628 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.2060903518 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.2028181341 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/30.rv_dm_alert_test.2909113240 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.3513322056 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/31.rv_dm_alert_test.3835440453 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/31.rv_dm_stress_all.3823114834 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/32.rv_dm_alert_test.1980703654 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/32.rv_dm_stress_all.3292457660 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/33.rv_dm_alert_test.1609564863 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.2552596974 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/34.rv_dm_alert_test.3808796897 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/34.rv_dm_stress_all.1557800334 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/35.rv_dm_alert_test.2044322304 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/35.rv_dm_stress_all.381155734 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/36.rv_dm_alert_test.774106615 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/36.rv_dm_stress_all.2446551592 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/37.rv_dm_alert_test.4111115435 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/37.rv_dm_stress_all.813424238 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/38.rv_dm_alert_test.4155099391 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/38.rv_dm_stress_all.2229800547 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/39.rv_dm_alert_test.2911506233 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/39.rv_dm_stress_all.1364599088 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_alert_test.4184016783 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_autoincr_sba_tl_access.3400181348 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_bad_sba_tl_access.307467123 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_buffered_enable.1739345121 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3412023417 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.3076040457 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.2276795775 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_sba_tl_access.2974094497 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_sec_cm.4123272355 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.692005783 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/40.rv_dm_alert_test.1835844519 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/40.rv_dm_stress_all.1552654556 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/41.rv_dm_alert_test.2238663252 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/41.rv_dm_stress_all.850144963 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/42.rv_dm_alert_test.3812014707 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/42.rv_dm_stress_all.3111124273 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/43.rv_dm_alert_test.221162838 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/43.rv_dm_stress_all.4069899595 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/44.rv_dm_alert_test.840282494 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.27614277 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/45.rv_dm_alert_test.14720154 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/46.rv_dm_alert_test.1714831254 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.3688963634 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/47.rv_dm_alert_test.4225737938 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/47.rv_dm_stress_all.489266857 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/48.rv_dm_alert_test.4076323643 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/48.rv_dm_stress_all.2968425482 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/49.rv_dm_alert_test.635316253 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/49.rv_dm_stress_all.1083740387 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_alert_test.1872128663 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.328296032 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.3558059104 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_buffered_enable.933267112 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.3560470912 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_halt_resume_whereto.3853292444 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_sba_tl_access.3217437432 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.2864024341 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_alert_test.4271133395 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_autoincr_sba_tl_access.1455496663 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_bad_sba_tl_access.3850722184 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_buffered_enable.1407418704 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.2297809037 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_halt_resume_whereto.2385740206 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_sba_tl_access.733312762 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all.1297341996 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_alert_test.344525555 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.2147667488 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.3920759738 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_buffered_enable.3650037063 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3692971583 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.1165093819 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_sba_tl_access.4270476064 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all.4149502343 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.3724805895 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_alert_test.306838374 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.1803826384 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_bad_sba_tl_access.4143760077 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_buffered_enable.718162032 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.3492860126 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_sba_tl_access.3290174511 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.4146398939 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.2971450600 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.4187997218 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_autoincr_sba_tl_access.2272121445 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.3162153153 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_buffered_enable.4095402481 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.4255794942 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.3130000370 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.3904216290 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.4129896559 | Oct 09 10:49:26 PM UTC 24 | Oct 09 10:49:28 PM UTC 24 | 373264398 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_busy.1335677411 | Oct 09 10:49:24 PM UTC 24 | Oct 09 10:49:28 PM UTC 24 | 1384272707 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_resuming.2141736886 | Oct 09 10:49:26 PM UTC 24 | Oct 09 10:49:29 PM UTC 24 | 260438028 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_halted.2405750608 | Oct 09 10:49:26 PM UTC 24 | Oct 09 10:49:29 PM UTC 24 | 497147868 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.1970149722 | Oct 09 10:49:26 PM UTC 24 | Oct 09 10:49:29 PM UTC 24 | 161798318 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_hart_unavail.2017581750 | Oct 09 10:49:26 PM UTC 24 | Oct 09 10:49:29 PM UTC 24 | 350813117 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.1483633765 | Oct 09 10:49:26 PM UTC 24 | Oct 09 10:49:30 PM UTC 24 | 859342678 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.3431660494 | Oct 09 10:49:24 PM UTC 24 | Oct 09 10:49:30 PM UTC 24 | 3089767013 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_dataaddr_rw_access.1325414755 | Oct 09 10:49:29 PM UTC 24 | Oct 09 10:49:31 PM UTC 24 | 135488025 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_idle_hint.300621531 | Oct 09 10:49:29 PM UTC 24 | Oct 09 10:49:31 PM UTC 24 | 592762288 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.4213610972 | Oct 09 10:49:29 PM UTC 24 | Oct 09 10:49:31 PM UTC 24 | 109461082 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.3402252554 | Oct 09 10:49:29 PM UTC 24 | Oct 09 10:49:31 PM UTC 24 | 137539415 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.2899563120 | Oct 09 10:49:29 PM UTC 24 | Oct 09 10:49:31 PM UTC 24 | 22556844 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_hartsel_warl.4222426398 | Oct 09 10:49:29 PM UTC 24 | Oct 09 10:49:31 PM UTC 24 | 56983700 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.183520138 | Oct 09 10:49:29 PM UTC 24 | Oct 09 10:49:31 PM UTC 24 | 340176700 ps | ||
| T92 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_debug_disabled.4067381902 | Oct 09 10:49:29 PM UTC 24 | Oct 09 10:49:31 PM UTC 24 | 51374685 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.4106353817 | Oct 09 10:49:29 PM UTC 24 | Oct 09 10:49:32 PM UTC 24 | 122835012 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.3141398067 | Oct 09 10:49:29 PM UTC 24 | Oct 09 10:49:32 PM UTC 24 | 102078613 ps | ||
| T59 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.4059871779 | Oct 09 10:49:29 PM UTC 24 | Oct 09 10:49:32 PM UTC 24 | 454953614 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2214128652 | Oct 09 10:49:29 PM UTC 24 | Oct 09 10:49:32 PM UTC 24 | 687135743 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.49000722 | Oct 09 10:49:29 PM UTC 24 | Oct 09 10:49:32 PM UTC 24 | 162593380 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.378961795 | Oct 09 10:49:29 PM UTC 24 | Oct 09 10:49:32 PM UTC 24 | 1410552784 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.1554806547 | Oct 09 10:49:29 PM UTC 24 | Oct 09 10:49:32 PM UTC 24 | 954224337 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.2624769551 | Oct 09 10:49:29 PM UTC 24 | Oct 09 10:49:33 PM UTC 24 | 715724060 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.858791431 | Oct 09 10:49:29 PM UTC 24 | Oct 09 10:49:33 PM UTC 24 | 609960694 ps | ||
| T51 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.1728814406 | Oct 09 10:49:31 PM UTC 24 | Oct 09 10:49:33 PM UTC 24 | 125766281 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_busy.352792758 | Oct 09 10:49:31 PM UTC 24 | Oct 09 10:49:33 PM UTC 24 | 432809609 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.133075098 | Oct 09 10:49:31 PM UTC 24 | Oct 09 10:49:34 PM UTC 24 | 697611443 ps | ||
| T52 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.4205326269 | Oct 09 10:49:39 PM UTC 24 | Oct 09 10:49:41 PM UTC 24 | 70242451 ps | ||
| T98 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.2276795775 | Oct 09 10:49:40 PM UTC 24 | Oct 09 10:49:43 PM UTC 24 | 295311278 ps | ||
| T99 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_halted.2768277110 | Oct 09 10:49:32 PM UTC 24 | Oct 09 10:49:34 PM UTC 24 | 223267025 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.2228440018 | Oct 09 10:49:32 PM UTC 24 | Oct 09 10:49:34 PM UTC 24 | 519312944 ps | ||
| T61 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_smoke.266046063 | Oct 09 10:49:31 PM UTC 24 | Oct 09 10:49:34 PM UTC 24 | 1892302874 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.2811599321 | Oct 09 10:49:29 PM UTC 24 | Oct 09 10:49:34 PM UTC 24 | 1589311207 ps | ||
| T100 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_hart_unavail.826818143 | Oct 09 10:49:32 PM UTC 24 | Oct 09 10:49:35 PM UTC 24 | 76906726 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_not_supported.187613528 | Oct 09 10:49:32 PM UTC 24 | Oct 09 10:49:35 PM UTC 24 | 860048634 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_dataaddr_rw_access.278291530 | Oct 09 10:49:32 PM UTC 24 | Oct 09 10:49:35 PM UTC 24 | 129556195 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_resuming.615197822 | Oct 09 10:49:32 PM UTC 24 | Oct 09 10:49:35 PM UTC 24 | 507009366 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_ndmreset_req.3186400943 | Oct 09 10:49:32 PM UTC 24 | Oct 09 10:49:35 PM UTC 24 | 345199557 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_tl_access.2957597346 | Oct 09 10:49:31 PM UTC 24 | Oct 09 10:49:35 PM UTC 24 | 2542214371 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_halt_resume_whereto.929828807 | Oct 09 10:49:32 PM UTC 24 | Oct 09 10:49:35 PM UTC 24 | 666662568 ps | ||
| T77 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.982426051 | Oct 09 10:49:32 PM UTC 24 | Oct 09 10:49:36 PM UTC 24 | 1747864777 ps | ||
| T201 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_idle_hint.885090140 | Oct 09 10:49:32 PM UTC 24 | Oct 09 10:49:36 PM UTC 24 | 314170114 ps | ||
| T88 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_tl_access.1289487643 | Oct 09 10:49:24 PM UTC 24 | Oct 09 10:49:36 PM UTC 24 | 6801445449 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_hard_reset.2275590547 | Oct 09 10:49:34 PM UTC 24 | Oct 09 10:49:36 PM UTC 24 | 198011351 ps | ||
| T185 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.4101299355 | Oct 09 10:49:34 PM UTC 24 | Oct 09 10:49:37 PM UTC 24 | 533622633 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.1930394100 | Oct 09 10:49:34 PM UTC 24 | Oct 09 10:49:37 PM UTC 24 | 123879535 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_rom_read_access.2922304141 | Oct 09 10:49:34 PM UTC 24 | Oct 09 10:49:37 PM UTC 24 | 57264631 ps | ||
| T242 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.3014572821 | Oct 09 10:49:34 PM UTC 24 | Oct 09 10:49:37 PM UTC 24 | 1551644968 ps | ||
| T72 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_abstractcmd_status.1767820901 | Oct 09 10:49:34 PM UTC 24 | Oct 09 10:49:37 PM UTC 24 | 127810364 ps | ||
| T97 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_debug_disabled.3341018402 | Oct 09 10:49:34 PM UTC 24 | Oct 09 10:49:37 PM UTC 24 | 47408862 ps | ||
| T87 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_buffered_enable.2539137558 | Oct 09 10:49:34 PM UTC 24 | Oct 09 10:49:37 PM UTC 24 | 88412600 ps | ||
| T70 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_progbuf_read_write_execute.133234138 | Oct 09 10:49:34 PM UTC 24 | Oct 09 10:49:37 PM UTC 24 | 409878608 ps | ||
| T89 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_bad_sba_tl_access.1511470870 | Oct 09 10:49:31 PM UTC 24 | Oct 09 10:49:37 PM UTC 24 | 3085082591 ps | ||
| T147 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_debug_disabled.803446943 | Oct 09 10:49:32 PM UTC 24 | Oct 09 10:49:38 PM UTC 24 | 1088761658 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_alert_test.1395544135 | Oct 09 10:49:35 PM UTC 24 | Oct 09 10:49:38 PM UTC 24 | 50914628 ps | ||
| T122 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_sba_tl_access.2974094497 | Oct 09 10:49:39 PM UTC 24 | Oct 09 10:49:43 PM UTC 24 | 940591687 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.4051267925 | Oct 09 10:49:35 PM UTC 24 | Oct 09 10:49:38 PM UTC 24 | 120291177 ps | ||
| T103 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.3115683373 | Oct 09 10:49:36 PM UTC 24 | Oct 09 10:49:38 PM UTC 24 | 82260856 ps | ||
| T95 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_sec_cm.3463226935 | Oct 09 10:49:35 PM UTC 24 | Oct 09 10:49:39 PM UTC 24 | 575948428 ps | ||
| T91 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.3251655814 | Oct 09 10:49:36 PM UTC 24 | Oct 09 10:49:39 PM UTC 24 | 264455302 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.518681226 | Oct 09 10:49:36 PM UTC 24 | Oct 09 10:49:39 PM UTC 24 | 667287538 ps | ||
| T86 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_sparse_lc_gate_fsm.3335750074 | Oct 09 10:49:37 PM UTC 24 | Oct 09 10:49:39 PM UTC 24 | 56053122 ps | ||
| T104 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.2598090611 | Oct 09 10:49:37 PM UTC 24 | Oct 09 10:49:39 PM UTC 24 | 106935640 ps | ||
| T105 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.1807534780 | Oct 09 10:49:36 PM UTC 24 | Oct 09 10:49:40 PM UTC 24 | 3068225213 ps | ||
| T96 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.966039906 | Oct 09 10:49:37 PM UTC 24 | Oct 09 10:49:40 PM UTC 24 | 572449270 ps | ||
| T73 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.2416860136 | Oct 09 10:49:38 PM UTC 24 | Oct 09 10:49:41 PM UTC 24 | 109407893 ps | ||
| T203 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_hart_unavail.1623490824 | Oct 09 10:49:38 PM UTC 24 | Oct 09 10:49:41 PM UTC 24 | 297148302 ps | ||
| T90 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.2060903518 | Oct 09 10:49:38 PM UTC 24 | Oct 09 10:49:41 PM UTC 24 | 273464945 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.3137009147 | Oct 09 10:49:38 PM UTC 24 | Oct 09 10:49:42 PM UTC 24 | 467429755 ps | ||
| T101 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_sec_cm.4119802628 | Oct 09 10:49:39 PM UTC 24 | Oct 09 10:49:42 PM UTC 24 | 1071131075 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.3058991066 | Oct 09 10:49:35 PM UTC 24 | Oct 09 10:49:42 PM UTC 24 | 3273456493 ps | ||
| T123 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.3024998929 | Oct 09 10:49:24 PM UTC 24 | Oct 09 10:49:42 PM UTC 24 | 7239247523 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.1428670808 | Oct 09 10:49:36 PM UTC 24 | Oct 09 10:49:42 PM UTC 24 | 6316415659 ps | ||
| T141 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.2844833052 | Oct 09 10:49:35 PM UTC 24 | Oct 09 10:49:42 PM UTC 24 | 2262891643 ps | ||
| T102 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_sec_cm.4123272355 | Oct 09 10:49:40 PM UTC 24 | Oct 09 10:49:45 PM UTC 24 | 2613148387 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.974895095 | Oct 09 10:49:31 PM UTC 24 | Oct 09 10:49:43 PM UTC 24 | 2447042991 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_autoincr_sba_tl_access.3910034659 | Oct 09 10:49:31 PM UTC 24 | Oct 09 10:49:43 PM UTC 24 | 3564453379 ps | ||
| T80 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.3076040457 | Oct 09 10:49:40 PM UTC 24 | Oct 09 10:49:43 PM UTC 24 | 393342341 ps | ||
| T125 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.1932564277 | Oct 09 10:49:37 PM UTC 24 | Oct 09 10:49:43 PM UTC 24 | 3121794653 ps | ||
| T126 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_alert_test.4184016783 | Oct 09 10:49:42 PM UTC 24 | Oct 09 10:49:44 PM UTC 24 | 136736467 ps | ||
| T127 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.1953480246 | Oct 09 10:49:31 PM UTC 24 | Oct 09 10:49:44 PM UTC 24 | 11941892663 ps | ||
| T128 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_buffered_enable.1739345121 | Oct 09 10:49:40 PM UTC 24 | Oct 09 10:49:44 PM UTC 24 | 407184002 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_halt_resume_whereto.3853292444 | Oct 09 10:49:43 PM UTC 24 | Oct 09 10:49:45 PM UTC 24 | 262366666 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.2028181341 | Oct 09 10:49:38 PM UTC 24 | Oct 09 10:49:46 PM UTC 24 | 2896795950 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all.3787575169 | Oct 09 10:49:37 PM UTC 24 | Oct 09 10:49:46 PM UTC 24 | 2877613119 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.3558059104 | Oct 09 10:49:43 PM UTC 24 | Oct 09 10:49:46 PM UTC 24 | 781801528 ps | ||
| T236 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_alert_test.1872128663 | Oct 09 10:49:44 PM UTC 24 | Oct 09 10:49:46 PM UTC 24 | 96958293 ps | ||
| T142 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_buffered_enable.933267112 | Oct 09 10:49:44 PM UTC 24 | Oct 09 10:49:46 PM UTC 24 | 163916082 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.328296032 | Oct 09 10:49:43 PM UTC 24 | Oct 09 10:49:47 PM UTC 24 | 1162665758 ps | ||
| T171 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_alert_test.4271133395 | Oct 09 10:49:45 PM UTC 24 | Oct 09 10:49:47 PM UTC 24 | 35699631 ps | ||
| T76 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_halt_resume_whereto.2385740206 | Oct 09 10:49:44 PM UTC 24 | Oct 09 10:49:47 PM UTC 24 | 292510585 ps | ||
| T143 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_buffered_enable.1407418704 | Oct 09 10:49:44 PM UTC 24 | Oct 09 10:49:47 PM UTC 24 | 185333287 ps | ||
| T241 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.3560470912 | Oct 09 10:49:43 PM UTC 24 | Oct 09 10:49:48 PM UTC 24 | 1877778550 ps | ||
| T234 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_autoincr_sba_tl_access.1455496663 | Oct 09 10:49:44 PM UTC 24 | Oct 09 10:49:48 PM UTC 24 | 5402128169 ps | ||
| T243 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.2297809037 | Oct 09 10:49:44 PM UTC 24 | Oct 09 10:49:48 PM UTC 24 | 1699515129 ps | ||
| T222 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.3920759738 | Oct 09 10:49:45 PM UTC 24 | Oct 09 10:49:48 PM UTC 24 | 941955536 ps | ||
| T244 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_sba_tl_access.4270476064 | Oct 09 10:49:45 PM UTC 24 | Oct 09 10:49:48 PM UTC 24 | 872351098 ps | ||
| T245 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_sba_tl_access.3217437432 | Oct 09 10:49:43 PM UTC 24 | Oct 09 10:49:48 PM UTC 24 | 1204644705 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all.1297341996 | Oct 09 10:49:45 PM UTC 24 | Oct 09 10:49:49 PM UTC 24 | 3279305201 ps | ||
| T172 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_alert_test.344525555 | Oct 09 10:49:47 PM UTC 24 | Oct 09 10:49:50 PM UTC 24 | 165827928 ps | ||
| T84 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_buffered_enable.3650037063 | Oct 09 10:49:47 PM UTC 24 | Oct 09 10:49:50 PM UTC 24 | 405642194 ps | ||
| T81 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.1165093819 | Oct 09 10:49:47 PM UTC 24 | Oct 09 10:49:50 PM UTC 24 | 703530772 ps | ||
| T246 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.4030767855 | Oct 09 10:49:37 PM UTC 24 | Oct 09 10:49:52 PM UTC 24 | 7587091812 ps | ||
| T227 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_alert_test.306838374 | Oct 09 10:49:50 PM UTC 24 | Oct 09 10:49:52 PM UTC 24 | 60822817 ps | ||
| T247 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.2147667488 | Oct 09 10:49:45 PM UTC 24 | Oct 09 10:49:52 PM UTC 24 | 1977900876 ps | ||
| T219 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_buffered_enable.718162032 | Oct 09 10:49:50 PM UTC 24 | Oct 09 10:49:52 PM UTC 24 | 279283379 ps | ||
| T248 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_autoincr_sba_tl_access.3400181348 | Oct 09 10:49:40 PM UTC 24 | Oct 09 10:49:53 PM UTC 24 | 6259710398 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.3144841231 | Oct 09 10:49:40 PM UTC 24 | Oct 09 10:49:53 PM UTC 24 | 7062953339 ps | ||
| T189 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_buffered_enable.4095402481 | Oct 09 10:49:50 PM UTC 24 | Oct 09 10:49:53 PM UTC 24 | 109853429 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.85028671 | Oct 09 10:50:14 PM UTC 24 | Oct 09 10:50:23 PM UTC 24 | 4702317526 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all.4149502343 | Oct 09 10:49:47 PM UTC 24 | Oct 09 10:49:54 PM UTC 24 | 3018821729 ps | ||
| T226 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_bad_sba_tl_access.3850722184 | Oct 09 10:49:44 PM UTC 24 | Oct 09 10:49:54 PM UTC 24 | 1409158553 ps | ||
| T78 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.4146398939 | Oct 09 10:49:50 PM UTC 24 | Oct 09 10:49:55 PM UTC 24 | 5134646290 ps | ||
| T233 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.3492860126 | Oct 09 10:49:47 PM UTC 24 | Oct 09 10:49:55 PM UTC 24 | 1356046920 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.2864024341 | Oct 09 10:49:44 PM UTC 24 | Oct 09 10:49:55 PM UTC 24 | 2830887194 ps | ||
| T249 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.4187997218 | Oct 09 10:49:52 PM UTC 24 | Oct 09 10:49:55 PM UTC 24 | 44932655 ps | ||
| T239 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.1352964050 | Oct 09 10:49:37 PM UTC 24 | Oct 09 10:49:55 PM UTC 24 | 5929793616 ps | ||
| T250 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_sba_tl_access.3290174511 | Oct 09 10:49:47 PM UTC 24 | Oct 09 10:49:55 PM UTC 24 | 1748832881 ps | ||
| T251 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3412023417 | Oct 09 10:49:39 PM UTC 24 | Oct 09 10:49:55 PM UTC 24 | 8154911780 ps | ||
| T220 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_bad_sba_tl_access.4143760077 | Oct 09 10:49:47 PM UTC 24 | Oct 09 10:49:56 PM UTC 24 | 8760165886 ps | ||
| T252 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.3162153153 | Oct 09 10:49:50 PM UTC 24 | Oct 09 10:49:58 PM UTC 24 | 1359763481 ps | ||
| T228 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/10.rv_dm_alert_test.309177830 | Oct 09 10:49:55 PM UTC 24 | Oct 09 10:49:58 PM UTC 24 | 157061424 ps | ||
| T224 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.150906194 | Oct 09 10:49:37 PM UTC 24 | Oct 09 10:49:59 PM UTC 24 | 6083957337 ps | ||
| T205 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/10.rv_dm_stress_all.3029410230 | Oct 09 10:49:55 PM UTC 24 | Oct 09 10:49:59 PM UTC 24 | 3221531017 ps | ||
| T230 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/16.rv_dm_alert_test.2486601193 | Oct 09 10:50:07 PM UTC 24 | Oct 09 10:50:09 PM UTC 24 | 69455120 ps | ||
| T253 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/16.rv_dm_sba_tl_access.1196997897 | Oct 09 10:50:05 PM UTC 24 | Oct 09 10:50:10 PM UTC 24 | 1204387230 ps | ||
| T254 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.3832958346 | Oct 09 10:49:52 PM UTC 24 | Oct 09 10:49:59 PM UTC 24 | 4367911450 ps | ||
| T229 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/11.rv_dm_alert_test.768817219 | Oct 09 10:49:57 PM UTC 24 | Oct 09 10:50:00 PM UTC 24 | 67772838 ps | ||
| T255 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.3130000370 | Oct 09 10:49:50 PM UTC 24 | Oct 09 10:50:00 PM UTC 24 | 9982176300 ps | ||
| T256 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/10.rv_dm_sba_tl_access.3636877225 | Oct 09 10:49:52 PM UTC 24 | Oct 09 10:50:00 PM UTC 24 | 1667618311 ps | ||
| T231 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/12.rv_dm_alert_test.3476480760 | Oct 09 10:49:58 PM UTC 24 | Oct 09 10:50:00 PM UTC 24 | 124586719 ps | ||
| T237 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3692971583 | Oct 09 10:49:45 PM UTC 24 | Oct 09 10:50:00 PM UTC 24 | 6074872362 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.3904216290 | Oct 09 10:49:50 PM UTC 24 | Oct 09 10:50:00 PM UTC 24 | 3037998862 ps | ||
| T221 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_autoincr_sba_tl_access.2272121445 | Oct 09 10:49:50 PM UTC 24 | Oct 09 10:50:01 PM UTC 24 | 10812918807 ps | ||
| T257 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/11.rv_dm_bad_sba_tl_access.3901704575 | Oct 09 10:49:55 PM UTC 24 | Oct 09 10:50:01 PM UTC 24 | 1617794641 ps | ||
| T225 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/13.rv_dm_sba_tl_access.1604937456 | Oct 09 10:49:58 PM UTC 24 | Oct 09 10:50:01 PM UTC 24 | 1329686528 ps | ||
| T200 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/12.rv_dm_sba_tl_access.1230666218 | Oct 09 10:49:57 PM UTC 24 | Oct 09 10:50:01 PM UTC 24 | 1523504458 ps | ||
| T204 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/12.rv_dm_bad_sba_tl_access.504987242 | Oct 09 10:49:57 PM UTC 24 | Oct 09 10:50:02 PM UTC 24 | 1164575715 ps | ||
| T232 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.1803826384 | Oct 09 10:49:50 PM UTC 24 | Oct 09 10:50:03 PM UTC 24 | 3070290366 ps | ||
| T223 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/6.rv_dm_sba_tl_access.733312762 | Oct 09 10:49:44 PM UTC 24 | Oct 09 10:50:03 PM UTC 24 | 9967537429 ps | ||
| T79 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/12.rv_dm_stress_all.2794121099 | Oct 09 10:49:57 PM UTC 24 | Oct 09 10:50:03 PM UTC 24 | 807440737 ps | ||
| T199 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.2757855592 | Oct 09 10:49:57 PM UTC 24 | Oct 09 10:50:05 PM UTC 24 | 5203510654 ps | ||
| T240 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/13.rv_dm_alert_test.889618954 | Oct 09 10:50:02 PM UTC 24 | Oct 09 10:50:05 PM UTC 24 | 52886806 ps | ||
| T235 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/14.rv_dm_alert_test.3607064781 | Oct 09 10:50:02 PM UTC 24 | Oct 09 10:50:05 PM UTC 24 | 53750918 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.2699549530 | Oct 09 10:49:37 PM UTC 24 | Oct 09 10:50:05 PM UTC 24 | 6208729582 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/13.rv_dm_stress_all.1467645965 | Oct 09 10:50:00 PM UTC 24 | Oct 09 10:50:06 PM UTC 24 | 2433484657 ps | ||
| T177 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_bad_sba_tl_access.307467123 | Oct 09 10:49:40 PM UTC 24 | Oct 09 10:50:06 PM UTC 24 | 6480646188 ps | ||
| T178 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/14.rv_dm_autoincr_sba_tl_access.1287467000 | Oct 09 10:50:02 PM UTC 24 | Oct 09 10:50:07 PM UTC 24 | 1512095478 ps | ||
| T179 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/10.rv_dm_bad_sba_tl_access.113578460 | Oct 09 10:49:55 PM UTC 24 | Oct 09 10:50:07 PM UTC 24 | 2353590328 ps | ||
| T180 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/15.rv_dm_alert_test.969452034 | Oct 09 10:50:05 PM UTC 24 | Oct 09 10:50:07 PM UTC 24 | 82236448 ps | ||
| T181 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.3703888890 | Oct 09 10:50:00 PM UTC 24 | Oct 09 10:50:08 PM UTC 24 | 4180953114 ps | ||
| T182 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.3672548867 | Oct 09 10:50:02 PM UTC 24 | Oct 09 10:50:08 PM UTC 24 | 4166782215 ps | ||
| T183 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/14.rv_dm_sba_tl_access.1738655905 | Oct 09 10:50:02 PM UTC 24 | Oct 09 10:50:09 PM UTC 24 | 4991207243 ps | ||
| T184 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.2749529184 | Oct 09 10:49:36 PM UTC 24 | Oct 09 10:50:09 PM UTC 24 | 10092739196 ps | ||
| T238 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/13.rv_dm_bad_sba_tl_access.2895628364 | Oct 09 10:50:00 PM UTC 24 | Oct 09 10:50:09 PM UTC 24 | 8948982008 ps | ||
| T258 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.4045050041 | Oct 09 10:49:55 PM UTC 24 | Oct 09 10:50:10 PM UTC 24 | 5548418167 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/14.rv_dm_stress_all.3782237788 | Oct 09 10:50:02 PM UTC 24 | Oct 09 10:50:11 PM UTC 24 | 1835385390 ps | ||
| T188 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/15.rv_dm_bad_sba_tl_access.1623105532 | Oct 09 10:50:03 PM UTC 24 | Oct 09 10:50:11 PM UTC 24 | 3790687316 ps | ||
| T196 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.178733577 | Oct 09 10:50:07 PM UTC 24 | Oct 09 10:50:12 PM UTC 24 | 1724938832 ps | ||
| T259 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/17.rv_dm_alert_test.2805250790 | Oct 09 10:50:10 PM UTC 24 | Oct 09 10:50:12 PM UTC 24 | 35803040 ps | ||
| T194 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/16.rv_dm_stress_all.3505421335 | Oct 09 10:50:07 PM UTC 24 | Oct 09 10:50:13 PM UTC 24 | 888889985 ps | ||
| T260 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/17.rv_dm_sba_tl_access.4143561040 | Oct 09 10:50:07 PM UTC 24 | Oct 09 10:50:13 PM UTC 24 | 1917962463 ps | ||
| T261 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/18.rv_dm_alert_test.486973866 | Oct 09 10:50:12 PM UTC 24 | Oct 09 10:50:14 PM UTC 24 | 31606376 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.2264319204 | Oct 09 10:49:38 PM UTC 24 | Oct 09 10:50:14 PM UTC 24 | 2253642284 ps | ||
| T262 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/11.rv_dm_sba_tl_access.534357688 | Oct 09 10:49:55 PM UTC 24 | Oct 09 10:50:14 PM UTC 24 | 6830257392 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/11.rv_dm_stress_all.1944067238 | Oct 09 10:49:55 PM UTC 24 | Oct 09 10:50:15 PM UTC 24 | 4246618354 ps | ||
| T263 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/10.rv_dm_autoincr_sba_tl_access.3955886098 | Oct 09 10:49:55 PM UTC 24 | Oct 09 10:50:15 PM UTC 24 | 6395818198 ps | ||
| T264 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/14.rv_dm_bad_sba_tl_access.1836546259 | Oct 09 10:50:02 PM UTC 24 | Oct 09 10:50:15 PM UTC 24 | 3156277970 ps | ||
| T197 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/11.rv_dm_autoincr_sba_tl_access.3929064234 | Oct 09 10:49:55 PM UTC 24 | Oct 09 10:50:16 PM UTC 24 | 5235229133 ps | ||
| T265 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/18.rv_dm_bad_sba_tl_access.2425290055 | Oct 09 10:50:10 PM UTC 24 | Oct 09 10:50:16 PM UTC 24 | 5755080772 ps | ||
| T266 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/18.rv_dm_stress_all.2161115303 | Oct 09 10:50:12 PM UTC 24 | Oct 09 10:50:16 PM UTC 24 | 1372956668 ps | ||
| T267 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/19.rv_dm_alert_test.771612515 | Oct 09 10:50:15 PM UTC 24 | Oct 09 10:50:17 PM UTC 24 | 82714804 ps | ||
| T268 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2237468185 | Oct 09 10:50:03 PM UTC 24 | Oct 09 10:50:17 PM UTC 24 | 2633218018 ps | ||
| T269 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.4255794942 | Oct 09 10:49:50 PM UTC 24 | Oct 09 10:50:17 PM UTC 24 | 7479498891 ps | ||
| T270 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/19.rv_dm_sba_tl_access.2163014714 | Oct 09 10:50:12 PM UTC 24 | Oct 09 10:50:17 PM UTC 24 | 2179814821 ps | ||
| T82 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/15.rv_dm_stress_all.3665495201 | Oct 09 10:50:05 PM UTC 24 | Oct 09 10:50:17 PM UTC 24 | 2331420217 ps | ||
| T271 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/21.rv_dm_alert_test.1235712816 | Oct 09 10:50:17 PM UTC 24 | Oct 09 10:50:19 PM UTC 24 | 65497070 ps | ||
| T272 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/20.rv_dm_alert_test.3132786082 | Oct 09 10:50:17 PM UTC 24 | Oct 09 10:50:19 PM UTC 24 | 52993639 ps | ||
| T273 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/23.rv_dm_alert_test.1502326218 | Oct 09 10:50:17 PM UTC 24 | Oct 09 10:50:19 PM UTC 24 | 99303373 ps | ||
| T274 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/24.rv_dm_alert_test.3862175082 | Oct 09 10:50:17 PM UTC 24 | Oct 09 10:50:19 PM UTC 24 | 44227778 ps | ||
| T275 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/22.rv_dm_alert_test.309817671 | Oct 09 10:50:17 PM UTC 24 | Oct 09 10:50:19 PM UTC 24 | 47064952 ps | ||
| T276 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.748275767 | Oct 09 10:50:12 PM UTC 24 | Oct 09 10:50:20 PM UTC 24 | 1558996378 ps | ||
| T277 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/13.rv_dm_autoincr_sba_tl_access.2160367890 | Oct 09 10:50:00 PM UTC 24 | Oct 09 10:50:20 PM UTC 24 | 18539948370 ps | ||
| T119 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.692005783 | Oct 09 10:49:40 PM UTC 24 | Oct 09 10:50:20 PM UTC 24 | 2559397916 ps | ||
| T202 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/18.rv_dm_sba_tl_access.1758657506 | Oct 09 10:50:10 PM UTC 24 | Oct 09 10:50:21 PM UTC 24 | 2699673248 ps | ||
| T278 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/17.rv_dm_bad_sba_tl_access.4073092553 | Oct 09 10:50:07 PM UTC 24 | Oct 09 10:50:21 PM UTC 24 | 5343633540 ps | ||
| T279 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/25.rv_dm_alert_test.497941705 | Oct 09 10:50:19 PM UTC 24 | Oct 09 10:50:22 PM UTC 24 | 52284435 ps | ||
| T280 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/26.rv_dm_alert_test.314870552 | Oct 09 10:50:19 PM UTC 24 | Oct 09 10:50:22 PM UTC 24 | 45942851 ps | ||
| T281 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/27.rv_dm_alert_test.2548037490 | Oct 09 10:50:20 PM UTC 24 | Oct 09 10:50:22 PM UTC 24 | 60253058 ps | ||
| T282 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.3658075510 | Oct 09 10:50:05 PM UTC 24 | Oct 09 10:50:23 PM UTC 24 | 4713314602 ps | ||
| T93 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/17.rv_dm_stress_all.899501675 | Oct 09 10:50:10 PM UTC 24 | Oct 09 10:50:23 PM UTC 24 | 2902870123 ps | ||
| T283 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/30.rv_dm_alert_test.2909113240 | Oct 09 10:50:22 PM UTC 24 | Oct 09 10:50:24 PM UTC 24 | 99337942 ps | ||
| T284 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/29.rv_dm_alert_test.3152816035 | Oct 09 10:50:22 PM UTC 24 | Oct 09 10:50:24 PM UTC 24 | 89195111 ps | ||
| T285 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/28.rv_dm_alert_test.2762066220 | Oct 09 10:50:22 PM UTC 24 | Oct 09 10:50:24 PM UTC 24 | 54161182 ps | ||
| T193 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.1442563592 | Oct 09 10:50:17 PM UTC 24 | Oct 09 10:50:24 PM UTC 24 | 5399053263 ps | ||
| T286 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/15.rv_dm_autoincr_sba_tl_access.2903234474 | Oct 09 10:50:03 PM UTC 24 | Oct 09 10:50:25 PM UTC 24 | 13145293534 ps | ||
| T287 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/31.rv_dm_alert_test.3835440453 | Oct 09 10:50:23 PM UTC 24 | Oct 09 10:50:26 PM UTC 24 | 90616664 ps | ||
| T288 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/32.rv_dm_alert_test.1980703654 | Oct 09 10:50:23 PM UTC 24 | Oct 09 10:50:26 PM UTC 24 | 115219811 ps | ||
| T191 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/21.rv_dm_stress_all.1445873403 | Oct 09 10:50:17 PM UTC 24 | Oct 09 10:50:26 PM UTC 24 | 4191587999 ps | ||
| T289 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/33.rv_dm_alert_test.1609564863 | Oct 09 10:50:23 PM UTC 24 | Oct 09 10:50:26 PM UTC 24 | 66030726 ps | ||
| T290 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/15.rv_dm_sba_tl_access.770881744 | Oct 09 10:50:02 PM UTC 24 | Oct 09 10:50:26 PM UTC 24 | 7198114398 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.141661652 | Oct 09 10:50:17 PM UTC 24 | Oct 09 10:50:27 PM UTC 24 | 1564827846 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.2552596974 | Oct 09 10:50:23 PM UTC 24 | Oct 09 10:50:27 PM UTC 24 | 2809523256 ps | ||
| T190 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/26.rv_dm_stress_all.4178216192 | Oct 09 10:50:19 PM UTC 24 | Oct 09 10:50:27 PM UTC 24 | 6896777169 ps | ||
| T291 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/34.rv_dm_alert_test.3808796897 | Oct 09 10:50:26 PM UTC 24 | Oct 09 10:50:28 PM UTC 24 | 32779613 ps | ||
| T195 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/32.rv_dm_stress_all.3292457660 | Oct 09 10:50:23 PM UTC 24 | Oct 09 10:50:28 PM UTC 24 | 2912143839 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/23.rv_dm_stress_all.4234828298 | Oct 09 10:50:17 PM UTC 24 | Oct 09 10:50:28 PM UTC 24 | 2514667235 ps | ||
| T292 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/35.rv_dm_alert_test.2044322304 | Oct 09 10:50:26 PM UTC 24 | Oct 09 10:50:28 PM UTC 24 | 84698072 ps | ||
| T293 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/36.rv_dm_alert_test.774106615 | Oct 09 10:50:26 PM UTC 24 | Oct 09 10:50:28 PM UTC 24 | 58225103 ps | ||
| T294 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/37.rv_dm_alert_test.4111115435 | Oct 09 10:50:26 PM UTC 24 | Oct 09 10:50:29 PM UTC 24 | 134151513 ps | ||
| T295 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.3928526195 | Oct 09 10:50:20 PM UTC 24 | Oct 09 10:50:29 PM UTC 24 | 8163911950 ps | ||
| T296 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/29.rv_dm_stress_all.910601288 | Oct 09 10:50:22 PM UTC 24 | Oct 09 10:50:30 PM UTC 24 | 1968512016 ps | ||
| T297 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/39.rv_dm_stress_all.1364599088 | Oct 09 10:50:28 PM UTC 24 | Oct 09 10:50:34 PM UTC 24 | 5081564697 ps | ||
| T298 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/38.rv_dm_alert_test.4155099391 | Oct 09 10:50:28 PM UTC 24 | Oct 09 10:50:30 PM UTC 24 | 154002132 ps | ||
| T299 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/28.rv_dm_stress_all.3707606707 | Oct 09 10:50:21 PM UTC 24 | Oct 09 10:50:31 PM UTC 24 | 4306365215 ps | ||
| T300 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/39.rv_dm_alert_test.2911506233 | Oct 09 10:50:28 PM UTC 24 | Oct 09 10:50:31 PM UTC 24 | 63049298 ps | ||
| T301 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/41.rv_dm_alert_test.2238663252 | Oct 09 10:50:28 PM UTC 24 | Oct 09 10:50:31 PM UTC 24 | 70179377 ps | ||
| T302 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/40.rv_dm_alert_test.1835844519 | Oct 09 10:50:28 PM UTC 24 | Oct 09 10:50:31 PM UTC 24 | 68005337 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.3633084171 | Oct 09 10:50:15 PM UTC 24 | Oct 09 10:50:31 PM UTC 24 | 3789496668 ps | ||
| T198 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/35.rv_dm_stress_all.381155734 | Oct 09 10:50:26 PM UTC 24 | Oct 09 10:50:31 PM UTC 24 | 2619150943 ps | ||
| T303 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/38.rv_dm_stress_all.2229800547 | Oct 09 10:50:26 PM UTC 24 | Oct 09 10:50:31 PM UTC 24 | 1547559654 ps | ||
| T304 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/42.rv_dm_alert_test.3812014707 | Oct 09 10:50:29 PM UTC 24 | Oct 09 10:50:31 PM UTC 24 | 73205436 ps | ||
| T305 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/17.rv_dm_autoincr_sba_tl_access.1090999011 | Oct 09 10:50:10 PM UTC 24 | Oct 09 10:50:32 PM UTC 24 | 5925271304 ps | ||
| T192 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/34.rv_dm_stress_all.1557800334 | Oct 09 10:50:23 PM UTC 24 | Oct 09 10:50:32 PM UTC 24 | 1962896277 ps | ||
| T306 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/42.rv_dm_stress_all.3111124273 | Oct 09 10:50:29 PM UTC 24 | Oct 09 10:50:33 PM UTC 24 | 1296923624 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.3513322056 | Oct 09 10:50:22 PM UTC 24 | Oct 09 10:50:33 PM UTC 24 | 1735704612 ps | ||
| T307 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/43.rv_dm_alert_test.221162838 | Oct 09 10:50:31 PM UTC 24 | Oct 09 10:50:33 PM UTC 24 | 32012173 ps | ||
| T308 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/44.rv_dm_alert_test.840282494 | Oct 09 10:50:31 PM UTC 24 | Oct 09 10:50:33 PM UTC 24 | 44629285 ps | ||
| T309 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/24.rv_dm_stress_all.2174680518 | Oct 09 10:50:17 PM UTC 24 | Oct 09 10:50:33 PM UTC 24 | 4562264801 ps | ||
| T310 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.2115379561 | Oct 09 10:50:10 PM UTC 24 | Oct 09 10:50:33 PM UTC 24 | 8764401426 ps | ||
| T311 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/46.rv_dm_alert_test.1714831254 | Oct 09 10:50:31 PM UTC 24 | Oct 09 10:50:33 PM UTC 24 | 44994310 ps | ||
| T312 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/41.rv_dm_stress_all.850144963 | Oct 09 10:50:28 PM UTC 24 | Oct 09 10:50:33 PM UTC 24 | 2073065198 ps | ||
| T313 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/45.rv_dm_alert_test.14720154 | Oct 09 10:50:31 PM UTC 24 | Oct 09 10:50:33 PM UTC 24 | 172363401 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/40.rv_dm_stress_all.1552654556 | Oct 09 10:50:28 PM UTC 24 | Oct 09 10:50:34 PM UTC 24 | 809628089 ps | ||
| T314 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.27614277 | Oct 09 10:50:31 PM UTC 24 | Oct 09 10:50:36 PM UTC 24 | 3616278680 ps | ||
| T94 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/43.rv_dm_stress_all.4069899595 | Oct 09 10:50:31 PM UTC 24 | Oct 09 10:50:35 PM UTC 24 | 2275076064 ps | ||
| T315 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/47.rv_dm_alert_test.4225737938 | Oct 09 10:50:33 PM UTC 24 | Oct 09 10:50:35 PM UTC 24 | 30746695 ps | ||
| T316 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/49.rv_dm_alert_test.635316253 | Oct 09 10:50:34 PM UTC 24 | Oct 09 10:50:36 PM UTC 24 | 148506145 ps | ||
| T317 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/48.rv_dm_alert_test.4076323643 | Oct 09 10:50:33 PM UTC 24 | Oct 09 10:50:36 PM UTC 24 | 65808308 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.2971450600 | Oct 09 10:49:50 PM UTC 24 | Oct 09 10:50:37 PM UTC 24 | 15466572666 ps | ||
| T318 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/36.rv_dm_stress_all.2446551592 | Oct 09 10:50:26 PM UTC 24 | Oct 09 10:50:38 PM UTC 24 | 9240401999 ps | ||
| T319 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/49.rv_dm_stress_all.1083740387 | Oct 09 10:50:33 PM UTC 24 | Oct 09 10:50:38 PM UTC 24 | 708226926 ps | ||
| T320 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/16.rv_dm_bad_sba_tl_access.2225203859 | Oct 09 10:50:07 PM UTC 24 | Oct 09 10:50:39 PM UTC 24 | 10719720109 ps | ||
| T321 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/19.rv_dm_bad_sba_tl_access.481378552 | Oct 09 10:50:12 PM UTC 24 | Oct 09 10:50:39 PM UTC 24 | 15469985862 ps | ||
| T139 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/48.rv_dm_stress_all.2968425482 | Oct 09 10:50:33 PM UTC 24 | Oct 09 10:50:40 PM UTC 24 | 5668545946 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.3688963634 | Oct 09 10:50:31 PM UTC 24 | Oct 09 10:50:40 PM UTC 24 | 1375576748 ps | ||
| T186 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/47.rv_dm_stress_all.489266857 | Oct 09 10:50:33 PM UTC 24 | Oct 09 10:50:42 PM UTC 24 | 2228292693 ps | ||
| T187 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/45.rv_dm_stress_all.3194403923 | Oct 09 10:50:31 PM UTC 24 | Oct 09 10:50:45 PM UTC 24 | 7255539768 ps | ||
| T322 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/coverage/default/18.rv_dm_autoincr_sba_tl_access.1346772155 | Oct 09 10:50:12 PM UTC 24 | Oct 09 10:50:45 PM UTC 24 | 17943173888 ps |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |