| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 89.11 | 96.64 | 90.24 | 92.10 | 93.33 | 90.44 | 98.22 | 62.76 |
| T323 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/49.rv_dm_stress_all.2151807742 | Oct 12 12:50:27 AM UTC 24 | Oct 12 12:50:38 AM UTC 24 | 4565284437 ps | ||
| T109 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all_with_rand_reset.314540500 | Oct 12 12:49:33 AM UTC 24 | Oct 12 12:50:39 AM UTC 24 | 14379297378 ps | ||
| T324 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/10.rv_dm_autoincr_sba_tl_access.3866969997 | Oct 12 12:49:45 AM UTC 24 | Oct 12 12:50:39 AM UTC 24 | 15888821289 ps | ||
| T114 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.1056208096 | Oct 12 12:49:37 AM UTC 24 | Oct 12 12:50:41 AM UTC 24 | 8288545235 ps | ||
| T94 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.2697693824 | Oct 12 12:50:19 AM UTC 24 | Oct 12 12:50:41 AM UTC 24 | 6495979318 ps | ||
| T181 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.3417579787 | Oct 12 12:50:08 AM UTC 24 | Oct 12 12:50:44 AM UTC 24 | 21541101839 ps | ||
| T325 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/19.rv_dm_bad_sba_tl_access.740924073 | Oct 12 12:50:08 AM UTC 24 | Oct 12 12:50:44 AM UTC 24 | 7510214323 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.4093853573 | Oct 12 12:49:30 AM UTC 24 | Oct 12 12:50:48 AM UTC 24 | 5375246991 ps | ||
| T326 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.293422950 | Oct 12 12:49:36 AM UTC 24 | Oct 12 12:50:50 AM UTC 24 | 45689628562 ps | ||
| T327 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/11.rv_dm_autoincr_sba_tl_access.2751116444 | Oct 12 12:49:49 AM UTC 24 | Oct 12 12:50:53 AM UTC 24 | 40712251059 ps | ||
| T328 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/14.rv_dm_autoincr_sba_tl_access.172553003 | Oct 12 12:49:54 AM UTC 24 | Oct 12 12:51:12 AM UTC 24 | 31157787294 ps | ||
| T329 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.2583059737 | Oct 12 12:49:20 AM UTC 24 | Oct 12 12:51:35 AM UTC 24 | 39860572085 ps | ||
| T106 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1294682746 | Oct 12 12:46:51 AM UTC 24 | Oct 12 12:46:54 AM UTC 24 | 367493577 ps | ||
| T107 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1926579332 | Oct 12 12:46:51 AM UTC 24 | Oct 12 12:46:55 AM UTC 24 | 776033439 ps | ||
| T330 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.4226962838 | Oct 12 12:46:53 AM UTC 24 | Oct 12 12:46:57 AM UTC 24 | 53284669 ps | ||
| T331 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1321249141 | Oct 12 12:46:52 AM UTC 24 | Oct 12 12:46:58 AM UTC 24 | 1505876265 ps | ||
| T332 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.560393507 | Oct 12 12:46:56 AM UTC 24 | Oct 12 12:46:58 AM UTC 24 | 97291290 ps | ||
| T333 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.612168065 | Oct 12 12:46:56 AM UTC 24 | Oct 12 12:46:58 AM UTC 24 | 148828128 ps | ||
| T144 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2271768571 | Oct 12 12:46:51 AM UTC 24 | Oct 12 12:46:59 AM UTC 24 | 9185015145 ps | ||
| T108 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2266455452 | Oct 12 12:46:51 AM UTC 24 | Oct 12 12:47:00 AM UTC 24 | 1202374613 ps | ||
| T130 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.689661140 | Oct 12 12:46:57 AM UTC 24 | Oct 12 12:47:02 AM UTC 24 | 127805205 ps | ||
| T334 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1630691653 | Oct 12 12:47:00 AM UTC 24 | Oct 12 12:47:03 AM UTC 24 | 224909403 ps | ||
| T131 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.4168944291 | Oct 12 12:46:57 AM UTC 24 | Oct 12 12:47:05 AM UTC 24 | 527462009 ps | ||
| T335 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.22116723 | Oct 12 12:46:59 AM UTC 24 | Oct 12 12:47:05 AM UTC 24 | 156661690 ps | ||
| T336 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1757555430 | Oct 12 12:47:03 AM UTC 24 | Oct 12 12:47:06 AM UTC 24 | 294515807 ps | ||
| T337 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1914715005 | Oct 12 12:47:04 AM UTC 24 | Oct 12 12:47:06 AM UTC 24 | 397272774 ps | ||
| T132 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1310143710 | Oct 12 12:46:59 AM UTC 24 | Oct 12 12:47:08 AM UTC 24 | 372193935 ps | ||
| T338 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.2391075897 | Oct 12 12:47:08 AM UTC 24 | Oct 12 12:47:10 AM UTC 24 | 74250351 ps | ||
| T174 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.3598744186 | Oct 12 12:47:07 AM UTC 24 | Oct 12 12:47:11 AM UTC 24 | 804167358 ps | ||
| T339 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.642622004 | Oct 12 12:47:09 AM UTC 24 | Oct 12 12:47:11 AM UTC 24 | 112422581 ps | ||
| T133 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3033010451 | Oct 12 12:47:09 AM UTC 24 | Oct 12 12:47:13 AM UTC 24 | 139185927 ps | ||
| T172 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2314009753 | Oct 12 12:46:55 AM UTC 24 | Oct 12 12:47:13 AM UTC 24 | 5522067904 ps | ||
| T340 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3776734305 | Oct 12 12:47:06 AM UTC 24 | Oct 12 12:47:15 AM UTC 24 | 3915362656 ps | ||
| T134 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.3499403434 | Oct 12 12:47:11 AM UTC 24 | Oct 12 12:47:15 AM UTC 24 | 54262700 ps | ||
| T341 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1664329897 | Oct 12 12:47:14 AM UTC 24 | Oct 12 12:47:16 AM UTC 24 | 845329939 ps | ||
| T342 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3548187414 | Oct 12 12:47:14 AM UTC 24 | Oct 12 12:47:17 AM UTC 24 | 800593550 ps | ||
| T117 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.840361784 | Oct 12 12:47:13 AM UTC 24 | Oct 12 12:47:17 AM UTC 24 | 161981348 ps | ||
| T343 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2140318074 | Oct 12 12:47:16 AM UTC 24 | Oct 12 12:47:19 AM UTC 24 | 278797157 ps | ||
| T135 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.4289124952 | Oct 12 12:47:13 AM UTC 24 | Oct 12 12:47:21 AM UTC 24 | 372546547 ps | ||
| T344 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2666371584 | Oct 12 12:46:51 AM UTC 24 | Oct 12 12:47:21 AM UTC 24 | 5878302065 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3136128553 | Oct 12 12:47:07 AM UTC 24 | Oct 12 12:47:22 AM UTC 24 | 801945280 ps | ||
| T345 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1392966664 | Oct 12 12:47:18 AM UTC 24 | Oct 12 12:47:22 AM UTC 24 | 1440545727 ps | ||
| T145 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1430766635 | Oct 12 12:47:05 AM UTC 24 | Oct 12 12:47:23 AM UTC 24 | 16583957226 ps | ||
| T146 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1360733352 | Oct 12 12:47:17 AM UTC 24 | Oct 12 12:47:23 AM UTC 24 | 2351372915 ps | ||
| T346 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_walk.1616155865 | Oct 12 12:47:23 AM UTC 24 | Oct 12 12:47:25 AM UTC 24 | 33801595 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_errors.2896763161 | Oct 12 12:47:21 AM UTC 24 | Oct 12 12:47:26 AM UTC 24 | 221540505 ps | ||
| T347 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_partial_access.643822123 | Oct 12 12:47:24 AM UTC 24 | Oct 12 12:47:26 AM UTC 24 | 95316149 ps | ||
| T136 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3411577005 | Oct 12 12:47:24 AM UTC 24 | Oct 12 12:47:28 AM UTC 24 | 453645905 ps | ||
| T137 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_rw.3281732804 | Oct 12 12:47:26 AM UTC 24 | Oct 12 12:47:29 AM UTC 24 | 266122414 ps | ||
| T348 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1800042136 | Oct 12 12:47:04 AM UTC 24 | Oct 12 12:47:31 AM UTC 24 | 20110971167 ps | ||
| T349 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2304659291 | Oct 12 12:47:29 AM UTC 24 | Oct 12 12:47:31 AM UTC 24 | 224631952 ps | ||
| T350 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2916218767 | Oct 12 12:47:29 AM UTC 24 | Oct 12 12:47:32 AM UTC 24 | 331933028 ps | ||
| T118 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3334680941 | Oct 12 12:47:27 AM UTC 24 | Oct 12 12:47:33 AM UTC 24 | 60834042 ps | ||
| T351 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.342916919 | Oct 12 12:46:52 AM UTC 24 | Oct 12 12:47:35 AM UTC 24 | 23562598636 ps | ||
| T138 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2936375486 | Oct 12 12:47:27 AM UTC 24 | Oct 12 12:47:35 AM UTC 24 | 171074479 ps | ||
| T139 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1081379879 | Oct 12 12:47:00 AM UTC 24 | Oct 12 12:47:36 AM UTC 24 | 29831854658 ps | ||
| T215 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3773146015 | Oct 12 12:47:22 AM UTC 24 | Oct 12 12:47:38 AM UTC 24 | 2133282210 ps | ||
| T352 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1011315141 | Oct 12 12:47:37 AM UTC 24 | Oct 12 12:47:40 AM UTC 24 | 1116382375 ps | ||
| T353 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_walk.3678128933 | Oct 12 12:47:38 AM UTC 24 | Oct 12 12:47:40 AM UTC 24 | 160551712 ps | ||
| T354 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3360031050 | Oct 12 12:47:39 AM UTC 24 | Oct 12 12:47:41 AM UTC 24 | 140878526 ps | ||
| T148 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2302679901 | Oct 12 12:47:39 AM UTC 24 | Oct 12 12:47:43 AM UTC 24 | 1111943192 ps | ||
| T355 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_errors.4118823022 | Oct 12 12:47:38 AM UTC 24 | Oct 12 12:47:43 AM UTC 24 | 90353573 ps | ||
| T356 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_rw.1040101570 | Oct 12 12:47:40 AM UTC 24 | Oct 12 12:47:44 AM UTC 24 | 103567001 ps | ||
| T357 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1289683762 | Oct 12 12:46:51 AM UTC 24 | Oct 12 12:47:44 AM UTC 24 | 17276770473 ps | ||
| T358 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.237568655 | Oct 12 12:47:38 AM UTC 24 | Oct 12 12:47:44 AM UTC 24 | 783610881 ps | ||
| T359 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2131987569 | Oct 12 12:47:37 AM UTC 24 | Oct 12 12:47:45 AM UTC 24 | 4138895754 ps | ||
| T149 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.394747105 | Oct 12 12:46:59 AM UTC 24 | Oct 12 12:47:46 AM UTC 24 | 5121283677 ps | ||
| T360 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2539634441 | Oct 12 12:47:06 AM UTC 24 | Oct 12 12:47:46 AM UTC 24 | 16050592564 ps | ||
| T361 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.807048977 | Oct 12 12:47:37 AM UTC 24 | Oct 12 12:47:48 AM UTC 24 | 14484532768 ps | ||
| T362 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3070509277 | Oct 12 12:47:16 AM UTC 24 | Oct 12 12:47:50 AM UTC 24 | 8128727621 ps | ||
| T363 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.691436721 | Oct 12 12:47:49 AM UTC 24 | Oct 12 12:47:51 AM UTC 24 | 143567604 ps | ||
| T364 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2890963109 | Oct 12 12:47:49 AM UTC 24 | Oct 12 12:47:53 AM UTC 24 | 255412751 ps | ||
| T213 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2795342171 | Oct 12 12:47:38 AM UTC 24 | Oct 12 12:47:53 AM UTC 24 | 3661266307 ps | ||
| T365 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3021429852 | Oct 12 12:47:49 AM UTC 24 | Oct 12 12:47:53 AM UTC 24 | 169495409 ps | ||
| T366 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.725662681 | Oct 12 12:47:18 AM UTC 24 | Oct 12 12:47:55 AM UTC 24 | 22257826755 ps | ||
| T367 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3728287986 | Oct 12 12:47:54 AM UTC 24 | Oct 12 12:47:56 AM UTC 24 | 76174854 ps | ||
| T368 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_walk.2135783457 | Oct 12 12:47:54 AM UTC 24 | Oct 12 12:47:56 AM UTC 24 | 59354130 ps | ||
| T369 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1095369472 | Oct 12 12:46:52 AM UTC 24 | Oct 12 12:47:56 AM UTC 24 | 2078930099 ps | ||
| T162 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2092850686 | Oct 12 12:47:49 AM UTC 24 | Oct 12 12:47:56 AM UTC 24 | 522107303 ps | ||
| T150 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3308371360 | Oct 12 12:47:56 AM UTC 24 | Oct 12 12:47:59 AM UTC 24 | 246322361 ps | ||
| T151 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_rw.3580855917 | Oct 12 12:47:57 AM UTC 24 | Oct 12 12:48:00 AM UTC 24 | 39630173 ps | ||
| T370 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.4016394772 | Oct 12 12:47:49 AM UTC 24 | Oct 12 12:48:00 AM UTC 24 | 1441627540 ps | ||
| T157 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1236231432 | Oct 12 12:47:27 AM UTC 24 | Oct 12 12:48:01 AM UTC 24 | 892627216 ps | ||
| T371 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3062092397 | Oct 12 12:47:58 AM UTC 24 | Oct 12 12:48:01 AM UTC 24 | 193270168 ps | ||
| T372 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_errors.628659125 | Oct 12 12:47:52 AM UTC 24 | Oct 12 12:48:02 AM UTC 24 | 3360463243 ps | ||
| T373 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1958678409 | Oct 12 12:47:57 AM UTC 24 | Oct 12 12:48:02 AM UTC 24 | 40919996 ps | ||
| T374 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.30285940 | Oct 12 12:48:00 AM UTC 24 | Oct 12 12:48:05 AM UTC 24 | 1057924269 ps | ||
| T159 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_rw.1358709246 | Oct 12 12:48:02 AM UTC 24 | Oct 12 12:48:05 AM UTC 24 | 136463104 ps | ||
| T163 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2277787462 | Oct 12 12:47:57 AM UTC 24 | Oct 12 12:48:06 AM UTC 24 | 3630117128 ps | ||
| T176 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.719328435 | Oct 12 12:48:03 AM UTC 24 | Oct 12 12:48:07 AM UTC 24 | 100556744 ps | ||
| T375 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.831773483 | Oct 12 12:48:05 AM UTC 24 | Oct 12 12:48:07 AM UTC 24 | 158990649 ps | ||
| T376 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_errors.2100428244 | Oct 12 12:48:02 AM UTC 24 | Oct 12 12:48:07 AM UTC 24 | 108922927 ps | ||
| T377 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3577065382 | Oct 12 12:47:49 AM UTC 24 | Oct 12 12:48:10 AM UTC 24 | 5139778091 ps | ||
| T378 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2340286461 | Oct 12 12:47:49 AM UTC 24 | Oct 12 12:48:11 AM UTC 24 | 6408787615 ps | ||
| T379 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2589922267 | Oct 12 12:48:06 AM UTC 24 | Oct 12 12:48:12 AM UTC 24 | 2466118804 ps | ||
| T147 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1635080816 | Oct 12 12:47:49 AM UTC 24 | Oct 12 12:48:13 AM UTC 24 | 3504085661 ps | ||
| T380 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_errors.3023457315 | Oct 12 12:48:08 AM UTC 24 | Oct 12 12:48:13 AM UTC 24 | 247009201 ps | ||
| T158 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_rw.1243600129 | Oct 12 12:48:11 AM UTC 24 | Oct 12 12:48:16 AM UTC 24 | 212243196 ps | ||
| T164 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2932295306 | Oct 12 12:48:03 AM UTC 24 | Oct 12 12:48:16 AM UTC 24 | 713963202 ps | ||
| T381 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2600817227 | Oct 12 12:48:14 AM UTC 24 | Oct 12 12:48:17 AM UTC 24 | 469437044 ps | ||
| T209 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3705832025 | Oct 12 12:47:54 AM UTC 24 | Oct 12 12:48:18 AM UTC 24 | 2714619644 ps | ||
| T382 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1886278622 | Oct 12 12:48:14 AM UTC 24 | Oct 12 12:48:18 AM UTC 24 | 96316880 ps | ||
| T165 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.4055932034 | Oct 12 12:48:12 AM UTC 24 | Oct 12 12:48:20 AM UTC 24 | 295854419 ps | ||
| T383 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_errors.4089996480 | Oct 12 12:48:18 AM UTC 24 | Oct 12 12:48:22 AM UTC 24 | 339566675 ps | ||
| T384 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_rw.1847351399 | Oct 12 12:48:19 AM UTC 24 | Oct 12 12:48:23 AM UTC 24 | 216447571 ps | ||
| T385 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1597155800 | Oct 12 12:48:17 AM UTC 24 | Oct 12 12:48:23 AM UTC 24 | 10180617013 ps | ||
| T386 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3255058965 | Oct 12 12:47:38 AM UTC 24 | Oct 12 12:48:24 AM UTC 24 | 42709072362 ps | ||
| T387 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1172435337 | Oct 12 12:48:15 AM UTC 24 | Oct 12 12:48:25 AM UTC 24 | 7970683472 ps | ||
| T388 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3970684554 | Oct 12 12:48:22 AM UTC 24 | Oct 12 12:48:26 AM UTC 24 | 485128987 ps | ||
| T166 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.992608018 | Oct 12 12:48:19 AM UTC 24 | Oct 12 12:48:27 AM UTC 24 | 4453576920 ps | ||
| T389 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3443026284 | Oct 12 12:48:21 AM UTC 24 | Oct 12 12:48:28 AM UTC 24 | 109356553 ps | ||
| T160 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2369502995 | Oct 12 12:47:14 AM UTC 24 | Oct 12 12:48:29 AM UTC 24 | 9492885705 ps | ||
| T390 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2588295133 | Oct 12 12:47:06 AM UTC 24 | Oct 12 12:48:29 AM UTC 24 | 10679333093 ps | ||
| T219 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_intg_err.412180583 | Oct 12 12:48:18 AM UTC 24 | Oct 12 12:48:29 AM UTC 24 | 1656840090 ps | ||
| T391 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_errors.429311701 | Oct 12 12:48:25 AM UTC 24 | Oct 12 12:48:29 AM UTC 24 | 208785810 ps | ||
| T161 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_rw.2487655213 | Oct 12 12:48:27 AM UTC 24 | Oct 12 12:48:31 AM UTC 24 | 202511712 ps | ||
| T112 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.3482155557 | Oct 12 12:48:02 AM UTC 24 | Oct 12 12:48:32 AM UTC 24 | 5608963808 ps | ||
| T392 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2175147254 | Oct 12 12:48:29 AM UTC 24 | Oct 12 12:48:32 AM UTC 24 | 146264595 ps | ||
| T393 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1163139331 | Oct 12 12:48:29 AM UTC 24 | Oct 12 12:48:32 AM UTC 24 | 81325113 ps | ||
| T394 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1931670179 | Oct 12 12:47:49 AM UTC 24 | Oct 12 12:48:33 AM UTC 24 | 2901101997 ps | ||
| T395 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.3381263043 | Oct 12 12:48:23 AM UTC 24 | Oct 12 12:48:34 AM UTC 24 | 2169317297 ps | ||
| T396 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_rw.2983545397 | Oct 12 12:48:31 AM UTC 24 | Oct 12 12:48:35 AM UTC 24 | 46367516 ps | ||
| T397 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2125204332 | Oct 12 12:48:32 AM UTC 24 | Oct 12 12:48:35 AM UTC 24 | 297388570 ps | ||
| T398 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.432031049 | Oct 12 12:46:51 AM UTC 24 | Oct 12 12:48:35 AM UTC 24 | 7933592421 ps | ||
| T115 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3498417604 | Oct 12 12:48:32 AM UTC 24 | Oct 12 12:48:37 AM UTC 24 | 145738388 ps | ||
| T214 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3479998620 | Oct 12 12:48:08 AM UTC 24 | Oct 12 12:48:37 AM UTC 24 | 7275143118 ps | ||
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| T399 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3866627575 | Oct 12 12:47:49 AM UTC 24 | Oct 12 12:48:38 AM UTC 24 | 18661019799 ps | ||
| T400 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3472202745 | Oct 12 12:47:11 AM UTC 24 | Oct 12 12:48:39 AM UTC 24 | 29174159104 ps | ||
| T167 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1415703311 | Oct 12 12:48:28 AM UTC 24 | Oct 12 12:48:39 AM UTC 24 | 799224222 ps | ||
| T401 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.4286214383 | Oct 12 12:47:50 AM UTC 24 | Oct 12 12:48:39 AM UTC 24 | 51436907267 ps | ||
| T402 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_errors.2290441094 | Oct 12 12:48:30 AM UTC 24 | Oct 12 12:48:39 AM UTC 24 | 1708091508 ps | ||
| T403 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3782046630 | Oct 12 12:48:30 AM UTC 24 | Oct 12 12:48:41 AM UTC 24 | 1386103238 ps | ||
| T404 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.4000541070 | Oct 12 12:48:36 AM UTC 24 | Oct 12 12:48:41 AM UTC 24 | 112327656 ps | ||
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| T405 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3996265367 | Oct 12 12:48:23 AM UTC 24 | Oct 12 12:48:41 AM UTC 24 | 3648943665 ps | ||
| T406 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.2406168198 | Oct 12 12:48:37 AM UTC 24 | Oct 12 12:48:41 AM UTC 24 | 237581122 ps | ||
| T407 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1745791509 | Oct 12 12:48:38 AM UTC 24 | Oct 12 12:48:41 AM UTC 24 | 692452297 ps | ||
| T408 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3276446640 | Oct 12 12:48:07 AM UTC 24 | Oct 12 12:48:41 AM UTC 24 | 1724138646 ps | ||
| T409 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.545005304 | Oct 12 12:48:38 AM UTC 24 | Oct 12 12:48:42 AM UTC 24 | 48796302 ps | ||
| T410 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_rw.767351689 | Oct 12 12:48:40 AM UTC 24 | Oct 12 12:48:43 AM UTC 24 | 124663071 ps | ||
| T152 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.25474086 | Oct 12 12:48:37 AM UTC 24 | Oct 12 12:48:43 AM UTC 24 | 223076331 ps | ||
| T411 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.749177067 | Oct 12 12:48:42 AM UTC 24 | Oct 12 12:48:44 AM UTC 24 | 135323360 ps | ||
| T412 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2457683695 | Oct 12 12:48:34 AM UTC 24 | Oct 12 12:48:44 AM UTC 24 | 2646388138 ps | ||
| T413 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2387764107 | Oct 12 12:47:51 AM UTC 24 | Oct 12 12:48:44 AM UTC 24 | 2978411751 ps | ||
| T414 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_errors.3088429768 | Oct 12 12:48:39 AM UTC 24 | Oct 12 12:48:44 AM UTC 24 | 80297472 ps | ||
| T110 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3270511559 | Oct 12 12:48:42 AM UTC 24 | Oct 12 12:48:45 AM UTC 24 | 123000803 ps | ||
| T415 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.282712945 | Oct 12 12:48:00 AM UTC 24 | Oct 12 12:48:46 AM UTC 24 | 50210677684 ps | ||
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| T418 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_errors.3242206832 | Oct 12 12:48:42 AM UTC 24 | Oct 12 12:48:48 AM UTC 24 | 516254635 ps | ||
| T419 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3450206589 | Oct 12 12:48:40 AM UTC 24 | Oct 12 12:48:48 AM UTC 24 | 265998362 ps | ||
| T420 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2886629755 | Oct 12 12:48:47 AM UTC 24 | Oct 12 12:48:49 AM UTC 24 | 120701461 ps | ||
| T421 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_rw.3628028720 | Oct 12 12:48:46 AM UTC 24 | Oct 12 12:48:49 AM UTC 24 | 207488295 ps | ||
| T422 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.3526082057 | Oct 12 12:48:39 AM UTC 24 | Oct 12 12:48:50 AM UTC 24 | 5152171282 ps | ||
| T423 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.623340475 | Oct 12 12:48:48 AM UTC 24 | Oct 12 12:48:50 AM UTC 24 | 353470740 ps | ||
| T424 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.952700992 | Oct 12 12:47:49 AM UTC 24 | Oct 12 12:48:50 AM UTC 24 | 1880945021 ps | ||
| T211 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_intg_err.4286252970 | Oct 12 12:48:26 AM UTC 24 | Oct 12 12:48:50 AM UTC 24 | 2640655024 ps | ||
| T425 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1184585957 | Oct 12 12:47:27 AM UTC 24 | Oct 12 12:48:51 AM UTC 24 | 20455360676 ps | ||
| T426 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.277055079 | Oct 12 12:48:47 AM UTC 24 | Oct 12 12:48:51 AM UTC 24 | 1513496448 ps | ||
| T427 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_rw.2780411833 | Oct 12 12:48:47 AM UTC 24 | Oct 12 12:48:51 AM UTC 24 | 547402576 ps | ||
| T428 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2420390373 | Oct 12 12:48:46 AM UTC 24 | Oct 12 12:48:52 AM UTC 24 | 93197675 ps | ||
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| T153 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.694397490 | Oct 12 12:48:47 AM UTC 24 | Oct 12 12:48:53 AM UTC 24 | 191536271 ps | ||
| T430 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3917450371 | Oct 12 12:48:47 AM UTC 24 | Oct 12 12:48:53 AM UTC 24 | 308994648 ps | ||
| T431 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3100248796 | Oct 12 12:48:51 AM UTC 24 | Oct 12 12:48:54 AM UTC 24 | 384457928 ps | ||
| T432 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3720890018 | Oct 12 12:48:30 AM UTC 24 | Oct 12 12:48:54 AM UTC 24 | 41476654406 ps | ||
| T433 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_rw.2570954482 | Oct 12 12:48:50 AM UTC 24 | Oct 12 12:48:54 AM UTC 24 | 285481495 ps | ||
| T434 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_errors.3071532615 | Oct 12 12:48:47 AM UTC 24 | Oct 12 12:48:55 AM UTC 24 | 413266936 ps | ||
| T435 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_rw.53130988 | Oct 12 12:48:52 AM UTC 24 | Oct 12 12:48:56 AM UTC 24 | 112867681 ps | ||
| T436 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_errors.1649395054 | Oct 12 12:48:50 AM UTC 24 | Oct 12 12:48:56 AM UTC 24 | 1248710933 ps | ||
| T437 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1368656440 | Oct 12 12:48:54 AM UTC 24 | Oct 12 12:48:56 AM UTC 24 | 103659837 ps | ||
| T438 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.4038244188 | Oct 12 12:48:51 AM UTC 24 | Oct 12 12:48:56 AM UTC 24 | 187897833 ps | ||
| T216 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2980867110 | Oct 12 12:48:36 AM UTC 24 | Oct 12 12:48:56 AM UTC 24 | 5009883879 ps | ||
| T119 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1039397220 | Oct 12 12:48:52 AM UTC 24 | Oct 12 12:48:57 AM UTC 24 | 99901529 ps | ||
| T439 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.4156239502 | Oct 12 12:48:46 AM UTC 24 | Oct 12 12:48:57 AM UTC 24 | 919793164 ps | ||
| T113 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.1346086191 | Oct 12 12:47:38 AM UTC 24 | Oct 12 12:48:58 AM UTC 24 | 5060772518 ps | ||
| T440 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_errors.1612614969 | Oct 12 12:48:55 AM UTC 24 | Oct 12 12:48:58 AM UTC 24 | 69164459 ps | ||
| T441 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_errors.871308407 | Oct 12 12:48:51 AM UTC 24 | Oct 12 12:48:58 AM UTC 24 | 468985136 ps | ||
| T442 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.4016455207 | Oct 12 12:48:56 AM UTC 24 | Oct 12 12:48:59 AM UTC 24 | 258034872 ps | ||
| T443 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_rw.1429405125 | Oct 12 12:48:55 AM UTC 24 | Oct 12 12:48:59 AM UTC 24 | 157991779 ps | ||
| T212 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3198973020 | Oct 12 12:48:30 AM UTC 24 | Oct 12 12:48:59 AM UTC 24 | 3736961823 ps | ||
| T444 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1800032060 | Oct 12 12:48:42 AM UTC 24 | Oct 12 12:49:00 AM UTC 24 | 5808224046 ps | ||
| T445 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3286333222 | Oct 12 12:48:51 AM UTC 24 | Oct 12 12:49:00 AM UTC 24 | 3241256104 ps | ||
| T446 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.1696803586 | Oct 12 12:48:51 AM UTC 24 | Oct 12 12:49:00 AM UTC 24 | 2511302086 ps | ||
| T154 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.827391855 | Oct 12 12:48:52 AM UTC 24 | Oct 12 12:49:00 AM UTC 24 | 1126615403 ps | ||
| T220 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2629160133 | Oct 12 12:48:47 AM UTC 24 | Oct 12 12:49:00 AM UTC 24 | 6751232377 ps | ||
| T447 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.856781674 | Oct 12 12:48:51 AM UTC 24 | Oct 12 12:49:01 AM UTC 24 | 2252043727 ps | ||
| T120 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3643836465 | Oct 12 12:48:56 AM UTC 24 | Oct 12 12:49:01 AM UTC 24 | 280684712 ps | ||
| T448 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1214973793 | Oct 12 12:48:59 AM UTC 24 | Oct 12 12:49:01 AM UTC 24 | 204984869 ps | ||
| T449 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_rw.3987261619 | Oct 12 12:48:57 AM UTC 24 | Oct 12 12:49:01 AM UTC 24 | 152055535 ps | ||
| T450 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.610984819 | Oct 12 12:48:55 AM UTC 24 | Oct 12 12:49:01 AM UTC 24 | 257983993 ps | ||
| T218 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3124458799 | Oct 12 12:48:40 AM UTC 24 | Oct 12 12:49:01 AM UTC 24 | 2137132103 ps | ||
| T451 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.642397750 | Oct 12 12:48:56 AM UTC 24 | Oct 12 12:49:02 AM UTC 24 | 2217833232 ps | ||
| T452 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_errors.1332548309 | Oct 12 12:48:57 AM UTC 24 | Oct 12 12:49:02 AM UTC 24 | 209075670 ps | ||
| T453 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1888507285 | Oct 12 12:48:52 AM UTC 24 | Oct 12 12:49:02 AM UTC 24 | 1058278770 ps | ||
| T454 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.796838547 | Oct 12 12:48:54 AM UTC 24 | Oct 12 12:49:02 AM UTC 24 | 2345199202 ps | ||
| T455 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3050428346 | Oct 12 12:48:59 AM UTC 24 | Oct 12 12:49:03 AM UTC 24 | 147997252 ps | ||
| T456 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_rw.1251226837 | Oct 12 12:49:04 AM UTC 24 | Oct 12 12:49:06 AM UTC 24 | 228241986 ps | ||
| T457 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2603507013 | Oct 12 12:49:04 AM UTC 24 | Oct 12 12:49:07 AM UTC 24 | 1268837667 ps | ||
| T458 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3588501152 | Oct 12 12:48:58 AM UTC 24 | Oct 12 12:49:07 AM UTC 24 | 570519279 ps | ||
| T459 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1613802276 | Oct 12 12:49:05 AM UTC 24 | Oct 12 12:49:07 AM UTC 24 | 188615282 ps | ||
| T460 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.79220874 | Oct 12 12:48:57 AM UTC 24 | Oct 12 12:49:07 AM UTC 24 | 1651720382 ps | ||
| T461 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.10397208 | Oct 12 12:48:47 AM UTC 24 | Oct 12 12:49:08 AM UTC 24 | 14513992293 ps | ||
| T155 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_rw.4264025436 | Oct 12 12:49:05 AM UTC 24 | Oct 12 12:49:08 AM UTC 24 | 149790922 ps | ||
| T462 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1155321614 | Oct 12 12:49:05 AM UTC 24 | Oct 12 12:49:09 AM UTC 24 | 51497056 ps | ||
| T463 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.190717859 | Oct 12 12:48:55 AM UTC 24 | Oct 12 12:49:09 AM UTC 24 | 3918686450 ps | ||
| T464 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.190706996 | Oct 12 12:49:05 AM UTC 24 | Oct 12 12:49:10 AM UTC 24 | 83941951 ps | ||
| T465 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_errors.1771599798 | Oct 12 12:49:04 AM UTC 24 | Oct 12 12:49:10 AM UTC 24 | 287822543 ps | ||
| T221 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2077384542 | Oct 12 12:48:50 AM UTC 24 | Oct 12 12:49:11 AM UTC 24 | 1368525372 ps | ||
| T466 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2011121569 | Oct 12 12:49:05 AM UTC 24 | Oct 12 12:49:11 AM UTC 24 | 1707644404 ps | ||
| T467 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3046157347 | Oct 12 12:49:04 AM UTC 24 | Oct 12 12:49:12 AM UTC 24 | 232752006 ps | ||
| T468 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_errors.3156728523 | Oct 12 12:49:05 AM UTC 24 | Oct 12 12:49:12 AM UTC 24 | 748804992 ps | ||
| T156 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2463051192 | Oct 12 12:49:05 AM UTC 24 | Oct 12 12:49:15 AM UTC 24 | 700231501 ps | ||
| T469 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.341576654 | Oct 12 12:48:07 AM UTC 24 | Oct 12 12:49:16 AM UTC 24 | 16384846310 ps | ||
| T222 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3028295520 | Oct 12 12:49:04 AM UTC 24 | Oct 12 12:49:17 AM UTC 24 | 2651802742 ps | ||
| T81 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.4171876934 | Oct 12 12:48:17 AM UTC 24 | Oct 12 12:49:19 AM UTC 24 | 4054503671 ps | ||
| T470 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.79081326 | Oct 12 12:47:57 AM UTC 24 | Oct 12 12:49:19 AM UTC 24 | 7700576155 ps | ||
| T471 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3028215423 | Oct 12 12:48:30 AM UTC 24 | Oct 12 12:49:20 AM UTC 24 | 3686630190 ps | ||
| T111 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.442472587 | Oct 12 12:47:21 AM UTC 24 | Oct 12 12:49:21 AM UTC 24 | 10855199419 ps | ||
| T472 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2674255854 | Oct 12 12:47:38 AM UTC 24 | Oct 12 12:49:25 AM UTC 24 | 32083102724 ps | ||
| T473 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_intg_err.794445015 | Oct 12 12:49:05 AM UTC 24 | Oct 12 12:49:27 AM UTC 24 | 4975087037 ps | ||
| T474 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.753473957 | Oct 12 12:48:50 AM UTC 24 | Oct 12 12:49:29 AM UTC 24 | 10802631272 ps | ||
| T475 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.3918178633 | Oct 12 12:49:04 AM UTC 24 | Oct 12 12:49:37 AM UTC 24 | 44392430224 ps | ||
| T476 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.301811914 | Oct 12 12:48:25 AM UTC 24 | Oct 12 12:49:44 AM UTC 24 | 12806430148 ps | ||
| T477 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2173770462 | Oct 12 12:47:06 AM UTC 24 | Oct 12 12:49:59 AM UTC 24 | 101653430951 ps | ||
| T478 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1875076460 | Oct 12 12:48:56 AM UTC 24 | Oct 12 12:50:32 AM UTC 24 | 32118263641 ps | ||
| T479 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.4071382961 | Oct 12 12:49:05 AM UTC 24 | Oct 12 12:51:16 AM UTC 24 | 77708006053 ps | ||
| T480 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1390151380 | Oct 12 12:47:20 AM UTC 24 | Oct 12 12:51:18 AM UTC 24 | 73363029292 ps | ||
| T481 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2313139618 | Oct 12 12:48:42 AM UTC 24 | Oct 12 12:52:42 AM UTC 24 | 72867573523 ps | ||
| T482 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1902095647 | Oct 12 12:48:54 AM UTC 24 | Oct 12 12:53:28 AM UTC 24 | 83024649486 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.789520714 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 324603238 ps |
| CPU time | 1.98 seconds |
| Started | Oct 12 12:49:08 AM UTC 24 |
| Finished | Oct 12 12:49:11 AM UTC 24 |
| Peak memory | 214956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789520714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_cmderr_exception_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.789520714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_cmderr_exception/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.2682582803 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 7593386623 ps |
| CPU time | 8.09 seconds |
| Started | Oct 12 12:49:06 AM UTC 24 |
| Finished | Oct 12 12:49:15 AM UTC 24 |
| Peak memory | 225940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682582803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.2682582803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.4027757653 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 2365472787 ps |
| CPU time | 12.73 seconds |
| Started | Oct 12 12:49:20 AM UTC 24 |
| Finished | Oct 12 12:49:34 AM UTC 24 |
| Peak memory | 231992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=4027757653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stres s_all_with_rand_reset.4027757653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.314968690 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 219412289 ps |
| CPU time | 1.53 seconds |
| Started | Oct 12 12:49:10 AM UTC 24 |
| Finished | Oct 12 12:49:13 AM UTC 24 |
| Peak memory | 214952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314968690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.314968690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.1454609701 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 2690046913 ps |
| CPU time | 49.91 seconds |
| Started | Oct 12 12:49:23 AM UTC 24 |
| Finished | Oct 12 12:50:15 AM UTC 24 |
| Peak memory | 232752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1454609701 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stres s_all_with_rand_reset.1454609701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.2324626060 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 11493229999 ps |
| CPU time | 33.59 seconds |
| Started | Oct 12 12:49:05 AM UTC 24 |
| Finished | Oct 12 12:49:40 AM UTC 24 |
| Peak memory | 215616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324626060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.2324626060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.19717151 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 5193227349 ps |
| CPU time | 4.81 seconds |
| Started | Oct 12 12:49:26 AM UTC 24 |
| Finished | Oct 12 12:49:32 AM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19717151 -assert nopostproc +UVM_TESTNAME=rv_ dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.19717151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/4.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.1056208096 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 8288545235 ps |
| CPU time | 62.58 seconds |
| Started | Oct 12 12:49:37 AM UTC 24 |
| Finished | Oct 12 12:50:41 AM UTC 24 |
| Peak memory | 232776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1056208096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stres s_all_with_rand_reset.1056208096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.2318263184 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 190691007 ps |
| CPU time | 1.53 seconds |
| Started | Oct 12 12:49:23 AM UTC 24 |
| Finished | Oct 12 12:49:25 AM UTC 24 |
| Peak memory | 256764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318263184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_buffered_enable.2318263184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/3.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2314009753 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 5522067904 ps |
| CPU time | 16.98 seconds |
| Started | Oct 12 12:46:55 AM UTC 24 |
| Finished | Oct 12 12:47:13 AM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314009753 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.2314009753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.2173758272 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 569212202 ps |
| CPU time | 1.2 seconds |
| Started | Oct 12 12:49:12 AM UTC 24 |
| Finished | Oct 12 12:49:14 AM UTC 24 |
| Peak memory | 214900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173758272 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.2173758272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_dmi_failed_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/13.rv_dm_autoincr_sba_tl_access.2899239708 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 34603925407 ps |
| CPU time | 41.95 seconds |
| Started | Oct 12 12:49:53 AM UTC 24 |
| Finished | Oct 12 12:50:37 AM UTC 24 |
| Peak memory | 226020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899239708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.2899239708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/13.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.1346086191 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 5060772518 ps |
| CPU time | 77.88 seconds |
| Started | Oct 12 12:47:38 AM UTC 24 |
| Finished | Oct 12 12:48:58 AM UTC 24 |
| Peak memory | 229564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1346086191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_re set.1346086191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/3.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all.1845573109 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 2129281246 ps |
| CPU time | 3.37 seconds |
| Started | Oct 12 12:49:33 AM UTC 24 |
| Finished | Oct 12 12:49:38 AM UTC 24 |
| Peak memory | 225544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845573109 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.1845573109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/6.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.3723416936 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1153564595 ps |
| CPU time | 1.99 seconds |
| Started | Oct 12 12:49:13 AM UTC 24 |
| Finished | Oct 12 12:49:16 AM UTC 24 |
| Peak memory | 254840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723416936 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3723416936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_resuming.1209982740 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 538371021 ps |
| CPU time | 1.28 seconds |
| Started | Oct 12 12:49:08 AM UTC 24 |
| Finished | Oct 12 12:49:10 AM UTC 24 |
| Peak memory | 214956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209982740 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.1209982740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_resuming/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.442472587 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 10855199419 ps |
| CPU time | 117.35 seconds |
| Started | Oct 12 12:47:21 AM UTC 24 |
| Finished | Oct 12 12:49:21 AM UTC 24 |
| Peak memory | 231728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=442472587 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.442472587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/2.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3643836465 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 280684712 ps |
| CPU time | 3.55 seconds |
| Started | Oct 12 12:48:56 AM UTC 24 |
| Finished | Oct 12 12:49:01 AM UTC 24 |
| Peak memory | 229512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3643836465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_ rand_reset.3643836465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/16.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/17.rv_dm_stress_all.959901815 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 3884754652 ps |
| CPU time | 4.68 seconds |
| Started | Oct 12 12:50:04 AM UTC 24 |
| Finished | Oct 12 12:50:09 AM UTC 24 |
| Peak memory | 215484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959901815 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.959901815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/17.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.102268050 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 8964854859 ps |
| CPU time | 5.83 seconds |
| Started | Oct 12 12:49:28 AM UTC 24 |
| Finished | Oct 12 12:49:35 AM UTC 24 |
| Peak memory | 225948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102268050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.102268050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/5.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.3417579787 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 21541101839 ps |
| CPU time | 34.6 seconds |
| Started | Oct 12 12:50:08 AM UTC 24 |
| Finished | Oct 12 12:50:44 AM UTC 24 |
| Peak memory | 226076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417579787 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.3417579787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/19.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.4168944291 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 527462009 ps |
| CPU time | 6.21 seconds |
| Started | Oct 12 12:46:57 AM UTC 24 |
| Finished | Oct 12 12:47:05 AM UTC 24 |
| Peak memory | 224916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168944291 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.4168944291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.3842445803 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 3374633661 ps |
| CPU time | 9.31 seconds |
| Started | Oct 12 12:50:08 AM UTC 24 |
| Finished | Oct 12 12:50:18 AM UTC 24 |
| Peak memory | 225724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842445803 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.3842445803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/19.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.3877644295 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 94877903 ps |
| CPU time | 1.65 seconds |
| Started | Oct 12 12:49:12 AM UTC 24 |
| Finished | Oct 12 12:49:14 AM UTC 24 |
| Peak memory | 224756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877644295 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_rom_read_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.3877644295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_rom_read_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_alert_test.738280023 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 36723541 ps |
| CPU time | 0.8 seconds |
| Started | Oct 12 12:49:20 AM UTC 24 |
| Finished | Oct 12 12:49:22 AM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738280023 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.738280023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.1676326174 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 167000425 ps |
| CPU time | 1.32 seconds |
| Started | Oct 12 12:49:10 AM UTC 24 |
| Finished | Oct 12 12:49:13 AM UTC 24 |
| Peak memory | 224748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676326174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.1676326174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_ndmreset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.1260888023 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 2918954159 ps |
| CPU time | 4.84 seconds |
| Started | Oct 12 12:50:11 AM UTC 24 |
| Finished | Oct 12 12:50:17 AM UTC 24 |
| Peak memory | 215740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260888023 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.1260888023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/22.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3479998620 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 7275143118 ps |
| CPU time | 27.69 seconds |
| Started | Oct 12 12:48:08 AM UTC 24 |
| Finished | Oct 12 12:48:37 AM UTC 24 |
| Peak memory | 225464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479998620 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.3479998620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/6.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/12.rv_dm_autoincr_sba_tl_access.994745907 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 19000788146 ps |
| CPU time | 26.79 seconds |
| Started | Oct 12 12:49:49 AM UTC 24 |
| Finished | Oct 12 12:50:17 AM UTC 24 |
| Peak memory | 227868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994745907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.994745907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/12.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/16.rv_dm_stress_all.3739921788 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 1987401285 ps |
| CPU time | 9.02 seconds |
| Started | Oct 12 12:50:00 AM UTC 24 |
| Finished | Oct 12 12:50:10 AM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739921788 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.3739921788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/16.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.1342340373 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 727760728 ps |
| CPU time | 3.46 seconds |
| Started | Oct 12 12:49:13 AM UTC 24 |
| Finished | Oct 12 12:49:18 AM UTC 24 |
| Peak memory | 257800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342340373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_buffered_enable.1342340373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.1688341305 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 5037052357 ps |
| CPU time | 5.43 seconds |
| Started | Oct 12 12:49:10 AM UTC 24 |
| Finished | Oct 12 12:49:17 AM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688341305 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.1688341305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_sba_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3124458799 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 2137132103 ps |
| CPU time | 19.64 seconds |
| Started | Oct 12 12:48:40 AM UTC 24 |
| Finished | Oct 12 12:49:01 AM UTC 24 |
| Peak memory | 224936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124458799 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.3124458799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/11.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3773146015 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 2133282210 ps |
| CPU time | 13.91 seconds |
| Started | Oct 12 12:47:22 AM UTC 24 |
| Finished | Oct 12 12:47:38 AM UTC 24 |
| Peak memory | 225360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773146015 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.3773146015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/2.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.1264265111 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 15834403382 ps |
| CPU time | 50.75 seconds |
| Started | Oct 12 12:49:06 AM UTC 24 |
| Finished | Oct 12 12:49:58 AM UTC 24 |
| Peak memory | 226144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264265111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.1264265111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.2084578961 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 651745594 ps |
| CPU time | 1.92 seconds |
| Started | Oct 12 12:49:20 AM UTC 24 |
| Finished | Oct 12 12:49:23 AM UTC 24 |
| Peak memory | 214892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084578961 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.2084578961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/12.rv_dm_stress_all.169903101 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 4995201353 ps |
| CPU time | 5.76 seconds |
| Started | Oct 12 12:49:49 AM UTC 24 |
| Finished | Oct 12 12:49:56 AM UTC 24 |
| Peak memory | 215560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169903101 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.169903101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/12.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.429610832 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 715856831 ps |
| CPU time | 2.04 seconds |
| Started | Oct 12 12:50:26 AM UTC 24 |
| Finished | Oct 12 12:50:29 AM UTC 24 |
| Peak memory | 225600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429610832 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.429610832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/46.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.2702672938 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 132777664 ps |
| CPU time | 1.01 seconds |
| Started | Oct 12 12:49:19 AM UTC 24 |
| Finished | Oct 12 12:49:21 AM UTC 24 |
| Peak memory | 224748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702672938 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sparse_lc_gate_fsm.2702672938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_sparse_lc_gate_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2266455452 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 1202374613 ps |
| CPU time | 6.98 seconds |
| Started | Oct 12 12:46:51 AM UTC 24 |
| Finished | Oct 12 12:47:00 AM UTC 24 |
| Peak memory | 214788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266455452 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_aliasing.2266455452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.4093853573 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 5375246991 ps |
| CPU time | 76.81 seconds |
| Started | Oct 12 12:49:30 AM UTC 24 |
| Finished | Oct 12 12:50:48 AM UTC 24 |
| Peak memory | 232552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=4093853573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stres s_all_with_rand_reset.4093853573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2271768571 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 9185015145 ps |
| CPU time | 6.34 seconds |
| Started | Oct 12 12:46:51 AM UTC 24 |
| Finished | Oct 12 12:46:59 AM UTC 24 |
| Peak memory | 215008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271768571 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_hw_reset.2271768571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1310143710 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 372193935 ps |
| CPU time | 7.16 seconds |
| Started | Oct 12 12:46:59 AM UTC 24 |
| Finished | Oct 12 12:47:08 AM UTC 24 |
| Peak memory | 215140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310143710 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_csr_outstanding.1310143710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1081379879 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 29831854658 ps |
| CPU time | 34.75 seconds |
| Started | Oct 12 12:47:00 AM UTC 24 |
| Finished | Oct 12 12:47:36 AM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081379879 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_aliasing.1081379879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.182857464 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 396192233 ps |
| CPU time | 1.3 seconds |
| Started | Oct 12 12:49:09 AM UTC 24 |
| Finished | Oct 12 12:49:11 AM UTC 24 |
| Peak memory | 214892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182857464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_cmderr_halt_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.182857464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_cmderr_halt_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3136128553 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 801945280 ps |
| CPU time | 13.52 seconds |
| Started | Oct 12 12:47:07 AM UTC 24 |
| Finished | Oct 12 12:47:22 AM UTC 24 |
| Peak memory | 225380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136128553 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.3136128553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3559909929 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 1244122175 ps |
| CPU time | 8.79 seconds |
| Started | Oct 12 12:48:42 AM UTC 24 |
| Finished | Oct 12 12:48:52 AM UTC 24 |
| Peak memory | 225576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559909929 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.3559909929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/12.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/11.rv_dm_stress_all.3507076069 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 4006089165 ps |
| CPU time | 10.8 seconds |
| Started | Oct 12 12:49:49 AM UTC 24 |
| Finished | Oct 12 12:50:01 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507076069 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.3507076069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/11.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/15.rv_dm_stress_all.1167825128 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1898531467 ps |
| CPU time | 6.52 seconds |
| Started | Oct 12 12:49:58 AM UTC 24 |
| Finished | Oct 12 12:50:06 AM UTC 24 |
| Peak memory | 215600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167825128 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.1167825128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/15.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/18.rv_dm_autoincr_sba_tl_access.2814186804 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 6083029731 ps |
| CPU time | 18.58 seconds |
| Started | Oct 12 12:50:06 AM UTC 24 |
| Finished | Oct 12 12:50:26 AM UTC 24 |
| Peak memory | 225932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814186804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.2814186804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/18.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2160623131 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 5652097527 ps |
| CPU time | 18.92 seconds |
| Started | Oct 12 12:50:08 AM UTC 24 |
| Finished | Oct 12 12:50:28 AM UTC 24 |
| Peak memory | 226076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160623131 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_tl_access.2160623131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/19.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/47.rv_dm_stress_all.455645688 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 3519194403 ps |
| CPU time | 6.06 seconds |
| Started | Oct 12 12:50:26 AM UTC 24 |
| Finished | Oct 12 12:50:33 AM UTC 24 |
| Peak memory | 225748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455645688 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.455645688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/47.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/2.rv_dm_sparse_lc_gate_fsm.1443684292 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 282710359 ps |
| CPU time | 1.62 seconds |
| Started | Oct 12 12:49:22 AM UTC 24 |
| Finished | Oct 12 12:49:24 AM UTC 24 |
| Peak memory | 224748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443684292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sparse_lc_gate_fsm.1443684292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/2.rv_dm_sparse_lc_gate_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3308371360 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 246322361 ps |
| CPU time | 2.27 seconds |
| Started | Oct 12 12:47:56 AM UTC 24 |
| Finished | Oct 12 12:47:59 AM UTC 24 |
| Peak memory | 225528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308371360 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.3308371360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/4.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.432031049 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 7933592421 ps |
| CPU time | 102 seconds |
| Started | Oct 12 12:46:51 AM UTC 24 |
| Finished | Oct 12 12:48:35 AM UTC 24 |
| Peak memory | 225380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432031049 -asse rt nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_aliasing.432031049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.394747105 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 5121283677 ps |
| CPU time | 44.87 seconds |
| Started | Oct 12 12:46:59 AM UTC 24 |
| Finished | Oct 12 12:47:46 AM UTC 24 |
| Peak memory | 225528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394747105 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.394747105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.22116723 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 156661690 ps |
| CPU time | 5 seconds |
| Started | Oct 12 12:46:59 AM UTC 24 |
| Finished | Oct 12 12:47:05 AM UTC 24 |
| Peak memory | 231524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=22116723 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_ran d_reset.22116723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.689661140 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 127805205 ps |
| CPU time | 3.73 seconds |
| Started | Oct 12 12:46:57 AM UTC 24 |
| Finished | Oct 12 12:47:02 AM UTC 24 |
| Peak memory | 225220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689661140 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.689661140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.342916919 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 23562598636 ps |
| CPU time | 41.4 seconds |
| Started | Oct 12 12:46:52 AM UTC 24 |
| Finished | Oct 12 12:47:35 AM UTC 24 |
| Peak memory | 214944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342916919 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_aliasing.342916919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1321249141 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 1505876265 ps |
| CPU time | 5.05 seconds |
| Started | Oct 12 12:46:52 AM UTC 24 |
| Finished | Oct 12 12:46:58 AM UTC 24 |
| Peak memory | 214960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321249141 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_bit_bash.1321249141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2666371584 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 5878302065 ps |
| CPU time | 27.89 seconds |
| Started | Oct 12 12:46:51 AM UTC 24 |
| Finished | Oct 12 12:47:21 AM UTC 24 |
| Peak memory | 215032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666371584 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.2666371584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1289683762 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 17276770473 ps |
| CPU time | 51.14 seconds |
| Started | Oct 12 12:46:51 AM UTC 24 |
| Finished | Oct 12 12:47:44 AM UTC 24 |
| Peak memory | 215024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289683762 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_bit_bash.1289683762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1294682746 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 367493577 ps |
| CPU time | 1.9 seconds |
| Started | Oct 12 12:46:51 AM UTC 24 |
| Finished | Oct 12 12:46:54 AM UTC 24 |
| Peak memory | 213836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294682746 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_hw_reset.1294682746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1926579332 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 776033439 ps |
| CPU time | 2.64 seconds |
| Started | Oct 12 12:46:51 AM UTC 24 |
| Finished | Oct 12 12:46:55 AM UTC 24 |
| Peak memory | 214672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926579332 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.1926579332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.560393507 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 97291290 ps |
| CPU time | 1.03 seconds |
| Started | Oct 12 12:46:56 AM UTC 24 |
| Finished | Oct 12 12:46:58 AM UTC 24 |
| Peak memory | 214596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560393507 -assert nopostproc +UVM_ TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_partial_access.560393507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.612168065 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 148828128 ps |
| CPU time | 1.29 seconds |
| Started | Oct 12 12:46:56 AM UTC 24 |
| Finished | Oct 12 12:46:58 AM UTC 24 |
| Peak memory | 214592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612168065 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.612168065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1095369472 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 2078930099 ps |
| CPU time | 62.78 seconds |
| Started | Oct 12 12:46:52 AM UTC 24 |
| Finished | Oct 12 12:47:56 AM UTC 24 |
| Peak memory | 232008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1095369472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_re set.1095369472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.4226962838 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 53284669 ps |
| CPU time | 2.55 seconds |
| Started | Oct 12 12:46:53 AM UTC 24 |
| Finished | Oct 12 12:46:57 AM UTC 24 |
| Peak memory | 225340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226962838 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.4226962838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3472202745 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 29174159104 ps |
| CPU time | 85.4 seconds |
| Started | Oct 12 12:47:11 AM UTC 24 |
| Finished | Oct 12 12:48:39 AM UTC 24 |
| Peak memory | 225340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472202745 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.3472202745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3033010451 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 139185927 ps |
| CPU time | 2.65 seconds |
| Started | Oct 12 12:47:09 AM UTC 24 |
| Finished | Oct 12 12:47:13 AM UTC 24 |
| Peak memory | 225448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033010451 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.3033010451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.840361784 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 161981348 ps |
| CPU time | 3.81 seconds |
| Started | Oct 12 12:47:13 AM UTC 24 |
| Finished | Oct 12 12:47:17 AM UTC 24 |
| Peak memory | 225268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=840361784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_ra nd_reset.840361784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.3499403434 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 54262700 ps |
| CPU time | 2.92 seconds |
| Started | Oct 12 12:47:11 AM UTC 24 |
| Finished | Oct 12 12:47:15 AM UTC 24 |
| Peak memory | 225252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499403434 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.3499403434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2173770462 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 101653430951 ps |
| CPU time | 170.35 seconds |
| Started | Oct 12 12:47:06 AM UTC 24 |
| Finished | Oct 12 12:49:59 AM UTC 24 |
| Peak memory | 214944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173770462 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_aliasing.2173770462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2539634441 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 16050592564 ps |
| CPU time | 38.43 seconds |
| Started | Oct 12 12:47:06 AM UTC 24 |
| Finished | Oct 12 12:47:46 AM UTC 24 |
| Peak memory | 214944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539634441 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_bit_bash.2539634441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1430766635 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 16583957226 ps |
| CPU time | 16.93 seconds |
| Started | Oct 12 12:47:05 AM UTC 24 |
| Finished | Oct 12 12:47:23 AM UTC 24 |
| Peak memory | 215140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430766635 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_hw_reset.1430766635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3776734305 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 3915362656 ps |
| CPU time | 8.01 seconds |
| Started | Oct 12 12:47:06 AM UTC 24 |
| Finished | Oct 12 12:47:15 AM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776734305 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.3776734305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1914715005 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 397272774 ps |
| CPU time | 1.81 seconds |
| Started | Oct 12 12:47:04 AM UTC 24 |
| Finished | Oct 12 12:47:06 AM UTC 24 |
| Peak memory | 214596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914715005 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_aliasing.1914715005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1800042136 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 20110971167 ps |
| CPU time | 26.19 seconds |
| Started | Oct 12 12:47:04 AM UTC 24 |
| Finished | Oct 12 12:47:31 AM UTC 24 |
| Peak memory | 214964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800042136 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_bit_bash.1800042136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1630691653 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 224909403 ps |
| CPU time | 1.4 seconds |
| Started | Oct 12 12:47:00 AM UTC 24 |
| Finished | Oct 12 12:47:03 AM UTC 24 |
| Peak memory | 214596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630691653 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_hw_reset.1630691653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1757555430 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 294515807 ps |
| CPU time | 1.54 seconds |
| Started | Oct 12 12:47:03 AM UTC 24 |
| Finished | Oct 12 12:47:06 AM UTC 24 |
| Peak memory | 214604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757555430 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.1757555430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.642622004 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 112422581 ps |
| CPU time | 1.05 seconds |
| Started | Oct 12 12:47:09 AM UTC 24 |
| Finished | Oct 12 12:47:11 AM UTC 24 |
| Peak memory | 214596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642622004 -assert nopostproc +UVM_ TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_partial_access.642622004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.2391075897 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 74250351 ps |
| CPU time | 1.23 seconds |
| Started | Oct 12 12:47:08 AM UTC 24 |
| Finished | Oct 12 12:47:10 AM UTC 24 |
| Peak memory | 214588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391075897 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.2391075897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.4289124952 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 372546547 ps |
| CPU time | 7.12 seconds |
| Started | Oct 12 12:47:13 AM UTC 24 |
| Finished | Oct 12 12:47:21 AM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289124952 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_csr_outstanding.4289124952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2588295133 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 10679333093 ps |
| CPU time | 81.56 seconds |
| Started | Oct 12 12:47:06 AM UTC 24 |
| Finished | Oct 12 12:48:29 AM UTC 24 |
| Peak memory | 232080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2588295133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_re set.2588295133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.3598744186 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 804167358 ps |
| CPU time | 2.94 seconds |
| Started | Oct 12 12:47:07 AM UTC 24 |
| Finished | Oct 12 12:47:11 AM UTC 24 |
| Peak memory | 225340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598744186 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.3598744186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.545005304 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 48796302 ps |
| CPU time | 2.65 seconds |
| Started | Oct 12 12:48:38 AM UTC 24 |
| Finished | Oct 12 12:48:42 AM UTC 24 |
| Peak memory | 225516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=545005304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_r and_reset.545005304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/10.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.2406168198 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 237581122 ps |
| CPU time | 2.55 seconds |
| Started | Oct 12 12:48:37 AM UTC 24 |
| Finished | Oct 12 12:48:41 AM UTC 24 |
| Peak memory | 225256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406168198 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.2406168198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/10.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.770002408 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 5118951196 ps |
| CPU time | 10.44 seconds |
| Started | Oct 12 12:48:36 AM UTC 24 |
| Finished | Oct 12 12:48:47 AM UTC 24 |
| Peak memory | 214944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770002408 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_bit_bash.770002408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/10.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2457683695 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 2646388138 ps |
| CPU time | 9.22 seconds |
| Started | Oct 12 12:48:34 AM UTC 24 |
| Finished | Oct 12 12:48:44 AM UTC 24 |
| Peak memory | 214948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457683695 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.2457683695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/10.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2125204332 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 297388570 ps |
| CPU time | 1.23 seconds |
| Started | Oct 12 12:48:32 AM UTC 24 |
| Finished | Oct 12 12:48:35 AM UTC 24 |
| Peak memory | 214596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125204332 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.2125204332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/10.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.25474086 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 223076331 ps |
| CPU time | 4.69 seconds |
| Started | Oct 12 12:48:37 AM UTC 24 |
| Finished | Oct 12 12:48:43 AM UTC 24 |
| Peak memory | 215332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25474086 -assert nopostproc +UVM _TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_csr_outstanding.25474086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/10.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.4000541070 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 112327656 ps |
| CPU time | 3.54 seconds |
| Started | Oct 12 12:48:36 AM UTC 24 |
| Finished | Oct 12 12:48:41 AM UTC 24 |
| Peak memory | 225372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000541070 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.4000541070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/10.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2980867110 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 5009883879 ps |
| CPU time | 18.49 seconds |
| Started | Oct 12 12:48:36 AM UTC 24 |
| Finished | Oct 12 12:48:56 AM UTC 24 |
| Peak memory | 227432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980867110 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.2980867110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/10.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3270511559 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 123000803 ps |
| CPU time | 2.21 seconds |
| Started | Oct 12 12:48:42 AM UTC 24 |
| Finished | Oct 12 12:48:45 AM UTC 24 |
| Peak memory | 227384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3270511559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_ rand_reset.3270511559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/11.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_rw.767351689 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 124663071 ps |
| CPU time | 1.52 seconds |
| Started | Oct 12 12:48:40 AM UTC 24 |
| Finished | Oct 12 12:48:43 AM UTC 24 |
| Peak memory | 224624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767351689 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.767351689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/11.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.3526082057 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 5152171282 ps |
| CPU time | 8.99 seconds |
| Started | Oct 12 12:48:39 AM UTC 24 |
| Finished | Oct 12 12:48:50 AM UTC 24 |
| Peak memory | 215220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526082057 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_bit_bash.3526082057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/11.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.385732818 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 7042526628 ps |
| CPU time | 7.73 seconds |
| Started | Oct 12 12:48:39 AM UTC 24 |
| Finished | Oct 12 12:48:48 AM UTC 24 |
| Peak memory | 214944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385732818 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.385732818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/11.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1745791509 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 692452297 ps |
| CPU time | 1.87 seconds |
| Started | Oct 12 12:48:38 AM UTC 24 |
| Finished | Oct 12 12:48:41 AM UTC 24 |
| Peak memory | 214596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745791509 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.1745791509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/11.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3450206589 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 265998362 ps |
| CPU time | 6.83 seconds |
| Started | Oct 12 12:48:40 AM UTC 24 |
| Finished | Oct 12 12:48:48 AM UTC 24 |
| Peak memory | 215160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450206589 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_csr_outstanding.3450206589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/11.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_errors.3088429768 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 80297472 ps |
| CPU time | 3.87 seconds |
| Started | Oct 12 12:48:39 AM UTC 24 |
| Finished | Oct 12 12:48:44 AM UTC 24 |
| Peak memory | 225372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088429768 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.3088429768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/11.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2420390373 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 93197675 ps |
| CPU time | 4.66 seconds |
| Started | Oct 12 12:48:46 AM UTC 24 |
| Finished | Oct 12 12:48:52 AM UTC 24 |
| Peak memory | 225592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2420390373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_ rand_reset.2420390373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/12.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_rw.3628028720 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 207488295 ps |
| CPU time | 2.48 seconds |
| Started | Oct 12 12:48:46 AM UTC 24 |
| Finished | Oct 12 12:48:49 AM UTC 24 |
| Peak memory | 225320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628028720 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.3628028720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/12.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2313139618 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 72867573523 ps |
| CPU time | 236.68 seconds |
| Started | Oct 12 12:48:42 AM UTC 24 |
| Finished | Oct 12 12:52:42 AM UTC 24 |
| Peak memory | 214948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313139618 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_bit_bash.2313139618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/12.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1800032060 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 5808224046 ps |
| CPU time | 16.73 seconds |
| Started | Oct 12 12:48:42 AM UTC 24 |
| Finished | Oct 12 12:49:00 AM UTC 24 |
| Peak memory | 215220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800032060 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.1800032060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/12.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.749177067 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 135323360 ps |
| CPU time | 1.15 seconds |
| Started | Oct 12 12:48:42 AM UTC 24 |
| Finished | Oct 12 12:48:44 AM UTC 24 |
| Peak memory | 214604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749177067 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.749177067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/12.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.4156239502 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 919793164 ps |
| CPU time | 10.33 seconds |
| Started | Oct 12 12:48:46 AM UTC 24 |
| Finished | Oct 12 12:48:57 AM UTC 24 |
| Peak memory | 215332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156239502 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same_csr_outstanding.4156239502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/12.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_errors.3242206832 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 516254635 ps |
| CPU time | 5.4 seconds |
| Started | Oct 12 12:48:42 AM UTC 24 |
| Finished | Oct 12 12:48:48 AM UTC 24 |
| Peak memory | 225524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242206832 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.3242206832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/12.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3917450371 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 308994648 ps |
| CPU time | 4.33 seconds |
| Started | Oct 12 12:48:47 AM UTC 24 |
| Finished | Oct 12 12:48:53 AM UTC 24 |
| Peak memory | 231456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3917450371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_ rand_reset.3917450371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/13.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_rw.2780411833 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 547402576 ps |
| CPU time | 2.89 seconds |
| Started | Oct 12 12:48:47 AM UTC 24 |
| Finished | Oct 12 12:48:51 AM UTC 24 |
| Peak memory | 225452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780411833 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.2780411833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/13.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.10397208 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 14513992293 ps |
| CPU time | 19.32 seconds |
| Started | Oct 12 12:48:47 AM UTC 24 |
| Finished | Oct 12 12:49:08 AM UTC 24 |
| Peak memory | 215220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10397208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_bit_bash.10397208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/13.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.277055079 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 1513496448 ps |
| CPU time | 2.97 seconds |
| Started | Oct 12 12:48:47 AM UTC 24 |
| Finished | Oct 12 12:48:51 AM UTC 24 |
| Peak memory | 214136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277055079 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.277055079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/13.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2886629755 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 120701461 ps |
| CPU time | 0.93 seconds |
| Started | Oct 12 12:48:47 AM UTC 24 |
| Finished | Oct 12 12:48:49 AM UTC 24 |
| Peak memory | 214272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886629755 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.2886629755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/13.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.694397490 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 191536271 ps |
| CPU time | 4.12 seconds |
| Started | Oct 12 12:48:47 AM UTC 24 |
| Finished | Oct 12 12:48:53 AM UTC 24 |
| Peak memory | 215096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694397490 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_csr_outstanding.694397490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/13.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_errors.3071532615 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 413266936 ps |
| CPU time | 6.06 seconds |
| Started | Oct 12 12:48:47 AM UTC 24 |
| Finished | Oct 12 12:48:55 AM UTC 24 |
| Peak memory | 225584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071532615 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.3071532615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/13.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2629160133 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 6751232377 ps |
| CPU time | 11.77 seconds |
| Started | Oct 12 12:48:47 AM UTC 24 |
| Finished | Oct 12 12:49:00 AM UTC 24 |
| Peak memory | 225632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629160133 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.2629160133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/13.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.4038244188 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 187897833 ps |
| CPU time | 3.55 seconds |
| Started | Oct 12 12:48:51 AM UTC 24 |
| Finished | Oct 12 12:48:56 AM UTC 24 |
| Peak memory | 225396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=4038244188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_ rand_reset.4038244188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/14.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_rw.2570954482 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 285481495 ps |
| CPU time | 3.5 seconds |
| Started | Oct 12 12:48:50 AM UTC 24 |
| Finished | Oct 12 12:48:54 AM UTC 24 |
| Peak memory | 225260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570954482 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.2570954482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/14.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.753473957 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 10802631272 ps |
| CPU time | 37.64 seconds |
| Started | Oct 12 12:48:50 AM UTC 24 |
| Finished | Oct 12 12:49:29 AM UTC 24 |
| Peak memory | 215024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753473957 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_bit_bash.753473957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/14.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2713134443 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 1698756695 ps |
| CPU time | 2.36 seconds |
| Started | Oct 12 12:48:49 AM UTC 24 |
| Finished | Oct 12 12:48:52 AM UTC 24 |
| Peak memory | 214884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713134443 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.2713134443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/14.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.623340475 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 353470740 ps |
| CPU time | 1.33 seconds |
| Started | Oct 12 12:48:48 AM UTC 24 |
| Finished | Oct 12 12:48:50 AM UTC 24 |
| Peak memory | 214604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623340475 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.623340475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/14.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.856781674 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 2252043727 ps |
| CPU time | 8.6 seconds |
| Started | Oct 12 12:48:51 AM UTC 24 |
| Finished | Oct 12 12:49:01 AM UTC 24 |
| Peak memory | 215224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856781674 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same_csr_outstanding.856781674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/14.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_errors.1649395054 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 1248710933 ps |
| CPU time | 4.74 seconds |
| Started | Oct 12 12:48:50 AM UTC 24 |
| Finished | Oct 12 12:48:56 AM UTC 24 |
| Peak memory | 225372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649395054 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.1649395054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/14.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2077384542 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 1368525372 ps |
| CPU time | 19.58 seconds |
| Started | Oct 12 12:48:50 AM UTC 24 |
| Finished | Oct 12 12:49:11 AM UTC 24 |
| Peak memory | 225324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077384542 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.2077384542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/14.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1039397220 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 99901529 ps |
| CPU time | 3.53 seconds |
| Started | Oct 12 12:48:52 AM UTC 24 |
| Finished | Oct 12 12:48:57 AM UTC 24 |
| Peak memory | 229492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1039397220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_ rand_reset.1039397220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/15.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_rw.53130988 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 112867681 ps |
| CPU time | 2.84 seconds |
| Started | Oct 12 12:48:52 AM UTC 24 |
| Finished | Oct 12 12:48:56 AM UTC 24 |
| Peak memory | 225228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53130988 -assert nopostproc +UVM_TESTNAME=rv_dm_ba se_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv _dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.53130988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/15.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.1696803586 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 2511302086 ps |
| CPU time | 7.93 seconds |
| Started | Oct 12 12:48:51 AM UTC 24 |
| Finished | Oct 12 12:49:00 AM UTC 24 |
| Peak memory | 214948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696803586 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_bit_bash.1696803586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/15.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3286333222 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 3241256104 ps |
| CPU time | 7.93 seconds |
| Started | Oct 12 12:48:51 AM UTC 24 |
| Finished | Oct 12 12:49:00 AM UTC 24 |
| Peak memory | 214948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286333222 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.3286333222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/15.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3100248796 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 384457928 ps |
| CPU time | 1.54 seconds |
| Started | Oct 12 12:48:51 AM UTC 24 |
| Finished | Oct 12 12:48:54 AM UTC 24 |
| Peak memory | 214596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100248796 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.3100248796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/15.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.827391855 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 1126615403 ps |
| CPU time | 6.94 seconds |
| Started | Oct 12 12:48:52 AM UTC 24 |
| Finished | Oct 12 12:49:00 AM UTC 24 |
| Peak memory | 215160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827391855 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_csr_outstanding.827391855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/15.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_errors.871308407 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 468985136 ps |
| CPU time | 6.14 seconds |
| Started | Oct 12 12:48:51 AM UTC 24 |
| Finished | Oct 12 12:48:58 AM UTC 24 |
| Peak memory | 225372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871308407 -assert nopostproc +UVM_TESTNAME=rv_dm_base _test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.871308407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/15.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1888507285 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 1058278770 ps |
| CPU time | 8.78 seconds |
| Started | Oct 12 12:48:52 AM UTC 24 |
| Finished | Oct 12 12:49:02 AM UTC 24 |
| Peak memory | 225364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888507285 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.1888507285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/15.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_rw.1429405125 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 157991779 ps |
| CPU time | 2.8 seconds |
| Started | Oct 12 12:48:55 AM UTC 24 |
| Finished | Oct 12 12:48:59 AM UTC 24 |
| Peak memory | 225260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429405125 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.1429405125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/16.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1902095647 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 83024649486 ps |
| CPU time | 270.65 seconds |
| Started | Oct 12 12:48:54 AM UTC 24 |
| Finished | Oct 12 12:53:28 AM UTC 24 |
| Peak memory | 214948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902095647 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_bit_bash.1902095647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/16.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.796838547 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 2345199202 ps |
| CPU time | 7.63 seconds |
| Started | Oct 12 12:48:54 AM UTC 24 |
| Finished | Oct 12 12:49:02 AM UTC 24 |
| Peak memory | 214972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796838547 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.796838547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/16.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1368656440 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 103659837 ps |
| CPU time | 1.08 seconds |
| Started | Oct 12 12:48:54 AM UTC 24 |
| Finished | Oct 12 12:48:56 AM UTC 24 |
| Peak memory | 214596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368656440 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.1368656440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/16.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.610984819 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 257983993 ps |
| CPU time | 5.28 seconds |
| Started | Oct 12 12:48:55 AM UTC 24 |
| Finished | Oct 12 12:49:01 AM UTC 24 |
| Peak memory | 215016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610984819 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_csr_outstanding.610984819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/16.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_errors.1612614969 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 69164459 ps |
| CPU time | 2.65 seconds |
| Started | Oct 12 12:48:55 AM UTC 24 |
| Finished | Oct 12 12:48:58 AM UTC 24 |
| Peak memory | 225392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612614969 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.1612614969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/16.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.190717859 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 3918686450 ps |
| CPU time | 13.24 seconds |
| Started | Oct 12 12:48:55 AM UTC 24 |
| Finished | Oct 12 12:49:09 AM UTC 24 |
| Peak memory | 225404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190717859 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.190717859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/16.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3050428346 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 147997252 ps |
| CPU time | 3.31 seconds |
| Started | Oct 12 12:48:59 AM UTC 24 |
| Finished | Oct 12 12:49:03 AM UTC 24 |
| Peak memory | 229492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3050428346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_ rand_reset.3050428346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/17.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_rw.3987261619 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 152055535 ps |
| CPU time | 2.44 seconds |
| Started | Oct 12 12:48:57 AM UTC 24 |
| Finished | Oct 12 12:49:01 AM UTC 24 |
| Peak memory | 225260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987261619 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.3987261619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/17.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1875076460 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 32118263641 ps |
| CPU time | 94.09 seconds |
| Started | Oct 12 12:48:56 AM UTC 24 |
| Finished | Oct 12 12:50:32 AM UTC 24 |
| Peak memory | 215028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875076460 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_bit_bash.1875076460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/17.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.642397750 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 2217833232 ps |
| CPU time | 4.65 seconds |
| Started | Oct 12 12:48:56 AM UTC 24 |
| Finished | Oct 12 12:49:02 AM UTC 24 |
| Peak memory | 214952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642397750 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.642397750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/17.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.4016455207 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 258034872 ps |
| CPU time | 1.58 seconds |
| Started | Oct 12 12:48:56 AM UTC 24 |
| Finished | Oct 12 12:48:59 AM UTC 24 |
| Peak memory | 214596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016455207 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.4016455207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/17.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3588501152 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 570519279 ps |
| CPU time | 7.19 seconds |
| Started | Oct 12 12:48:58 AM UTC 24 |
| Finished | Oct 12 12:49:07 AM UTC 24 |
| Peak memory | 215340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588501152 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same_csr_outstanding.3588501152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/17.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_errors.1332548309 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 209075670 ps |
| CPU time | 3.46 seconds |
| Started | Oct 12 12:48:57 AM UTC 24 |
| Finished | Oct 12 12:49:02 AM UTC 24 |
| Peak memory | 225564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332548309 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.1332548309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/17.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.79220874 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 1651720382 ps |
| CPU time | 8.81 seconds |
| Started | Oct 12 12:48:57 AM UTC 24 |
| Finished | Oct 12 12:49:07 AM UTC 24 |
| Peak memory | 225384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79220874 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.79220874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/17.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.190706996 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 83941951 ps |
| CPU time | 3.61 seconds |
| Started | Oct 12 12:49:05 AM UTC 24 |
| Finished | Oct 12 12:49:10 AM UTC 24 |
| Peak memory | 229440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=190706996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_r and_reset.190706996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/18.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_rw.1251226837 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 228241986 ps |
| CPU time | 1.47 seconds |
| Started | Oct 12 12:49:04 AM UTC 24 |
| Finished | Oct 12 12:49:06 AM UTC 24 |
| Peak memory | 224696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251226837 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.1251226837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/18.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.3918178633 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 44392430224 ps |
| CPU time | 32.23 seconds |
| Started | Oct 12 12:49:04 AM UTC 24 |
| Finished | Oct 12 12:49:37 AM UTC 24 |
| Peak memory | 215220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918178633 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_bit_bash.3918178633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/18.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2603507013 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 1268837667 ps |
| CPU time | 2.1 seconds |
| Started | Oct 12 12:49:04 AM UTC 24 |
| Finished | Oct 12 12:49:07 AM UTC 24 |
| Peak memory | 214884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603507013 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.2603507013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/18.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1214973793 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 204984869 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 12:48:59 AM UTC 24 |
| Finished | Oct 12 12:49:01 AM UTC 24 |
| Peak memory | 214596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214973793 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.1214973793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/18.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3046157347 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 232752006 ps |
| CPU time | 7.39 seconds |
| Started | Oct 12 12:49:04 AM UTC 24 |
| Finished | Oct 12 12:49:12 AM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046157347 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same_csr_outstanding.3046157347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/18.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_errors.1771599798 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 287822543 ps |
| CPU time | 5.2 seconds |
| Started | Oct 12 12:49:04 AM UTC 24 |
| Finished | Oct 12 12:49:10 AM UTC 24 |
| Peak memory | 225392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771599798 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.1771599798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/18.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3028295520 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 2651802742 ps |
| CPU time | 12.3 seconds |
| Started | Oct 12 12:49:04 AM UTC 24 |
| Finished | Oct 12 12:49:17 AM UTC 24 |
| Peak memory | 225656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028295520 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3028295520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/18.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1155321614 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 51497056 ps |
| CPU time | 2.78 seconds |
| Started | Oct 12 12:49:05 AM UTC 24 |
| Finished | Oct 12 12:49:09 AM UTC 24 |
| Peak memory | 227464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1155321614 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_ rand_reset.1155321614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/19.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_rw.4264025436 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 149790922 ps |
| CPU time | 2 seconds |
| Started | Oct 12 12:49:05 AM UTC 24 |
| Finished | Oct 12 12:49:08 AM UTC 24 |
| Peak memory | 224656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264025436 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.4264025436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/19.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.4071382961 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 77708006053 ps |
| CPU time | 128.41 seconds |
| Started | Oct 12 12:49:05 AM UTC 24 |
| Finished | Oct 12 12:51:16 AM UTC 24 |
| Peak memory | 215136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071382961 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_bit_bash.4071382961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/19.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2011121569 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 1707644404 ps |
| CPU time | 5.04 seconds |
| Started | Oct 12 12:49:05 AM UTC 24 |
| Finished | Oct 12 12:49:11 AM UTC 24 |
| Peak memory | 214884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011121569 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.2011121569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/19.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1613802276 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 188615282 ps |
| CPU time | 1.07 seconds |
| Started | Oct 12 12:49:05 AM UTC 24 |
| Finished | Oct 12 12:49:07 AM UTC 24 |
| Peak memory | 214596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613802276 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.1613802276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/19.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2463051192 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 700231501 ps |
| CPU time | 8.86 seconds |
| Started | Oct 12 12:49:05 AM UTC 24 |
| Finished | Oct 12 12:49:15 AM UTC 24 |
| Peak memory | 215056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463051192 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_csr_outstanding.2463051192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/19.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_errors.3156728523 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 748804992 ps |
| CPU time | 6.09 seconds |
| Started | Oct 12 12:49:05 AM UTC 24 |
| Finished | Oct 12 12:49:12 AM UTC 24 |
| Peak memory | 225568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156728523 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.3156728523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/19.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_intg_err.794445015 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 4975087037 ps |
| CPU time | 20.26 seconds |
| Started | Oct 12 12:49:05 AM UTC 24 |
| Finished | Oct 12 12:49:27 AM UTC 24 |
| Peak memory | 225576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794445015 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.794445015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/19.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2369502995 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 9492885705 ps |
| CPU time | 73.26 seconds |
| Started | Oct 12 12:47:14 AM UTC 24 |
| Finished | Oct 12 12:48:29 AM UTC 24 |
| Peak memory | 225344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369502995 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_aliasing.2369502995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/2.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1184585957 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 20455360676 ps |
| CPU time | 81.81 seconds |
| Started | Oct 12 12:47:27 AM UTC 24 |
| Finished | Oct 12 12:48:51 AM UTC 24 |
| Peak memory | 225312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184585957 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.1184585957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/2.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3411577005 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 453645905 ps |
| CPU time | 3.76 seconds |
| Started | Oct 12 12:47:24 AM UTC 24 |
| Finished | Oct 12 12:47:28 AM UTC 24 |
| Peak memory | 225400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411577005 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3411577005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/2.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3334680941 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 60834042 ps |
| CPU time | 4.93 seconds |
| Started | Oct 12 12:47:27 AM UTC 24 |
| Finished | Oct 12 12:47:33 AM UTC 24 |
| Peak memory | 229492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3334680941 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_r and_reset.3334680941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/2.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_rw.3281732804 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 266122414 ps |
| CPU time | 2.32 seconds |
| Started | Oct 12 12:47:26 AM UTC 24 |
| Finished | Oct 12 12:47:29 AM UTC 24 |
| Peak memory | 225468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281732804 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.3281732804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/2.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1390151380 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 73363029292 ps |
| CPU time | 234.4 seconds |
| Started | Oct 12 12:47:20 AM UTC 24 |
| Finished | Oct 12 12:51:18 AM UTC 24 |
| Peak memory | 215004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390151380 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_aliasing.1390151380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.725662681 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 22257826755 ps |
| CPU time | 35.69 seconds |
| Started | Oct 12 12:47:18 AM UTC 24 |
| Finished | Oct 12 12:47:55 AM UTC 24 |
| Peak memory | 215200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725662681 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_bit_bash.725662681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1360733352 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 2351372915 ps |
| CPU time | 5.02 seconds |
| Started | Oct 12 12:47:17 AM UTC 24 |
| Finished | Oct 12 12:47:23 AM UTC 24 |
| Peak memory | 214940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360733352 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_hw_reset.1360733352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1392966664 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 1440545727 ps |
| CPU time | 2.62 seconds |
| Started | Oct 12 12:47:18 AM UTC 24 |
| Finished | Oct 12 12:47:22 AM UTC 24 |
| Peak memory | 214968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392966664 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1392966664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2140318074 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 278797157 ps |
| CPU time | 2.48 seconds |
| Started | Oct 12 12:47:16 AM UTC 24 |
| Finished | Oct 12 12:47:19 AM UTC 24 |
| Peak memory | 214664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140318074 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_aliasing.2140318074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3070509277 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 8128727621 ps |
| CPU time | 32.24 seconds |
| Started | Oct 12 12:47:16 AM UTC 24 |
| Finished | Oct 12 12:47:50 AM UTC 24 |
| Peak memory | 215028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070509277 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_bit_bash.3070509277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1664329897 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 845329939 ps |
| CPU time | 1.6 seconds |
| Started | Oct 12 12:47:14 AM UTC 24 |
| Finished | Oct 12 12:47:16 AM UTC 24 |
| Peak memory | 214596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664329897 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_hw_reset.1664329897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3548187414 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 800593550 ps |
| CPU time | 2.12 seconds |
| Started | Oct 12 12:47:14 AM UTC 24 |
| Finished | Oct 12 12:47:17 AM UTC 24 |
| Peak memory | 214664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548187414 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.3548187414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_partial_access.643822123 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 95316149 ps |
| CPU time | 1.55 seconds |
| Started | Oct 12 12:47:24 AM UTC 24 |
| Finished | Oct 12 12:47:26 AM UTC 24 |
| Peak memory | 214596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643822123 -assert nopostproc +UVM_ TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_partial_access.643822123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/2.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_walk.1616155865 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 33801595 ps |
| CPU time | 1.2 seconds |
| Started | Oct 12 12:47:23 AM UTC 24 |
| Finished | Oct 12 12:47:25 AM UTC 24 |
| Peak memory | 214540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616155865 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.1616155865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/2.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2936375486 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 171074479 ps |
| CPU time | 7.23 seconds |
| Started | Oct 12 12:47:27 AM UTC 24 |
| Finished | Oct 12 12:47:35 AM UTC 24 |
| Peak memory | 215032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936375486 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_csr_outstanding.2936375486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/2.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_errors.2896763161 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 221540505 ps |
| CPU time | 3.29 seconds |
| Started | Oct 12 12:47:21 AM UTC 24 |
| Finished | Oct 12 12:47:26 AM UTC 24 |
| Peak memory | 225512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896763161 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.2896763161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/2.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1236231432 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 892627216 ps |
| CPU time | 32.35 seconds |
| Started | Oct 12 12:47:27 AM UTC 24 |
| Finished | Oct 12 12:48:01 AM UTC 24 |
| Peak memory | 214956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236231432 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_aliasing.1236231432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/3.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.952700992 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 1880945021 ps |
| CPU time | 59.48 seconds |
| Started | Oct 12 12:47:49 AM UTC 24 |
| Finished | Oct 12 12:48:50 AM UTC 24 |
| Peak memory | 214992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952700992 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.952700992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/3.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2302679901 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 1111943192 ps |
| CPU time | 2.42 seconds |
| Started | Oct 12 12:47:39 AM UTC 24 |
| Finished | Oct 12 12:47:43 AM UTC 24 |
| Peak memory | 225192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302679901 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.2302679901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/3.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3021429852 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 169495409 ps |
| CPU time | 3.11 seconds |
| Started | Oct 12 12:47:49 AM UTC 24 |
| Finished | Oct 12 12:47:53 AM UTC 24 |
| Peak memory | 225544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3021429852 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_r and_reset.3021429852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/3.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_rw.1040101570 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 103567001 ps |
| CPU time | 2.42 seconds |
| Started | Oct 12 12:47:40 AM UTC 24 |
| Finished | Oct 12 12:47:44 AM UTC 24 |
| Peak memory | 225276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040101570 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.1040101570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/3.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3255058965 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 42709072362 ps |
| CPU time | 44.42 seconds |
| Started | Oct 12 12:47:38 AM UTC 24 |
| Finished | Oct 12 12:48:24 AM UTC 24 |
| Peak memory | 214944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255058965 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_aliasing.3255058965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2674255854 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 32083102724 ps |
| CPU time | 104.8 seconds |
| Started | Oct 12 12:47:38 AM UTC 24 |
| Finished | Oct 12 12:49:25 AM UTC 24 |
| Peak memory | 214944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674255854 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_bit_bash.2674255854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2131987569 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 4138895754 ps |
| CPU time | 6.87 seconds |
| Started | Oct 12 12:47:37 AM UTC 24 |
| Finished | Oct 12 12:47:45 AM UTC 24 |
| Peak memory | 214944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131987569 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_hw_reset.2131987569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.237568655 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 783610881 ps |
| CPU time | 5.6 seconds |
| Started | Oct 12 12:47:38 AM UTC 24 |
| Finished | Oct 12 12:47:44 AM UTC 24 |
| Peak memory | 214960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237568655 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.237568655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1011315141 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 1116382375 ps |
| CPU time | 1.91 seconds |
| Started | Oct 12 12:47:37 AM UTC 24 |
| Finished | Oct 12 12:47:40 AM UTC 24 |
| Peak memory | 214596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011315141 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_aliasing.1011315141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.807048977 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 14484532768 ps |
| CPU time | 10.59 seconds |
| Started | Oct 12 12:47:37 AM UTC 24 |
| Finished | Oct 12 12:47:48 AM UTC 24 |
| Peak memory | 215216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807048977 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_bit_bash.807048977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2304659291 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 224631952 ps |
| CPU time | 1.3 seconds |
| Started | Oct 12 12:47:29 AM UTC 24 |
| Finished | Oct 12 12:47:31 AM UTC 24 |
| Peak memory | 214596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304659291 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_hw_reset.2304659291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2916218767 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 331933028 ps |
| CPU time | 1.38 seconds |
| Started | Oct 12 12:47:29 AM UTC 24 |
| Finished | Oct 12 12:47:32 AM UTC 24 |
| Peak memory | 214604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916218767 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.2916218767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3360031050 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 140878526 ps |
| CPU time | 1.03 seconds |
| Started | Oct 12 12:47:39 AM UTC 24 |
| Finished | Oct 12 12:47:41 AM UTC 24 |
| Peak memory | 214596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360031050 -assert nopostproc +UVM _TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_partial_access.3360031050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/3.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_walk.3678128933 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 160551712 ps |
| CPU time | 1.06 seconds |
| Started | Oct 12 12:47:38 AM UTC 24 |
| Finished | Oct 12 12:47:40 AM UTC 24 |
| Peak memory | 214588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678128933 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.3678128933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/3.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2092850686 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 522107303 ps |
| CPU time | 6.4 seconds |
| Started | Oct 12 12:47:49 AM UTC 24 |
| Finished | Oct 12 12:47:56 AM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092850686 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_csr_outstanding.2092850686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/3.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_errors.4118823022 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 90353573 ps |
| CPU time | 4.12 seconds |
| Started | Oct 12 12:47:38 AM UTC 24 |
| Finished | Oct 12 12:47:43 AM UTC 24 |
| Peak memory | 225340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118823022 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.4118823022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/3.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2795342171 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 3661266307 ps |
| CPU time | 13.36 seconds |
| Started | Oct 12 12:47:38 AM UTC 24 |
| Finished | Oct 12 12:47:53 AM UTC 24 |
| Peak memory | 225700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795342171 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.2795342171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/3.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1931670179 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 2901101997 ps |
| CPU time | 42.46 seconds |
| Started | Oct 12 12:47:49 AM UTC 24 |
| Finished | Oct 12 12:48:33 AM UTC 24 |
| Peak memory | 225344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931670179 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_aliasing.1931670179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/4.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.79081326 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 7700576155 ps |
| CPU time | 79.59 seconds |
| Started | Oct 12 12:47:57 AM UTC 24 |
| Finished | Oct 12 12:49:19 AM UTC 24 |
| Peak memory | 215100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79081326 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.79081326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/4.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1958678409 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 40919996 ps |
| CPU time | 3.68 seconds |
| Started | Oct 12 12:47:57 AM UTC 24 |
| Finished | Oct 12 12:48:02 AM UTC 24 |
| Peak memory | 225392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1958678409 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_r and_reset.1958678409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/4.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_rw.3580855917 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 39630173 ps |
| CPU time | 2.05 seconds |
| Started | Oct 12 12:47:57 AM UTC 24 |
| Finished | Oct 12 12:48:00 AM UTC 24 |
| Peak memory | 225404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580855917 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.3580855917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/4.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.4286214383 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 51436907267 ps |
| CPU time | 47.88 seconds |
| Started | Oct 12 12:47:50 AM UTC 24 |
| Finished | Oct 12 12:48:39 AM UTC 24 |
| Peak memory | 215004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286214383 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_aliasing.4286214383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3866627575 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 18661019799 ps |
| CPU time | 47.5 seconds |
| Started | Oct 12 12:47:49 AM UTC 24 |
| Finished | Oct 12 12:48:38 AM UTC 24 |
| Peak memory | 215216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866627575 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_bit_bash.3866627575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1635080816 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 3504085661 ps |
| CPU time | 22.4 seconds |
| Started | Oct 12 12:47:49 AM UTC 24 |
| Finished | Oct 12 12:48:13 AM UTC 24 |
| Peak memory | 215004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635080816 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_hw_reset.1635080816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2340286461 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 6408787615 ps |
| CPU time | 20.81 seconds |
| Started | Oct 12 12:47:49 AM UTC 24 |
| Finished | Oct 12 12:48:11 AM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340286461 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.2340286461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.4016394772 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 1441627540 ps |
| CPU time | 10.04 seconds |
| Started | Oct 12 12:47:49 AM UTC 24 |
| Finished | Oct 12 12:48:00 AM UTC 24 |
| Peak memory | 214664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016394772 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_aliasing.4016394772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3577065382 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 5139778091 ps |
| CPU time | 19.91 seconds |
| Started | Oct 12 12:47:49 AM UTC 24 |
| Finished | Oct 12 12:48:10 AM UTC 24 |
| Peak memory | 215024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577065382 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_bit_bash.3577065382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.691436721 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 143567604 ps |
| CPU time | 1.15 seconds |
| Started | Oct 12 12:47:49 AM UTC 24 |
| Finished | Oct 12 12:47:51 AM UTC 24 |
| Peak memory | 214592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691436721 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_hw_reset.691436721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2890963109 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 255412751 ps |
| CPU time | 2.32 seconds |
| Started | Oct 12 12:47:49 AM UTC 24 |
| Finished | Oct 12 12:47:53 AM UTC 24 |
| Peak memory | 214672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890963109 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.2890963109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3728287986 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 76174854 ps |
| CPU time | 1.02 seconds |
| Started | Oct 12 12:47:54 AM UTC 24 |
| Finished | Oct 12 12:47:56 AM UTC 24 |
| Peak memory | 214596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728287986 -assert nopostproc +UVM _TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_partial_access.3728287986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/4.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_walk.2135783457 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 59354130 ps |
| CPU time | 1.09 seconds |
| Started | Oct 12 12:47:54 AM UTC 24 |
| Finished | Oct 12 12:47:56 AM UTC 24 |
| Peak memory | 214588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135783457 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.2135783457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/4.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2277787462 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 3630117128 ps |
| CPU time | 7.78 seconds |
| Started | Oct 12 12:47:57 AM UTC 24 |
| Finished | Oct 12 12:48:06 AM UTC 24 |
| Peak memory | 215164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277787462 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_csr_outstanding.2277787462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/4.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2387764107 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 2978411751 ps |
| CPU time | 51.99 seconds |
| Started | Oct 12 12:47:51 AM UTC 24 |
| Finished | Oct 12 12:48:44 AM UTC 24 |
| Peak memory | 232164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2387764107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_re set.2387764107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/4.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_errors.628659125 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 3360463243 ps |
| CPU time | 8.84 seconds |
| Started | Oct 12 12:47:52 AM UTC 24 |
| Finished | Oct 12 12:48:02 AM UTC 24 |
| Peak memory | 225436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628659125 -assert nopostproc +UVM_TESTNAME=rv_dm_base _test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.628659125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/4.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3705832025 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 2714619644 ps |
| CPU time | 23.13 seconds |
| Started | Oct 12 12:47:54 AM UTC 24 |
| Finished | Oct 12 12:48:18 AM UTC 24 |
| Peak memory | 225660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705832025 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.3705832025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/4.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.719328435 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 100556744 ps |
| CPU time | 2.69 seconds |
| Started | Oct 12 12:48:03 AM UTC 24 |
| Finished | Oct 12 12:48:07 AM UTC 24 |
| Peak memory | 227432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=719328435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_ra nd_reset.719328435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/5.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_rw.1358709246 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 136463104 ps |
| CPU time | 2.65 seconds |
| Started | Oct 12 12:48:02 AM UTC 24 |
| Finished | Oct 12 12:48:05 AM UTC 24 |
| Peak memory | 225272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358709246 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.1358709246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/5.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.282712945 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 50210677684 ps |
| CPU time | 43.89 seconds |
| Started | Oct 12 12:48:00 AM UTC 24 |
| Finished | Oct 12 12:48:46 AM UTC 24 |
| Peak memory | 215024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282712945 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_bit_bash.282712945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/5.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.30285940 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 1057924269 ps |
| CPU time | 3.11 seconds |
| Started | Oct 12 12:48:00 AM UTC 24 |
| Finished | Oct 12 12:48:05 AM UTC 24 |
| Peak memory | 214960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30285940 -assert nopostproc +UVM_TESTNAME=rv_dm_ba se_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.30285940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/5.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3062092397 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 193270168 ps |
| CPU time | 1.4 seconds |
| Started | Oct 12 12:47:58 AM UTC 24 |
| Finished | Oct 12 12:48:01 AM UTC 24 |
| Peak memory | 214596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062092397 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.3062092397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/5.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2932295306 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 713963202 ps |
| CPU time | 12.42 seconds |
| Started | Oct 12 12:48:03 AM UTC 24 |
| Finished | Oct 12 12:48:16 AM UTC 24 |
| Peak memory | 215332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932295306 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_csr_outstanding.2932295306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/5.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.3482155557 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 5608963808 ps |
| CPU time | 28.93 seconds |
| Started | Oct 12 12:48:02 AM UTC 24 |
| Finished | Oct 12 12:48:32 AM UTC 24 |
| Peak memory | 229528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3482155557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_re set.3482155557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/5.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_errors.2100428244 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 108922927 ps |
| CPU time | 4.65 seconds |
| Started | Oct 12 12:48:02 AM UTC 24 |
| Finished | Oct 12 12:48:07 AM UTC 24 |
| Peak memory | 225400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100428244 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.2100428244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/5.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2669301328 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 3524129037 ps |
| CPU time | 34.55 seconds |
| Started | Oct 12 12:48:02 AM UTC 24 |
| Finished | Oct 12 12:48:38 AM UTC 24 |
| Peak memory | 225612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669301328 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.2669301328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/5.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1886278622 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 96316880 ps |
| CPU time | 3.48 seconds |
| Started | Oct 12 12:48:14 AM UTC 24 |
| Finished | Oct 12 12:48:18 AM UTC 24 |
| Peak memory | 229488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1886278622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_r and_reset.1886278622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/6.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_rw.1243600129 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 212243196 ps |
| CPU time | 3.69 seconds |
| Started | Oct 12 12:48:11 AM UTC 24 |
| Finished | Oct 12 12:48:16 AM UTC 24 |
| Peak memory | 225312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243600129 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.1243600129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/6.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.341576654 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 16384846310 ps |
| CPU time | 67.28 seconds |
| Started | Oct 12 12:48:07 AM UTC 24 |
| Finished | Oct 12 12:49:16 AM UTC 24 |
| Peak memory | 215136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341576654 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_bit_bash.341576654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/6.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2589922267 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 2466118804 ps |
| CPU time | 5.37 seconds |
| Started | Oct 12 12:48:06 AM UTC 24 |
| Finished | Oct 12 12:48:12 AM UTC 24 |
| Peak memory | 214952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589922267 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.2589922267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/6.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.831773483 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 158990649 ps |
| CPU time | 1.3 seconds |
| Started | Oct 12 12:48:05 AM UTC 24 |
| Finished | Oct 12 12:48:07 AM UTC 24 |
| Peak memory | 214596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831773483 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.831773483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/6.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.4055932034 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 295854419 ps |
| CPU time | 6.95 seconds |
| Started | Oct 12 12:48:12 AM UTC 24 |
| Finished | Oct 12 12:48:20 AM UTC 24 |
| Peak memory | 215208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055932034 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_csr_outstanding.4055932034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/6.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3276446640 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 1724138646 ps |
| CPU time | 32.73 seconds |
| Started | Oct 12 12:48:07 AM UTC 24 |
| Finished | Oct 12 12:48:41 AM UTC 24 |
| Peak memory | 225380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3276446640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_re set.3276446640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/6.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_errors.3023457315 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 247009201 ps |
| CPU time | 4 seconds |
| Started | Oct 12 12:48:08 AM UTC 24 |
| Finished | Oct 12 12:48:13 AM UTC 24 |
| Peak memory | 225572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023457315 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.3023457315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/6.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3443026284 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 109356553 ps |
| CPU time | 4.86 seconds |
| Started | Oct 12 12:48:21 AM UTC 24 |
| Finished | Oct 12 12:48:28 AM UTC 24 |
| Peak memory | 229708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3443026284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_r and_reset.3443026284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/7.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_rw.1847351399 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 216447571 ps |
| CPU time | 2.48 seconds |
| Started | Oct 12 12:48:19 AM UTC 24 |
| Finished | Oct 12 12:48:23 AM UTC 24 |
| Peak memory | 225460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847351399 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.1847351399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/7.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1597155800 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 10180617013 ps |
| CPU time | 5.61 seconds |
| Started | Oct 12 12:48:17 AM UTC 24 |
| Finished | Oct 12 12:48:23 AM UTC 24 |
| Peak memory | 215008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597155800 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_bit_bash.1597155800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/7.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1172435337 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 7970683472 ps |
| CPU time | 9.16 seconds |
| Started | Oct 12 12:48:15 AM UTC 24 |
| Finished | Oct 12 12:48:25 AM UTC 24 |
| Peak memory | 214952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172435337 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.1172435337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/7.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2600817227 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 469437044 ps |
| CPU time | 2.01 seconds |
| Started | Oct 12 12:48:14 AM UTC 24 |
| Finished | Oct 12 12:48:17 AM UTC 24 |
| Peak memory | 214572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600817227 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.2600817227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/7.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.992608018 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 4453576920 ps |
| CPU time | 6.8 seconds |
| Started | Oct 12 12:48:19 AM UTC 24 |
| Finished | Oct 12 12:48:27 AM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992608018 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_csr_outstanding.992608018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/7.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.4171876934 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 4054503671 ps |
| CPU time | 60.14 seconds |
| Started | Oct 12 12:48:17 AM UTC 24 |
| Finished | Oct 12 12:49:19 AM UTC 24 |
| Peak memory | 227496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=4171876934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_re set.4171876934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/7.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_errors.4089996480 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 339566675 ps |
| CPU time | 2.87 seconds |
| Started | Oct 12 12:48:18 AM UTC 24 |
| Finished | Oct 12 12:48:22 AM UTC 24 |
| Peak memory | 225356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089996480 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.4089996480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/7.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_intg_err.412180583 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 1656840090 ps |
| CPU time | 10.29 seconds |
| Started | Oct 12 12:48:18 AM UTC 24 |
| Finished | Oct 12 12:48:29 AM UTC 24 |
| Peak memory | 225320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412180583 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.412180583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/7.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1163139331 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 81325113 ps |
| CPU time | 2.05 seconds |
| Started | Oct 12 12:48:29 AM UTC 24 |
| Finished | Oct 12 12:48:32 AM UTC 24 |
| Peak memory | 227456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1163139331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_r and_reset.1163139331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/8.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_rw.2487655213 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 202511712 ps |
| CPU time | 3.02 seconds |
| Started | Oct 12 12:48:27 AM UTC 24 |
| Finished | Oct 12 12:48:31 AM UTC 24 |
| Peak memory | 225252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487655213 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.2487655213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/8.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.3381263043 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 2169317297 ps |
| CPU time | 9.73 seconds |
| Started | Oct 12 12:48:23 AM UTC 24 |
| Finished | Oct 12 12:48:34 AM UTC 24 |
| Peak memory | 214944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381263043 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_bit_bash.3381263043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/8.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3996265367 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 3648943665 ps |
| CPU time | 16.28 seconds |
| Started | Oct 12 12:48:23 AM UTC 24 |
| Finished | Oct 12 12:48:41 AM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996265367 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.3996265367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/8.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3970684554 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 485128987 ps |
| CPU time | 2.3 seconds |
| Started | Oct 12 12:48:22 AM UTC 24 |
| Finished | Oct 12 12:48:26 AM UTC 24 |
| Peak memory | 214668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970684554 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.3970684554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/8.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1415703311 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 799224222 ps |
| CPU time | 10.05 seconds |
| Started | Oct 12 12:48:28 AM UTC 24 |
| Finished | Oct 12 12:48:39 AM UTC 24 |
| Peak memory | 215100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415703311 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_csr_outstanding.1415703311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/8.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.301811914 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 12806430148 ps |
| CPU time | 77.59 seconds |
| Started | Oct 12 12:48:25 AM UTC 24 |
| Finished | Oct 12 12:49:44 AM UTC 24 |
| Peak memory | 229548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=301811914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.301811914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/8.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_errors.429311701 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 208785810 ps |
| CPU time | 3.74 seconds |
| Started | Oct 12 12:48:25 AM UTC 24 |
| Finished | Oct 12 12:48:29 AM UTC 24 |
| Peak memory | 225312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429311701 -assert nopostproc +UVM_TESTNAME=rv_dm_base _test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.429311701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/8.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_intg_err.4286252970 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 2640655024 ps |
| CPU time | 23.26 seconds |
| Started | Oct 12 12:48:26 AM UTC 24 |
| Finished | Oct 12 12:48:50 AM UTC 24 |
| Peak memory | 231588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286252970 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.4286252970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/8.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3498417604 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 145738388 ps |
| CPU time | 3.33 seconds |
| Started | Oct 12 12:48:32 AM UTC 24 |
| Finished | Oct 12 12:48:37 AM UTC 24 |
| Peak memory | 229492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3498417604 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_r and_reset.3498417604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/9.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_rw.2983545397 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 46367516 ps |
| CPU time | 2.09 seconds |
| Started | Oct 12 12:48:31 AM UTC 24 |
| Finished | Oct 12 12:48:35 AM UTC 24 |
| Peak memory | 225336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983545397 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.2983545397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/9.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3720890018 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 41476654406 ps |
| CPU time | 22.75 seconds |
| Started | Oct 12 12:48:30 AM UTC 24 |
| Finished | Oct 12 12:48:54 AM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720890018 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_bit_bash.3720890018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/9.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3782046630 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 1386103238 ps |
| CPU time | 9.56 seconds |
| Started | Oct 12 12:48:30 AM UTC 24 |
| Finished | Oct 12 12:48:41 AM UTC 24 |
| Peak memory | 214968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782046630 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.3782046630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/9.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2175147254 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 146264595 ps |
| CPU time | 1.87 seconds |
| Started | Oct 12 12:48:29 AM UTC 24 |
| Finished | Oct 12 12:48:32 AM UTC 24 |
| Peak memory | 214604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175147254 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.2175147254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/9.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1919006149 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 1824430833 ps |
| CPU time | 7.29 seconds |
| Started | Oct 12 12:48:32 AM UTC 24 |
| Finished | Oct 12 12:48:41 AM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919006149 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_csr_outstanding.1919006149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/9.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3028215423 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 3686630190 ps |
| CPU time | 48.44 seconds |
| Started | Oct 12 12:48:30 AM UTC 24 |
| Finished | Oct 12 12:49:20 AM UTC 24 |
| Peak memory | 229504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3028215423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_re set.3028215423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/9.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_errors.2290441094 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 1708091508 ps |
| CPU time | 8.03 seconds |
| Started | Oct 12 12:48:30 AM UTC 24 |
| Finished | Oct 12 12:48:39 AM UTC 24 |
| Peak memory | 225380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290441094 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.2290441094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/9.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3198973020 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 3736961823 ps |
| CPU time | 27.41 seconds |
| Started | Oct 12 12:48:30 AM UTC 24 |
| Finished | Oct 12 12:48:59 AM UTC 24 |
| Peak memory | 225576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198973020 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.3198973020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/9.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.3561398442 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 165320010 ps |
| CPU time | 1.66 seconds |
| Started | Oct 12 12:49:12 AM UTC 24 |
| Finished | Oct 12 12:49:14 AM UTC 24 |
| Peak memory | 214888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561398442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_abstractcmd_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.3561398442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_abstractcmd_status/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.390074279 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 87800417 ps |
| CPU time | 1.04 seconds |
| Started | Oct 12 12:49:13 AM UTC 24 |
| Finished | Oct 12 12:49:15 AM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390074279 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.390074279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_busy.193097800 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 221024587 ps |
| CPU time | 2.54 seconds |
| Started | Oct 12 12:49:06 AM UTC 24 |
| Finished | Oct 12 12:49:09 AM UTC 24 |
| Peak memory | 215028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193097800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.193097800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_cmderr_busy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.3966363305 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 115328680 ps |
| CPU time | 1.27 seconds |
| Started | Oct 12 12:49:07 AM UTC 24 |
| Finished | Oct 12 12:49:09 AM UTC 24 |
| Peak memory | 214436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966363305 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.3966363305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_cmderr_not_supported/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_dataaddr_rw_access.906763810 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 320932617 ps |
| CPU time | 1.26 seconds |
| Started | Oct 12 12:49:09 AM UTC 24 |
| Finished | Oct 12 12:49:11 AM UTC 24 |
| Peak memory | 214892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906763810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_dataaddr_rw_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.906763810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_dataaddr_rw_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_debug_disabled.1898310505 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 118057607 ps |
| CPU time | 1.5 seconds |
| Started | Oct 12 12:49:12 AM UTC 24 |
| Finished | Oct 12 12:49:14 AM UTC 24 |
| Peak memory | 237228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898310505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.1898310505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.1268599747 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 2805508975 ps |
| CPU time | 5.41 seconds |
| Started | Oct 12 12:49:05 AM UTC 24 |
| Finished | Oct 12 12:49:12 AM UTC 24 |
| Peak memory | 215588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268599747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_tl_access.1268599747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_hart_unavail.4240367799 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 87233850 ps |
| CPU time | 1.16 seconds |
| Started | Oct 12 12:49:09 AM UTC 24 |
| Finished | Oct 12 12:49:11 AM UTC 24 |
| Peak memory | 214948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240367799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.4240367799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_hartsel_warl.1474574493 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 96073845 ps |
| CPU time | 1.12 seconds |
| Started | Oct 12 12:49:12 AM UTC 24 |
| Finished | Oct 12 12:49:14 AM UTC 24 |
| Peak memory | 214948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474574493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.1474574493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_hartsel_warl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.1834934824 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 187695867 ps |
| CPU time | 1.08 seconds |
| Started | Oct 12 12:49:10 AM UTC 24 |
| Finished | Oct 12 12:49:12 AM UTC 24 |
| Peak memory | 214952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834934824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.1834934824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.183978035 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 2173212087 ps |
| CPU time | 2.65 seconds |
| Started | Oct 12 12:49:10 AM UTC 24 |
| Finished | Oct 12 12:49:14 AM UTC 24 |
| Peak memory | 215024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183978035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.183978035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_dm_inactive/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_hard_reset.320510854 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 419113050 ps |
| CPU time | 1.44 seconds |
| Started | Oct 12 12:49:11 AM UTC 24 |
| Finished | Oct 12 12:49:14 AM UTC 24 |
| Peak memory | 214952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320510854 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.320510854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_hard_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_idle_hint.3181334388 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 330082624 ps |
| CPU time | 1.06 seconds |
| Started | Oct 12 12:49:10 AM UTC 24 |
| Finished | Oct 12 12:49:12 AM UTC 24 |
| Peak memory | 214888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181334388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.3181334388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_idle_hint/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_halted.204445550 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 451712781 ps |
| CPU time | 1.52 seconds |
| Started | Oct 12 12:49:08 AM UTC 24 |
| Finished | Oct 12 12:49:10 AM UTC 24 |
| Peak memory | 215016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204445550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.204445550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_halted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.243214923 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 155275040 ps |
| CPU time | 1.42 seconds |
| Started | Oct 12 12:49:12 AM UTC 24 |
| Finished | Oct 12 12:49:14 AM UTC 24 |
| Peak memory | 214952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243214923 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_progbuf_read_write_execute_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.243214923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_progbuf_read_write_execute/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_tl_access.1638603491 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 6204882863 ps |
| CPU time | 6.02 seconds |
| Started | Oct 12 12:49:05 AM UTC 24 |
| Finished | Oct 12 12:49:13 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638603491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.1638603491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.1966565920 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 18293605 ps |
| CPU time | 1.05 seconds |
| Started | Oct 12 12:49:13 AM UTC 24 |
| Finished | Oct 12 12:49:15 AM UTC 24 |
| Peak memory | 214956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966565920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_scanmode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 0.rv_dm_scanmode.1966565920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_scanmode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_smoke.1663290457 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 678256786 ps |
| CPU time | 3.14 seconds |
| Started | Oct 12 12:49:05 AM UTC 24 |
| Finished | Oct 12 12:49:10 AM UTC 24 |
| Peak memory | 215296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663290457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.1663290457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.1873838397 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 71434941 ps |
| CPU time | 1.22 seconds |
| Started | Oct 12 12:49:13 AM UTC 24 |
| Finished | Oct 12 12:49:15 AM UTC 24 |
| Peak memory | 224748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873838397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sparse_lc_gate_fsm.1873838397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_sparse_lc_gate_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.1077755661 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 2776353381 ps |
| CPU time | 32.95 seconds |
| Started | Oct 12 12:49:13 AM UTC 24 |
| Finished | Oct 12 12:49:47 AM UTC 24 |
| Peak memory | 232364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1077755661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stres s_all_with_rand_reset.1077755661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_abstractcmd_status.3489744117 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 133926895 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 12:49:17 AM UTC 24 |
| Finished | Oct 12 12:49:19 AM UTC 24 |
| Peak memory | 214888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489744117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_abstractcmd_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.3489744117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_abstractcmd_status/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_autoincr_sba_tl_access.2258852675 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 2850401883 ps |
| CPU time | 6.02 seconds |
| Started | Oct 12 12:49:14 AM UTC 24 |
| Finished | Oct 12 12:49:22 AM UTC 24 |
| Peak memory | 215716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258852675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.2258852675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_bad_sba_tl_access.1900027430 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 10454370079 ps |
| CPU time | 28.13 seconds |
| Started | Oct 12 12:49:14 AM UTC 24 |
| Finished | Oct 12 12:49:44 AM UTC 24 |
| Peak memory | 225896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900027430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.1900027430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_buffered_enable.3989750390 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 375350943 ps |
| CPU time | 1.45 seconds |
| Started | Oct 12 12:49:19 AM UTC 24 |
| Finished | Oct 12 12:49:21 AM UTC 24 |
| Peak memory | 256312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989750390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_buffered_enable.3989750390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_busy.799211618 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 336015681 ps |
| CPU time | 1.31 seconds |
| Started | Oct 12 12:49:14 AM UTC 24 |
| Finished | Oct 12 12:49:17 AM UTC 24 |
| Peak memory | 214892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799211618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.799211618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_cmderr_busy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.381812547 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 246690330 ps |
| CPU time | 1.68 seconds |
| Started | Oct 12 12:49:16 AM UTC 24 |
| Finished | Oct 12 12:49:18 AM UTC 24 |
| Peak memory | 214956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381812547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_cmderr_exception_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.381812547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_cmderr_exception/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.152295087 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 654631759 ps |
| CPU time | 1.83 seconds |
| Started | Oct 12 12:49:16 AM UTC 24 |
| Finished | Oct 12 12:49:19 AM UTC 24 |
| Peak memory | 214892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152295087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_cmderr_halt_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.152295087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_cmderr_halt_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_not_supported.4033499379 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 175384988 ps |
| CPU time | 1.54 seconds |
| Started | Oct 12 12:49:15 AM UTC 24 |
| Finished | Oct 12 12:49:17 AM UTC 24 |
| Peak memory | 214952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033499379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.4033499379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_cmderr_not_supported/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_dataaddr_rw_access.3989805743 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 95619717 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 12:49:16 AM UTC 24 |
| Finished | Oct 12 12:49:18 AM UTC 24 |
| Peak memory | 214888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989805743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.3989805743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_dataaddr_rw_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_debug_disabled.4133110586 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 67940361 ps |
| CPU time | 1.01 seconds |
| Started | Oct 12 12:49:19 AM UTC 24 |
| Finished | Oct 12 12:49:21 AM UTC 24 |
| Peak memory | 236988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133110586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.4133110586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.1814610871 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 2916253559 ps |
| CPU time | 7.09 seconds |
| Started | Oct 12 12:49:14 AM UTC 24 |
| Finished | Oct 12 12:49:23 AM UTC 24 |
| Peak memory | 215644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814610871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_tl_access.1814610871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.3349367089 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 221383617 ps |
| CPU time | 0.98 seconds |
| Started | Oct 12 12:49:19 AM UTC 24 |
| Finished | Oct 12 12:49:21 AM UTC 24 |
| Peak memory | 214900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349367089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.3349367089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_dmi_failed_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_halt_resume_whereto.3676867182 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 799084151 ps |
| CPU time | 1.58 seconds |
| Started | Oct 12 12:49:16 AM UTC 24 |
| Finished | Oct 12 12:49:19 AM UTC 24 |
| Peak memory | 214952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676867182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.3676867182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_hart_unavail.4143149274 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 247393626 ps |
| CPU time | 2.42 seconds |
| Started | Oct 12 12:49:16 AM UTC 24 |
| Finished | Oct 12 12:49:19 AM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143149274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.4143149274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.3241150217 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 384202855 ps |
| CPU time | 2.34 seconds |
| Started | Oct 12 12:49:17 AM UTC 24 |
| Finished | Oct 12 12:49:21 AM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241150217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.3241150217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1932135073 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 576268076 ps |
| CPU time | 2.97 seconds |
| Started | Oct 12 12:49:17 AM UTC 24 |
| Finished | Oct 12 12:49:21 AM UTC 24 |
| Peak memory | 214892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932135073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.1932135073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_dm_inactive/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_hard_reset.1359726084 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 311272876 ps |
| CPU time | 1.67 seconds |
| Started | Oct 12 12:49:17 AM UTC 24 |
| Finished | Oct 12 12:49:20 AM UTC 24 |
| Peak memory | 214952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359726084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.1359726084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_hard_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1252591298 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 151594692 ps |
| CPU time | 1.24 seconds |
| Started | Oct 12 12:49:17 AM UTC 24 |
| Finished | Oct 12 12:49:19 AM UTC 24 |
| Peak memory | 214888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252591298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.1252591298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_idle_hint/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_halted.3362046730 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 145893396 ps |
| CPU time | 0.97 seconds |
| Started | Oct 12 12:49:16 AM UTC 24 |
| Finished | Oct 12 12:49:18 AM UTC 24 |
| Peak memory | 214952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362046730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.3362046730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_mem_tl_access_halted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_resuming.1729047111 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 848182458 ps |
| CPU time | 3.3 seconds |
| Started | Oct 12 12:49:16 AM UTC 24 |
| Finished | Oct 12 12:49:20 AM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729047111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.1729047111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_mem_tl_access_resuming/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_ndmreset_req.692312521 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 467218832 ps |
| CPU time | 1.97 seconds |
| Started | Oct 12 12:49:17 AM UTC 24 |
| Finished | Oct 12 12:49:20 AM UTC 24 |
| Peak memory | 224752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692312521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.692312521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_ndmreset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_progbuf_read_write_execute.4093052348 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 268731083 ps |
| CPU time | 1.48 seconds |
| Started | Oct 12 12:49:19 AM UTC 24 |
| Finished | Oct 12 12:49:21 AM UTC 24 |
| Peak memory | 214960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093052348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_progbuf_read_write_execute_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_d m-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.4093052348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_progbuf_read_write_execute/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_rom_read_access.288678305 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 187107420 ps |
| CPU time | 1.33 seconds |
| Started | Oct 12 12:49:19 AM UTC 24 |
| Finished | Oct 12 12:49:21 AM UTC 24 |
| Peak memory | 224696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288678305 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_rom_read_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.288678305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_rom_read_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_debug_disabled.1285788414 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 3184859235 ps |
| CPU time | 9.59 seconds |
| Started | Oct 12 12:49:16 AM UTC 24 |
| Finished | Oct 12 12:49:27 AM UTC 24 |
| Peak memory | 215416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285788414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.1285788414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_sba_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_tl_access.1802335519 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 1966143613 ps |
| CPU time | 4.24 seconds |
| Started | Oct 12 12:49:14 AM UTC 24 |
| Finished | Oct 12 12:49:20 AM UTC 24 |
| Peak memory | 215532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802335519 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.1802335519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_sec_cm.4226606697 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 1484287510 ps |
| CPU time | 4.88 seconds |
| Started | Oct 12 12:49:20 AM UTC 24 |
| Finished | Oct 12 12:49:26 AM UTC 24 |
| Peak memory | 256020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226606697 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.4226606697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_smoke.3855863399 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 333031530 ps |
| CPU time | 1.08 seconds |
| Started | Oct 12 12:49:13 AM UTC 24 |
| Finished | Oct 12 12:49:15 AM UTC 24 |
| Peak memory | 215012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855863399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.3855863399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/1.rv_dm_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/10.rv_dm_alert_test.3673993664 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 96941072 ps |
| CPU time | 1.16 seconds |
| Started | Oct 12 12:49:45 AM UTC 24 |
| Finished | Oct 12 12:49:47 AM UTC 24 |
| Peak memory | 214804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673993664 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.3673993664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/10.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/10.rv_dm_autoincr_sba_tl_access.3866969997 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 15888821289 ps |
| CPU time | 52.71 seconds |
| Started | Oct 12 12:49:45 AM UTC 24 |
| Finished | Oct 12 12:50:39 AM UTC 24 |
| Peak memory | 226212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866969997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.3866969997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/10.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/10.rv_dm_bad_sba_tl_access.908956063 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 3458437314 ps |
| CPU time | 6.81 seconds |
| Started | Oct 12 12:49:45 AM UTC 24 |
| Finished | Oct 12 12:49:53 AM UTC 24 |
| Peak memory | 215952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908956063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.908956063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/10.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.2697423496 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 2951334750 ps |
| CPU time | 4.86 seconds |
| Started | Oct 12 12:49:44 AM UTC 24 |
| Finished | Oct 12 12:49:50 AM UTC 24 |
| Peak memory | 215508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697423496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_tl_access.2697423496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/10.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/10.rv_dm_sba_tl_access.1758561738 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 1358708076 ps |
| CPU time | 2.4 seconds |
| Started | Oct 12 12:49:43 AM UTC 24 |
| Finished | Oct 12 12:49:46 AM UTC 24 |
| Peak memory | 215768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758561738 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.1758561738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/10.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/10.rv_dm_stress_all.249983989 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1987890946 ps |
| CPU time | 3.11 seconds |
| Started | Oct 12 12:49:45 AM UTC 24 |
| Finished | Oct 12 12:49:49 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249983989 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.249983989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/10.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/11.rv_dm_alert_test.2994679025 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 35982042 ps |
| CPU time | 1.07 seconds |
| Started | Oct 12 12:49:49 AM UTC 24 |
| Finished | Oct 12 12:49:51 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994679025 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.2994679025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/11.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/11.rv_dm_autoincr_sba_tl_access.2751116444 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 40712251059 ps |
| CPU time | 62.25 seconds |
| Started | Oct 12 12:49:49 AM UTC 24 |
| Finished | Oct 12 12:50:53 AM UTC 24 |
| Peak memory | 232712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751116444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.2751116444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/11.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/11.rv_dm_bad_sba_tl_access.2997857659 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 1441730021 ps |
| CPU time | 3.41 seconds |
| Started | Oct 12 12:49:49 AM UTC 24 |
| Finished | Oct 12 12:49:53 AM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997857659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.2997857659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/11.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.824860887 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 1930877310 ps |
| CPU time | 4.63 seconds |
| Started | Oct 12 12:49:49 AM UTC 24 |
| Finished | Oct 12 12:49:55 AM UTC 24 |
| Peak memory | 215452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824860887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_tl_access.824860887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/11.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/11.rv_dm_sba_tl_access.2069885953 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 2041478094 ps |
| CPU time | 8.73 seconds |
| Started | Oct 12 12:49:49 AM UTC 24 |
| Finished | Oct 12 12:49:59 AM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069885953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.2069885953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/11.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/12.rv_dm_alert_test.3271387588 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 88844262 ps |
| CPU time | 1.45 seconds |
| Started | Oct 12 12:49:49 AM UTC 24 |
| Finished | Oct 12 12:49:52 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271387588 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.3271387588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/12.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/12.rv_dm_bad_sba_tl_access.2253904233 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 4500552017 ps |
| CPU time | 7.48 seconds |
| Started | Oct 12 12:49:49 AM UTC 24 |
| Finished | Oct 12 12:49:58 AM UTC 24 |
| Peak memory | 215588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253904233 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.2253904233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/12.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.3081012904 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 9190575109 ps |
| CPU time | 8.49 seconds |
| Started | Oct 12 12:49:49 AM UTC 24 |
| Finished | Oct 12 12:49:59 AM UTC 24 |
| Peak memory | 226084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081012904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_tl_access.3081012904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/12.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/12.rv_dm_sba_tl_access.2786316347 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 5338844315 ps |
| CPU time | 13.95 seconds |
| Started | Oct 12 12:49:49 AM UTC 24 |
| Finished | Oct 12 12:50:04 AM UTC 24 |
| Peak memory | 215568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786316347 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.2786316347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/12.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/13.rv_dm_alert_test.1613324102 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 92866893 ps |
| CPU time | 1.03 seconds |
| Started | Oct 12 12:49:54 AM UTC 24 |
| Finished | Oct 12 12:49:56 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613324102 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.1613324102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/13.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/13.rv_dm_bad_sba_tl_access.4232021745 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 2736273281 ps |
| CPU time | 8.2 seconds |
| Started | Oct 12 12:49:50 AM UTC 24 |
| Finished | Oct 12 12:49:59 AM UTC 24 |
| Peak memory | 215580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232021745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.4232021745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/13.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.212710622 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 7883986096 ps |
| CPU time | 15.58 seconds |
| Started | Oct 12 12:49:50 AM UTC 24 |
| Finished | Oct 12 12:50:06 AM UTC 24 |
| Peak memory | 215640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212710622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_tl_access.212710622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/13.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/13.rv_dm_sba_tl_access.286591123 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 12207313912 ps |
| CPU time | 15.83 seconds |
| Started | Oct 12 12:49:49 AM UTC 24 |
| Finished | Oct 12 12:50:07 AM UTC 24 |
| Peak memory | 215568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286591123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.286591123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/13.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/13.rv_dm_stress_all.1865422093 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 3767021687 ps |
| CPU time | 13.22 seconds |
| Started | Oct 12 12:49:54 AM UTC 24 |
| Finished | Oct 12 12:50:08 AM UTC 24 |
| Peak memory | 215488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865422093 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.1865422093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/13.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/14.rv_dm_alert_test.2357632260 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 64229490 ps |
| CPU time | 1.01 seconds |
| Started | Oct 12 12:49:56 AM UTC 24 |
| Finished | Oct 12 12:49:58 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357632260 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.2357632260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/14.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/14.rv_dm_autoincr_sba_tl_access.172553003 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 31157787294 ps |
| CPU time | 76.82 seconds |
| Started | Oct 12 12:49:54 AM UTC 24 |
| Finished | Oct 12 12:51:12 AM UTC 24 |
| Peak memory | 215644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172553003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.172553003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/14.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/14.rv_dm_bad_sba_tl_access.1302436240 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 5401136615 ps |
| CPU time | 27.42 seconds |
| Started | Oct 12 12:49:54 AM UTC 24 |
| Finished | Oct 12 12:50:22 AM UTC 24 |
| Peak memory | 226148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302436240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.1302436240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/14.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.1284752693 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 1323405046 ps |
| CPU time | 5.46 seconds |
| Started | Oct 12 12:49:54 AM UTC 24 |
| Finished | Oct 12 12:50:00 AM UTC 24 |
| Peak memory | 215452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284752693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_tl_access.1284752693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/14.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/14.rv_dm_sba_tl_access.1526244697 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 9490431357 ps |
| CPU time | 36.36 seconds |
| Started | Oct 12 12:49:54 AM UTC 24 |
| Finished | Oct 12 12:50:31 AM UTC 24 |
| Peak memory | 215852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526244697 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.1526244697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/14.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/14.rv_dm_stress_all.2388874352 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 4094555738 ps |
| CPU time | 10.38 seconds |
| Started | Oct 12 12:49:55 AM UTC 24 |
| Finished | Oct 12 12:50:06 AM UTC 24 |
| Peak memory | 225992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388874352 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.2388874352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/14.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/15.rv_dm_alert_test.1279225860 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 41281516 ps |
| CPU time | 1.03 seconds |
| Started | Oct 12 12:49:58 AM UTC 24 |
| Finished | Oct 12 12:50:01 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279225860 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.1279225860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/15.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/15.rv_dm_autoincr_sba_tl_access.1561492353 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 2921642530 ps |
| CPU time | 13.44 seconds |
| Started | Oct 12 12:49:57 AM UTC 24 |
| Finished | Oct 12 12:50:12 AM UTC 24 |
| Peak memory | 215652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561492353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.1561492353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/15.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/15.rv_dm_bad_sba_tl_access.2308737883 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 1036606741 ps |
| CPU time | 4.15 seconds |
| Started | Oct 12 12:49:57 AM UTC 24 |
| Finished | Oct 12 12:50:03 AM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308737883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.2308737883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/15.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2395776876 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 4248456895 ps |
| CPU time | 9.96 seconds |
| Started | Oct 12 12:49:57 AM UTC 24 |
| Finished | Oct 12 12:50:08 AM UTC 24 |
| Peak memory | 215644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395776876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_tl_access.2395776876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/15.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/15.rv_dm_sba_tl_access.2940057416 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 5077588404 ps |
| CPU time | 6.32 seconds |
| Started | Oct 12 12:49:56 AM UTC 24 |
| Finished | Oct 12 12:50:03 AM UTC 24 |
| Peak memory | 215520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940057416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.2940057416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/15.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/16.rv_dm_alert_test.2933273757 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 86987644 ps |
| CPU time | 1.04 seconds |
| Started | Oct 12 12:50:00 AM UTC 24 |
| Finished | Oct 12 12:50:02 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933273757 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.2933273757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/16.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/16.rv_dm_autoincr_sba_tl_access.2540684403 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 798290935 ps |
| CPU time | 5.06 seconds |
| Started | Oct 12 12:50:00 AM UTC 24 |
| Finished | Oct 12 12:50:06 AM UTC 24 |
| Peak memory | 226020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540684403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.2540684403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/16.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/16.rv_dm_bad_sba_tl_access.3525037802 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 7282836964 ps |
| CPU time | 5.97 seconds |
| Started | Oct 12 12:50:00 AM UTC 24 |
| Finished | Oct 12 12:50:07 AM UTC 24 |
| Peak memory | 225868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525037802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.3525037802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/16.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.3079187574 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 7756721585 ps |
| CPU time | 17.33 seconds |
| Started | Oct 12 12:50:00 AM UTC 24 |
| Finished | Oct 12 12:50:18 AM UTC 24 |
| Peak memory | 215644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079187574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_tl_access.3079187574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/16.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/16.rv_dm_sba_tl_access.3547999371 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 900484966 ps |
| CPU time | 5.36 seconds |
| Started | Oct 12 12:49:59 AM UTC 24 |
| Finished | Oct 12 12:50:05 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547999371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.3547999371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/16.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/17.rv_dm_alert_test.1629794201 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 110950017 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 12:50:04 AM UTC 24 |
| Finished | Oct 12 12:50:06 AM UTC 24 |
| Peak memory | 214772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629794201 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.1629794201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/17.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/17.rv_dm_autoincr_sba_tl_access.2733242742 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 5343633040 ps |
| CPU time | 7.35 seconds |
| Started | Oct 12 12:50:03 AM UTC 24 |
| Finished | Oct 12 12:50:11 AM UTC 24 |
| Peak memory | 225884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733242742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.2733242742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/17.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/17.rv_dm_bad_sba_tl_access.3334908733 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 4399513337 ps |
| CPU time | 6.39 seconds |
| Started | Oct 12 12:50:02 AM UTC 24 |
| Finished | Oct 12 12:50:10 AM UTC 24 |
| Peak memory | 226148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334908733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.3334908733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/17.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.4283223788 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 3819688074 ps |
| CPU time | 14.44 seconds |
| Started | Oct 12 12:50:01 AM UTC 24 |
| Finished | Oct 12 12:50:17 AM UTC 24 |
| Peak memory | 215636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283223788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_tl_access.4283223788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/17.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/17.rv_dm_sba_tl_access.3001137534 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 4266684614 ps |
| CPU time | 15.2 seconds |
| Started | Oct 12 12:50:01 AM UTC 24 |
| Finished | Oct 12 12:50:18 AM UTC 24 |
| Peak memory | 215592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001137534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.3001137534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/17.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/18.rv_dm_alert_test.2129313162 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 51854240 ps |
| CPU time | 1.16 seconds |
| Started | Oct 12 12:50:06 AM UTC 24 |
| Finished | Oct 12 12:50:09 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129313162 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.2129313162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/18.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/18.rv_dm_bad_sba_tl_access.3670966756 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 6427851396 ps |
| CPU time | 11.69 seconds |
| Started | Oct 12 12:50:06 AM UTC 24 |
| Finished | Oct 12 12:50:19 AM UTC 24 |
| Peak memory | 225956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670966756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.3670966756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/18.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.3778038520 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 5649941885 ps |
| CPU time | 7.18 seconds |
| Started | Oct 12 12:50:05 AM UTC 24 |
| Finished | Oct 12 12:50:13 AM UTC 24 |
| Peak memory | 226076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778038520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_tl_access.3778038520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/18.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/18.rv_dm_sba_tl_access.606613115 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 6961511349 ps |
| CPU time | 26.34 seconds |
| Started | Oct 12 12:50:05 AM UTC 24 |
| Finished | Oct 12 12:50:33 AM UTC 24 |
| Peak memory | 215656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606613115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.606613115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/18.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/18.rv_dm_stress_all.286886764 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4263275359 ps |
| CPU time | 7.46 seconds |
| Started | Oct 12 12:50:06 AM UTC 24 |
| Finished | Oct 12 12:50:15 AM UTC 24 |
| Peak memory | 215688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286886764 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.286886764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/18.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/19.rv_dm_alert_test.1565739122 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 45576115 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 12:50:08 AM UTC 24 |
| Finished | Oct 12 12:50:10 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565739122 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.1565739122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/19.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/19.rv_dm_bad_sba_tl_access.740924073 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 7510214323 ps |
| CPU time | 34.97 seconds |
| Started | Oct 12 12:50:08 AM UTC 24 |
| Finished | Oct 12 12:50:44 AM UTC 24 |
| Peak memory | 226160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740924073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.740924073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/19.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/19.rv_dm_sba_tl_access.4146131655 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 1579891057 ps |
| CPU time | 6.52 seconds |
| Started | Oct 12 12:50:08 AM UTC 24 |
| Finished | Oct 12 12:50:15 AM UTC 24 |
| Peak memory | 215464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146131655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.4146131655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/19.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.3635002145 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 147137683 ps |
| CPU time | 1 seconds |
| Started | Oct 12 12:49:22 AM UTC 24 |
| Finished | Oct 12 12:49:24 AM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635002145 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.3635002145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/2.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.2583059737 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 39860572085 ps |
| CPU time | 132.16 seconds |
| Started | Oct 12 12:49:20 AM UTC 24 |
| Finished | Oct 12 12:51:35 AM UTC 24 |
| Peak memory | 225820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583059737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.2583059737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/2.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.3648743159 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 15791412557 ps |
| CPU time | 16.96 seconds |
| Started | Oct 12 12:49:20 AM UTC 24 |
| Finished | Oct 12 12:49:38 AM UTC 24 |
| Peak memory | 225960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648743159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.3648743159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/2.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.2453613392 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 123581286 ps |
| CPU time | 1.3 seconds |
| Started | Oct 12 12:49:21 AM UTC 24 |
| Finished | Oct 12 12:49:24 AM UTC 24 |
| Peak memory | 256824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453613392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_buffered_enable.2453613392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/2.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.2369808847 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 930070615 ps |
| CPU time | 2.99 seconds |
| Started | Oct 12 12:49:20 AM UTC 24 |
| Finished | Oct 12 12:49:24 AM UTC 24 |
| Peak memory | 215844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369808847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_tl_access.2369808847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/2.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.3064451789 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1122131963 ps |
| CPU time | 2.06 seconds |
| Started | Oct 12 12:49:21 AM UTC 24 |
| Finished | Oct 12 12:49:24 AM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064451789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_halt_resume_whereto.3064451789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/2.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.1135841512 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 69421057 ps |
| CPU time | 0.87 seconds |
| Started | Oct 12 12:49:20 AM UTC 24 |
| Finished | Oct 12 12:49:22 AM UTC 24 |
| Peak memory | 214948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135841512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.1135841512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/2.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.3114896315 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 4455502072 ps |
| CPU time | 14.17 seconds |
| Started | Oct 12 12:49:20 AM UTC 24 |
| Finished | Oct 12 12:49:35 AM UTC 24 |
| Peak memory | 215652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114896315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.3114896315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/2.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.3218493075 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 592716466 ps |
| CPU time | 1.54 seconds |
| Started | Oct 12 12:49:22 AM UTC 24 |
| Finished | Oct 12 12:49:24 AM UTC 24 |
| Peak memory | 254888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218493075 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.3218493075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/2.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all.1448578001 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 4594847931 ps |
| CPU time | 17.44 seconds |
| Started | Oct 12 12:49:22 AM UTC 24 |
| Finished | Oct 12 12:49:40 AM UTC 24 |
| Peak memory | 225804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448578001 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.1448578001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/2.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.1399983164 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 2365190969 ps |
| CPU time | 55.36 seconds |
| Started | Oct 12 12:49:22 AM UTC 24 |
| Finished | Oct 12 12:50:19 AM UTC 24 |
| Peak memory | 232440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1399983164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stres s_all_with_rand_reset.1399983164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/20.rv_dm_alert_test.825343541 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 27540123 ps |
| CPU time | 1.05 seconds |
| Started | Oct 12 12:50:09 AM UTC 24 |
| Finished | Oct 12 12:50:11 AM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825343541 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.825343541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/20.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.1098680386 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 1410814229 ps |
| CPU time | 7.88 seconds |
| Started | Oct 12 12:50:09 AM UTC 24 |
| Finished | Oct 12 12:50:18 AM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098680386 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.1098680386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/20.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/21.rv_dm_alert_test.3065984513 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 98518156 ps |
| CPU time | 1.26 seconds |
| Started | Oct 12 12:50:11 AM UTC 24 |
| Finished | Oct 12 12:50:13 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065984513 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.3065984513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/21.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/21.rv_dm_stress_all.3818251736 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 2125483999 ps |
| CPU time | 7.29 seconds |
| Started | Oct 12 12:50:09 AM UTC 24 |
| Finished | Oct 12 12:50:18 AM UTC 24 |
| Peak memory | 215360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818251736 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.3818251736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/21.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/22.rv_dm_alert_test.4171778571 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 92157327 ps |
| CPU time | 0.96 seconds |
| Started | Oct 12 12:50:11 AM UTC 24 |
| Finished | Oct 12 12:50:13 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171778571 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.4171778571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/22.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/23.rv_dm_alert_test.1089775005 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 141373173 ps |
| CPU time | 1.32 seconds |
| Started | Oct 12 12:50:12 AM UTC 24 |
| Finished | Oct 12 12:50:15 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089775005 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.1089775005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/23.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/23.rv_dm_stress_all.3430626327 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 2592660800 ps |
| CPU time | 6.22 seconds |
| Started | Oct 12 12:50:11 AM UTC 24 |
| Finished | Oct 12 12:50:18 AM UTC 24 |
| Peak memory | 225732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430626327 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.3430626327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/23.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/24.rv_dm_alert_test.1772757639 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 121234557 ps |
| CPU time | 1.37 seconds |
| Started | Oct 12 12:50:12 AM UTC 24 |
| Finished | Oct 12 12:50:15 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772757639 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.1772757639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/24.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/24.rv_dm_stress_all.357993499 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 1486517974 ps |
| CPU time | 3.86 seconds |
| Started | Oct 12 12:50:12 AM UTC 24 |
| Finished | Oct 12 12:50:18 AM UTC 24 |
| Peak memory | 215368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357993499 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.357993499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/24.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/25.rv_dm_alert_test.32122539 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 41711085 ps |
| CPU time | 0.96 seconds |
| Started | Oct 12 12:50:14 AM UTC 24 |
| Finished | Oct 12 12:50:17 AM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32122539 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.32122539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/25.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.1201918242 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 2859128463 ps |
| CPU time | 3.49 seconds |
| Started | Oct 12 12:50:13 AM UTC 24 |
| Finished | Oct 12 12:50:18 AM UTC 24 |
| Peak memory | 215480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201918242 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.1201918242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/25.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/26.rv_dm_alert_test.710870323 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 58016487 ps |
| CPU time | 1.21 seconds |
| Started | Oct 12 12:50:15 AM UTC 24 |
| Finished | Oct 12 12:50:17 AM UTC 24 |
| Peak memory | 214832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710870323 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.710870323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/26.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/26.rv_dm_stress_all.3640166039 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 2593741033 ps |
| CPU time | 6.29 seconds |
| Started | Oct 12 12:50:14 AM UTC 24 |
| Finished | Oct 12 12:50:22 AM UTC 24 |
| Peak memory | 225856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640166039 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.3640166039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/26.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/27.rv_dm_alert_test.730175077 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 90060757 ps |
| CPU time | 1.38 seconds |
| Started | Oct 12 12:50:16 AM UTC 24 |
| Finished | Oct 12 12:50:18 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730175077 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.730175077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/27.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.2718604763 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 1651379998 ps |
| CPU time | 3.95 seconds |
| Started | Oct 12 12:50:16 AM UTC 24 |
| Finished | Oct 12 12:50:21 AM UTC 24 |
| Peak memory | 215488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718604763 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.2718604763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/27.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/28.rv_dm_alert_test.4038664368 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 153408148 ps |
| CPU time | 1.24 seconds |
| Started | Oct 12 12:50:16 AM UTC 24 |
| Finished | Oct 12 12:50:18 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038664368 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.4038664368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/28.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/28.rv_dm_stress_all.2526482640 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 2612625940 ps |
| CPU time | 2.72 seconds |
| Started | Oct 12 12:50:16 AM UTC 24 |
| Finished | Oct 12 12:50:20 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526482640 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.2526482640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/28.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/29.rv_dm_alert_test.1470912419 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 73970214 ps |
| CPU time | 0.88 seconds |
| Started | Oct 12 12:50:17 AM UTC 24 |
| Finished | Oct 12 12:50:19 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470912419 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.1470912419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/29.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/29.rv_dm_stress_all.677269579 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 3518455116 ps |
| CPU time | 8.03 seconds |
| Started | Oct 12 12:50:17 AM UTC 24 |
| Finished | Oct 12 12:50:26 AM UTC 24 |
| Peak memory | 215416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677269579 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.677269579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/29.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.981459140 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 135135637 ps |
| CPU time | 1.16 seconds |
| Started | Oct 12 12:49:24 AM UTC 24 |
| Finished | Oct 12 12:49:26 AM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981459140 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.981459140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/3.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.2397956938 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 43183397644 ps |
| CPU time | 32.9 seconds |
| Started | Oct 12 12:49:22 AM UTC 24 |
| Finished | Oct 12 12:49:56 AM UTC 24 |
| Peak memory | 225876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397956938 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.2397956938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/3.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.1944700338 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 2095860671 ps |
| CPU time | 7.55 seconds |
| Started | Oct 12 12:49:22 AM UTC 24 |
| Finished | Oct 12 12:49:30 AM UTC 24 |
| Peak memory | 215520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944700338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.1944700338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/3.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.202934138 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 2604114050 ps |
| CPU time | 7.36 seconds |
| Started | Oct 12 12:49:22 AM UTC 24 |
| Finished | Oct 12 12:49:30 AM UTC 24 |
| Peak memory | 215700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202934138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_tl_access.202934138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/3.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.3570432740 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 558960902 ps |
| CPU time | 3.17 seconds |
| Started | Oct 12 12:49:23 AM UTC 24 |
| Finished | Oct 12 12:49:27 AM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570432740 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_halt_resume_whereto.3570432740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/3.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/3.rv_dm_hart_unavail.920375821 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 353762584 ps |
| CPU time | 1.5 seconds |
| Started | Oct 12 12:49:22 AM UTC 24 |
| Finished | Oct 12 12:49:24 AM UTC 24 |
| Peak memory | 214952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920375821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.920375821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/3.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.3279196410 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 9264154238 ps |
| CPU time | 22.62 seconds |
| Started | Oct 12 12:49:22 AM UTC 24 |
| Finished | Oct 12 12:49:46 AM UTC 24 |
| Peak memory | 225764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279196410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.3279196410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/3.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/3.rv_dm_sec_cm.2274649733 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 1000014595 ps |
| CPU time | 2.7 seconds |
| Started | Oct 12 12:49:23 AM UTC 24 |
| Finished | Oct 12 12:49:27 AM UTC 24 |
| Peak memory | 253760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274649733 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.2274649733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/3.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.2776609648 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 263037811 ps |
| CPU time | 1.44 seconds |
| Started | Oct 12 12:49:23 AM UTC 24 |
| Finished | Oct 12 12:49:26 AM UTC 24 |
| Peak memory | 224748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776609648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sparse_lc_gate_fsm.2776609648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/3.rv_dm_sparse_lc_gate_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.2988981290 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 4161053406 ps |
| CPU time | 10.05 seconds |
| Started | Oct 12 12:49:23 AM UTC 24 |
| Finished | Oct 12 12:49:34 AM UTC 24 |
| Peak memory | 226192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988981290 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.2988981290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/3.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/30.rv_dm_alert_test.3236686327 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 80909534 ps |
| CPU time | 1.04 seconds |
| Started | Oct 12 12:50:19 AM UTC 24 |
| Finished | Oct 12 12:50:21 AM UTC 24 |
| Peak memory | 214712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236686327 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.3236686327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/30.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.2697693824 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 6495979318 ps |
| CPU time | 21.32 seconds |
| Started | Oct 12 12:50:19 AM UTC 24 |
| Finished | Oct 12 12:50:41 AM UTC 24 |
| Peak memory | 226056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697693824 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.2697693824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/30.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/31.rv_dm_alert_test.3641909598 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 29033696 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 12:50:19 AM UTC 24 |
| Finished | Oct 12 12:50:21 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641909598 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.3641909598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/31.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/31.rv_dm_stress_all.211067682 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 2696314721 ps |
| CPU time | 4.8 seconds |
| Started | Oct 12 12:50:19 AM UTC 24 |
| Finished | Oct 12 12:50:25 AM UTC 24 |
| Peak memory | 215424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211067682 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.211067682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/31.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/32.rv_dm_alert_test.1491140116 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 45925719 ps |
| CPU time | 0.86 seconds |
| Started | Oct 12 12:50:19 AM UTC 24 |
| Finished | Oct 12 12:50:21 AM UTC 24 |
| Peak memory | 214804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491140116 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.1491140116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/32.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/32.rv_dm_stress_all.3412920175 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 3860301921 ps |
| CPU time | 13.26 seconds |
| Started | Oct 12 12:50:19 AM UTC 24 |
| Finished | Oct 12 12:50:33 AM UTC 24 |
| Peak memory | 225732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412920175 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.3412920175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/32.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/33.rv_dm_alert_test.903715200 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 50876988 ps |
| CPU time | 0.8 seconds |
| Started | Oct 12 12:50:19 AM UTC 24 |
| Finished | Oct 12 12:50:21 AM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903715200 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.903715200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/33.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.307171997 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 2969963942 ps |
| CPU time | 3.05 seconds |
| Started | Oct 12 12:50:19 AM UTC 24 |
| Finished | Oct 12 12:50:23 AM UTC 24 |
| Peak memory | 225604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307171997 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.307171997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/33.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/34.rv_dm_alert_test.1261821607 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 116500938 ps |
| CPU time | 1.19 seconds |
| Started | Oct 12 12:50:20 AM UTC 24 |
| Finished | Oct 12 12:50:23 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261821607 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.1261821607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/34.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/34.rv_dm_stress_all.3277611960 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 2196957678 ps |
| CPU time | 5.15 seconds |
| Started | Oct 12 12:50:20 AM UTC 24 |
| Finished | Oct 12 12:50:27 AM UTC 24 |
| Peak memory | 225984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277611960 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.3277611960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/34.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/35.rv_dm_alert_test.3122214777 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 98432806 ps |
| CPU time | 1.05 seconds |
| Started | Oct 12 12:50:20 AM UTC 24 |
| Finished | Oct 12 12:50:23 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122214777 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.3122214777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/35.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/35.rv_dm_stress_all.1353590690 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 2197393628 ps |
| CPU time | 7.33 seconds |
| Started | Oct 12 12:50:20 AM UTC 24 |
| Finished | Oct 12 12:50:29 AM UTC 24 |
| Peak memory | 225796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353590690 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.1353590690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/35.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/36.rv_dm_alert_test.2450417215 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 81850274 ps |
| CPU time | 1.06 seconds |
| Started | Oct 12 12:50:20 AM UTC 24 |
| Finished | Oct 12 12:50:23 AM UTC 24 |
| Peak memory | 214784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450417215 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.2450417215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/36.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/36.rv_dm_stress_all.1997254396 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 3397778229 ps |
| CPU time | 10.86 seconds |
| Started | Oct 12 12:50:20 AM UTC 24 |
| Finished | Oct 12 12:50:33 AM UTC 24 |
| Peak memory | 225920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997254396 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.1997254396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/36.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/37.rv_dm_alert_test.3894722993 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 27993643 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 12:50:21 AM UTC 24 |
| Finished | Oct 12 12:50:23 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894722993 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.3894722993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/37.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/37.rv_dm_stress_all.1077971863 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 2642735215 ps |
| CPU time | 3.41 seconds |
| Started | Oct 12 12:50:21 AM UTC 24 |
| Finished | Oct 12 12:50:25 AM UTC 24 |
| Peak memory | 226092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077971863 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.1077971863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/37.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/38.rv_dm_alert_test.512721567 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 126696031 ps |
| CPU time | 0.93 seconds |
| Started | Oct 12 12:50:21 AM UTC 24 |
| Finished | Oct 12 12:50:23 AM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512721567 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.512721567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/38.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/38.rv_dm_stress_all.3164770823 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 1833828872 ps |
| CPU time | 7.84 seconds |
| Started | Oct 12 12:50:21 AM UTC 24 |
| Finished | Oct 12 12:50:30 AM UTC 24 |
| Peak memory | 215288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164770823 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.3164770823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/38.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/39.rv_dm_alert_test.830727513 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 40055882 ps |
| CPU time | 1.1 seconds |
| Started | Oct 12 12:50:22 AM UTC 24 |
| Finished | Oct 12 12:50:24 AM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830727513 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.830727513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/39.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/39.rv_dm_stress_all.3470621745 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 3801800718 ps |
| CPU time | 3.55 seconds |
| Started | Oct 12 12:50:22 AM UTC 24 |
| Finished | Oct 12 12:50:27 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470621745 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.3470621745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/39.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/4.rv_dm_alert_test.2032543313 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 70505258 ps |
| CPU time | 1.01 seconds |
| Started | Oct 12 12:49:27 AM UTC 24 |
| Finished | Oct 12 12:49:29 AM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032543313 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.2032543313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/4.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/4.rv_dm_autoincr_sba_tl_access.3474944197 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 5564726523 ps |
| CPU time | 11.93 seconds |
| Started | Oct 12 12:49:26 AM UTC 24 |
| Finished | Oct 12 12:49:39 AM UTC 24 |
| Peak memory | 225824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474944197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.3474944197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/4.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/4.rv_dm_bad_sba_tl_access.1368421856 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 1836253116 ps |
| CPU time | 3.57 seconds |
| Started | Oct 12 12:49:26 AM UTC 24 |
| Finished | Oct 12 12:49:30 AM UTC 24 |
| Peak memory | 225704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368421856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.1368421856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/4.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/4.rv_dm_buffered_enable.3291035389 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 207764510 ps |
| CPU time | 1.85 seconds |
| Started | Oct 12 12:49:26 AM UTC 24 |
| Finished | Oct 12 12:49:29 AM UTC 24 |
| Peak memory | 244680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291035389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_buffered_enable.3291035389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/4.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3668101222 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 2192604321 ps |
| CPU time | 7.55 seconds |
| Started | Oct 12 12:49:24 AM UTC 24 |
| Finished | Oct 12 12:49:33 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668101222 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_tl_access.3668101222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/4.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.3352524945 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 385789944 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 12:49:26 AM UTC 24 |
| Finished | Oct 12 12:49:28 AM UTC 24 |
| Peak memory | 214952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352524945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_halt_resume_whereto.3352524945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/4.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.948249725 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 337909628 ps |
| CPU time | 0.94 seconds |
| Started | Oct 12 12:49:26 AM UTC 24 |
| Finished | Oct 12 12:49:28 AM UTC 24 |
| Peak memory | 214952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948249725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.948249725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/4.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/4.rv_dm_sba_tl_access.846793790 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 5848393500 ps |
| CPU time | 17.45 seconds |
| Started | Oct 12 12:49:24 AM UTC 24 |
| Finished | Oct 12 12:49:43 AM UTC 24 |
| Peak memory | 215724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846793790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.846793790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/4.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/4.rv_dm_sec_cm.849385438 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 1067096857 ps |
| CPU time | 2.81 seconds |
| Started | Oct 12 12:49:27 AM UTC 24 |
| Finished | Oct 12 12:49:31 AM UTC 24 |
| Peak memory | 255948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849385438 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.849385438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/4.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.2616727490 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1918223831 ps |
| CPU time | 35.3 seconds |
| Started | Oct 12 12:49:27 AM UTC 24 |
| Finished | Oct 12 12:50:04 AM UTC 24 |
| Peak memory | 228104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2616727490 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stres s_all_with_rand_reset.2616727490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/40.rv_dm_alert_test.1160321562 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 78287239 ps |
| CPU time | 1.19 seconds |
| Started | Oct 12 12:50:22 AM UTC 24 |
| Finished | Oct 12 12:50:25 AM UTC 24 |
| Peak memory | 214816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160321562 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.1160321562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/40.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/40.rv_dm_stress_all.3739610863 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 2618819046 ps |
| CPU time | 8.21 seconds |
| Started | Oct 12 12:50:22 AM UTC 24 |
| Finished | Oct 12 12:50:32 AM UTC 24 |
| Peak memory | 215416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739610863 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.3739610863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/40.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/41.rv_dm_alert_test.4158005822 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 61203046 ps |
| CPU time | 0.89 seconds |
| Started | Oct 12 12:50:22 AM UTC 24 |
| Finished | Oct 12 12:50:24 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158005822 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.4158005822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/41.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/41.rv_dm_stress_all.347011377 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 1997007098 ps |
| CPU time | 5.21 seconds |
| Started | Oct 12 12:50:22 AM UTC 24 |
| Finished | Oct 12 12:50:29 AM UTC 24 |
| Peak memory | 215360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347011377 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.347011377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/41.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/42.rv_dm_alert_test.1028093890 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 43278380 ps |
| CPU time | 1.1 seconds |
| Started | Oct 12 12:50:24 AM UTC 24 |
| Finished | Oct 12 12:50:26 AM UTC 24 |
| Peak memory | 214820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028093890 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.1028093890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/42.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/42.rv_dm_stress_all.328078709 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1867112751 ps |
| CPU time | 8.24 seconds |
| Started | Oct 12 12:50:24 AM UTC 24 |
| Finished | Oct 12 12:50:33 AM UTC 24 |
| Peak memory | 215216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328078709 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.328078709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/42.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/43.rv_dm_alert_test.2846419790 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 48396515 ps |
| CPU time | 1.05 seconds |
| Started | Oct 12 12:50:24 AM UTC 24 |
| Finished | Oct 12 12:50:26 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846419790 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.2846419790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/43.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/43.rv_dm_stress_all.1707907121 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 1184793498 ps |
| CPU time | 2.15 seconds |
| Started | Oct 12 12:50:24 AM UTC 24 |
| Finished | Oct 12 12:50:27 AM UTC 24 |
| Peak memory | 225928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707907121 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.1707907121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/43.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/44.rv_dm_alert_test.2948027513 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 155673384 ps |
| CPU time | 1.2 seconds |
| Started | Oct 12 12:50:24 AM UTC 24 |
| Finished | Oct 12 12:50:26 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948027513 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.2948027513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/44.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.2764905058 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1818979804 ps |
| CPU time | 2.09 seconds |
| Started | Oct 12 12:50:24 AM UTC 24 |
| Finished | Oct 12 12:50:27 AM UTC 24 |
| Peak memory | 215360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764905058 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.2764905058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/44.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/45.rv_dm_alert_test.1442464331 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 135702411 ps |
| CPU time | 1.04 seconds |
| Started | Oct 12 12:50:24 AM UTC 24 |
| Finished | Oct 12 12:50:26 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442464331 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.1442464331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/45.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/45.rv_dm_stress_all.3480434846 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 1731854782 ps |
| CPU time | 3.45 seconds |
| Started | Oct 12 12:50:24 AM UTC 24 |
| Finished | Oct 12 12:50:29 AM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480434846 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.3480434846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/45.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/46.rv_dm_alert_test.3515364883 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 90314805 ps |
| CPU time | 1.15 seconds |
| Started | Oct 12 12:50:26 AM UTC 24 |
| Finished | Oct 12 12:50:28 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515364883 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3515364883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/46.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/47.rv_dm_alert_test.873312905 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 32723594 ps |
| CPU time | 1.01 seconds |
| Started | Oct 12 12:50:26 AM UTC 24 |
| Finished | Oct 12 12:50:28 AM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873312905 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.873312905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/47.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/48.rv_dm_alert_test.4250892259 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 100429140 ps |
| CPU time | 1 seconds |
| Started | Oct 12 12:50:27 AM UTC 24 |
| Finished | Oct 12 12:50:29 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250892259 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.4250892259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/48.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/48.rv_dm_stress_all.4045249293 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 3611301145 ps |
| CPU time | 5.88 seconds |
| Started | Oct 12 12:50:26 AM UTC 24 |
| Finished | Oct 12 12:50:33 AM UTC 24 |
| Peak memory | 215352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045249293 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.4045249293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/48.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/49.rv_dm_alert_test.1715342046 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 28327676 ps |
| CPU time | 0.94 seconds |
| Started | Oct 12 12:50:27 AM UTC 24 |
| Finished | Oct 12 12:50:29 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715342046 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.1715342046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/49.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/49.rv_dm_stress_all.2151807742 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 4565284437 ps |
| CPU time | 9.1 seconds |
| Started | Oct 12 12:50:27 AM UTC 24 |
| Finished | Oct 12 12:50:38 AM UTC 24 |
| Peak memory | 215480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151807742 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.2151807742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/49.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/5.rv_dm_alert_test.1865138098 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 127285448 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 12:49:30 AM UTC 24 |
| Finished | Oct 12 12:49:32 AM UTC 24 |
| Peak memory | 214712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865138098 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.1865138098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/5.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.4102154470 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 895695664 ps |
| CPU time | 6.95 seconds |
| Started | Oct 12 12:49:28 AM UTC 24 |
| Finished | Oct 12 12:49:37 AM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102154470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.4102154470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/5.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/5.rv_dm_buffered_enable.1965533297 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 679906185 ps |
| CPU time | 2.6 seconds |
| Started | Oct 12 12:49:29 AM UTC 24 |
| Finished | Oct 12 12:49:32 AM UTC 24 |
| Peak memory | 258032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965533297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_buffered_enable.1965533297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/5.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.3415522031 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 2039530144 ps |
| CPU time | 7.62 seconds |
| Started | Oct 12 12:49:28 AM UTC 24 |
| Finished | Oct 12 12:49:37 AM UTC 24 |
| Peak memory | 215372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415522031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl_access.3415522031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/5.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/5.rv_dm_halt_resume_whereto.1507970887 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 202647561 ps |
| CPU time | 1.26 seconds |
| Started | Oct 12 12:49:28 AM UTC 24 |
| Finished | Oct 12 12:49:31 AM UTC 24 |
| Peak memory | 214952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507970887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_halt_resume_whereto.1507970887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/5.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/5.rv_dm_sba_tl_access.1164839744 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 1673543511 ps |
| CPU time | 6.51 seconds |
| Started | Oct 12 12:49:27 AM UTC 24 |
| Finished | Oct 12 12:49:35 AM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164839744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.1164839744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/5.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.3846611340 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 8026651991 ps |
| CPU time | 27.37 seconds |
| Started | Oct 12 12:49:30 AM UTC 24 |
| Finished | Oct 12 12:49:58 AM UTC 24 |
| Peak memory | 215516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846611340 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.3846611340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/5.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/6.rv_dm_alert_test.3876903616 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 111315814 ps |
| CPU time | 1 seconds |
| Started | Oct 12 12:49:33 AM UTC 24 |
| Finished | Oct 12 12:49:35 AM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876903616 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.3876903616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/6.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/6.rv_dm_autoincr_sba_tl_access.3818571035 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 13134844000 ps |
| CPU time | 9.59 seconds |
| Started | Oct 12 12:49:31 AM UTC 24 |
| Finished | Oct 12 12:49:42 AM UTC 24 |
| Peak memory | 215652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818571035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.3818571035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/6.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/6.rv_dm_bad_sba_tl_access.50782917 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 9766954534 ps |
| CPU time | 18.53 seconds |
| Started | Oct 12 12:49:31 AM UTC 24 |
| Finished | Oct 12 12:49:51 AM UTC 24 |
| Peak memory | 215648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50782917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv _dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.50782917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/6.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/6.rv_dm_buffered_enable.482584105 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 119056002 ps |
| CPU time | 1.99 seconds |
| Started | Oct 12 12:49:32 AM UTC 24 |
| Finished | Oct 12 12:49:35 AM UTC 24 |
| Peak memory | 250484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482584105 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_buffered_enable.482584105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/6.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.1914857893 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 2816506767 ps |
| CPU time | 2.85 seconds |
| Started | Oct 12 12:49:31 AM UTC 24 |
| Finished | Oct 12 12:49:35 AM UTC 24 |
| Peak memory | 215572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914857893 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_tl_access.1914857893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/6.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/6.rv_dm_halt_resume_whereto.3371584389 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 314560537 ps |
| CPU time | 1.38 seconds |
| Started | Oct 12 12:49:32 AM UTC 24 |
| Finished | Oct 12 12:49:35 AM UTC 24 |
| Peak memory | 214952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371584389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_halt_resume_whereto.3371584389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/6.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/6.rv_dm_sba_tl_access.1795904544 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 9015280115 ps |
| CPU time | 33.52 seconds |
| Started | Oct 12 12:49:30 AM UTC 24 |
| Finished | Oct 12 12:50:05 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795904544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.1795904544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/6.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all_with_rand_reset.314540500 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 14379297378 ps |
| CPU time | 63.68 seconds |
| Started | Oct 12 12:49:33 AM UTC 24 |
| Finished | Oct 12 12:50:39 AM UTC 24 |
| Peak memory | 232448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=314540500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress _all_with_rand_reset.314540500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/7.rv_dm_alert_test.3325349803 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 119780945 ps |
| CPU time | 1.36 seconds |
| Started | Oct 12 12:49:37 AM UTC 24 |
| Finished | Oct 12 12:49:39 AM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325349803 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.3325349803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/7.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.293422950 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 45689628562 ps |
| CPU time | 72.86 seconds |
| Started | Oct 12 12:49:36 AM UTC 24 |
| Finished | Oct 12 12:50:50 AM UTC 24 |
| Peak memory | 225812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293422950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.293422950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/7.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.3191831730 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 7902511075 ps |
| CPU time | 10.02 seconds |
| Started | Oct 12 12:49:36 AM UTC 24 |
| Finished | Oct 12 12:49:47 AM UTC 24 |
| Peak memory | 226208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191831730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.3191831730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/7.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/7.rv_dm_buffered_enable.1680223856 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 185951742 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 12:49:36 AM UTC 24 |
| Finished | Oct 12 12:49:38 AM UTC 24 |
| Peak memory | 250064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680223856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_buffered_enable.1680223856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/7.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.1904939565 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 5414684772 ps |
| CPU time | 5.63 seconds |
| Started | Oct 12 12:49:34 AM UTC 24 |
| Finished | Oct 12 12:49:41 AM UTC 24 |
| Peak memory | 225820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904939565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_tl_access.1904939565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/7.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.2224445201 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 719855078 ps |
| CPU time | 4.29 seconds |
| Started | Oct 12 12:49:36 AM UTC 24 |
| Finished | Oct 12 12:49:41 AM UTC 24 |
| Peak memory | 215348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224445201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_halt_resume_whereto.2224445201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/7.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/7.rv_dm_sba_tl_access.3277868217 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 8204041171 ps |
| CPU time | 29 seconds |
| Started | Oct 12 12:49:34 AM UTC 24 |
| Finished | Oct 12 12:50:05 AM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277868217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.3277868217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/7.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all.2533322083 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 3980780376 ps |
| CPU time | 19.72 seconds |
| Started | Oct 12 12:49:36 AM UTC 24 |
| Finished | Oct 12 12:49:57 AM UTC 24 |
| Peak memory | 225928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533322083 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.2533322083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/7.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/8.rv_dm_alert_test.2917502314 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 66002269 ps |
| CPU time | 1 seconds |
| Started | Oct 12 12:49:39 AM UTC 24 |
| Finished | Oct 12 12:49:41 AM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917502314 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.2917502314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/8.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.3238471560 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 2176516589 ps |
| CPU time | 6.09 seconds |
| Started | Oct 12 12:49:38 AM UTC 24 |
| Finished | Oct 12 12:49:45 AM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238471560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.3238471560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/8.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/8.rv_dm_bad_sba_tl_access.2972019411 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 8950292830 ps |
| CPU time | 7.77 seconds |
| Started | Oct 12 12:49:38 AM UTC 24 |
| Finished | Oct 12 12:49:47 AM UTC 24 |
| Peak memory | 225896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972019411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.2972019411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/8.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/8.rv_dm_buffered_enable.359143931 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 171986956 ps |
| CPU time | 1.72 seconds |
| Started | Oct 12 12:49:39 AM UTC 24 |
| Finished | Oct 12 12:49:42 AM UTC 24 |
| Peak memory | 250632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359143931 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_buffered_enable.359143931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/8.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.689460178 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 10390405866 ps |
| CPU time | 9.07 seconds |
| Started | Oct 12 12:49:38 AM UTC 24 |
| Finished | Oct 12 12:49:48 AM UTC 24 |
| Peak memory | 225876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689460178 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl_access.689460178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/8.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/8.rv_dm_sba_tl_access.4019269792 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 3297662542 ps |
| CPU time | 6.64 seconds |
| Started | Oct 12 12:49:37 AM UTC 24 |
| Finished | Oct 12 12:49:45 AM UTC 24 |
| Peak memory | 215524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019269792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.4019269792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/8.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.177848933 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 2595680612 ps |
| CPU time | 5.3 seconds |
| Started | Oct 12 12:49:39 AM UTC 24 |
| Finished | Oct 12 12:49:45 AM UTC 24 |
| Peak memory | 225676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177848933 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.177848933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/8.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.1707439260 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 2522184939 ps |
| CPU time | 55.06 seconds |
| Started | Oct 12 12:49:39 AM UTC 24 |
| Finished | Oct 12 12:50:36 AM UTC 24 |
| Peak memory | 230216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1707439260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stres s_all_with_rand_reset.1707439260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.3246339827 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 55762365 ps |
| CPU time | 1.32 seconds |
| Started | Oct 12 12:49:43 AM UTC 24 |
| Finished | Oct 12 12:49:45 AM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246339827 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.3246339827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/9.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/9.rv_dm_autoincr_sba_tl_access.961349211 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 4312062426 ps |
| CPU time | 5.72 seconds |
| Started | Oct 12 12:49:42 AM UTC 24 |
| Finished | Oct 12 12:49:48 AM UTC 24 |
| Peak memory | 225820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961349211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.961349211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/9.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.3682317594 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 1526241448 ps |
| CPU time | 2.98 seconds |
| Started | Oct 12 12:49:42 AM UTC 24 |
| Finished | Oct 12 12:49:46 AM UTC 24 |
| Peak memory | 225960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682317594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.3682317594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/9.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/9.rv_dm_buffered_enable.92993732 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 187774486 ps |
| CPU time | 2.38 seconds |
| Started | Oct 12 12:49:42 AM UTC 24 |
| Finished | Oct 12 12:49:45 AM UTC 24 |
| Peak memory | 251916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92993732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv _dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_buffered_enable.92993732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/9.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.2465472138 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 750379683 ps |
| CPU time | 1.91 seconds |
| Started | Oct 12 12:49:42 AM UTC 24 |
| Finished | Oct 12 12:49:44 AM UTC 24 |
| Peak memory | 214080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465472138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_tl_access.2465472138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/9.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.2406723572 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 4576766966 ps |
| CPU time | 5.05 seconds |
| Started | Oct 12 12:49:40 AM UTC 24 |
| Finished | Oct 12 12:49:46 AM UTC 24 |
| Peak memory | 215964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406723572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.2406723572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/9.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.856581456 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 6901021619 ps |
| CPU time | 23.57 seconds |
| Started | Oct 12 12:49:43 AM UTC 24 |
| Finished | Oct 12 12:50:08 AM UTC 24 |
| Peak memory | 215876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856581456 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.856581456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/9.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.3855064424 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 2136795335 ps |
| CPU time | 36.79 seconds |
| Started | Oct 12 12:49:43 AM UTC 24 |
| Finished | Oct 12 12:50:21 AM UTC 24 |
| Peak memory | 227712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3855064424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stres s_all_with_rand_reset.3855064424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |