| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 89.11 | 96.64 | 90.24 | 92.10 | 93.33 | 90.44 | 98.22 | 62.76 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 53.36 | 53.36 | 84.69 | 84.69 | 54.88 | 54.88 | 33.57 | 33.57 | 40.00 | 40.00 | 64.42 | 64.42 | 92.77 | 92.77 | 3.16 | 3.16 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.789520714 |
| 63.45 | 10.10 | 88.00 | 3.31 | 62.80 | 7.92 | 64.55 | 30.98 | 57.33 | 17.33 | 71.33 | 6.90 | 94.76 | 1.99 | 5.39 | 2.24 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.2682582803 |
| 73.02 | 9.56 | 91.42 | 3.41 | 72.84 | 10.04 | 69.02 | 4.47 | 68.00 | 10.67 | 80.00 | 8.67 | 96.02 | 1.26 | 33.82 | 28.42 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.4027757653 |
| 78.11 | 5.10 | 92.71 | 1.29 | 76.94 | 4.10 | 89.41 | 20.39 | 73.33 | 5.33 | 83.01 | 3.01 | 96.12 | 0.10 | 35.26 | 1.45 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.314968690 |
| 80.97 | 2.85 | 93.33 | 0.62 | 78.36 | 1.41 | 90.91 | 1.51 | 74.67 | 1.33 | 83.89 | 0.88 | 96.12 | 0.00 | 49.47 | 14.21 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.1454609701 |
| 82.45 | 1.48 | 93.54 | 0.21 | 79.92 | 1.56 | 91.15 | 0.24 | 80.00 | 5.33 | 85.49 | 1.59 | 96.12 | 0.00 | 50.92 | 1.45 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.2324626060 |
| 83.37 | 0.92 | 94.21 | 0.67 | 83.31 | 3.39 | 91.24 | 0.09 | 81.33 | 1.33 | 86.19 | 0.71 | 96.23 | 0.10 | 51.05 | 0.13 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.19717151 |
| 84.15 | 0.79 | 94.21 | 0.00 | 83.31 | 0.00 | 92.61 | 1.37 | 85.33 | 4.00 | 86.19 | 0.00 | 96.23 | 0.00 | 51.18 | 0.13 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.1056208096 |
| 84.74 | 0.58 | 94.62 | 0.41 | 84.58 | 1.27 | 92.80 | 0.19 | 86.67 | 1.33 | 87.08 | 0.88 | 96.23 | 0.00 | 51.18 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.2318263184 |
| 85.29 | 0.55 | 94.67 | 0.05 | 85.57 | 0.99 | 92.89 | 0.09 | 86.67 | 0.00 | 87.43 | 0.35 | 96.23 | 0.00 | 53.55 | 2.37 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2314009753 |
| 85.74 | 0.45 | 95.09 | 0.41 | 86.14 | 0.57 | 92.94 | 0.05 | 88.00 | 1.33 | 87.96 | 0.53 | 96.23 | 0.00 | 53.82 | 0.26 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.2173758272 |
| 86.16 | 0.42 | 95.09 | 0.00 | 86.14 | 0.00 | 95.10 | 2.17 | 88.00 | 0.00 | 87.96 | 0.00 | 96.23 | 0.00 | 54.61 | 0.79 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/13.rv_dm_autoincr_sba_tl_access.2899239708 |
| 86.54 | 0.38 | 95.09 | 0.00 | 86.14 | 0.00 | 95.10 | 0.00 | 90.67 | 2.67 | 87.96 | 0.00 | 96.23 | 0.00 | 54.61 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.1346086191 |
| 86.87 | 0.33 | 95.66 | 0.57 | 86.70 | 0.57 | 95.15 | 0.05 | 90.67 | 0.00 | 88.32 | 0.35 | 96.23 | 0.00 | 55.39 | 0.79 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all.1845573109 |
| 87.16 | 0.28 | 95.66 | 0.00 | 86.99 | 0.28 | 96.09 | 0.94 | 90.67 | 0.00 | 88.32 | 0.00 | 96.33 | 0.10 | 56.05 | 0.66 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.3723416936 |
| 87.42 | 0.26 | 95.81 | 0.16 | 88.26 | 1.27 | 96.14 | 0.05 | 90.67 | 0.00 | 88.67 | 0.35 | 96.33 | 0.00 | 56.05 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_resuming.1209982740 |
| 87.62 | 0.20 | 95.81 | 0.00 | 88.26 | 0.00 | 96.23 | 0.09 | 92.00 | 1.33 | 88.67 | 0.00 | 96.33 | 0.00 | 56.05 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.442472587 |
| 87.81 | 0.19 | 95.81 | 0.00 | 88.26 | 0.00 | 96.23 | 0.00 | 93.33 | 1.33 | 88.67 | 0.00 | 96.33 | 0.00 | 56.05 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3643836465 |
| 87.99 | 0.17 | 96.12 | 0.31 | 88.54 | 0.28 | 96.23 | 0.00 | 93.33 | 0.00 | 89.03 | 0.35 | 96.33 | 0.00 | 56.32 | 0.26 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/17.rv_dm_stress_all.959901815 |
| 88.15 | 0.17 | 96.12 | 0.00 | 88.54 | 0.00 | 96.47 | 0.24 | 93.33 | 0.00 | 89.03 | 0.00 | 96.33 | 0.00 | 57.24 | 0.92 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.102268050 |
| 88.31 | 0.16 | 96.12 | 0.00 | 88.54 | 0.00 | 96.66 | 0.19 | 93.33 | 0.00 | 89.03 | 0.00 | 96.33 | 0.00 | 58.16 | 0.92 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.3417579787 |
| 88.46 | 0.15 | 96.12 | 0.00 | 88.54 | 0.00 | 96.66 | 0.00 | 93.33 | 0.00 | 89.03 | 0.00 | 97.38 | 1.05 | 58.16 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.4168944291 |
| 88.60 | 0.14 | 96.28 | 0.16 | 88.83 | 0.28 | 96.75 | 0.09 | 93.33 | 0.00 | 89.20 | 0.18 | 97.38 | 0.00 | 58.42 | 0.26 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.3842445803 |
| 88.71 | 0.11 | 96.33 | 0.05 | 89.11 | 0.28 | 96.85 | 0.09 | 93.33 | 0.00 | 89.56 | 0.35 | 97.38 | 0.00 | 58.42 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.3877644295 |
| 88.80 | 0.09 | 96.33 | 0.00 | 89.67 | 0.57 | 96.94 | 0.09 | 93.33 | 0.00 | 89.56 | 0.00 | 97.38 | 0.00 | 58.42 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_alert_test.738280023 |
| 88.89 | 0.09 | 96.48 | 0.16 | 89.67 | 0.00 | 96.94 | 0.00 | 93.33 | 0.00 | 89.73 | 0.18 | 97.38 | 0.00 | 58.68 | 0.26 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.1676326174 |
| 88.97 | 0.08 | 96.48 | 0.00 | 89.82 | 0.14 | 96.94 | 0.00 | 93.33 | 0.00 | 89.73 | 0.00 | 97.38 | 0.00 | 59.08 | 0.39 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.1260888023 |
| 89.04 | 0.08 | 96.48 | 0.00 | 89.82 | 0.00 | 97.08 | 0.14 | 93.33 | 0.00 | 89.73 | 0.00 | 97.38 | 0.00 | 59.47 | 0.39 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3479998620 |
| 89.10 | 0.06 | 96.48 | 0.00 | 89.82 | 0.00 | 97.22 | 0.14 | 93.33 | 0.00 | 89.73 | 0.00 | 97.38 | 0.00 | 59.74 | 0.26 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/12.rv_dm_autoincr_sba_tl_access.994745907 |
| 89.16 | 0.06 | 96.48 | 0.00 | 89.82 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 89.73 | 0.00 | 97.38 | 0.00 | 60.13 | 0.39 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/16.rv_dm_stress_all.3739921788 |
| 89.21 | 0.05 | 96.54 | 0.05 | 89.96 | 0.14 | 97.22 | 0.00 | 93.33 | 0.00 | 89.91 | 0.18 | 97.38 | 0.00 | 60.13 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.1342340373 |
| 89.26 | 0.05 | 96.54 | 0.00 | 90.10 | 0.14 | 97.22 | 0.00 | 93.33 | 0.00 | 90.09 | 0.18 | 97.38 | 0.00 | 60.13 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.1688341305 |
| 89.29 | 0.04 | 96.54 | 0.00 | 90.10 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 90.09 | 0.00 | 97.38 | 0.00 | 60.39 | 0.26 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3124458799 |
| 89.33 | 0.04 | 96.54 | 0.00 | 90.10 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 90.09 | 0.00 | 97.38 | 0.00 | 60.66 | 0.26 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3773146015 |
| 89.37 | 0.04 | 96.54 | 0.00 | 90.10 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 90.09 | 0.00 | 97.38 | 0.00 | 60.92 | 0.26 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.1264265111 |
| 89.41 | 0.04 | 96.54 | 0.00 | 90.10 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 90.09 | 0.00 | 97.38 | 0.00 | 61.18 | 0.26 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.2084578961 |
| 89.44 | 0.04 | 96.54 | 0.00 | 90.10 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 90.09 | 0.00 | 97.38 | 0.00 | 61.45 | 0.26 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/12.rv_dm_stress_all.169903101 |
| 89.48 | 0.04 | 96.54 | 0.00 | 90.10 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 90.09 | 0.00 | 97.38 | 0.00 | 61.71 | 0.26 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.429610832 |
| 89.52 | 0.03 | 96.54 | 0.00 | 90.10 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 90.09 | 0.00 | 97.48 | 0.10 | 61.84 | 0.13 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.2702672938 |
| 89.55 | 0.03 | 96.59 | 0.05 | 90.10 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 90.27 | 0.18 | 97.48 | 0.00 | 61.84 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2266455452 |
| 89.58 | 0.03 | 96.64 | 0.05 | 90.10 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 90.44 | 0.18 | 97.48 | 0.00 | 61.84 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.4093853573 |
| 89.61 | 0.03 | 96.64 | 0.00 | 90.10 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 97.69 | 0.21 | 61.84 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2271768571 |
| 89.64 | 0.03 | 96.64 | 0.00 | 90.10 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 97.90 | 0.21 | 61.84 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1310143710 |
| 89.67 | 0.03 | 96.64 | 0.00 | 90.10 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 98.11 | 0.21 | 61.84 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1081379879 |
| 89.69 | 0.02 | 96.64 | 0.00 | 90.24 | 0.14 | 97.22 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 98.11 | 0.00 | 61.84 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.182857464 |
| 89.71 | 0.02 | 96.64 | 0.00 | 90.24 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 98.11 | 0.00 | 61.97 | 0.13 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3136128553 |
| 89.73 | 0.02 | 96.64 | 0.00 | 90.24 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 98.11 | 0.00 | 62.11 | 0.13 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3559909929 |
| 89.75 | 0.02 | 96.64 | 0.00 | 90.24 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 98.11 | 0.00 | 62.24 | 0.13 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/11.rv_dm_stress_all.3507076069 |
| 89.77 | 0.02 | 96.64 | 0.00 | 90.24 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 98.11 | 0.00 | 62.37 | 0.13 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/15.rv_dm_stress_all.1167825128 |
| 89.78 | 0.02 | 96.64 | 0.00 | 90.24 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 98.11 | 0.00 | 62.50 | 0.13 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/18.rv_dm_autoincr_sba_tl_access.2814186804 |
| 89.80 | 0.02 | 96.64 | 0.00 | 90.24 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 98.11 | 0.00 | 62.63 | 0.13 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2160623131 |
| 89.82 | 0.02 | 96.64 | 0.00 | 90.24 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 98.11 | 0.00 | 62.76 | 0.13 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/47.rv_dm_stress_all.455645688 |
| 89.84 | 0.01 | 96.64 | 0.00 | 90.24 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 98.22 | 0.10 | 62.76 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/2.rv_dm_sparse_lc_gate_fsm.1443684292 |
| 89.84 | 0.01 | 96.64 | 0.00 | 90.24 | 0.00 | 97.27 | 0.05 | 93.33 | 0.00 | 90.44 | 0.00 | 98.22 | 0.00 | 62.76 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3308371360 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.432031049 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.394747105 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.22116723 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.689661140 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.342916919 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1321249141 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2666371584 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1289683762 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1294682746 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1926579332 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.560393507 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.612168065 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1095369472 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.4226962838 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3472202745 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3033010451 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.840361784 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.3499403434 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2173770462 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2539634441 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1430766635 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3776734305 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1914715005 |
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| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/17.rv_dm_alert_test.1629794201 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/17.rv_dm_autoincr_sba_tl_access.2733242742 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/17.rv_dm_bad_sba_tl_access.3334908733 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.4283223788 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/17.rv_dm_sba_tl_access.3001137534 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/18.rv_dm_alert_test.2129313162 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/18.rv_dm_bad_sba_tl_access.3670966756 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.3778038520 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/18.rv_dm_sba_tl_access.606613115 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/18.rv_dm_stress_all.286886764 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/19.rv_dm_alert_test.1565739122 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/19.rv_dm_bad_sba_tl_access.740924073 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/19.rv_dm_sba_tl_access.4146131655 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.3635002145 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.2583059737 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.3648743159 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.2453613392 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.2369808847 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.3064451789 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.1135841512 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.3114896315 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.3218493075 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all.1448578001 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.1399983164 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/20.rv_dm_alert_test.825343541 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.1098680386 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/21.rv_dm_alert_test.3065984513 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/21.rv_dm_stress_all.3818251736 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/22.rv_dm_alert_test.4171778571 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/23.rv_dm_alert_test.1089775005 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/23.rv_dm_stress_all.3430626327 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/24.rv_dm_alert_test.1772757639 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/24.rv_dm_stress_all.357993499 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/25.rv_dm_alert_test.32122539 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.1201918242 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/26.rv_dm_alert_test.710870323 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/26.rv_dm_stress_all.3640166039 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/27.rv_dm_alert_test.730175077 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.2718604763 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/28.rv_dm_alert_test.4038664368 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/28.rv_dm_stress_all.2526482640 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/29.rv_dm_alert_test.1470912419 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/29.rv_dm_stress_all.677269579 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.981459140 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.2397956938 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.1944700338 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.202934138 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.3570432740 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/3.rv_dm_hart_unavail.920375821 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.3279196410 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/3.rv_dm_sec_cm.2274649733 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.2776609648 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.2988981290 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/30.rv_dm_alert_test.3236686327 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.2697693824 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/31.rv_dm_alert_test.3641909598 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/31.rv_dm_stress_all.211067682 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/32.rv_dm_alert_test.1491140116 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/32.rv_dm_stress_all.3412920175 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/33.rv_dm_alert_test.903715200 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.307171997 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/34.rv_dm_alert_test.1261821607 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/34.rv_dm_stress_all.3277611960 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/35.rv_dm_alert_test.3122214777 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/35.rv_dm_stress_all.1353590690 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/36.rv_dm_alert_test.2450417215 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/36.rv_dm_stress_all.1997254396 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/37.rv_dm_alert_test.3894722993 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/37.rv_dm_stress_all.1077971863 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/38.rv_dm_alert_test.512721567 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/38.rv_dm_stress_all.3164770823 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/39.rv_dm_alert_test.830727513 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/39.rv_dm_stress_all.3470621745 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/4.rv_dm_alert_test.2032543313 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/4.rv_dm_autoincr_sba_tl_access.3474944197 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/4.rv_dm_bad_sba_tl_access.1368421856 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/4.rv_dm_buffered_enable.3291035389 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3668101222 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.3352524945 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.948249725 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/4.rv_dm_sba_tl_access.846793790 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/4.rv_dm_sec_cm.849385438 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.2616727490 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/40.rv_dm_alert_test.1160321562 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/40.rv_dm_stress_all.3739610863 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/41.rv_dm_alert_test.4158005822 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/41.rv_dm_stress_all.347011377 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/42.rv_dm_alert_test.1028093890 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/42.rv_dm_stress_all.328078709 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/43.rv_dm_alert_test.2846419790 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/43.rv_dm_stress_all.1707907121 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/44.rv_dm_alert_test.2948027513 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.2764905058 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/45.rv_dm_alert_test.1442464331 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/45.rv_dm_stress_all.3480434846 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/46.rv_dm_alert_test.3515364883 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/47.rv_dm_alert_test.873312905 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/48.rv_dm_alert_test.4250892259 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/48.rv_dm_stress_all.4045249293 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/49.rv_dm_alert_test.1715342046 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/49.rv_dm_stress_all.2151807742 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/5.rv_dm_alert_test.1865138098 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.4102154470 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/5.rv_dm_buffered_enable.1965533297 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.3415522031 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/5.rv_dm_halt_resume_whereto.1507970887 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/5.rv_dm_sba_tl_access.1164839744 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.3846611340 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/6.rv_dm_alert_test.3876903616 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/6.rv_dm_autoincr_sba_tl_access.3818571035 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/6.rv_dm_bad_sba_tl_access.50782917 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/6.rv_dm_buffered_enable.482584105 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.1914857893 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/6.rv_dm_halt_resume_whereto.3371584389 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/6.rv_dm_sba_tl_access.1795904544 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all_with_rand_reset.314540500 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/7.rv_dm_alert_test.3325349803 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.293422950 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.3191831730 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/7.rv_dm_buffered_enable.1680223856 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.1904939565 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.2224445201 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/7.rv_dm_sba_tl_access.3277868217 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all.2533322083 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/8.rv_dm_alert_test.2917502314 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.3238471560 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/8.rv_dm_bad_sba_tl_access.2972019411 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/8.rv_dm_buffered_enable.359143931 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.689460178 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/8.rv_dm_sba_tl_access.4019269792 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.177848933 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.1707439260 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.3246339827 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/9.rv_dm_autoincr_sba_tl_access.961349211 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.3682317594 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/9.rv_dm_buffered_enable.92993732 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.2465472138 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.2406723572 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.856581456 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.3855064424 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.3966363305 | Oct 12 12:49:07 AM UTC 24 | Oct 12 12:49:09 AM UTC 24 | 115328680 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_busy.193097800 | Oct 12 12:49:06 AM UTC 24 | Oct 12 12:49:09 AM UTC 24 | 221024587 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_smoke.1663290457 | Oct 12 12:49:05 AM UTC 24 | Oct 12 12:49:10 AM UTC 24 | 678256786 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_resuming.1209982740 | Oct 12 12:49:08 AM UTC 24 | Oct 12 12:49:10 AM UTC 24 | 538371021 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_halted.204445550 | Oct 12 12:49:08 AM UTC 24 | Oct 12 12:49:10 AM UTC 24 | 451712781 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.789520714 | Oct 12 12:49:08 AM UTC 24 | Oct 12 12:49:11 AM UTC 24 | 324603238 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_hart_unavail.4240367799 | Oct 12 12:49:09 AM UTC 24 | Oct 12 12:49:11 AM UTC 24 | 87233850 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.182857464 | Oct 12 12:49:09 AM UTC 24 | Oct 12 12:49:11 AM UTC 24 | 396192233 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_dataaddr_rw_access.906763810 | Oct 12 12:49:09 AM UTC 24 | Oct 12 12:49:11 AM UTC 24 | 320932617 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.2318263184 | Oct 12 12:49:23 AM UTC 24 | Oct 12 12:49:25 AM UTC 24 | 190691007 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.1268599747 | Oct 12 12:49:05 AM UTC 24 | Oct 12 12:49:12 AM UTC 24 | 2805508975 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_idle_hint.3181334388 | Oct 12 12:49:10 AM UTC 24 | Oct 12 12:49:12 AM UTC 24 | 330082624 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.1834934824 | Oct 12 12:49:10 AM UTC 24 | Oct 12 12:49:12 AM UTC 24 | 187695867 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.1676326174 | Oct 12 12:49:10 AM UTC 24 | Oct 12 12:49:13 AM UTC 24 | 167000425 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_tl_access.1638603491 | Oct 12 12:49:05 AM UTC 24 | Oct 12 12:49:13 AM UTC 24 | 6204882863 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.314968690 | Oct 12 12:49:10 AM UTC 24 | Oct 12 12:49:13 AM UTC 24 | 219412289 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_hartsel_warl.1474574493 | Oct 12 12:49:12 AM UTC 24 | Oct 12 12:49:14 AM UTC 24 | 96073845 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_hard_reset.320510854 | Oct 12 12:49:11 AM UTC 24 | Oct 12 12:49:14 AM UTC 24 | 419113050 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.183978035 | Oct 12 12:49:10 AM UTC 24 | Oct 12 12:49:14 AM UTC 24 | 2173212087 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.2173758272 | Oct 12 12:49:12 AM UTC 24 | Oct 12 12:49:14 AM UTC 24 | 569212202 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.243214923 | Oct 12 12:49:12 AM UTC 24 | Oct 12 12:49:14 AM UTC 24 | 155275040 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.3561398442 | Oct 12 12:49:12 AM UTC 24 | Oct 12 12:49:14 AM UTC 24 | 165320010 ps | ||
| T59 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.3877644295 | Oct 12 12:49:12 AM UTC 24 | Oct 12 12:49:14 AM UTC 24 | 94877903 ps | ||
| T97 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_debug_disabled.1898310505 | Oct 12 12:49:12 AM UTC 24 | Oct 12 12:49:14 AM UTC 24 | 118057607 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.2682582803 | Oct 12 12:49:06 AM UTC 24 | Oct 12 12:49:15 AM UTC 24 | 7593386623 ps | ||
| T96 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.1966565920 | Oct 12 12:49:13 AM UTC 24 | Oct 12 12:49:15 AM UTC 24 | 18293605 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.1873838397 | Oct 12 12:49:13 AM UTC 24 | Oct 12 12:49:15 AM UTC 24 | 71434941 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_smoke.3855863399 | Oct 12 12:49:13 AM UTC 24 | Oct 12 12:49:15 AM UTC 24 | 333031530 ps | ||
| T91 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.390074279 | Oct 12 12:49:13 AM UTC 24 | Oct 12 12:49:15 AM UTC 24 | 87800417 ps | ||
| T70 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.3723416936 | Oct 12 12:49:13 AM UTC 24 | Oct 12 12:49:16 AM UTC 24 | 1153564595 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.1688341305 | Oct 12 12:49:10 AM UTC 24 | Oct 12 12:49:17 AM UTC 24 | 5037052357 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_busy.799211618 | Oct 12 12:49:14 AM UTC 24 | Oct 12 12:49:17 AM UTC 24 | 336015681 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_not_supported.4033499379 | Oct 12 12:49:15 AM UTC 24 | Oct 12 12:49:17 AM UTC 24 | 175384988 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.1342340373 | Oct 12 12:49:13 AM UTC 24 | Oct 12 12:49:18 AM UTC 24 | 727760728 ps | ||
| T102 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_halted.3362046730 | Oct 12 12:49:16 AM UTC 24 | Oct 12 12:49:18 AM UTC 24 | 145893396 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_dataaddr_rw_access.3989805743 | Oct 12 12:49:16 AM UTC 24 | Oct 12 12:49:18 AM UTC 24 | 95619717 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.381812547 | Oct 12 12:49:16 AM UTC 24 | Oct 12 12:49:18 AM UTC 24 | 246690330 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_halt_resume_whereto.3676867182 | Oct 12 12:49:16 AM UTC 24 | Oct 12 12:49:19 AM UTC 24 | 799084151 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.152295087 | Oct 12 12:49:16 AM UTC 24 | Oct 12 12:49:19 AM UTC 24 | 654631759 ps | ||
| T206 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_hart_unavail.4143149274 | Oct 12 12:49:16 AM UTC 24 | Oct 12 12:49:19 AM UTC 24 | 247393626 ps | ||
| T80 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1252591298 | Oct 12 12:49:17 AM UTC 24 | Oct 12 12:49:19 AM UTC 24 | 151594692 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_abstractcmd_status.3489744117 | Oct 12 12:49:17 AM UTC 24 | Oct 12 12:49:19 AM UTC 24 | 133926895 ps | ||
| T121 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_tl_access.1802335519 | Oct 12 12:49:14 AM UTC 24 | Oct 12 12:49:20 AM UTC 24 | 1966143613 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_resuming.1729047111 | Oct 12 12:49:16 AM UTC 24 | Oct 12 12:49:20 AM UTC 24 | 848182458 ps | ||
| T78 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_hard_reset.1359726084 | Oct 12 12:49:17 AM UTC 24 | Oct 12 12:49:20 AM UTC 24 | 311272876 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_ndmreset_req.692312521 | Oct 12 12:49:17 AM UTC 24 | Oct 12 12:49:20 AM UTC 24 | 467218832 ps | ||
| T98 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.3241150217 | Oct 12 12:49:17 AM UTC 24 | Oct 12 12:49:21 AM UTC 24 | 384202855 ps | ||
| T95 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_debug_disabled.4133110586 | Oct 12 12:49:19 AM UTC 24 | Oct 12 12:49:21 AM UTC 24 | 67940361 ps | ||
| T76 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.3349367089 | Oct 12 12:49:19 AM UTC 24 | Oct 12 12:49:21 AM UTC 24 | 221383617 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.2702672938 | Oct 12 12:49:19 AM UTC 24 | Oct 12 12:49:21 AM UTC 24 | 132777664 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_rom_read_access.288678305 | Oct 12 12:49:19 AM UTC 24 | Oct 12 12:49:21 AM UTC 24 | 187107420 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_progbuf_read_write_execute.4093052348 | Oct 12 12:49:19 AM UTC 24 | Oct 12 12:49:21 AM UTC 24 | 268731083 ps | ||
| T263 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1932135073 | Oct 12 12:49:17 AM UTC 24 | Oct 12 12:49:21 AM UTC 24 | 576268076 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_buffered_enable.3989750390 | Oct 12 12:49:19 AM UTC 24 | Oct 12 12:49:21 AM UTC 24 | 375350943 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_autoincr_sba_tl_access.2258852675 | Oct 12 12:49:14 AM UTC 24 | Oct 12 12:49:22 AM UTC 24 | 2850401883 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_alert_test.738280023 | Oct 12 12:49:20 AM UTC 24 | Oct 12 12:49:22 AM UTC 24 | 36723541 ps | ||
| T169 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.1135841512 | Oct 12 12:49:20 AM UTC 24 | Oct 12 12:49:22 AM UTC 24 | 69421057 ps | ||
| T122 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.1814610871 | Oct 12 12:49:14 AM UTC 24 | Oct 12 12:49:23 AM UTC 24 | 2916253559 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.2084578961 | Oct 12 12:49:20 AM UTC 24 | Oct 12 12:49:23 AM UTC 24 | 651745594 ps | ||
| T82 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.1944700338 | Oct 12 12:49:22 AM UTC 24 | Oct 12 12:49:30 AM UTC 24 | 2095860671 ps | ||
| T72 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.3635002145 | Oct 12 12:49:22 AM UTC 24 | Oct 12 12:49:24 AM UTC 24 | 147137683 ps | ||
| T85 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.2453613392 | Oct 12 12:49:21 AM UTC 24 | Oct 12 12:49:24 AM UTC 24 | 123581286 ps | ||
| T84 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/2.rv_dm_sparse_lc_gate_fsm.1443684292 | Oct 12 12:49:22 AM UTC 24 | Oct 12 12:49:24 AM UTC 24 | 282710359 ps | ||
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| T89 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.3218493075 | Oct 12 12:49:22 AM UTC 24 | Oct 12 12:49:24 AM UTC 24 | 592716466 ps | ||
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| T50 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.3064451789 | Oct 12 12:49:21 AM UTC 24 | Oct 12 12:49:24 AM UTC 24 | 1122131963 ps | ||
| T86 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.2776609648 | Oct 12 12:49:23 AM UTC 24 | Oct 12 12:49:26 AM UTC 24 | 263037811 ps | ||
| T90 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_sec_cm.4226606697 | Oct 12 12:49:20 AM UTC 24 | Oct 12 12:49:26 AM UTC 24 | 1484287510 ps | ||
| T73 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.981459140 | Oct 12 12:49:24 AM UTC 24 | Oct 12 12:49:26 AM UTC 24 | 135135637 ps | ||
| T105 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_debug_disabled.1285788414 | Oct 12 12:49:16 AM UTC 24 | Oct 12 12:49:27 AM UTC 24 | 3184859235 ps | ||
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| T53 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.3570432740 | Oct 12 12:49:23 AM UTC 24 | Oct 12 12:49:27 AM UTC 24 | 558960902 ps | ||
| T264 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.948249725 | Oct 12 12:49:26 AM UTC 24 | Oct 12 12:49:28 AM UTC 24 | 337909628 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.3352524945 | Oct 12 12:49:26 AM UTC 24 | Oct 12 12:49:28 AM UTC 24 | 385789944 ps | ||
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| T141 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/4.rv_dm_bad_sba_tl_access.1368421856 | Oct 12 12:49:26 AM UTC 24 | Oct 12 12:49:30 AM UTC 24 | 1836253116 ps | ||
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| T61 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/5.rv_dm_halt_resume_whereto.1507970887 | Oct 12 12:49:28 AM UTC 24 | Oct 12 12:49:31 AM UTC 24 | 202647561 ps | ||
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| T41 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.4027757653 | Oct 12 12:49:20 AM UTC 24 | Oct 12 12:49:34 AM UTC 24 | 2365472787 ps | ||
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| T126 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/6.rv_dm_buffered_enable.482584105 | Oct 12 12:49:32 AM UTC 24 | Oct 12 12:49:35 AM UTC 24 | 119056002 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.102268050 | Oct 12 12:49:28 AM UTC 24 | Oct 12 12:49:35 AM UTC 24 | 8964854859 ps | ||
| T127 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.3114896315 | Oct 12 12:49:20 AM UTC 24 | Oct 12 12:49:35 AM UTC 24 | 4455502072 ps | ||
| T128 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/6.rv_dm_alert_test.3876903616 | Oct 12 12:49:33 AM UTC 24 | Oct 12 12:49:35 AM UTC 24 | 111315814 ps | ||
| T129 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.4102154470 | Oct 12 12:49:28 AM UTC 24 | Oct 12 12:49:37 AM UTC 24 | 895695664 ps | ||
| T227 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/12.rv_dm_sba_tl_access.2786316347 | Oct 12 12:49:49 AM UTC 24 | Oct 12 12:50:04 AM UTC 24 | 5338844315 ps | ||
| T266 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.3415522031 | Oct 12 12:49:28 AM UTC 24 | Oct 12 12:49:37 AM UTC 24 | 2039530144 ps | ||
| T143 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/7.rv_dm_buffered_enable.1680223856 | Oct 12 12:49:36 AM UTC 24 | Oct 12 12:49:38 AM UTC 24 | 185951742 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all.1845573109 | Oct 12 12:49:33 AM UTC 24 | Oct 12 12:49:38 AM UTC 24 | 2129281246 ps | ||
| T261 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.3648743159 | Oct 12 12:49:20 AM UTC 24 | Oct 12 12:49:38 AM UTC 24 | 15791412557 ps | ||
| T182 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/4.rv_dm_autoincr_sba_tl_access.3474944197 | Oct 12 12:49:26 AM UTC 24 | Oct 12 12:49:39 AM UTC 24 | 5564726523 ps | ||
| T267 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/7.rv_dm_alert_test.3325349803 | Oct 12 12:49:37 AM UTC 24 | Oct 12 12:49:39 AM UTC 24 | 119780945 ps | ||
| T52 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all.1448578001 | Oct 12 12:49:22 AM UTC 24 | Oct 12 12:49:40 AM UTC 24 | 4594847931 ps | ||
| T87 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.2324626060 | Oct 12 12:49:05 AM UTC 24 | Oct 12 12:49:40 AM UTC 24 | 11493229999 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/11.rv_dm_stress_all.3507076069 | Oct 12 12:49:49 AM UTC 24 | Oct 12 12:50:01 AM UTC 24 | 4006089165 ps | ||
| T256 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/15.rv_dm_bad_sba_tl_access.2308737883 | Oct 12 12:49:57 AM UTC 24 | Oct 12 12:50:03 AM UTC 24 | 1036606741 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.2224445201 | Oct 12 12:49:36 AM UTC 24 | Oct 12 12:49:41 AM UTC 24 | 719855078 ps | ||
| T238 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/8.rv_dm_alert_test.2917502314 | Oct 12 12:49:39 AM UTC 24 | Oct 12 12:49:41 AM UTC 24 | 66002269 ps | ||
| T268 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.1904939565 | Oct 12 12:49:34 AM UTC 24 | Oct 12 12:49:41 AM UTC 24 | 5414684772 ps | ||
| T269 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/6.rv_dm_autoincr_sba_tl_access.3818571035 | Oct 12 12:49:31 AM UTC 24 | Oct 12 12:49:42 AM UTC 24 | 13134844000 ps | ||
| T223 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/8.rv_dm_buffered_enable.359143931 | Oct 12 12:49:39 AM UTC 24 | Oct 12 12:49:42 AM UTC 24 | 171986956 ps | ||
| T270 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/4.rv_dm_sba_tl_access.846793790 | Oct 12 12:49:24 AM UTC 24 | Oct 12 12:49:43 AM UTC 24 | 5848393500 ps | ||
| T224 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/1.rv_dm_bad_sba_tl_access.1900027430 | Oct 12 12:49:14 AM UTC 24 | Oct 12 12:49:44 AM UTC 24 | 10454370079 ps | ||
| T185 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.2465472138 | Oct 12 12:49:42 AM UTC 24 | Oct 12 12:49:44 AM UTC 24 | 750379683 ps | ||
| T243 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/8.rv_dm_sba_tl_access.4019269792 | Oct 12 12:49:37 AM UTC 24 | Oct 12 12:49:45 AM UTC 24 | 3297662542 ps | ||
| T178 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/9.rv_dm_buffered_enable.92993732 | Oct 12 12:49:42 AM UTC 24 | Oct 12 12:49:45 AM UTC 24 | 187774486 ps | ||
| T189 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.3238471560 | Oct 12 12:49:38 AM UTC 24 | Oct 12 12:49:45 AM UTC 24 | 2176516589 ps | ||
| T239 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.3246339827 | Oct 12 12:49:43 AM UTC 24 | Oct 12 12:49:45 AM UTC 24 | 55762365 ps | ||
| T99 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.177848933 | Oct 12 12:49:39 AM UTC 24 | Oct 12 12:49:45 AM UTC 24 | 2595680612 ps | ||
| T236 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.3682317594 | Oct 12 12:49:42 AM UTC 24 | Oct 12 12:49:46 AM UTC 24 | 1526241448 ps | ||
| T254 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.3279196410 | Oct 12 12:49:22 AM UTC 24 | Oct 12 12:49:46 AM UTC 24 | 9264154238 ps | ||
| T255 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/10.rv_dm_sba_tl_access.1758561738 | Oct 12 12:49:43 AM UTC 24 | Oct 12 12:49:46 AM UTC 24 | 1358708076 ps | ||
| T262 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.2406723572 | Oct 12 12:49:40 AM UTC 24 | Oct 12 12:49:46 AM UTC 24 | 4576766966 ps | ||
| T233 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.3191831730 | Oct 12 12:49:36 AM UTC 24 | Oct 12 12:49:47 AM UTC 24 | 7902511075 ps | ||
| T246 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/8.rv_dm_bad_sba_tl_access.2972019411 | Oct 12 12:49:38 AM UTC 24 | Oct 12 12:49:47 AM UTC 24 | 8950292830 ps | ||
| T237 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/10.rv_dm_alert_test.3673993664 | Oct 12 12:49:45 AM UTC 24 | Oct 12 12:49:47 AM UTC 24 | 96941072 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.1077755661 | Oct 12 12:49:13 AM UTC 24 | Oct 12 12:49:47 AM UTC 24 | 2776353381 ps | ||
| T258 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.689460178 | Oct 12 12:49:38 AM UTC 24 | Oct 12 12:49:48 AM UTC 24 | 10390405866 ps | ||
| T271 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/9.rv_dm_autoincr_sba_tl_access.961349211 | Oct 12 12:49:42 AM UTC 24 | Oct 12 12:49:48 AM UTC 24 | 4312062426 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/10.rv_dm_stress_all.249983989 | Oct 12 12:49:45 AM UTC 24 | Oct 12 12:49:49 AM UTC 24 | 1987890946 ps | ||
| T260 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.2697423496 | Oct 12 12:49:44 AM UTC 24 | Oct 12 12:49:50 AM UTC 24 | 2951334750 ps | ||
| T195 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/7.rv_dm_sba_tl_access.3277868217 | Oct 12 12:49:34 AM UTC 24 | Oct 12 12:50:05 AM UTC 24 | 8204041171 ps | ||
| T272 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/6.rv_dm_bad_sba_tl_access.50782917 | Oct 12 12:49:31 AM UTC 24 | Oct 12 12:49:51 AM UTC 24 | 9766954534 ps | ||
| T273 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/16.rv_dm_sba_tl_access.3547999371 | Oct 12 12:49:59 AM UTC 24 | Oct 12 12:50:05 AM UTC 24 | 900484966 ps | ||
| T234 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/11.rv_dm_alert_test.2994679025 | Oct 12 12:49:49 AM UTC 24 | Oct 12 12:49:51 AM UTC 24 | 35982042 ps | ||
| T225 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/12.rv_dm_alert_test.3271387588 | Oct 12 12:49:49 AM UTC 24 | Oct 12 12:49:52 AM UTC 24 | 88844262 ps | ||
| T188 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/10.rv_dm_bad_sba_tl_access.908956063 | Oct 12 12:49:45 AM UTC 24 | Oct 12 12:49:53 AM UTC 24 | 3458437314 ps | ||
| T232 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/11.rv_dm_bad_sba_tl_access.2997857659 | Oct 12 12:49:49 AM UTC 24 | Oct 12 12:49:53 AM UTC 24 | 1441730021 ps | ||
| T274 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.824860887 | Oct 12 12:49:49 AM UTC 24 | Oct 12 12:49:55 AM UTC 24 | 1930877310 ps | ||
| T241 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/13.rv_dm_alert_test.1613324102 | Oct 12 12:49:54 AM UTC 24 | Oct 12 12:49:56 AM UTC 24 | 92866893 ps | ||
| T184 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.2397956938 | Oct 12 12:49:22 AM UTC 24 | Oct 12 12:49:56 AM UTC 24 | 43183397644 ps | ||
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| T31 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all.2533322083 | Oct 12 12:49:36 AM UTC 24 | Oct 12 12:49:57 AM UTC 24 | 3980780376 ps | ||
| T253 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/12.rv_dm_bad_sba_tl_access.2253904233 | Oct 12 12:49:49 AM UTC 24 | Oct 12 12:49:58 AM UTC 24 | 4500552017 ps | ||
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| T252 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/14.rv_dm_alert_test.2357632260 | Oct 12 12:49:56 AM UTC 24 | Oct 12 12:49:58 AM UTC 24 | 64229490 ps | ||
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| T193 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.3081012904 | Oct 12 12:49:49 AM UTC 24 | Oct 12 12:49:59 AM UTC 24 | 9190575109 ps | ||
| T276 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/13.rv_dm_bad_sba_tl_access.4232021745 | Oct 12 12:49:50 AM UTC 24 | Oct 12 12:49:59 AM UTC 24 | 2736273281 ps | ||
| T191 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.1284752693 | Oct 12 12:49:54 AM UTC 24 | Oct 12 12:50:00 AM UTC 24 | 1323405046 ps | ||
| T277 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/15.rv_dm_alert_test.1279225860 | Oct 12 12:49:58 AM UTC 24 | Oct 12 12:50:01 AM UTC 24 | 41281516 ps | ||
| T230 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/16.rv_dm_alert_test.2933273757 | Oct 12 12:50:00 AM UTC 24 | Oct 12 12:50:02 AM UTC 24 | 86987644 ps | ||
| T278 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/15.rv_dm_sba_tl_access.2940057416 | Oct 12 12:49:56 AM UTC 24 | Oct 12 12:50:03 AM UTC 24 | 5077588404 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.2616727490 | Oct 12 12:49:27 AM UTC 24 | Oct 12 12:50:04 AM UTC 24 | 1918223831 ps | ||
| T242 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/17.rv_dm_alert_test.1629794201 | Oct 12 12:50:04 AM UTC 24 | Oct 12 12:50:06 AM UTC 24 | 110950017 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/15.rv_dm_stress_all.1167825128 | Oct 12 12:49:58 AM UTC 24 | Oct 12 12:50:06 AM UTC 24 | 1898531467 ps | ||
| T279 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/16.rv_dm_autoincr_sba_tl_access.2540684403 | Oct 12 12:50:00 AM UTC 24 | Oct 12 12:50:06 AM UTC 24 | 798290935 ps | ||
| T240 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.212710622 | Oct 12 12:49:50 AM UTC 24 | Oct 12 12:50:06 AM UTC 24 | 7883986096 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/14.rv_dm_stress_all.2388874352 | Oct 12 12:49:55 AM UTC 24 | Oct 12 12:50:06 AM UTC 24 | 4094555738 ps | ||
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| T231 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/16.rv_dm_bad_sba_tl_access.3525037802 | Oct 12 12:50:00 AM UTC 24 | Oct 12 12:50:07 AM UTC 24 | 7282836964 ps | ||
| T88 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.856581456 | Oct 12 12:49:43 AM UTC 24 | Oct 12 12:50:08 AM UTC 24 | 6901021619 ps | ||
| T228 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/13.rv_dm_stress_all.1865422093 | Oct 12 12:49:54 AM UTC 24 | Oct 12 12:50:08 AM UTC 24 | 3767021687 ps | ||
| T281 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2395776876 | Oct 12 12:49:57 AM UTC 24 | Oct 12 12:50:08 AM UTC 24 | 4248456895 ps | ||
| T282 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/18.rv_dm_alert_test.2129313162 | Oct 12 12:50:06 AM UTC 24 | Oct 12 12:50:09 AM UTC 24 | 51854240 ps | ||
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| T284 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/19.rv_dm_alert_test.1565739122 | Oct 12 12:50:08 AM UTC 24 | Oct 12 12:50:10 AM UTC 24 | 45576115 ps | ||
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| T286 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/22.rv_dm_alert_test.4171778571 | Oct 12 12:50:11 AM UTC 24 | Oct 12 12:50:13 AM UTC 24 | 92157327 ps | ||
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| T9 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.1454609701 | Oct 12 12:49:23 AM UTC 24 | Oct 12 12:50:15 AM UTC 24 | 2690046913 ps | ||
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| T290 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/19.rv_dm_sba_tl_access.4146131655 | Oct 12 12:50:08 AM UTC 24 | Oct 12 12:50:15 AM UTC 24 | 1579891057 ps | ||
| T251 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/25.rv_dm_alert_test.32122539 | Oct 12 12:50:14 AM UTC 24 | Oct 12 12:50:17 AM UTC 24 | 41711085 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.1260888023 | Oct 12 12:50:11 AM UTC 24 | Oct 12 12:50:17 AM UTC 24 | 2918954159 ps | ||
| T291 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.4283223788 | Oct 12 12:50:01 AM UTC 24 | Oct 12 12:50:17 AM UTC 24 | 3819688074 ps | ||
| T226 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/26.rv_dm_alert_test.710870323 | Oct 12 12:50:15 AM UTC 24 | Oct 12 12:50:17 AM UTC 24 | 58016487 ps | ||
| T180 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/12.rv_dm_autoincr_sba_tl_access.994745907 | Oct 12 12:49:49 AM UTC 24 | Oct 12 12:50:17 AM UTC 24 | 19000788146 ps | ||
| T203 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/24.rv_dm_stress_all.357993499 | Oct 12 12:50:12 AM UTC 24 | Oct 12 12:50:18 AM UTC 24 | 1486517974 ps | ||
| T292 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/17.rv_dm_sba_tl_access.3001137534 | Oct 12 12:50:01 AM UTC 24 | Oct 12 12:50:18 AM UTC 24 | 4266684614 ps | ||
| T229 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/45.rv_dm_stress_all.3480434846 | Oct 12 12:50:24 AM UTC 24 | Oct 12 12:50:29 AM UTC 24 | 1731854782 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/21.rv_dm_stress_all.3818251736 | Oct 12 12:50:09 AM UTC 24 | Oct 12 12:50:18 AM UTC 24 | 2125483999 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.1201918242 | Oct 12 12:50:13 AM UTC 24 | Oct 12 12:50:18 AM UTC 24 | 2859128463 ps | ||
| T190 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.3079187574 | Oct 12 12:50:00 AM UTC 24 | Oct 12 12:50:18 AM UTC 24 | 7756721585 ps | ||
| T207 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/23.rv_dm_stress_all.3430626327 | Oct 12 12:50:11 AM UTC 24 | Oct 12 12:50:18 AM UTC 24 | 2592660800 ps | ||
| T202 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.1098680386 | Oct 12 12:50:09 AM UTC 24 | Oct 12 12:50:18 AM UTC 24 | 1410814229 ps | ||
| T235 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/27.rv_dm_alert_test.730175077 | Oct 12 12:50:16 AM UTC 24 | Oct 12 12:50:18 AM UTC 24 | 90060757 ps | ||
| T245 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/28.rv_dm_alert_test.4038664368 | Oct 12 12:50:16 AM UTC 24 | Oct 12 12:50:18 AM UTC 24 | 153408148 ps | ||
| T93 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.3842445803 | Oct 12 12:50:08 AM UTC 24 | Oct 12 12:50:18 AM UTC 24 | 3374633661 ps | ||
| T83 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.1399983164 | Oct 12 12:49:22 AM UTC 24 | Oct 12 12:50:19 AM UTC 24 | 2365190969 ps | ||
| T194 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/18.rv_dm_bad_sba_tl_access.3670966756 | Oct 12 12:50:06 AM UTC 24 | Oct 12 12:50:19 AM UTC 24 | 6427851396 ps | ||
| T293 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/29.rv_dm_alert_test.1470912419 | Oct 12 12:50:17 AM UTC 24 | Oct 12 12:50:19 AM UTC 24 | 73970214 ps | ||
| T294 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/28.rv_dm_stress_all.2526482640 | Oct 12 12:50:16 AM UTC 24 | Oct 12 12:50:20 AM UTC 24 | 2612625940 ps | ||
| T249 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/32.rv_dm_alert_test.1491140116 | Oct 12 12:50:19 AM UTC 24 | Oct 12 12:50:21 AM UTC 24 | 45925719 ps | ||
| T244 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/30.rv_dm_alert_test.3236686327 | Oct 12 12:50:19 AM UTC 24 | Oct 12 12:50:21 AM UTC 24 | 80909534 ps | ||
| T295 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/33.rv_dm_alert_test.903715200 | Oct 12 12:50:19 AM UTC 24 | Oct 12 12:50:21 AM UTC 24 | 50876988 ps | ||
| T296 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/31.rv_dm_alert_test.3641909598 | Oct 12 12:50:19 AM UTC 24 | Oct 12 12:50:21 AM UTC 24 | 29033696 ps | ||
| T123 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.3855064424 | Oct 12 12:49:43 AM UTC 24 | Oct 12 12:50:21 AM UTC 24 | 2136795335 ps | ||
| T204 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.2718604763 | Oct 12 12:50:16 AM UTC 24 | Oct 12 12:50:21 AM UTC 24 | 1651379998 ps | ||
| T198 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/26.rv_dm_stress_all.3640166039 | Oct 12 12:50:14 AM UTC 24 | Oct 12 12:50:22 AM UTC 24 | 2593741033 ps | ||
| T297 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/14.rv_dm_bad_sba_tl_access.1302436240 | Oct 12 12:49:54 AM UTC 24 | Oct 12 12:50:22 AM UTC 24 | 5401136615 ps | ||
| T298 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/34.rv_dm_alert_test.1261821607 | Oct 12 12:50:20 AM UTC 24 | Oct 12 12:50:23 AM UTC 24 | 116500938 ps | ||
| T299 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/35.rv_dm_alert_test.3122214777 | Oct 12 12:50:20 AM UTC 24 | Oct 12 12:50:23 AM UTC 24 | 98432806 ps | ||
| T300 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/36.rv_dm_alert_test.2450417215 | Oct 12 12:50:20 AM UTC 24 | Oct 12 12:50:23 AM UTC 24 | 81850274 ps | ||
| T301 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/38.rv_dm_alert_test.512721567 | Oct 12 12:50:21 AM UTC 24 | Oct 12 12:50:23 AM UTC 24 | 126696031 ps | ||
| T302 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/37.rv_dm_alert_test.3894722993 | Oct 12 12:50:21 AM UTC 24 | Oct 12 12:50:23 AM UTC 24 | 27993643 ps | ||
| T303 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.307171997 | Oct 12 12:50:19 AM UTC 24 | Oct 12 12:50:23 AM UTC 24 | 2969963942 ps | ||
| T304 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/39.rv_dm_alert_test.830727513 | Oct 12 12:50:22 AM UTC 24 | Oct 12 12:50:24 AM UTC 24 | 40055882 ps | ||
| T305 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/41.rv_dm_alert_test.4158005822 | Oct 12 12:50:22 AM UTC 24 | Oct 12 12:50:24 AM UTC 24 | 61203046 ps | ||
| T306 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/31.rv_dm_stress_all.211067682 | Oct 12 12:50:19 AM UTC 24 | Oct 12 12:50:25 AM UTC 24 | 2696314721 ps | ||
| T307 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/40.rv_dm_alert_test.1160321562 | Oct 12 12:50:22 AM UTC 24 | Oct 12 12:50:25 AM UTC 24 | 78287239 ps | ||
| T179 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/37.rv_dm_stress_all.1077971863 | Oct 12 12:50:21 AM UTC 24 | Oct 12 12:50:25 AM UTC 24 | 2642735215 ps | ||
| T308 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/42.rv_dm_alert_test.1028093890 | Oct 12 12:50:24 AM UTC 24 | Oct 12 12:50:26 AM UTC 24 | 43278380 ps | ||
| T186 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/18.rv_dm_autoincr_sba_tl_access.2814186804 | Oct 12 12:50:06 AM UTC 24 | Oct 12 12:50:26 AM UTC 24 | 6083029731 ps | ||
| T309 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/43.rv_dm_alert_test.2846419790 | Oct 12 12:50:24 AM UTC 24 | Oct 12 12:50:26 AM UTC 24 | 48396515 ps | ||
| T310 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/45.rv_dm_alert_test.1442464331 | Oct 12 12:50:24 AM UTC 24 | Oct 12 12:50:26 AM UTC 24 | 135702411 ps | ||
| T311 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/44.rv_dm_alert_test.2948027513 | Oct 12 12:50:24 AM UTC 24 | Oct 12 12:50:26 AM UTC 24 | 155673384 ps | ||
| T312 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/29.rv_dm_stress_all.677269579 | Oct 12 12:50:17 AM UTC 24 | Oct 12 12:50:26 AM UTC 24 | 3518455116 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/34.rv_dm_stress_all.3277611960 | Oct 12 12:50:20 AM UTC 24 | Oct 12 12:50:27 AM UTC 24 | 2196957678 ps | ||
| T140 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/39.rv_dm_stress_all.3470621745 | Oct 12 12:50:22 AM UTC 24 | Oct 12 12:50:27 AM UTC 24 | 3801800718 ps | ||
| T205 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/43.rv_dm_stress_all.1707907121 | Oct 12 12:50:24 AM UTC 24 | Oct 12 12:50:27 AM UTC 24 | 1184793498 ps | ||
| T77 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.2764905058 | Oct 12 12:50:24 AM UTC 24 | Oct 12 12:50:27 AM UTC 24 | 1818979804 ps | ||
| T313 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/47.rv_dm_alert_test.873312905 | Oct 12 12:50:26 AM UTC 24 | Oct 12 12:50:28 AM UTC 24 | 32723594 ps | ||
| T314 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/46.rv_dm_alert_test.3515364883 | Oct 12 12:50:26 AM UTC 24 | Oct 12 12:50:28 AM UTC 24 | 90314805 ps | ||
| T187 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2160623131 | Oct 12 12:50:08 AM UTC 24 | Oct 12 12:50:28 AM UTC 24 | 5652097527 ps | ||
| T315 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/41.rv_dm_stress_all.347011377 | Oct 12 12:50:22 AM UTC 24 | Oct 12 12:50:29 AM UTC 24 | 1997007098 ps | ||
| T197 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/35.rv_dm_stress_all.1353590690 | Oct 12 12:50:20 AM UTC 24 | Oct 12 12:50:29 AM UTC 24 | 2197393628 ps | ||
| T200 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.429610832 | Oct 12 12:50:26 AM UTC 24 | Oct 12 12:50:29 AM UTC 24 | 715856831 ps | ||
| T316 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/48.rv_dm_alert_test.4250892259 | Oct 12 12:50:27 AM UTC 24 | Oct 12 12:50:29 AM UTC 24 | 100429140 ps | ||
| T317 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/49.rv_dm_alert_test.1715342046 | Oct 12 12:50:27 AM UTC 24 | Oct 12 12:50:29 AM UTC 24 | 28327676 ps | ||
| T201 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/38.rv_dm_stress_all.3164770823 | Oct 12 12:50:21 AM UTC 24 | Oct 12 12:50:30 AM UTC 24 | 1833828872 ps | ||
| T318 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/14.rv_dm_sba_tl_access.1526244697 | Oct 12 12:49:54 AM UTC 24 | Oct 12 12:50:31 AM UTC 24 | 9490431357 ps | ||
| T319 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/40.rv_dm_stress_all.3739610863 | Oct 12 12:50:22 AM UTC 24 | Oct 12 12:50:32 AM UTC 24 | 2618819046 ps | ||
| T320 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/36.rv_dm_stress_all.1997254396 | Oct 12 12:50:20 AM UTC 24 | Oct 12 12:50:33 AM UTC 24 | 3397778229 ps | ||
| T321 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/18.rv_dm_sba_tl_access.606613115 | Oct 12 12:50:05 AM UTC 24 | Oct 12 12:50:33 AM UTC 24 | 6961511349 ps | ||
| T322 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/48.rv_dm_stress_all.4045249293 | Oct 12 12:50:26 AM UTC 24 | Oct 12 12:50:33 AM UTC 24 | 3611301145 ps | ||
| T199 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/47.rv_dm_stress_all.455645688 | Oct 12 12:50:26 AM UTC 24 | Oct 12 12:50:33 AM UTC 24 | 3519194403 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/42.rv_dm_stress_all.328078709 | Oct 12 12:50:24 AM UTC 24 | Oct 12 12:50:33 AM UTC 24 | 1867112751 ps | ||
| T208 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/32.rv_dm_stress_all.3412920175 | Oct 12 12:50:19 AM UTC 24 | Oct 12 12:50:33 AM UTC 24 | 3860301921 ps | ||
| T116 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.1707439260 | Oct 12 12:49:39 AM UTC 24 | Oct 12 12:50:36 AM UTC 24 | 2522184939 ps | ||
| T192 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/coverage/default/13.rv_dm_autoincr_sba_tl_access.2899239708 | Oct 12 12:49:53 AM UTC 24 | Oct 12 12:50:37 AM UTC 24 | 34603925407 ps |
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