| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 89.20 | 96.64 | 90.52 | 92.10 | 93.33 | 90.44 | 98.74 | 62.63 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 57.99 | 57.99 | 85.94 | 85.94 | 56.86 | 56.86 | 52.35 | 52.35 | 46.67 | 46.67 | 67.08 | 67.08 | 92.98 | 92.98 | 4.08 | 4.08 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.59112776 |
| 67.98 | 9.99 | 87.18 | 1.24 | 65.49 | 8.63 | 55.37 | 3.01 | 53.33 | 6.67 | 73.10 | 6.02 | 94.03 | 1.05 | 47.37 | 43.29 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.2819749502 |
| 74.68 | 6.70 | 90.43 | 3.26 | 71.29 | 5.80 | 73.87 | 18.50 | 64.00 | 10.67 | 78.94 | 5.84 | 95.70 | 1.68 | 48.55 | 1.18 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.3591596300 |
| 78.06 | 3.38 | 90.54 | 0.10 | 75.25 | 3.96 | 89.45 | 15.58 | 66.67 | 2.67 | 79.29 | 0.35 | 96.02 | 0.31 | 49.21 | 0.66 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.1210175528 |
| 81.15 | 3.09 | 92.45 | 1.91 | 81.05 | 5.80 | 90.82 | 1.37 | 74.67 | 8.00 | 82.65 | 3.36 | 96.12 | 0.10 | 50.26 | 1.05 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.642997972 |
| 82.24 | 1.09 | 92.66 | 0.21 | 82.46 | 1.41 | 91.10 | 0.28 | 78.67 | 4.00 | 83.36 | 0.71 | 96.12 | 0.00 | 51.32 | 1.05 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.1916770217 |
| 83.10 | 0.86 | 93.43 | 0.78 | 83.88 | 1.41 | 92.94 | 1.84 | 80.00 | 1.33 | 83.89 | 0.53 | 96.12 | 0.00 | 51.45 | 0.13 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.2637864355 |
| 83.87 | 0.76 | 93.49 | 0.05 | 85.01 | 1.13 | 93.60 | 0.66 | 80.00 | 0.00 | 84.25 | 0.35 | 96.12 | 0.00 | 54.61 | 3.16 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2143418191 |
| 84.47 | 0.60 | 94.05 | 0.57 | 85.86 | 0.85 | 93.64 | 0.05 | 81.33 | 1.33 | 85.13 | 0.88 | 96.12 | 0.00 | 55.13 | 0.53 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.1698021664 |
| 85.06 | 0.59 | 94.83 | 0.78 | 87.13 | 1.27 | 93.64 | 0.00 | 81.33 | 0.00 | 86.55 | 1.42 | 96.12 | 0.00 | 55.79 | 0.66 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.2816134843 |
| 85.51 | 0.45 | 94.98 | 0.16 | 87.27 | 0.14 | 93.64 | 0.00 | 84.00 | 2.67 | 86.73 | 0.18 | 96.12 | 0.00 | 55.79 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.2607259863 |
| 85.92 | 0.42 | 95.35 | 0.36 | 87.84 | 0.57 | 93.64 | 0.00 | 85.33 | 1.33 | 87.26 | 0.53 | 96.12 | 0.00 | 55.92 | 0.13 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.3994006258 |
| 86.30 | 0.38 | 95.35 | 0.00 | 87.84 | 0.00 | 93.64 | 0.00 | 88.00 | 2.67 | 87.26 | 0.00 | 96.12 | 0.00 | 55.92 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1712382388 |
| 86.63 | 0.32 | 95.35 | 0.00 | 87.84 | 0.00 | 95.90 | 2.26 | 88.00 | 0.00 | 87.26 | 0.00 | 96.12 | 0.00 | 55.92 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.21908632 |
| 86.87 | 0.24 | 95.35 | 0.00 | 87.98 | 0.14 | 95.90 | 0.00 | 89.33 | 1.33 | 87.26 | 0.00 | 96.33 | 0.21 | 55.92 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.567859112 |
| 87.10 | 0.23 | 95.50 | 0.16 | 88.40 | 0.42 | 96.28 | 0.38 | 89.33 | 0.00 | 87.79 | 0.53 | 96.33 | 0.00 | 56.05 | 0.13 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.123195574 |
| 87.32 | 0.22 | 95.55 | 0.05 | 88.54 | 0.14 | 96.47 | 0.19 | 89.33 | 0.00 | 88.14 | 0.35 | 96.33 | 0.00 | 56.84 | 0.79 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/9.rv_dm_autoincr_sba_tl_access.1068131495 |
| 87.51 | 0.19 | 95.55 | 0.00 | 88.54 | 0.00 | 96.47 | 0.00 | 90.67 | 1.33 | 88.14 | 0.00 | 96.33 | 0.00 | 56.84 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.619712428 |
| 87.70 | 0.19 | 95.55 | 0.00 | 88.54 | 0.00 | 96.47 | 0.00 | 92.00 | 1.33 | 88.14 | 0.00 | 96.33 | 0.00 | 56.84 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2863543884 |
| 87.89 | 0.19 | 95.55 | 0.00 | 88.54 | 0.00 | 96.47 | 0.00 | 93.33 | 1.33 | 88.14 | 0.00 | 96.33 | 0.00 | 56.84 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.2436516784 |
| 88.06 | 0.17 | 95.55 | 0.00 | 88.54 | 0.00 | 96.75 | 0.28 | 93.33 | 0.00 | 88.14 | 0.00 | 96.33 | 0.00 | 57.76 | 0.92 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.1492852321 |
| 88.23 | 0.17 | 95.86 | 0.31 | 89.11 | 0.57 | 96.89 | 0.14 | 93.33 | 0.00 | 88.32 | 0.18 | 96.33 | 0.00 | 57.76 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.37730167 |
| 88.38 | 0.15 | 95.86 | 0.00 | 89.11 | 0.00 | 96.89 | 0.00 | 93.33 | 0.00 | 88.32 | 0.00 | 97.38 | 1.05 | 57.76 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2456528865 |
| 88.53 | 0.15 | 96.12 | 0.26 | 89.11 | 0.00 | 97.03 | 0.14 | 93.33 | 0.00 | 88.67 | 0.35 | 97.38 | 0.00 | 58.03 | 0.26 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.476664209 |
| 88.66 | 0.14 | 96.43 | 0.31 | 89.39 | 0.28 | 97.03 | 0.00 | 93.33 | 0.00 | 89.03 | 0.35 | 97.38 | 0.00 | 58.03 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.2119822898 |
| 88.77 | 0.11 | 96.48 | 0.05 | 89.67 | 0.28 | 97.03 | 0.00 | 93.33 | 0.00 | 89.20 | 0.18 | 97.38 | 0.00 | 58.29 | 0.26 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.274390158 |
| 88.88 | 0.11 | 96.54 | 0.05 | 89.82 | 0.14 | 97.22 | 0.19 | 93.33 | 0.00 | 89.56 | 0.35 | 97.38 | 0.00 | 58.29 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.3425029598 |
| 88.97 | 0.09 | 96.54 | 0.00 | 89.82 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 89.56 | 0.00 | 97.38 | 0.00 | 58.95 | 0.66 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/40.rv_dm_stress_all.1000520638 |
| 89.06 | 0.09 | 96.54 | 0.00 | 89.82 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 89.56 | 0.00 | 98.01 | 0.63 | 58.95 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3249941230 |
| 89.15 | 0.09 | 96.54 | 0.00 | 89.96 | 0.14 | 97.22 | 0.00 | 93.33 | 0.00 | 89.91 | 0.35 | 98.01 | 0.00 | 59.08 | 0.13 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2428715139 |
| 89.22 | 0.08 | 96.54 | 0.00 | 89.96 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 89.91 | 0.00 | 98.01 | 0.00 | 59.61 | 0.53 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.90756656 |
| 89.29 | 0.06 | 96.54 | 0.00 | 90.10 | 0.14 | 97.22 | 0.00 | 93.33 | 0.00 | 90.09 | 0.18 | 98.01 | 0.00 | 59.74 | 0.13 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_debug_disabled.2495551992 |
| 89.35 | 0.06 | 96.54 | 0.00 | 90.10 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 90.09 | 0.00 | 98.01 | 0.00 | 60.13 | 0.39 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2592024801 |
| 89.40 | 0.06 | 96.54 | 0.00 | 90.10 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 90.09 | 0.00 | 98.01 | 0.00 | 60.53 | 0.39 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/37.rv_dm_stress_all.2812556346 |
| 89.44 | 0.04 | 96.54 | 0.00 | 90.38 | 0.28 | 97.22 | 0.00 | 93.33 | 0.00 | 90.09 | 0.00 | 98.01 | 0.00 | 60.53 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.4209167188 |
| 89.48 | 0.04 | 96.54 | 0.00 | 90.52 | 0.14 | 97.22 | 0.00 | 93.33 | 0.00 | 90.09 | 0.00 | 98.01 | 0.00 | 60.66 | 0.13 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.1193841208 |
| 89.52 | 0.04 | 96.54 | 0.00 | 90.52 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 90.09 | 0.00 | 98.01 | 0.00 | 60.92 | 0.26 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.2159014742 |
| 89.56 | 0.04 | 96.54 | 0.00 | 90.52 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 90.09 | 0.00 | 98.01 | 0.00 | 61.18 | 0.26 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.2496879580 |
| 89.59 | 0.04 | 96.54 | 0.00 | 90.52 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 90.09 | 0.00 | 98.01 | 0.00 | 61.45 | 0.26 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.246582610 |
| 89.63 | 0.03 | 96.59 | 0.05 | 90.52 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 90.27 | 0.18 | 98.01 | 0.00 | 61.45 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1334103136 |
| 89.66 | 0.03 | 96.64 | 0.05 | 90.52 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 90.44 | 0.18 | 98.01 | 0.00 | 61.45 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.3948319646 |
| 89.69 | 0.03 | 96.64 | 0.00 | 90.52 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 98.22 | 0.21 | 61.45 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3558206780 |
| 89.72 | 0.03 | 96.64 | 0.00 | 90.52 | 0.00 | 97.22 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 98.43 | 0.21 | 61.45 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.990202596 |
| 89.74 | 0.03 | 96.64 | 0.00 | 90.52 | 0.00 | 97.27 | 0.05 | 93.33 | 0.00 | 90.44 | 0.00 | 98.43 | 0.00 | 61.58 | 0.13 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/18.rv_dm_stress_all.2959218755 |
| 89.76 | 0.02 | 96.64 | 0.00 | 90.52 | 0.00 | 97.27 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 98.43 | 0.00 | 61.71 | 0.13 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_intg_err.519590747 |
| 89.78 | 0.02 | 96.64 | 0.00 | 90.52 | 0.00 | 97.27 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 98.43 | 0.00 | 61.84 | 0.13 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.535399975 |
| 89.80 | 0.02 | 96.64 | 0.00 | 90.52 | 0.00 | 97.27 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 98.43 | 0.00 | 61.97 | 0.13 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.2753153097 |
| 89.82 | 0.02 | 96.64 | 0.00 | 90.52 | 0.00 | 97.27 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 98.43 | 0.00 | 62.11 | 0.13 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.773939087 |
| 89.84 | 0.02 | 96.64 | 0.00 | 90.52 | 0.00 | 97.27 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 98.43 | 0.00 | 62.24 | 0.13 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_dataaddr_rw_access.840030457 |
| 89.86 | 0.02 | 96.64 | 0.00 | 90.52 | 0.00 | 97.27 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 98.43 | 0.00 | 62.37 | 0.13 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/15.rv_dm_stress_all.1755433740 |
| 89.88 | 0.02 | 96.64 | 0.00 | 90.52 | 0.00 | 97.27 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 98.43 | 0.00 | 62.50 | 0.13 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/28.rv_dm_stress_all.1485083626 |
| 89.90 | 0.02 | 96.64 | 0.00 | 90.52 | 0.00 | 97.27 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 98.43 | 0.00 | 62.63 | 0.13 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/36.rv_dm_stress_all.3093226842 |
| 89.91 | 0.01 | 96.64 | 0.00 | 90.52 | 0.00 | 97.27 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 98.53 | 0.10 | 62.63 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_rw.3577687786 |
| 89.93 | 0.01 | 96.64 | 0.00 | 90.52 | 0.00 | 97.27 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 98.64 | 0.10 | 62.63 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.1088285414 |
| 89.94 | 0.01 | 96.64 | 0.00 | 90.52 | 0.00 | 97.27 | 0.00 | 93.33 | 0.00 | 90.44 | 0.00 | 98.74 | 0.10 | 62.63 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.3786425985 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1603587181 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1235488627 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3339317547 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.709105668 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.3074771012 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3609537834 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3677488552 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2663165378 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2130636795 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3525402693 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1290968424 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.817299692 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.1671511773 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3272206061 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.3270178079 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4253265537 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2669978042 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.3769516477 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1178503529 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3892310590 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.661003020 |
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| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/15.rv_dm_sba_tl_access.1356405300 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/16.rv_dm_alert_test.1951719138 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/16.rv_dm_autoincr_sba_tl_access.4134295651 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/16.rv_dm_bad_sba_tl_access.3989310296 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.3592304876 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/16.rv_dm_sba_tl_access.3224141961 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/16.rv_dm_stress_all.3379840230 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/17.rv_dm_alert_test.4152511508 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/17.rv_dm_autoincr_sba_tl_access.1962849841 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/17.rv_dm_bad_sba_tl_access.1467525877 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.2311357191 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/17.rv_dm_sba_tl_access.1034192822 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/17.rv_dm_stress_all.1382388834 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/18.rv_dm_alert_test.464227181 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/18.rv_dm_autoincr_sba_tl_access.3326066943 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/18.rv_dm_bad_sba_tl_access.168458234 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.659134955 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/18.rv_dm_sba_tl_access.3570167122 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/19.rv_dm_alert_test.741689492 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/19.rv_dm_bad_sba_tl_access.328886484 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.3367789598 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/19.rv_dm_sba_tl_access.1348595167 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.3530809822 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.2602867933 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.1765752033 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.3310241377 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.4122850759 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.551391094 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.386882211 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.3081093125 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/2.rv_dm_sparse_lc_gate_fsm.3488339316 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/20.rv_dm_alert_test.534316597 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.3788268677 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/21.rv_dm_alert_test.1998153916 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/21.rv_dm_stress_all.2576849231 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/22.rv_dm_alert_test.2207122629 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.1172067305 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/23.rv_dm_alert_test.3386738111 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/23.rv_dm_stress_all.2982591764 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/24.rv_dm_alert_test.2738588264 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/24.rv_dm_stress_all.4190222105 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/25.rv_dm_alert_test.3766901911 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.1055661796 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/26.rv_dm_alert_test.216719530 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/26.rv_dm_stress_all.3480439804 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/27.rv_dm_alert_test.3248824828 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.1511325186 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/28.rv_dm_alert_test.3391414304 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/29.rv_dm_alert_test.3580422687 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.1227119379 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.1227649374 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.3181503759 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.419622812 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.4185723493 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/3.rv_dm_hart_unavail.2765667742 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.2969182360 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/3.rv_dm_sec_cm.2834656089 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.2689571136 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.4171445271 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/30.rv_dm_alert_test.278190996 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/31.rv_dm_alert_test.1818940979 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/32.rv_dm_alert_test.3219127481 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/32.rv_dm_stress_all.3979592757 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/33.rv_dm_alert_test.1293227445 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.2410548354 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/34.rv_dm_alert_test.262058397 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/34.rv_dm_stress_all.1349662841 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/35.rv_dm_alert_test.413960948 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/35.rv_dm_stress_all.1611715214 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/36.rv_dm_alert_test.278506040 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/37.rv_dm_alert_test.2952832481 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/38.rv_dm_alert_test.2021527149 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/38.rv_dm_stress_all.1140804743 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/39.rv_dm_alert_test.441108454 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/39.rv_dm_stress_all.512824415 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/4.rv_dm_alert_test.2195942884 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/4.rv_dm_autoincr_sba_tl_access.207599214 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/4.rv_dm_bad_sba_tl_access.1276925422 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/4.rv_dm_buffered_enable.3930726267 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3339606754 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.2642188330 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.1973213598 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/4.rv_dm_sba_tl_access.2468293739 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/4.rv_dm_sec_cm.4040948270 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/40.rv_dm_alert_test.18466663 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/41.rv_dm_alert_test.279139338 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/41.rv_dm_stress_all.1837361523 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/42.rv_dm_alert_test.2722718204 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/42.rv_dm_stress_all.406163748 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/43.rv_dm_alert_test.1576054536 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/43.rv_dm_stress_all.260190410 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/44.rv_dm_alert_test.1951396548 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.384329124 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/45.rv_dm_alert_test.291175557 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/45.rv_dm_stress_all.51518127 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/46.rv_dm_alert_test.832326198 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.1437762200 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/47.rv_dm_alert_test.3286596662 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/47.rv_dm_stress_all.3022861183 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/48.rv_dm_alert_test.117376207 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/49.rv_dm_alert_test.1682303798 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/49.rv_dm_stress_all.3522450402 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/5.rv_dm_alert_test.2007251271 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.924763800 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.3018320421 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/5.rv_dm_buffered_enable.3721227144 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.2865916164 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/5.rv_dm_halt_resume_whereto.2182212838 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/5.rv_dm_sba_tl_access.4240549302 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.122467378 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/6.rv_dm_autoincr_sba_tl_access.2879608922 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.754222265 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/6.rv_dm_sba_tl_access.1673875083 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/7.rv_dm_alert_test.758006160 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/7.rv_dm_buffered_enable.2186976933 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all.2666624630 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/8.rv_dm_alert_test.1003491334 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.1338679405 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/8.rv_dm_bad_sba_tl_access.3595684435 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/8.rv_dm_buffered_enable.1636244441 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.1276841628 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/8.rv_dm_sba_tl_access.1846008901 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.2207125744 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.1092462516 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.3983190736 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/9.rv_dm_buffered_enable.4129240544 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.1295448509 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.752981797 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.1934725767 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_resuming.384678116 | Oct 15 01:10:42 AM UTC 24 | Oct 15 01:10:47 AM UTC 24 | 531338418 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.1193841208 | Oct 15 01:10:44 AM UTC 24 | Oct 15 01:10:47 AM UTC 24 | 1389126393 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_busy.4270499187 | Oct 15 01:10:36 AM UTC 24 | Oct 15 01:10:49 AM UTC 24 | 1072221836 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.1152551129 | Oct 15 01:10:37 AM UTC 24 | Oct 15 01:10:49 AM UTC 24 | 213461288 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.37730167 | Oct 15 01:10:39 AM UTC 24 | Oct 15 01:10:51 AM UTC 24 | 129834228 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.1210175528 | Oct 15 01:10:58 AM UTC 24 | Oct 15 01:11:02 AM UTC 24 | 526687756 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.814221283 | Oct 15 01:10:37 AM UTC 24 | Oct 15 01:10:52 AM UTC 24 | 338867009 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.59112776 | Oct 15 01:10:36 AM UTC 24 | Oct 15 01:10:52 AM UTC 24 | 298783641 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1970802722 | Oct 15 01:10:49 AM UTC 24 | Oct 15 01:10:52 AM UTC 24 | 142811436 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.3425029598 | Oct 15 01:10:37 AM UTC 24 | Oct 15 01:10:52 AM UTC 24 | 76569606 ps | ||
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| T8 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.1698021664 | Oct 15 01:10:37 AM UTC 24 | Oct 15 01:10:52 AM UTC 24 | 188629202 ps | ||
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| T51 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.1088285414 | Oct 15 01:10:37 AM UTC 24 | Oct 15 01:10:52 AM UTC 24 | 109610847 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.3987645635 | Oct 15 01:10:49 AM UTC 24 | Oct 15 01:10:52 AM UTC 24 | 426598935 ps | ||
| T78 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_idle_hint.117406 | Oct 15 01:10:37 AM UTC 24 | Oct 15 01:10:52 AM UTC 24 | 425835247 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.476664209 | Oct 15 01:10:37 AM UTC 24 | Oct 15 01:10:53 AM UTC 24 | 519734748 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.2159014742 | Oct 15 01:10:37 AM UTC 24 | Oct 15 01:10:53 AM UTC 24 | 1000093061 ps | ||
| T107 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.2207151132 | Oct 15 01:10:51 AM UTC 24 | Oct 15 01:10:53 AM UTC 24 | 182846717 ps | ||
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| T29 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.123195574 | Oct 15 01:10:40 AM UTC 24 | Oct 15 01:10:53 AM UTC 24 | 693029649 ps | ||
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| T42 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_dataaddr_rw_access.840030457 | Oct 15 01:10:48 AM UTC 24 | Oct 15 01:10:53 AM UTC 24 | 62715733 ps | ||
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| T5 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_hart_unavail.533816711 | Oct 15 01:10:42 AM UTC 24 | Oct 15 01:10:54 AM UTC 24 | 140815882 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_tl_access.2819771401 | Oct 15 01:10:39 AM UTC 24 | Oct 15 01:10:54 AM UTC 24 | 4436621589 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_abstractcmd_status.3104638600 | Oct 15 01:10:53 AM UTC 24 | Oct 15 01:10:55 AM UTC 24 | 121270250 ps | ||
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| T61 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_progbuf_read_write_execute.1564407506 | Oct 15 01:10:53 AM UTC 24 | Oct 15 01:10:55 AM UTC 24 | 260474302 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_rom_read_access.2840956454 | Oct 15 01:10:53 AM UTC 24 | Oct 15 01:10:55 AM UTC 24 | 102031200 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.3530809822 | Oct 15 01:10:58 AM UTC 24 | Oct 15 01:11:00 AM UTC 24 | 62278360 ps | ||
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| T45 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_buffered_enable.3520362638 | Oct 15 01:10:53 AM UTC 24 | Oct 15 01:10:55 AM UTC 24 | 207310227 ps | ||
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| T43 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_ndmreset_req.1944193657 | Oct 15 01:10:49 AM UTC 24 | Oct 15 01:10:55 AM UTC 24 | 687408522 ps | ||
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| T114 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_dataaddr_rw_access.201220640 | Oct 15 01:10:36 AM UTC 24 | Oct 15 01:10:55 AM UTC 24 | 83074525 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.2753153097 | Oct 15 01:10:36 AM UTC 24 | Oct 15 01:10:56 AM UTC 24 | 197585996 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.3674079712 | Oct 15 01:10:36 AM UTC 24 | Oct 15 01:10:56 AM UTC 24 | 146826710 ps | ||
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| T150 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/45.rv_dm_alert_test.291175557 | Oct 15 01:11:40 AM UTC 24 | Oct 15 01:11:41 AM UTC 24 | 150104879 ps | ||
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| T152 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.1511325186 | Oct 15 01:11:32 AM UTC 24 | Oct 15 01:11:42 AM UTC 24 | 1411688726 ps | ||
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| T36 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.3948319646 | Oct 15 01:11:00 AM UTC 24 | Oct 15 01:11:44 AM UTC 24 | 26892037748 ps | ||
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| T196 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.21908632 | Oct 15 01:11:29 AM UTC 24 | Oct 15 01:11:47 AM UTC 24 | 18452645918 ps | ||
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| T303 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/16.rv_dm_bad_sba_tl_access.3989310296 | Oct 15 01:11:26 AM UTC 24 | Oct 15 01:11:49 AM UTC 24 | 6961649841 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.2637864355 | Oct 15 01:11:02 AM UTC 24 | Oct 15 01:11:49 AM UTC 24 | 9455938520 ps | ||
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| T32 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.384329124 | Oct 15 01:11:39 AM UTC 24 | Oct 15 01:11:50 AM UTC 24 | 2787372605 ps | ||
| T225 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/47.rv_dm_stress_all.3022861183 | Oct 15 01:11:41 AM UTC 24 | Oct 15 01:11:50 AM UTC 24 | 4121261366 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/41.rv_dm_stress_all.1837361523 | Oct 15 01:11:39 AM UTC 24 | Oct 15 01:11:51 AM UTC 24 | 2973124925 ps | ||
| T304 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/18.rv_dm_bad_sba_tl_access.168458234 | Oct 15 01:11:29 AM UTC 24 | Oct 15 01:11:51 AM UTC 24 | 6373588759 ps | ||
| T305 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/19.rv_dm_sba_tl_access.1348595167 | Oct 15 01:11:29 AM UTC 24 | Oct 15 01:11:52 AM UTC 24 | 6485375093 ps | ||
| T306 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.1338679405 | Oct 15 01:11:03 AM UTC 24 | Oct 15 01:11:52 AM UTC 24 | 21856515298 ps | ||
| T307 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/47.rv_dm_alert_test.3286596662 | Oct 15 01:11:41 AM UTC 24 | Oct 15 01:11:53 AM UTC 24 | 65477997 ps | ||
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| T311 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/17.rv_dm_bad_sba_tl_access.1467525877 | Oct 15 01:11:27 AM UTC 24 | Oct 15 01:11:55 AM UTC 24 | 10428643230 ps | ||
| T197 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/35.rv_dm_stress_all.1611715214 | Oct 15 01:11:37 AM UTC 24 | Oct 15 01:11:57 AM UTC 24 | 4995130495 ps | ||
| T79 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.567859112 | Oct 15 01:11:06 AM UTC 24 | Oct 15 01:12:00 AM UTC 24 | 2383375437 ps | ||
| T118 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.4171445271 | Oct 15 01:10:58 AM UTC 24 | Oct 15 01:12:01 AM UTC 24 | 18733052322 ps | ||
| T312 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_autoincr_sba_tl_access.1285439591 | Oct 15 01:10:40 AM UTC 24 | Oct 15 01:12:08 AM UTC 24 | 25867018942 ps | ||
| T313 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/6.rv_dm_autoincr_sba_tl_access.2879608922 | Oct 15 01:11:00 AM UTC 24 | Oct 15 01:12:08 AM UTC 24 | 25592449318 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.2436516784 | Oct 15 01:10:53 AM UTC 24 | Oct 15 01:12:08 AM UTC 24 | 3507126896 ps | ||
| T210 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/15.rv_dm_autoincr_sba_tl_access.775584652 | Oct 15 01:11:24 AM UTC 24 | Oct 15 01:12:12 AM UTC 24 | 13983157431 ps | ||
| T242 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/49.rv_dm_stress_all.3522450402 | Oct 15 01:11:42 AM UTC 24 | Oct 15 01:12:14 AM UTC 24 | 6238165904 ps | ||
| T314 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/11.rv_dm_autoincr_sba_tl_access.3970999631 | Oct 15 01:11:06 AM UTC 24 | Oct 15 01:12:15 AM UTC 24 | 18866837340 ps | ||
| T315 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/13.rv_dm_autoincr_sba_tl_access.3853570874 | Oct 15 01:11:21 AM UTC 24 | Oct 15 01:12:25 AM UTC 24 | 33069710742 ps | ||
| T94 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.2607259863 | Oct 15 01:10:58 AM UTC 24 | Oct 15 01:12:27 AM UTC 24 | 22807593823 ps | ||
| T219 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/10.rv_dm_autoincr_sba_tl_access.402369490 | Oct 15 01:11:06 AM UTC 24 | Oct 15 01:13:16 AM UTC 24 | 33765061912 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.2119822898 | Oct 15 01:10:58 AM UTC 24 | Oct 15 01:13:31 AM UTC 24 | 16751616395 ps | ||
| T316 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/18.rv_dm_autoincr_sba_tl_access.3326066943 | Oct 15 01:11:29 AM UTC 24 | Oct 15 01:14:16 AM UTC 24 | 66825125974 ps |
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