RV_DM Lint Results
Wednesday August 21 2024 23:02:35 UTC
Branch: os_regression
Tool: ASCENTLINT
| Build Mode |
Flow Infos |
Flow Warnings |
Flow Errors |
Lint Infos |
Lint Warnings |
Lint Errors |
| default |
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294 |
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Messages for Build Mode 'default'
Lint Infos
I FSM_DEFAULT_REQ: prim_sync_reqack.sv:99 Next state register 'gen_rz_hs_protocol.src_fsm_d' has no assignment in the default branch of the case statement for this finite state machine New
I FSM_DEFAULT_REQ: prim_sync_reqack.sv:151 Next state register 'gen_rz_hs_protocol.dst_fsm_d' has no assignment in the default branch of the case statement for this finite state machine New
I FSM_DEFAULT_REQ: prim_diff_decode.sv:158 Next state register 'gen_async.state_d' has no assignment in the default branch of the case statement for this finite state machine New
I FSM_DEFAULT_REQ: dm_mem.sv:201 Next state register 'state_d' has no assignment in the default branch of the case statement for this finite state machine New
I FSM_DEFAULT_REQ: dmi_jtag.sv:223 Next state register 'state_d' is not always assigned in the default branch of the case statement for this finite state machine New
I FSM_DEFAULT_REQ: dmi_jtag_tap.sv:297 Next state register 'tap_state_d' has no assignment in the default branch of the case statement for this finite state machine New
I NESTED_SUBPROG: tlul_pkg.sv:143 Function 'prim_mubi_pkg::mubi4_test_invalid' is called from within a function New
I VAR_INDEX_WRITE: prim_fifo_sync.sv:124 Variable index expression 'gen_normal_fifo.storage[gen_normal_fifo.fifo_wptr]' encountered New
I VAR_INDEX_WRITE: dm_csrs.sv:372 Variable index expression 'data_d[dmi_req_i.addr[$clog2(dm::DataCount) - 1:0]]' encountered New
I VAR_INDEX_WRITE: dm_csrs.sv:388 Variable index expression 'havereset_d_aligned[selected_hart]' encountered New
I VAR_INDEX_WRITE: dm_csrs.sv:441 Variable index expression 'progbuf_d[dmi_req_i.addr[$clog2(dm::ProgBufSize) - 1:0]]' encountered New
I VAR_INDEX_WRITE: dm_csrs.sv:573 Variable index expression 'haltreq_o[selected_hart]' encountered New
I VAR_INDEX_WRITE: dm_csrs.sv:574 Variable index expression 'resumereq_o[selected_hart]' encountered New
I VAR_INDEX_WRITE: dm_mem.sv:254 Variable index expression 'resuming_d_aligned[hartsel]' encountered New
I VAR_INDEX_WRITE: dm_mem.sv:262 Variable index expression 'halted_aligned[wdata_hartsel]' encountered New
I VAR_INDEX_WRITE: dm_mem.sv:263 Variable index expression 'halted_d_aligned[wdata_hartsel]' encountered New
I VAR_INDEX_WRITE: dm_mem.sv:270 Variable index expression 'halted_d_aligned[wdata_hartsel]' encountered New
I VAR_INDEX_WRITE: dm_mem.sv:272 Variable index expression 'resuming_d_aligned[wdata_hartsel]' encountered New
I VAR_INDEX_WRITE: dm_mem.sv:349 Variable index expression 'rdata[DbgAddressBits'(hartsel) & DbgAddressBits'(3'b111)]' encountered New
I VAR_INDEX_WRITE: dm_sba.sv:77 Variable index expression 'be_mask[be_idx]' encountered New
I VAR_INDEX_WRITE: dm_sba.sv:80 Variable range select expression 'be_mask[int '({be_idx[$high(be_idx):1],1'b0}) +: 2]' encountered New
I VAR_INDEX_WRITE: dm_sba.sv:83 Variable range select expression 'be_mask[int '({be_idx[$high(be_idx)],2'h0}) +: 4]' encountered New
I CASE_INC: prim_alert_sender.sv:199 Case statement tag not specified for value 'b111 New
I CASE_INC: prim_diff_decode.sv:115 Case statement tag not specified for value 'b11 New
I CASE_INC: tlul_err.sv:62 Case statement tag not specified for value 'h3 New
I CASE_INC: tlul_lc_gate.sv:171 Case statement tag not specified for value 'b000000000 and many other values New
I CASE_INC: dm_mem.sv:440 Case statement tag not specified for value 'b00000100 and many other values New
I CASE_INC: dm_sba.sv:75 Case statement tag not specified for value 'b100 and 3 other values New
I CASE_INC: dm_sba.sv:114 Case statement tag not specified for value 'b101 and 2 other values New
I CASE_INC: dmi_jtag.sv:157 Case statement tag not specified for value 'b101 and 2 other values New
I CASE_INC: dmi_jtag.sv:183 Case statement tag not specified for value 'b01 New
I CASE_INC: dmi_jtag.sv:214 Case statement tag not specified for value 'b00 and 1 other value New
I CASE_INC: dmi_jtag_tap.sv:155 Case statement tag not specified for value 'b00010 and 26 other values New
I CASE_INC: dmi_jtag_tap.sv:176 Case statement tag not specified for value 'b00000 and 28 other values New
I CASE_SEL_CONST: rv_dm_regs_reg_top.sv:253 Constant value '1'b1' found as case statement selector New
I ONE_BIT_VEC: rv_dm.sv:18 Declaration range '[NumAlerts - 1:0]' ([0:0]) of 'AlertAsyncOn' has a length of one, instance 'rv_dm' of module 'rv_dm' (NumAlerts=1) New
I ONE_BIT_VEC: rv_dm.sv:44 Declaration range '[NrHarts - 1:0]' ([0:0]) of 'debug_req_o' has a length of one, instance 'rv_dm' of module 'rv_dm' (NrHarts=1) New
I ONE_BIT_VEC: rv_dm.sv:45 Declaration range '[NrHarts - 1:0]' ([0:0]) of 'unavailable_i' has a length of one, instance 'rv_dm' of module 'rv_dm' (NrHarts=1) New
I ONE_BIT_VEC: rv_dm.sv:61 Declaration range '[NumAlerts - 1:0]' ([0:0]) of 'alert_rx_i' has a length of one, instance 'rv_dm' of module 'rv_dm' (NumAlerts=1) New
I ONE_BIT_VEC: rv_dm.sv:62 Declaration range '[NumAlerts - 1:0]' ([0:0]) of 'alert_tx_o' has a length of one, instance 'rv_dm' of module 'rv_dm' (NumAlerts=1) New
I ONE_BIT_VEC: rv_dm.sv:90 Declaration range '[NrHarts - 1:0]' ([0:0]) of 'hartinfo' has a length of one, instance 'rv_dm' of module 'rv_dm' (NrHarts=1) New
I ONE_BIT_VEC: rv_dm.sv:98 Declaration range '[NrHarts - 1:0]' ([0:0]) of 'SelectableHarts' has a length of one, instance 'rv_dm' of module 'rv_dm' (NrHarts=1) New
I ONE_BIT_VEC: rv_dm.sv:126 Declaration range '[NumAlerts - 1:0]' ([0:0]) of 'alert_test' has a length of one, instance 'rv_dm' of module 'rv_dm' (NumAlerts=1) New
I ONE_BIT_VEC: rv_dm.sv:434 Declaration range '[NrHarts - 1:0]' ([0:0]) of 'debug_req_en' has a length of one, instance 'rv_dm' of module 'rv_dm' (NrHarts=1) New
I ONE_BIT_VEC: rv_dm.sv:435 Declaration range '[NrHarts - 1:0]' ([0:0]) of 'debug_req' has a length of one, instance 'rv_dm' of module 'rv_dm' (NrHarts=1) New
I ONE_BIT_VEC: rv_dm_regs_reg_top.sv:135 Declaration range '[0:0]' of 'alert_test_flds_we' has a length of one New
I ONE_BIT_VEC: prim_buf.sv:24 Declaration range '[Width - 1:0]' ([0:0]) of 'in_i' has a length of one, instance 'rv_dm.u_prim_lc_sync_lc_hw_debug_en.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf' of module 'prim_buf' (Width=1) New
I ONE_BIT_VEC: prim_buf.sv:25 Declaration range '[Width - 1:0]' ([0:0]) of 'out_o' has a length of one, instance 'rv_dm.u_prim_lc_sync_lc_hw_debug_en.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf' of module 'prim_buf' (Width=1) New
I ONE_BIT_VEC: prim_flop.sv:22 Declaration range '[Width - 1:0]' ([0:0]) of 'ResetValue' has a length of one, instance 'rv_dm.u_prim_flop_2sync_lc_rst_assert.gen_generic.u_impl_generic.u_sync_1' of module 'prim_flop' (Width=1) New
I ONE_BIT_VEC: prim_flop.sv:27 Declaration range '[Width - 1:0]' ([0:0]) of 'd_i' has a length of one, instance 'rv_dm.u_prim_flop_2sync_lc_rst_assert.gen_generic.u_impl_generic.u_sync_1' of module 'prim_flop' (Width=1) New
I ONE_BIT_VEC: prim_flop.sv:28 Declaration range '[Width - 1:0]' ([0:0]) of 'q_o' has a length of one, instance 'rv_dm.u_prim_flop_2sync_lc_rst_assert.gen_generic.u_impl_generic.u_sync_1' of module 'prim_flop' (Width=1) New
I ONE_BIT_VEC: prim_flop_2sync.sv:19 Declaration range '[Width - 1:0]' ([0:0]) of 'ResetValue' has a length of one, instance 'rv_dm.u_prim_flop_2sync_lc_rst_assert' of module 'prim_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_flop_2sync.sv:25 Declaration range '[Width - 1:0]' ([0:0]) of 'd_i' has a length of one, instance 'rv_dm.u_prim_flop_2sync_lc_rst_assert' of module 'prim_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_flop_2sync.sv:26 Declaration range '[Width - 1:0]' ([0:0]) of 'q_o' has a length of one, instance 'rv_dm.u_prim_flop_2sync_lc_rst_assert' of module 'prim_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_fifo_sync.sv:63 Declaration range '[gen_normal_fifo.PtrW - 1:0]' ([0:0]) of 'gen_normal_fifo.fifo_wptr' has a length of one, instance 'rv_dm.u_dm_top.i_dm_csrs.i_fifo' of module 'prim_fifo_sync' (Depth=2,gen_normal_fifo.PtrW=1 ('prim_util_pkg::vbits(Depth)')) New
I ONE_BIT_VEC: prim_fifo_sync_cnt.sv:25 Declaration range '[PtrW - 1:0]' ([0:0]) of 'wptr_o' has a length of one, instance 'rv_dm.u_dm_top.i_dm_csrs.i_fifo.gen_normal_fifo.u_fifo_cnt' of module 'prim_fifo_sync_cnt' (Depth=2,PtrW=1 ('prim_util_pkg::vbits(Depth)')) New
I ONE_BIT_VEC: prim_fifo_sync_cnt.sv:26 Declaration range '[PtrW - 1:0]' ([0:0]) of 'rptr_o' has a length of one, instance 'rv_dm.u_dm_top.i_dm_csrs.i_fifo.gen_normal_fifo.u_fifo_cnt' of module 'prim_fifo_sync_cnt' (Depth=2,PtrW=1 ('prim_util_pkg::vbits(Depth)')) New
I ONE_BIT_VEC: prim_generic_buf.sv:10 Declaration range '[Width - 1:0]' ([0:0]) of 'in_i' has a length of one, instance 'rv_dm.u_prim_lc_sync_lc_hw_debug_en.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic' of module 'prim_generic_buf' (Width=1) New
I ONE_BIT_VEC: prim_generic_buf.sv:11 Declaration range '[Width - 1:0]' ([0:0]) of 'out_o' has a length of one, instance 'rv_dm.u_prim_lc_sync_lc_hw_debug_en.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic' of module 'prim_generic_buf' (Width=1) New
I ONE_BIT_VEC: prim_generic_buf.sv:14 Declaration range '[Width - 1:0]' ([0:0]) of 'inv' has a length of one, instance 'rv_dm.u_prim_lc_sync_lc_hw_debug_en.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic' of module 'prim_generic_buf' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop.sv:9 Declaration range '[Width - 1:0]' ([0:0]) of 'ResetValue' has a length of one, instance 'rv_dm.u_prim_flop_2sync_lc_rst_assert.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic' of module 'prim_generic_flop' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop.sv:13 Declaration range '[Width - 1:0]' ([0:0]) of 'd_i' has a length of one, instance 'rv_dm.u_prim_flop_2sync_lc_rst_assert.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic' of module 'prim_generic_flop' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop.sv:14 Declaration range '[Width - 1:0]' ([0:0]) of 'q_o' has a length of one, instance 'rv_dm.u_prim_flop_2sync_lc_rst_assert.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic' of module 'prim_generic_flop' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop_2sync.sv:9 Declaration range '[Width - 1:0]' ([0:0]) of 'ResetValue' has a length of one, instance 'rv_dm.u_prim_flop_2sync_lc_rst_assert.gen_generic.u_impl_generic' of module 'prim_generic_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop_2sync.sv:14 Declaration range '[Width - 1:0]' ([0:0]) of 'd_i' has a length of one, instance 'rv_dm.u_prim_flop_2sync_lc_rst_assert.gen_generic.u_impl_generic' of module 'prim_generic_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop_2sync.sv:15 Declaration range '[Width - 1:0]' ([0:0]) of 'q_o' has a length of one, instance 'rv_dm.u_prim_flop_2sync_lc_rst_assert.gen_generic.u_impl_generic' of module 'prim_generic_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop_2sync.sv:18 Declaration range '[Width - 1:0]' ([0:0]) of 'd_o' has a length of one, instance 'rv_dm.u_prim_flop_2sync_lc_rst_assert.gen_generic.u_impl_generic' of module 'prim_generic_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop_2sync.sv:19 Declaration range '[Width - 1:0]' ([0:0]) of 'intq' has a length of one, instance 'rv_dm.u_prim_flop_2sync_lc_rst_assert.gen_generic.u_impl_generic' of module 'prim_generic_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_lc_sync.sv:30 Declaration range '[NumCopies - 1:0]' ([0:0]) of 'lc_en_o' has a length of one, instance 'rv_dm.u_prim_lc_sync_lc_hw_debug_en' of module 'prim_lc_sync' (NumCopies=1) New
I ONE_BIT_VEC: prim_sec_anchor_buf.sv:10 Declaration range '[Width - 1:0]' ([0:0]) of 'in_i' has a length of one, instance 'rv_dm.u_prim_lc_sync_lc_hw_debug_en.gen_buffs[0].gen_bits[0].u_prim_buf' of module 'prim_sec_anchor_buf' (Width=1) New
I ONE_BIT_VEC: prim_sec_anchor_buf.sv:11 Declaration range '[Width - 1:0]' ([0:0]) of 'out_o' has a length of one, instance 'rv_dm.u_prim_lc_sync_lc_hw_debug_en.gen_buffs[0].gen_bits[0].u_prim_buf' of module 'prim_sec_anchor_buf' (Width=1) New
I ONE_BIT_VEC: prim_subreg.sv:12 Declaration range '[DW - 1:0]' ([0:0]) of 'RESVAL' has a length of one, instance 'rv_dm.u_reg_regs.u_late_debug_enable_regwen' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:21 Declaration range '[DW - 1:0]' ([0:0]) of 'wd' has a length of one, instance 'rv_dm.u_reg_regs.u_late_debug_enable_regwen' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:25 Declaration range '[DW - 1:0]' ([0:0]) of 'd' has a length of one, instance 'rv_dm.u_reg_regs.u_late_debug_enable_regwen' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:29 Declaration range '[DW - 1:0]' ([0:0]) of 'q' has a length of one, instance 'rv_dm.u_reg_regs.u_late_debug_enable_regwen' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:34 Declaration range '[DW - 1:0]' ([0:0]) of 'ds' has a length of one, instance 'rv_dm.u_reg_regs.u_late_debug_enable_regwen' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:35 Declaration range '[DW - 1:0]' ([0:0]) of 'qs' has a length of one, instance 'rv_dm.u_reg_regs.u_late_debug_enable_regwen' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:39 Declaration range '[DW - 1:0]' ([0:0]) of 'wr_data' has a length of one, instance 'rv_dm.u_reg_regs.u_late_debug_enable_regwen' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:17 Declaration range '[DW - 1:0]' ([0:0]) of 'wd' has a length of one, instance 'rv_dm.u_reg_regs.u_late_debug_enable_regwen.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:21 Declaration range '[DW - 1:0]' ([0:0]) of 'd' has a length of one, instance 'rv_dm.u_reg_regs.u_late_debug_enable_regwen.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:24 Declaration range '[DW - 1:0]' ([0:0]) of 'q' has a length of one, instance 'rv_dm.u_reg_regs.u_late_debug_enable_regwen.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:28 Declaration range '[DW - 1:0]' ([0:0]) of 'wr_data' has a length of one, instance 'rv_dm.u_reg_regs.u_late_debug_enable_regwen.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_ext.sv:12 Declaration range '[DW - 1:0]' ([0:0]) of 'wd' has a length of one, instance 'rv_dm.u_reg_regs.u_alert_test' of module 'prim_subreg_ext' (DW=1) New
I ONE_BIT_VEC: prim_subreg_ext.sv:14 Declaration range '[DW - 1:0]' ([0:0]) of 'd' has a length of one, instance 'rv_dm.u_reg_regs.u_alert_test' of module 'prim_subreg_ext' (DW=1) New
I ONE_BIT_VEC: prim_subreg_ext.sv:19 Declaration range '[DW - 1:0]' ([0:0]) of 'q' has a length of one, instance 'rv_dm.u_reg_regs.u_alert_test' of module 'prim_subreg_ext' (DW=1) New
I ONE_BIT_VEC: prim_subreg_ext.sv:20 Declaration range '[DW - 1:0]' ([0:0]) of 'ds' has a length of one, instance 'rv_dm.u_reg_regs.u_alert_test' of module 'prim_subreg_ext' (DW=1) New
I ONE_BIT_VEC: prim_subreg_ext.sv:21 Declaration range '[DW - 1:0]' ([0:0]) of 'qs' has a length of one, instance 'rv_dm.u_reg_regs.u_alert_test' of module 'prim_subreg_ext' (DW=1) New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'd_sink' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'mem_tl_d_o' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'mem_tl_win_d2h' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'mem_tl_win_d2h_gated' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'regs_tl_d_o' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'sba_tl_h_i' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'sba_tl_h_i_int' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_d2h_error' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_d2h_i' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_d2h_int' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_d2h_o' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_d2h_t' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_h_o' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_h_o_int' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_i' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_o' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_o_pre' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_reg_d2h' has a length of one New
I ONE_BIT_VEC: dm_csrs.sv:21 Declaration range '[NrHarts - 1:0]' ([0:0]) of 'SelectableHarts' has a length of one, instance 'rv_dm.u_dm_top.i_dm_csrs' of module 'dm_csrs' (NrHarts=1) New
I ONE_BIT_VEC: dm_csrs.sv:42 Declaration range '[NrHarts - 1:0]' ([0:0]) of 'hartinfo_i' has a length of one, instance 'rv_dm.u_dm_top.i_dm_csrs' of module 'dm_csrs' (NrHarts=1) New
I ONE_BIT_VEC: dm_csrs.sv:43 Declaration range '[NrHarts - 1:0]' ([0:0]) of 'halted_i' has a length of one, instance 'rv_dm.u_dm_top.i_dm_csrs' of module 'dm_csrs' (NrHarts=1) New
I ONE_BIT_VEC: dm_csrs.sv:44 Declaration range '[NrHarts - 1:0]' ([0:0]) of 'unavailable_i' has a length of one, instance 'rv_dm.u_dm_top.i_dm_csrs' of module 'dm_csrs' (NrHarts=1) New
I ONE_BIT_VEC: dm_csrs.sv:45 Declaration range '[NrHarts - 1:0]' ([0:0]) of 'resumeack_i' has a length of one, instance 'rv_dm.u_dm_top.i_dm_csrs' of module 'dm_csrs' (NrHarts=1) New
I ONE_BIT_VEC: dm_csrs.sv:48 Declaration range '[NrHarts - 1:0]' ([0:0]) of 'haltreq_o' has a length of one, instance 'rv_dm.u_dm_top.i_dm_csrs' of module 'dm_csrs' (NrHarts=1) New
I ONE_BIT_VEC: dm_csrs.sv:49 Declaration range '[NrHarts - 1:0]' ([0:0]) of 'resumereq_o' has a length of one, instance 'rv_dm.u_dm_top.i_dm_csrs' of module 'dm_csrs' (NrHarts=1) New
I ONE_BIT_VEC: dm_csrs.sv:97 Declaration range '[(NrHarts - 1) / 2 ** 5:0]' ([0:0]) of 'halted_reshaped0' has a length of one, instance 'rv_dm.u_dm_top.i_dm_csrs' of module 'dm_csrs' (NrHarts=1) New
I ONE_BIT_VEC: dm_csrs.sv:98 Declaration range '[(NrHarts - 1) / 2 ** 10:0]' ([0:0]) of 'halted_reshaped1' has a length of one, instance 'rv_dm.u_dm_top.i_dm_csrs' of module 'dm_csrs' (NrHarts=1) New
I ONE_BIT_VEC: dm_csrs.sv:99 Declaration range '[(NrHarts - 1) / 2 ** 15:0]' ([0:0]) of 'halted_reshaped2' has a length of one, instance 'rv_dm.u_dm_top.i_dm_csrs' of module 'dm_csrs' (NrHarts=1) New
I ONE_BIT_VEC: dm_csrs.sv:172 Declaration range '[NrHarts - 1:0]' ([0:0]) of 'havereset_d' has a length of one, instance 'rv_dm.u_dm_top.i_dm_csrs' of module 'dm_csrs' (NrHarts=1) New
I ONE_BIT_VEC: dm_csrs.sv:177 Declaration range '[HartSelLen - 1:0]' ([0:0]) of 'selected_hart' has a length of one, instance 'rv_dm.u_dm_top.i_dm_csrs' of module 'dm_csrs' (HartSelLen=1 ('(NrHarts == 1) ? 1 : $clog2(NrHarts)'),NrHarts=1) New
I ONE_BIT_VEC: dm_mem.sv:22 Declaration range '[NrHarts - 1:0]' ([0:0]) of 'SelectableHarts' has a length of one, instance 'rv_dm.u_dm_top.i_dm_mem' of module 'dm_mem' (NrHarts=1) New
I ONE_BIT_VEC: dm_mem.sv:29 Declaration range '[NrHarts - 1:0]' ([0:0]) of 'debug_req_o' has a length of one, instance 'rv_dm.u_dm_top.i_dm_mem' of module 'dm_mem' (NrHarts=1) New
I ONE_BIT_VEC: dm_mem.sv:33 Declaration range '[NrHarts - 1:0]' ([0:0]) of 'haltreq_i' has a length of one, instance 'rv_dm.u_dm_top.i_dm_mem' of module 'dm_mem' (NrHarts=1) New
I ONE_BIT_VEC: dm_mem.sv:34 Declaration range '[NrHarts - 1:0]' ([0:0]) of 'resumereq_i' has a length of one, instance 'rv_dm.u_dm_top.i_dm_mem' of module 'dm_mem' (NrHarts=1) New
I ONE_BIT_VEC: dm_mem.sv:38 Declaration range '[NrHarts - 1:0]' ([0:0]) of 'halted_o' has a length of one, instance 'rv_dm.u_dm_top.i_dm_mem' of module 'dm_mem' (NrHarts=1) New
I ONE_BIT_VEC: dm_mem.sv:39 Declaration range '[NrHarts - 1:0]' ([0:0]) of 'resuming_o' has a length of one, instance 'rv_dm.u_dm_top.i_dm_mem' of module 'dm_mem' (NrHarts=1) New
I ONE_BIT_VEC: dm_mem.sv:97 Declaration range '[NrHarts - 1:0]' ([0:0]) of 'halted_d' has a length of one, instance 'rv_dm.u_dm_top.i_dm_mem' of module 'dm_mem' (NrHarts=1) New
I ONE_BIT_VEC: dm_mem.sv:98 Declaration range '[NrHarts - 1:0]' ([0:0]) of 'resuming_d' has a length of one, instance 'rv_dm.u_dm_top.i_dm_mem' of module 'dm_mem' (NrHarts=1) New
I ONE_BIT_VEC: dm_mem.sv:110 Declaration range '[HartSelLen - 1:0]' ([0:0]) of 'hartsel' has a length of one, instance 'rv_dm.u_dm_top.i_dm_mem' of module 'dm_mem' (HartSelLen=1 ('(NrHarts == 1) ? 1 : $clog2(NrHarts)'),NrHarts=1) New
I ONE_BIT_VEC: dm_top.sv:26 Declaration range '[NrHarts - 1:0]' ([0:0]) of 'SelectableHarts' has a length of one, instance 'rv_dm.u_dm_top' of module 'dm_top' (NrHarts=1) New
I ONE_BIT_VEC: dm_top.sv:43 Declaration range '[NrHarts - 1:0]' ([0:0]) of 'debug_req_o' has a length of one, instance 'rv_dm.u_dm_top' of module 'dm_top' (NrHarts=1) New
I ONE_BIT_VEC: dm_top.sv:45 Declaration range '[NrHarts - 1:0]' ([0:0]) of 'unavailable_i' has a length of one, instance 'rv_dm.u_dm_top' of module 'dm_top' (NrHarts=1) New
I ONE_BIT_VEC: dm_top.sv:46 Declaration range '[NrHarts - 1:0]' ([0:0]) of 'hartinfo_i' has a length of one, instance 'rv_dm.u_dm_top' of module 'dm_top' (NrHarts=1) New
I ONE_BIT_VEC: dm_top.sv:81 Declaration range '[NrHarts - 1:0]' ([0:0]) of 'halted' has a length of one, instance 'rv_dm.u_dm_top' of module 'dm_top' (NrHarts=1) New
I ONE_BIT_VEC: dm_top.sv:83 Declaration range '[NrHarts - 1:0]' ([0:0]) of 'resumeack' has a length of one, instance 'rv_dm.u_dm_top' of module 'dm_top' (NrHarts=1) New
I ONE_BIT_VEC: dm_top.sv:84 Declaration range '[NrHarts - 1:0]' ([0:0]) of 'haltreq' has a length of one, instance 'rv_dm.u_dm_top' of module 'dm_top' (NrHarts=1) New
I ONE_BIT_VEC: dm_top.sv:85 Declaration range '[NrHarts - 1:0]' ([0:0]) of 'resumereq' has a length of one, instance 'rv_dm.u_dm_top' of module 'dm_top' (NrHarts=1) New
I EXPLICIT_BITLEN: prim_fifo_sync_cnt.sv:51 Bit length not specified for constant '1' New
I EXPLICIT_BITLEN: prim_fifo_sync_cnt.sv:52 Bit length not specified for constant '1' New
I EXPLICIT_BITLEN: prim_util_pkg.sv:85 Bit length not specified for constant '1' New
I EXPLICIT_BITLEN: tlul_err.sv:69 Bit length not specified for constant "'h1" New
I EXPLICIT_BITLEN: tlul_err.sv:77 Bit length not specified for constant "'h2" New
I EXPLICIT_BITLEN: dm_csrs.sv:554 Bit length not specified for constant '1' New
I EXPLICIT_BITLEN: dm_csrs.sv:554 Bit length not specified for constant '2' New
I MIN_NAME_LEN: rv_dm_reg_pkg.sv:22 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: rv_dm_reg_pkg.sv:27 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:80 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:80 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:85 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:106 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:106 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:111 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:124 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:124 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:131 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:131 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:212 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:212 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:217 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:238 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:238 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:243 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:256 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:256 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:263 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:263 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:344 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:344 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:349 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:370 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:370 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:375 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:388 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:388 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:395 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:395 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:476 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:476 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:481 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:502 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:502 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:507 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:520 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:520 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:527 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:527 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg.sv:25 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg.sv:29 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg_arb.sv:21 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg_arb.sv:24 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg_ext.sv:14 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg_ext.sv:19 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: dm_csrs.sv:124 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: dm_csrs.sv:141 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: dm_csrs.sv:154 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: dm_mem.sv:281 Name 'i' is shorter than minimum length 2 New
I ZERO_BASED: dm_pkg.sv:102 Declaration range '[31:23]' of 'dmstatus' is not zero-based New
I ZERO_BASED: dm_pkg.sv:102 Declaration range '[31:23]' of 'dmstatus_t' is not zero-based New
I ZERO_BASED: dm_pkg.sv:102 Declaration range '[31:23]' of 'zero1' is not zero-based New
I ZERO_BASED: dm_pkg.sv:104 Declaration range '[21:20]' of 'dmstatus' is not zero-based New
I ZERO_BASED: dm_pkg.sv:104 Declaration range '[21:20]' of 'dmstatus_t' is not zero-based New
I ZERO_BASED: dm_pkg.sv:104 Declaration range '[21:20]' of 'zero0' is not zero-based New
I ZERO_BASED: dm_pkg.sv:131 Declaration range '[25:16]' of 'dmcontrol_d' is not zero-based New
I ZERO_BASED: dm_pkg.sv:131 Declaration range '[25:16]' of 'dmcontrol_t' is not zero-based New
I ZERO_BASED: dm_pkg.sv:131 Declaration range '[25:16]' of 'hartsello' is not zero-based New
I ZERO_BASED: dm_pkg.sv:132 Declaration range '[15:6]' of 'dmcontrol_d' is not zero-based New
I ZERO_BASED: dm_pkg.sv:132 Declaration range '[15:6]' of 'dmcontrol_t' is not zero-based New
I ZERO_BASED: dm_pkg.sv:132 Declaration range '[15:6]' of 'hartselhi' is not zero-based New
I ZERO_BASED: dm_pkg.sv:133 Declaration range '[5:4]' of 'dmcontrol_d' is not zero-based New
I ZERO_BASED: dm_pkg.sv:133 Declaration range '[5:4]' of 'dmcontrol_t' is not zero-based New
I ZERO_BASED: dm_pkg.sv:133 Declaration range '[5:4]' of 'zero0' is not zero-based New
I ZERO_BASED: dm_pkg.sv:141 Declaration range '[31:24]' of 'DebugHartInfo' is not zero-based New
I ZERO_BASED: dm_pkg.sv:141 Declaration range '[31:24]' of 'hartinfo' is not zero-based New
I ZERO_BASED: dm_pkg.sv:141 Declaration range '[31:24]' of 'hartinfo_aligned' is not zero-based New
I ZERO_BASED: dm_pkg.sv:141 Declaration range '[31:24]' of 'hartinfo_i' is not zero-based New
I ZERO_BASED: dm_pkg.sv:141 Declaration range '[31:24]' of 'hartinfo_t' is not zero-based New
I ZERO_BASED: dm_pkg.sv:141 Declaration range '[31:24]' of 'zero1' is not zero-based New
I ZERO_BASED: dm_pkg.sv:142 Declaration range '[23:20]' of 'DebugHartInfo' is not zero-based New
I ZERO_BASED: dm_pkg.sv:142 Declaration range '[23:20]' of 'hartinfo' is not zero-based New
I ZERO_BASED: dm_pkg.sv:142 Declaration range '[23:20]' of 'hartinfo_aligned' is not zero-based New
I ZERO_BASED: dm_pkg.sv:142 Declaration range '[23:20]' of 'hartinfo_i' is not zero-based New
I ZERO_BASED: dm_pkg.sv:142 Declaration range '[23:20]' of 'hartinfo_t' is not zero-based New
I ZERO_BASED: dm_pkg.sv:142 Declaration range '[23:20]' of 'nscratch' is not zero-based New
I ZERO_BASED: dm_pkg.sv:143 Declaration range '[19:17]' of 'DebugHartInfo' is not zero-based New
I ZERO_BASED: dm_pkg.sv:143 Declaration range '[19:17]' of 'hartinfo' is not zero-based New
I ZERO_BASED: dm_pkg.sv:143 Declaration range '[19:17]' of 'hartinfo_aligned' is not zero-based New
I ZERO_BASED: dm_pkg.sv:143 Declaration range '[19:17]' of 'hartinfo_i' is not zero-based New
I ZERO_BASED: dm_pkg.sv:143 Declaration range '[19:17]' of 'hartinfo_t' is not zero-based New
I ZERO_BASED: dm_pkg.sv:143 Declaration range '[19:17]' of 'zero0' is not zero-based New
I ZERO_BASED: dm_pkg.sv:145 Declaration range '[15:12]' of 'DebugHartInfo' is not zero-based New
I ZERO_BASED: dm_pkg.sv:145 Declaration range '[15:12]' of 'datasize' is not zero-based New
I ZERO_BASED: dm_pkg.sv:145 Declaration range '[15:12]' of 'hartinfo' is not zero-based New
I ZERO_BASED: dm_pkg.sv:145 Declaration range '[15:12]' of 'hartinfo_aligned' is not zero-based New
I ZERO_BASED: dm_pkg.sv:145 Declaration range '[15:12]' of 'hartinfo_i' is not zero-based New
I ZERO_BASED: dm_pkg.sv:145 Declaration range '[15:12]' of 'hartinfo_t' is not zero-based New
I ZERO_BASED: dm_pkg.sv:156 Declaration range '[31:29]' of 'a_abstractcs' is not zero-based New
I ZERO_BASED: dm_pkg.sv:156 Declaration range '[31:29]' of 'abstractcs' is not zero-based New
I ZERO_BASED: dm_pkg.sv:156 Declaration range '[31:29]' of 'abstractcs_t' is not zero-based New
I ZERO_BASED: dm_pkg.sv:156 Declaration range '[31:29]' of 'zero3' is not zero-based New
I ZERO_BASED: dm_pkg.sv:157 Declaration range '[28:24]' of 'a_abstractcs' is not zero-based New
I ZERO_BASED: dm_pkg.sv:157 Declaration range '[28:24]' of 'abstractcs' is not zero-based New
I ZERO_BASED: dm_pkg.sv:157 Declaration range '[28:24]' of 'abstractcs_t' is not zero-based New
I ZERO_BASED: dm_pkg.sv:157 Declaration range '[28:24]' of 'progbufsize' is not zero-based New
I ZERO_BASED: dm_pkg.sv:158 Declaration range '[23:13]' of 'a_abstractcs' is not zero-based New
I ZERO_BASED: dm_pkg.sv:158 Declaration range '[23:13]' of 'abstractcs' is not zero-based New
I ZERO_BASED: dm_pkg.sv:158 Declaration range '[23:13]' of 'abstractcs_t' is not zero-based New
I ZERO_BASED: dm_pkg.sv:158 Declaration range '[23:13]' of 'zero2' is not zero-based New
I ZERO_BASED: dm_pkg.sv:162 Declaration range '[7:4]' of 'a_abstractcs' is not zero-based New
I ZERO_BASED: dm_pkg.sv:162 Declaration range '[7:4]' of 'abstractcs' is not zero-based New
I ZERO_BASED: dm_pkg.sv:162 Declaration range '[7:4]' of 'abstractcs_t' is not zero-based New
I ZERO_BASED: dm_pkg.sv:162 Declaration range '[7:4]' of 'zero0' is not zero-based New
I ZERO_BASED: dm_pkg.sv:178 Declaration range '[31:16]' of 'abstractauto_d' is not zero-based New
I ZERO_BASED: dm_pkg.sv:178 Declaration range '[31:16]' of 'abstractauto_t' is not zero-based New
I ZERO_BASED: dm_pkg.sv:178 Declaration range '[31:16]' of 'autoexecprogbuf' is not zero-based New
I ZERO_BASED: dm_pkg.sv:179 Declaration range '[15:12]' of 'abstractauto_d' is not zero-based New
I ZERO_BASED: dm_pkg.sv:179 Declaration range '[15:12]' of 'abstractauto_t' is not zero-based New
I ZERO_BASED: dm_pkg.sv:179 Declaration range '[15:12]' of 'zero0' is not zero-based New
I ZERO_BASED: dm_pkg.sv:185 Declaration range '[22:20]' of 'aarsize' is not zero-based New
I ZERO_BASED: dm_pkg.sv:185 Declaration range '[22:20]' of 'ac_ar' is not zero-based New
I ZERO_BASED: dm_pkg.sv:185 Declaration range '[22:20]' of 'ac_ar_cmd_t' is not zero-based New
I ZERO_BASED: dm_pkg.sv:207 Declaration range '[31:29]' of 'sbcs' is not zero-based New
I ZERO_BASED: dm_pkg.sv:207 Declaration range '[31:29]' of 'sbcs_d' is not zero-based New
I ZERO_BASED: dm_pkg.sv:207 Declaration range '[31:29]' of 'sbcs_t' is not zero-based New
I ZERO_BASED: dm_pkg.sv:207 Declaration range '[31:29]' of 'sbversion' is not zero-based New
I ZERO_BASED: dm_pkg.sv:208 Declaration range '[28:23]' of 'sbcs' is not zero-based New
I ZERO_BASED: dm_pkg.sv:208 Declaration range '[28:23]' of 'sbcs_d' is not zero-based New
I ZERO_BASED: dm_pkg.sv:208 Declaration range '[28:23]' of 'sbcs_t' is not zero-based New
I ZERO_BASED: dm_pkg.sv:208 Declaration range '[28:23]' of 'zero0' is not zero-based New
I ZERO_BASED: dm_pkg.sv:212 Declaration range '[19:17]' of 'sbaccess' is not zero-based New
I ZERO_BASED: dm_pkg.sv:212 Declaration range '[19:17]' of 'sbcs' is not zero-based New
I ZERO_BASED: dm_pkg.sv:212 Declaration range '[19:17]' of 'sbcs_d' is not zero-based New
I ZERO_BASED: dm_pkg.sv:212 Declaration range '[19:17]' of 'sbcs_t' is not zero-based New
I ZERO_BASED: dm_pkg.sv:215 Declaration range '[14:12]' of 'sbcs' is not zero-based New
I ZERO_BASED: dm_pkg.sv:215 Declaration range '[14:12]' of 'sbcs_d' is not zero-based New
I ZERO_BASED: dm_pkg.sv:215 Declaration range '[14:12]' of 'sbcs_t' is not zero-based New
I ZERO_BASED: dm_pkg.sv:215 Declaration range '[14:12]' of 'sberror' is not zero-based New
I ZERO_BASED: dm_pkg.sv:216 Declaration range '[11:5]' of 'sbasize' is not zero-based New
I ZERO_BASED: dm_pkg.sv:216 Declaration range '[11:5]' of 'sbcs' is not zero-based New
I ZERO_BASED: dm_pkg.sv:216 Declaration range '[11:5]' of 'sbcs_d' is not zero-based New
I ZERO_BASED: dm_pkg.sv:216 Declaration range '[11:5]' of 'sbcs_t' is not zero-based New
I ZERO_BASED: dm_pkg.sv:236 Declaration range '[31:18]' of 'dtmcs_d' is not zero-based New
I ZERO_BASED: dm_pkg.sv:236 Declaration range '[31:18]' of 'dtmcs_t' is not zero-based New
I ZERO_BASED: dm_pkg.sv:236 Declaration range '[31:18]' of 'zero1' is not zero-based New
I ZERO_BASED: dm_pkg.sv:240 Declaration range '[14:12]' of 'dtmcs_d' is not zero-based New
I ZERO_BASED: dm_pkg.sv:240 Declaration range '[14:12]' of 'dtmcs_t' is not zero-based New
I ZERO_BASED: dm_pkg.sv:240 Declaration range '[14:12]' of 'idle' is not zero-based New
I ZERO_BASED: dm_pkg.sv:241 Declaration range '[11:10]' of 'dmistat' is not zero-based New
I ZERO_BASED: dm_pkg.sv:241 Declaration range '[11:10]' of 'dtmcs_d' is not zero-based New
I ZERO_BASED: dm_pkg.sv:241 Declaration range '[11:10]' of 'dtmcs_t' is not zero-based New
I ZERO_BASED: dm_pkg.sv:242 Declaration range '[9:4]' of 'abits' is not zero-based New
I ZERO_BASED: dm_pkg.sv:242 Declaration range '[9:4]' of 'dtmcs_d' is not zero-based New
I ZERO_BASED: dm_pkg.sv:242 Declaration range '[9:4]' of 'dtmcs_t' is not zero-based New
I CONST_OUTPUT: prim_fifo_sync.sv:98 Output 'err_o' is driven by constant zero by port 'gen_normal_fifo.u_fifo_cnt.err_o' in module 'prim_fifo_sync' (Width=32'h22,Pass=1'h0,Depth=2) New
I CONST_OUTPUT: prim_fifo_sync_cnt.sv:136 Output 'err_o' is driven by constant zero in module 'prim_fifo_sync_cnt' (Depth=32'h2) New
I CONST_OUTPUT: tlul_adapter_reg.sv:91 Output 'addr_o[1:0]' is driven by constant zeros in module 'tlul_adapter_reg' (RegAw=4) New
I CONST_OUTPUT: tlul_adapter_reg.sv:195 Output 'intg_error_o' is driven by constant zero in module 'tlul_adapter_reg' (RegAw=4) New
Past Results