RV_TIMER Simulation Results

Monday May 15 2023 07:07:46 UTC

GitHub Revision: `3d5660d90`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 705130430

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	56.743m	654.769ms	190	200	95.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.610s	210.942us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.610s	27.662us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.590s	1.558ms	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.790s	132.360us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.380s	102.553us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.610s	27.662us	20	20	100.00
		rv_timer_csr_aliasing	0.790s	132.360us	5	5	100.00
V1		TOTAL			245	255	96.08
V2	random_reset	rv_timer_random_reset	24.390m	42.335ms	50	50	100.00
V2	disabled	rv_timer_disabled	6.864m	914.922ms	45	50	90.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	21.176m	4.434s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	21.176m	4.434s	50	50	100.00
V2	stress	rv_timer_stress_all	1.236h	707.928ms	49	50	98.00
V2	intr_test	rv_timer_intr_test	0.580s	18.247us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.790s	215.554us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.790s	215.554us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.610s	210.942us	5	5	100.00
		rv_timer_csr_rw	0.610s	27.662us	20	20	100.00
		rv_timer_csr_aliasing	0.790s	132.360us	5	5	100.00
		rv_timer_same_csr_outstanding	0.860s	137.404us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.610s	210.942us	5	5	100.00
		rv_timer_csr_rw	0.610s	27.662us	20	20	100.00
		rv_timer_csr_aliasing	0.790s	132.360us	5	5	100.00
		rv_timer_same_csr_outstanding	0.860s	137.404us	20	20	100.00
V2		TOTAL			284	290	97.93
V2S	tl_intg_err	rv_timer_sec_cm	0.900s	182.572us	5	5	100.00
		rv_timer_tl_intg_err	2.050s	710.631us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.050s	710.631us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	25.776m	722.195ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			604	620	97.42

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	7	7	5	71.43
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.61	99.38	98.73	100.00	--	100.00	100.00	99.55

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 16 failures:

Test rv_timer_disabled has 5 failures.

23.rv_timer_disabled.859022193
Line 219, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/23.rv_timer_disabled/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

36.rv_timer_disabled.906537293
Line 218, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/36.rv_timer_disabled/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test rv_timer_random has 10 failures.

40.rv_timer_random.395680986
Line 220, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/40.rv_timer_random/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

46.rv_timer_random.4045544809
Line 220, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/46.rv_timer_random/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test rv_timer_stress_all has 1 failures.

43.rv_timer_stress_all.850604587
Line 240, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/43.rv_timer_stress_all/latest/run.log

  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---