b938dde05c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 48.362m | 787.603ms | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.630s | 17.108us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.610s | 195.374us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.280s | 1.929ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.790s | 64.776us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.620s | 39.520us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.610s | 195.374us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.790s | 64.776us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 32.783m | 179.308ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 5.374m | 215.229ms | 48 | 50 | 96.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 39.458m | 10.000s | 49 | 50 | 98.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 39.458m | 10.000s | 49 | 50 | 98.00 |
| V2 | stress | rv_timer_stress_all | 1.079h | 1.925s | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.650s | 24.788us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 3.320s | 752.049us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 3.320s | 752.049us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.630s | 17.108us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.610s | 195.374us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.790s | 64.776us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.840s | 357.246us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.630s | 17.108us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.610s | 195.374us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.790s | 64.776us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.840s | 357.246us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 287 | 290 | 98.97 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.920s | 83.085us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.440s | 486.041us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.440s | 486.041us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 27.734m | 94.828ms | 13 | 50 | 26.00 |
| V3 | TOTAL | 13 | 50 | 26.00 | |||
| TOTAL | 580 | 620 | 93.55 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 5 | 71.43 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.66 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.89 |
UVM_ERROR (cip_base_vseq.sv:829) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 37 failures:
0.rv_timer_stress_all_with_rand_reset.15431313925930917175542342090228168631411265284528344412017499578020747530171
Line 1156, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 158944489144 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 158944489144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rv_timer_stress_all_with_rand_reset.4001228243985400946662278562934813446105808541112301665460365276115897011533
Line 931, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 64744225094 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10011 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 64744225094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 35 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
Test rv_timer_cfg_update_on_fly has 1 failures.
3.rv_timer_cfg_update_on_fly.23467994820417836089145111835659443961726487520660252055119754919427890470316
Line 279, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/3.rv_timer_cfg_update_on_fly/latest/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_timer_disabled has 2 failures.
6.rv_timer_disabled.43309548827179749573144901813366469843567657660115912442551927001782468786032
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/6.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
46.rv_timer_disabled.24349957399300860887243158599546688910018578593610438626285357000545446888970
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/46.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---