RV_TIMER Simulation Results

Monday May 29 2023 07:02:33 UTC

GitHub Revision: `877a77116`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88555427

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	44.120m	74.029ms	190	200	95.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.620s	37.564us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.690s	14.788us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.650s	1.139ms	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.820s	136.638us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.090s	26.280us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.690s	14.788us	20	20	100.00
		rv_timer_csr_aliasing	0.820s	136.638us	5	5	100.00
V1		TOTAL			245	255	96.08
V2	random_reset	rv_timer_random_reset	28.406m	45.479ms	50	50	100.00
V2	disabled	rv_timer_disabled	4.453m	1.000s	47	50	94.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	24.676m	2.827s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	24.676m	2.827s	50	50	100.00
V2	stress	rv_timer_stress_all	1.326h	349.599ms	49	50	98.00
V2	intr_test	rv_timer_intr_test	0.600s	30.055us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.150s	166.583us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.150s	166.583us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.620s	37.564us	5	5	100.00
		rv_timer_csr_rw	0.690s	14.788us	20	20	100.00
		rv_timer_csr_aliasing	0.820s	136.638us	5	5	100.00
		rv_timer_same_csr_outstanding	0.840s	36.012us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.620s	37.564us	5	5	100.00
		rv_timer_csr_rw	0.690s	14.788us	20	20	100.00
		rv_timer_csr_aliasing	0.820s	136.638us	5	5	100.00
		rv_timer_same_csr_outstanding	0.840s	36.012us	20	20	100.00
V2		TOTAL			286	290	98.62
V2S	tl_intg_err	rv_timer_sec_cm	0.920s	106.461us	5	5	100.00
		rv_timer_tl_intg_err	1.430s	211.192us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.430s	211.192us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	28.901m	157.549ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			606	620	97.74

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	7	7	5	71.43
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.65	99.38	98.73	100.00	--	100.00	100.00	99.77

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 14 failures:

Test rv_timer_disabled has 3 failures.

0.rv_timer_disabled.2575962188
Line 221, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_disabled/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

37.rv_timer_disabled.3686139454
Line 217, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/37.rv_timer_disabled/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test rv_timer_random has 10 failures.

17.rv_timer_random.1033696408
Line 218, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/17.rv_timer_random/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

72.rv_timer_random.2636602597
Line 220, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/72.rv_timer_random/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test rv_timer_stress_all has 1 failures.

37.rv_timer_stress_all.1547800271
Line 237, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/37.rv_timer_stress_all/latest/run.log

  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---