RV_TIMER Simulation Results

Monday October 14 2024 17:26:15 UTC

GitHub Revision: `12e3b8572e`

Branch: os_regression_2024_10_14

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85025606402499621082521464627961092918263397067038954055071960501195381950243

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	53.915m	131.904ms	199	200	99.50
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.880s	15.345us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.900s	41.070us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	5.620s	1.659ms	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.230s	72.890us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	2.010s	27.854us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.900s	41.070us	20	20	100.00
		rv_timer_csr_aliasing	1.230s	72.890us	5	5	100.00
V1		TOTAL			254	255	99.61
V2	random_reset	rv_timer_random_reset	7.888m	86.360ms	50	50	100.00
V2	disabled	rv_timer_disabled	8.524m	141.975ms	48	50	96.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	24.590m	2.704s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	24.590m	2.704s	50	50	100.00
V2	stress	rv_timer_stress_all	1.087h	2.089s	49	50	98.00
V2	intr_test	rv_timer_intr_test	0.890s	18.007us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	4.310s	151.938us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	4.310s	151.938us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.880s	15.345us	5	5	100.00
		rv_timer_csr_rw	0.900s	41.070us	20	20	100.00
		rv_timer_csr_aliasing	1.230s	72.890us	5	5	100.00
		rv_timer_same_csr_outstanding	1.230s	136.854us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.880s	15.345us	5	5	100.00
		rv_timer_csr_rw	0.900s	41.070us	20	20	100.00
		rv_timer_csr_aliasing	1.230s	72.890us	5	5	100.00
		rv_timer_same_csr_outstanding	1.230s	136.854us	20	20	100.00
V2		TOTAL			287	290	98.97
V2S	tl_intg_err	rv_timer_sec_cm	1.450s	250.123us	5	5	100.00
		rv_timer_tl_intg_err	2.060s	606.397us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.060s	606.397us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	1.110m	3.383ms	13	50	26.00
V3		TOTAL			13	50	26.00
		TOTAL			579	620	93.39

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	7	7	5	71.43
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.65	99.33	99.04	100.00	--	100.00	100.00	99.55

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 37 failures:
- Test rv_timer_stress_all_with_rand_reset has 37 failures.
  - 1.rv_timer_stress_all_with_rand_reset.70445978660810647831094821179233017918700558448580904807762878289072357463292
    Line 99, in log /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4387099708 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10027 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4387099708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.rv_timer_stress_all_with_rand_reset.53506637783878015974976020044629797128905782894461698639771941733700412660244
    Line 68, in log /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/2.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1690382757 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10026 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1690382757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 35 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test rv_timer_stress_all has 1 failures.
  - 16.rv_timer_stress_all.61248007917877749786375864403217840983850891532692211842599045278382972416001
    Line 91, in log /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/16.rv_timer_stress_all/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_timer_disabled has 2 failures.
  - 25.rv_timer_disabled.6784110281153886224343351774551998768715573565474328263738337611163883380474
    Line 66, in log /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/25.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 42.rv_timer_disabled.22789134151805821202053530035713225891013783952329038709424173023570429933380
    Line 64, in log /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/42.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test rv_timer_random has 1 failures.
  - 79.rv_timer_random.92617873173009468375266851290520870372436026908694839709155545964884022591197
    Log /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/79.rv_timer_random/latest/run.log
```
  Job timed out after 60 minutes
```

RV_TIMER Simulation Results

Monday October 14 2024 17:26:15 UTC

GitHub Revision: 12e3b8572e

Branch: os_regression_2024_10_14

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85025606402499621082521464627961092918263397067038954055071960501195381950243

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `12e3b8572e`