a47820eb4c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 54.930m | 721.029ms | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.580s | 54.281us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.630s | 21.002us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.680s | 414.316us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.800s | 122.527us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.300s | 109.784us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.630s | 21.002us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.800s | 122.527us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 43.324m | 291.654ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 5.481m | 1.000s | 46 | 50 | 92.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 25.175m | 4.370s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 25.175m | 4.370s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 53.289m | 1.408s | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.610s | 17.241us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 2.700s | 130.109us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 2.700s | 130.109us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.580s | 54.281us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.630s | 21.002us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.800s | 122.527us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.830s | 37.660us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.580s | 54.281us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.630s | 21.002us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.800s | 122.527us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.830s | 37.660us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 286 | 290 | 98.62 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.900s | 166.153us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.420s | 115.974us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.420s | 115.974us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 13.011m | 315.803ms | 11 | 50 | 22.00 |
| V3 | TOTAL | 11 | 50 | 22.00 | |||
| TOTAL | 577 | 620 | 93.06 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.61 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.55 |
UVM_ERROR (cip_base_vseq.sv:839) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 39 failures:
0.rv_timer_stress_all_with_rand_reset.92438257362843686615685860977295079576265464994971879390258653412287499235611
Line 1100, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 315802710354 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 315802710354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rv_timer_stress_all_with_rand_reset.82166223665309491342318306569505382602688963801902038049463331384217343277231
Line 385, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 30306316135 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 30306316135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 37 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
11.rv_timer_disabled.77711868296504613920451581863430394509814012711753579694911363895046654824523
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/11.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.rv_timer_disabled.39739919807889045041541561973453484348827150377196727569317297803774681648622
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/43.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.