9f20940d49| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 45.362m | 633.625ms | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.890s | 17.016us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.860s | 12.545us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 4.920s | 284.811us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 1.220s | 240.759us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 2.290s | 289.114us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.860s | 12.545us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 1.220s | 240.759us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 11.532m | 263.651ms | 49 | 50 | 98.00 |
| V2 | disabled | rv_timer_disabled | 7.101m | 150.238ms | 49 | 50 | 98.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 22.309m | 1.544s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 22.309m | 1.544s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.148h | 997.065ms | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.860s | 14.429us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 3.700s | 280.440us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 3.700s | 280.440us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.890s | 17.016us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.860s | 12.545us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 1.220s | 240.759us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 1.230s | 38.884us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.890s | 17.016us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.860s | 12.545us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 1.220s | 240.759us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 1.230s | 38.884us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 288 | 290 | 99.31 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 1.340s | 93.054us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 2.150s | 131.721us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 2.150s | 131.721us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 32.681m | 478.213ms | 10 | 50 | 20.00 |
| V3 | TOTAL | 10 | 50 | 20.00 | |||
| TOTAL | 578 | 620 | 93.23 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 5 | 71.43 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.61 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.55 |
UVM_ERROR (cip_base_vseq.sv:836) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 40 failures:
0.rv_timer_stress_all_with_rand_reset.89892612705353631574215210759795737435648808315387373193361951630271647563299
Line 65, in log /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 265186729 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10027 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 265186729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_stress_all_with_rand_reset.45826775431193223218694332696874831919294859237178464808199382185530570631879
Line 255, in log /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 46918459762 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 46918459762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 38 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
Test rv_timer_disabled has 1 failures.
18.rv_timer_disabled.112302963275326122112157898127872845346347845669389768901740878126493056198919
Line 63, in log /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/18.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_timer_random_reset has 1 failures.
41.rv_timer_random_reset.85175043119573539971755103524942531939988152916028897177056714886094489776960
Line 65, in log /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/41.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---