Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35545110	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	43811800	1		T1	956		T2	5373		T3	5373

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	72305260	1		T1	1930		T2	10672		T3	10672
values[0x0]	3350340	1		T1	2		T2	4		T3	4
values[0x1]	3701310	1		T1	4		T2	5		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28192320	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	51164590	1		T1	1149		T2	6488		T3	6488

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	321050	1		T1	1		T2	21		T3	21
valid_sources[0x01]	294580	1		T1	13		T2	49		T3	49
valid_sources[0x02]	316535	1		T1	14		T2	42		T3	42
valid_sources[0x03]	289965	1		T1	4		T2	37		T3	37
valid_sources[0x04]	310080	1		T1	9		T2	31		T3	31
valid_sources[0x05]	312690	1		T1	11		T2	49		T3	49
valid_sources[0x06]	288205	1		T1	4		T2	34		T3	34
valid_sources[0x07]	308330	1		T1	1		T2	55		T3	55
valid_sources[0x08]	295895	1		T1	4		T2	32		T3	32
valid_sources[0x09]	325095	1		T1	1		T2	46		T3	46
valid_sources[0x0a]	312115	1		T1	39		T2	44		T3	44
valid_sources[0x0b]	305000	1		T1	7		T2	35		T3	35
valid_sources[0x0c]	322905	1		T1	5		T2	47		T3	47
valid_sources[0x0d]	314640	1		T1	1		T2	48		T3	48
valid_sources[0x0e]	343785	1		T1	16		T2	38		T3	38
valid_sources[0x0f]	306550	1		T1	12		T2	39		T3	39
valid_sources[0x10]	325340	1		T1	1		T2	41		T3	41
valid_sources[0x11]	312770	1		T1	16		T2	31		T3	31
valid_sources[0x12]	298200	1		T1	1		T2	52		T3	52
valid_sources[0x13]	313345	1		T1	7		T2	37		T3	37
valid_sources[0x14]	310150	1		T1	4		T2	46		T3	46
valid_sources[0x15]	302215	1		T2	16		T3	16		T4	1115
valid_sources[0x16]	302290	1		T1	18		T2	58		T3	58
valid_sources[0x17]	313125	1		T1	4		T2	39		T3	39
valid_sources[0x18]	322235	1		T1	1		T2	34		T3	34
valid_sources[0x19]	309410	1		T2	13		T3	13		T4	1168
valid_sources[0x1a]	308265	1		T1	2		T2	39		T3	39
valid_sources[0x1b]	309190	1		T1	11		T2	27		T3	27
valid_sources[0x1c]	318430	1		T2	44		T3	44		T4	1179
valid_sources[0x1d]	296215	1		T1	10		T2	64		T3	64
valid_sources[0x1e]	320480	1		T1	3		T2	35		T3	35
valid_sources[0x1f]	315210	1		T1	3		T2	54		T3	54
valid_sources[0x20]	311580	1		T1	13		T2	51		T3	51
valid_sources[0x21]	295815	1		T2	32		T3	32		T4	1069
valid_sources[0x22]	309395	1		T1	15		T2	42		T3	42
valid_sources[0x23]	306435	1		T1	14		T2	13		T3	13
valid_sources[0x24]	301435	1		T1	7		T2	29		T3	29
valid_sources[0x25]	302825	1		T2	36		T3	36		T4	964
valid_sources[0x26]	320460	1		T1	9		T2	34		T3	34
valid_sources[0x27]	305845	1		T1	17		T2	49		T3	49
valid_sources[0x28]	304185	1		T1	6		T2	27		T3	27
valid_sources[0x29]	304305	1		T1	6		T2	41		T3	41
valid_sources[0x2a]	302925	1		T1	39		T2	23		T3	23
valid_sources[0x2b]	285120	1		T1	9		T2	25		T3	25
valid_sources[0x2c]	307640	1		T1	4		T2	23		T3	23
valid_sources[0x2d]	308095	1		T1	22		T2	74		T3	74
valid_sources[0x2e]	294545	1		T1	4		T2	26		T3	26
valid_sources[0x2f]	302395	1		T2	31		T3	31		T4	1039
valid_sources[0x30]	310970	1		T1	8		T2	41		T3	41
valid_sources[0x31]	321645	1		T1	19		T2	59		T3	59
valid_sources[0x32]	296665	1		T1	14		T2	37		T3	37
valid_sources[0x33]	295615	1		T1	12		T2	53		T3	53
valid_sources[0x34]	324260	1		T1	5		T2	52		T3	52
valid_sources[0x35]	307550	1		T1	1		T2	42		T3	42
valid_sources[0x36]	302105	1		T1	5		T2	45		T3	45
valid_sources[0x37]	303000	1		T1	4		T2	24		T3	24
valid_sources[0x38]	321320	1		T1	14		T2	70		T3	70
valid_sources[0x39]	298110	1		T1	16		T2	61		T3	61
valid_sources[0x3a]	313720	1		T1	5		T2	46		T3	46
valid_sources[0x3b]	298060	1		T1	12		T2	49		T3	49
valid_sources[0x3c]	301460	1		T1	3		T2	53		T3	53
valid_sources[0x3d]	316750	1		T1	2		T2	47		T3	47
valid_sources[0x3e]	287845	1		T1	10		T2	48		T3	48
valid_sources[0x3f]	310770	1		T1	6		T2	16		T3	16
valid_sources[0x40]	337010	1		T1	6		T2	111		T3	111
valid_sources[0x41]	328075	1		T1	10		T2	56		T3	56
valid_sources[0x42]	296135	1		T1	7		T2	40		T3	40
valid_sources[0x43]	307895	1		T2	38		T3	38		T4	1162
valid_sources[0x44]	321685	1		T1	8		T2	85		T3	85
valid_sources[0x45]	302235	1		T2	43		T3	43		T4	1005
valid_sources[0x46]	336955	1		T1	1		T2	64		T3	64
valid_sources[0x47]	309385	1		T2	62		T3	62		T4	1087
valid_sources[0x48]	315225	1		T1	8		T2	80		T3	80
valid_sources[0x49]	320595	1		T1	4		T2	59		T3	59
valid_sources[0x4a]	300190	1		T1	12		T2	31		T3	31
valid_sources[0x4b]	304035	1		T1	8		T2	10		T3	10
valid_sources[0x4c]	306270	1		T1	6		T2	18		T3	18
valid_sources[0x4d]	304500	1		T1	15		T2	39		T3	39
valid_sources[0x4e]	318615	1		T1	2		T2	89		T3	89
valid_sources[0x4f]	310070	1		T1	1		T2	99		T3	99
valid_sources[0x50]	320345	1		T1	3		T2	93		T3	93
valid_sources[0x51]	311040	1		T1	9		T2	42		T3	42
valid_sources[0x52]	304630	1		T1	8		T2	24		T3	24
valid_sources[0x53]	317875	1		T1	1		T2	22		T3	22
valid_sources[0x54]	311730	1		T1	1		T2	33		T3	33
valid_sources[0x55]	321540	1		T1	3		T2	38		T3	38
valid_sources[0x56]	318195	1		T1	18		T2	21		T3	21
valid_sources[0x57]	297970	1		T1	8		T2	24		T3	24
valid_sources[0x58]	315220	1		T1	7		T2	22		T3	22
valid_sources[0x59]	317075	1		T2	73		T3	73		T4	1133
valid_sources[0x5a]	309040	1		T1	4		T2	54		T3	54
valid_sources[0x5b]	319665	1		T1	19		T2	54		T3	54
valid_sources[0x5c]	301685	1		T1	4		T2	29		T3	29
valid_sources[0x5d]	310445	1		T1	12		T2	39		T3	39
valid_sources[0x5e]	306270	1		T1	2		T2	18		T3	18
valid_sources[0x5f]	313740	1		T1	8		T2	45		T3	45
valid_sources[0x60]	306495	1		T2	38		T3	38		T4	1002
valid_sources[0x61]	317235	1		T1	2		T2	38		T3	38
valid_sources[0x62]	304410	1		T1	10		T2	51		T3	51
valid_sources[0x63]	308115	1		T1	2		T2	40		T3	40
valid_sources[0x64]	322210	1		T1	3		T2	63		T3	63
valid_sources[0x65]	309060	1		T1	16		T2	21		T3	21
valid_sources[0x66]	303475	1		T1	4		T2	47		T3	47
valid_sources[0x67]	322600	1		T2	34		T3	34		T4	1130
valid_sources[0x68]	309810	1		T1	6		T2	48		T3	48
valid_sources[0x69]	321275	1		T1	14		T2	59		T3	59
valid_sources[0x6a]	308245	1		T1	10		T2	27		T3	27
valid_sources[0x6b]	300045	1		T1	8		T2	23		T3	23
valid_sources[0x6c]	315690	1		T1	4		T2	23		T3	23
valid_sources[0x6d]	303540	1		T1	13		T2	37		T3	37
valid_sources[0x6e]	310940	1		T1	6		T2	39		T3	39
valid_sources[0x6f]	311810	1		T2	25		T3	25		T4	1114
valid_sources[0x70]	300190	1		T1	1		T2	41		T3	41
valid_sources[0x71]	306135	1		T1	5		T2	48		T3	48
valid_sources[0x72]	321045	1		T1	2		T2	68		T3	68
valid_sources[0x73]	315710	1		T1	5		T2	46		T3	46
valid_sources[0x74]	315535	1		T1	9		T2	30		T3	30
valid_sources[0x75]	297915	1		T1	12		T2	36		T3	36
valid_sources[0x76]	305865	1		T1	7		T2	32		T3	32
valid_sources[0x77]	288365	1		T1	10		T2	20		T3	20
valid_sources[0x78]	305250	1		T1	30		T2	43		T3	43
valid_sources[0x79]	294870	1		T2	26		T3	26		T4	991
valid_sources[0x7a]	279965	1		T1	6		T2	20		T3	20
valid_sources[0x7b]	294245	1		T2	14		T3	14		T4	1140
valid_sources[0x7c]	317655	1		T1	7		T2	27		T3	27
valid_sources[0x7d]	307740	1		T1	10		T2	75		T3	75
valid_sources[0x7e]	304430	1		T2	57		T3	57		T4	1099
valid_sources[0x7f]	300850	1		T1	1		T2	22		T3	22
valid_sources[0x80]	318700	1		T1	10		T2	52		T3	52

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

37212885

1

T1

952

T2

5369

T3

5369

values[0x0]

all_enables

biggest_size

3301400

1

T1

1

T2

1

T3

1

values[0x1]

all_enables

biggest_size

3297515

1

T1

3

T2

3

T3

3