Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	11738200	0	0
cfg0_rd_A	2147483647	66185	0	0
compare_lower0_0_rd_A	2147483647	76110	0	0
compare_upper0_0_rd_A	2147483647	62165	0	0
ctrl_rd_A	2147483647	67425	0	0
intr_enable0_rd_A	2147483647	89060	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	11738200	0	0
T4	116213	234430	0	0
T5	397140	0	0	0
T6	397140	0	0	0
T7	587127	0	0	0
T8	339944	0	0	0
T9	397140	0	0	0
T10	116213	234430	0	0
T11	0	234430	0	0
T13	0	49	0	0
T29	0	234430	0	0
T30	0	234430	0	0
T31	0	234430	0	0
T32	0	772	0	0
T33	0	14	0	0
T34	0	14	0	0
T36	397140	0	0	0
T37	339944	0	0	0
T38	179769	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	66185	0	0
T4	116213	1227	0	0
T5	397140	0	0	0
T6	397140	0	0	0
T7	587127	0	0	0
T8	339944	0	0	0
T9	397140	0	0	0
T10	116213	1227	0	0
T11	0	1227	0	0
T12	0	416	0	0
T13	0	24	0	0
T14	0	38	0	0
T29	0	1227	0	0
T30	0	1227	0	0
T31	0	1227	0	0
T36	397140	0	0	0
T37	339944	0	0	0
T38	179769	0	0	0
T39	0	55	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	76110	0	0
T4	116213	1428	0	0
T5	397140	0	0	0
T6	397140	0	0	0
T7	587127	0	0	0
T8	339944	0	0	0
T9	397140	0	0	0
T10	116213	1428	0	0
T11	0	1428	0	0
T12	0	393	0	0
T13	0	8	0	0
T29	0	1428	0	0
T30	0	1428	0	0
T31	0	1428	0	0
T32	0	9	0	0
T36	397140	0	0	0
T37	339944	0	0	0
T38	179769	0	0	0
T39	0	64	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	62165	0	0
T4	116213	1165	0	0
T5	397140	0	0	0
T6	397140	0	0	0
T7	587127	0	0	0
T8	339944	0	0	0
T9	397140	0	0	0
T10	116213	1165	0	0
T11	0	1165	0	0
T12	0	359	0	0
T13	0	16	0	0
T14	0	19	0	0
T29	0	1165	0	0
T30	0	1165	0	0
T31	0	1165	0	0
T36	397140	0	0	0
T37	339944	0	0	0
T38	179769	0	0	0
T39	0	49	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	67425	0	0
T4	116213	1282	0	0
T5	397140	0	0	0
T6	397140	0	0	0
T7	587127	0	0	0
T8	339944	0	0	0
T9	397140	0	0	0
T10	116213	1282	0	0
T11	0	1282	0	0
T12	0	361	0	0
T13	0	3	0	0
T14	0	15	0	0
T29	0	1282	0	0
T30	0	1282	0	0
T31	0	1282	0	0
T36	397140	0	0	0
T37	339944	0	0	0
T38	179769	0	0	0
T39	0	71	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	89060	0	0
T4	116213	1631	0	0
T5	397140	0	0	0
T6	397140	0	0	0
T7	587127	40	0	0
T8	339944	0	0	0
T9	397140	0	0	0
T10	116213	1631	0	0
T11	0	1631	0	0
T29	0	1631	0	0
T30	0	1631	0	0
T36	397140	0	0	0
T37	339944	0	0	0
T38	179769	0	0	0
T59	0	40	0	0
T60	0	40	0	0
T61	0	40	0	0
T62	0	40	0	0