RV_TIMER Simulation Results

Wednesday November 22 2023 20:02:38 UTC

GitHub Revision: 4002b28ec4

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56541452733628775295814943325285397402671097056517970046183331126493552547969

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 random rv_timer_random 1.262m 70.917ms 200 200 100.00
V1 csr_hw_reset rv_timer_csr_hw_reset 0.610s 29.619us 5 5 100.00
V1 csr_rw rv_timer_csr_rw 0.610s 24.154us 20 20 100.00
V1 csr_bit_bash rv_timer_csr_bit_bash 3.900s 639.239us 5 5 100.00
V1 csr_aliasing rv_timer_csr_aliasing 0.860s 61.136us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_timer_csr_mem_rw_with_rand_reset 0.930s 50.083us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_timer_csr_rw 0.610s 24.154us 20 20 100.00
rv_timer_csr_aliasing 0.860s 61.136us 5 5 100.00
V1 TOTAL 255 255 100.00
V2 random_reset rv_timer_random_reset 5.138m 60.704ms 50 50 100.00
V2 disabled rv_timer_disabled 30.960s 32.101ms 50 50 100.00
V2 cfg_update_on_fly rv_timer_cfg_update_on_fly 10.406m 544.576ms 50 50 100.00
V2 no_interrupt_test rv_timer_cfg_update_on_fly 10.406m 544.576ms 50 50 100.00
V2 stress rv_timer_stress_all 27.283m 1.048s 50 50 100.00
V2 intr_test rv_timer_intr_test 0.670s 27.797us 50 50 100.00
V2 tl_d_oob_addr_access rv_timer_tl_errors 2.770s 261.313us 20 20 100.00
V2 tl_d_illegal_access rv_timer_tl_errors 2.770s 261.313us 20 20 100.00
V2 tl_d_outstanding_access rv_timer_csr_hw_reset 0.610s 29.619us 5 5 100.00
rv_timer_csr_rw 0.610s 24.154us 20 20 100.00
rv_timer_csr_aliasing 0.860s 61.136us 5 5 100.00
rv_timer_same_csr_outstanding 0.850s 63.083us 20 20 100.00
V2 tl_d_partial_access rv_timer_csr_hw_reset 0.610s 29.619us 5 5 100.00
rv_timer_csr_rw 0.610s 24.154us 20 20 100.00
rv_timer_csr_aliasing 0.860s 61.136us 5 5 100.00
rv_timer_same_csr_outstanding 0.850s 63.083us 20 20 100.00
V2 TOTAL 290 290 100.00
V2S tl_intg_err rv_timer_sec_cm 0.960s 135.136us 5 5 100.00
rv_timer_tl_intg_err 1.390s 191.367us 20 20 100.00
V2S sec_cm_bus_integrity rv_timer_tl_intg_err 1.390s 191.367us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset rv_timer_stress_all_with_rand_reset 14.114m 207.523ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 620 620 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 7 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
89.65 99.36 98.73 100.00 -- 100.00 99.35 40.43

Past Results