Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	64637346	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	71040526	1		T1	105285		T2	57012		T3	1947

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	130203111	1		T1	54391		T2	113545		T3	3868
values[0x0]	2600353	1		T1	34297		T2	36		T3	8
values[0x1]	2874408	1		T1	38040		T2	42		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	51495819	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	84182053	1		T1	111742		T2	68423		T3	2312

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	388706	1		T1	554		T2	464		T3	19
valid_sources[0x01]	386221	1		T1	460		T2	463		T3	16
valid_sources[0x02]	383078	1		T1	522		T2	498		T3	7
valid_sources[0x03]	383379	1		T1	441		T2	421		T3	9
valid_sources[0x04]	390849	1		T1	492		T2	421		T3	19
valid_sources[0x05]	389705	1		T1	511		T2	454		T3	25
valid_sources[0x06]	391657	1		T1	503		T2	456		T3	29
valid_sources[0x07]	393134	1		T1	507		T2	505		T3	10
valid_sources[0x08]	387201	1		T1	512		T2	442		T3	16
valid_sources[0x09]	517667	1		T1	504		T2	435		T3	10
valid_sources[0x0a]	387396	1		T1	514		T2	439		T3	27
valid_sources[0x0b]	394418	1		T1	537		T2	418		T3	14
valid_sources[0x0c]	389569	1		T1	508		T2	402		T3	1
valid_sources[0x0d]	387667	1		T1	477		T2	438		T3	18
valid_sources[0x0e]	450691	1		T1	524		T2	422		T3	17
valid_sources[0x0f]	389081	1		T1	500		T2	469		T3	22
valid_sources[0x10]	396620	1		T1	526		T2	474		T3	11
valid_sources[0x11]	382389	1		T1	527		T2	459		T3	15
valid_sources[0x12]	389253	1		T1	471		T2	433		T3	15
valid_sources[0x13]	395410	1		T1	550		T2	436		T3	18
valid_sources[0x14]	388894	1		T1	457		T2	441		T3	7
valid_sources[0x15]	387245	1		T1	452		T2	435		T3	28
valid_sources[0x16]	379124	1		T1	530		T2	492		T3	27
valid_sources[0x17]	391422	1		T1	458		T2	480		T3	3
valid_sources[0x18]	392519	1		T1	486		T2	462		T3	24
valid_sources[0x19]	388962	1		T1	561		T2	505		T3	5
valid_sources[0x1a]	388415	1		T1	528		T2	454		T3	14
valid_sources[0x1b]	408170	1		T1	444		T2	407		T3	5
valid_sources[0x1c]	385336	1		T1	497		T2	437		T3	9
valid_sources[0x1d]	2057009	1		T1	512		T2	436		T3	19
valid_sources[0x1e]	387964	1		T1	478		T2	495		T5	682
valid_sources[0x1f]	390047	1		T1	563		T2	440		T3	17
valid_sources[0x20]	389249	1		T1	504		T2	417		T3	10
valid_sources[0x21]	391004	1		T1	544		T2	431		T3	23
valid_sources[0x22]	391019	1		T1	507		T2	451		T3	7
valid_sources[0x23]	605423	1		T1	568		T2	462		T3	15
valid_sources[0x24]	406199	1		T1	577		T2	437		T3	2
valid_sources[0x25]	444578	1		T1	489		T2	451		T3	10
valid_sources[0x26]	388543	1		T1	525		T2	447		T3	12
valid_sources[0x27]	386411	1		T1	449		T2	402		T3	16
valid_sources[0x28]	393505	1		T1	503		T2	423		T3	10
valid_sources[0x29]	391964	1		T1	495		T2	453		T3	11
valid_sources[0x2a]	383149	1		T1	508		T2	445		T3	18
valid_sources[0x2b]	768359	1		T1	467		T2	441		T3	10
valid_sources[0x2c]	390327	1		T1	453		T2	439		T3	11
valid_sources[0x2d]	389773	1		T1	441		T2	406		T3	30
valid_sources[0x2e]	382644	1		T1	471		T2	414		T3	11
valid_sources[0x2f]	508270	1		T1	460		T2	462		T3	19
valid_sources[0x30]	393249	1		T1	543		T2	426		T3	3
valid_sources[0x31]	394727	1		T1	539		T2	431		T3	22
valid_sources[0x32]	391671	1		T1	505		T2	452		T3	20
valid_sources[0x33]	392003	1		T1	505		T2	469		T3	4
valid_sources[0x34]	387990	1		T1	499		T2	450		T3	31
valid_sources[0x35]	716477	1		T1	488		T2	473		T3	11
valid_sources[0x36]	1353180	1		T1	525		T2	429		T3	20
valid_sources[0x37]	386405	1		T1	483		T2	468		T3	23
valid_sources[0x38]	387702	1		T1	477		T2	435		T3	27
valid_sources[0x39]	409157	1		T1	542		T2	457		T3	7
valid_sources[0x3a]	379700	1		T1	450		T2	447		T3	20
valid_sources[0x3b]	384652	1		T1	521		T2	452		T3	36
valid_sources[0x3c]	394132	1		T1	426		T2	461		T3	32
valid_sources[0x3d]	384348	1		T1	512		T2	429		T3	3
valid_sources[0x3e]	2731994	1		T1	540		T2	383		T3	19
valid_sources[0x3f]	384178	1		T1	462		T2	436		T3	22
valid_sources[0x40]	393282	1		T1	533		T2	488		T3	1
valid_sources[0x41]	453143	1		T1	496		T2	465		T3	37
valid_sources[0x42]	1145135	1		T1	522		T2	424		T3	34
valid_sources[0x43]	392517	1		T1	462		T2	446		T3	13
valid_sources[0x44]	384116	1		T1	457		T2	479		T3	31
valid_sources[0x45]	385130	1		T1	463		T2	430		T3	20
valid_sources[0x46]	521717	1		T1	494		T2	432		T3	10
valid_sources[0x47]	389997	1		T1	441		T2	490		T3	25
valid_sources[0x48]	425018	1		T1	458		T2	451		T3	17
valid_sources[0x49]	384892	1		T1	515		T2	419		T3	10
valid_sources[0x4a]	397651	1		T1	456		T2	462		T3	11
valid_sources[0x4b]	399945	1		T1	474		T2	416		T3	19
valid_sources[0x4c]	1204424	1		T1	525		T2	414		T3	6
valid_sources[0x4d]	431477	1		T1	519		T2	387		T3	21
valid_sources[0x4e]	700667	1		T1	497		T2	433		T3	11
valid_sources[0x4f]	3580342	1		T1	479		T2	410		T3	27
valid_sources[0x50]	389750	1		T1	468		T2	431		T3	18
valid_sources[0x51]	2331673	1		T1	432		T2	465		T3	4
valid_sources[0x52]	391561	1		T1	468		T2	474		T3	24
valid_sources[0x53]	390633	1		T1	504		T2	489		T3	21
valid_sources[0x54]	387419	1		T1	503		T2	476		T3	13
valid_sources[0x55]	978366	1		T1	524		T2	473		T3	9
valid_sources[0x56]	392396	1		T1	466		T2	455		T3	13
valid_sources[0x57]	383691	1		T1	483		T2	492		T3	34
valid_sources[0x58]	1176942	1		T1	555		T2	395		T3	23
valid_sources[0x59]	390051	1		T1	514		T2	430		T3	25
valid_sources[0x5a]	388967	1		T1	482		T2	467		T3	10
valid_sources[0x5b]	388145	1		T1	469		T2	463		T3	20
valid_sources[0x5c]	393732	1		T1	520		T2	464		T3	24
valid_sources[0x5d]	386821	1		T1	434		T2	400		T5	716
valid_sources[0x5e]	387722	1		T1	505		T2	414		T3	15
valid_sources[0x5f]	394766	1		T1	501		T2	443		T3	11
valid_sources[0x60]	386709	1		T1	526		T2	449		T3	18
valid_sources[0x61]	400668	1		T1	500		T2	490		T5	748
valid_sources[0x62]	690900	1		T1	532		T2	437		T3	10
valid_sources[0x63]	383080	1		T1	477		T2	421		T3	21
valid_sources[0x64]	391762	1		T1	475		T2	471		T3	17
valid_sources[0x65]	713530	1		T1	438		T2	428		T3	28
valid_sources[0x66]	389359	1		T1	478		T2	439		T3	15
valid_sources[0x67]	391420	1		T1	425		T2	417		T3	7
valid_sources[0x68]	388062	1		T1	471		T2	435		T3	10
valid_sources[0x69]	389107	1		T1	403		T2	445		T3	9
valid_sources[0x6a]	611825	1		T1	534		T2	425		T3	8
valid_sources[0x6b]	788678	1		T1	505		T2	429		T3	7
valid_sources[0x6c]	402397	1		T1	529		T2	476		T3	6
valid_sources[0x6d]	385815	1		T1	454		T2	458		T3	34
valid_sources[0x6e]	1813888	1		T1	458		T2	452		T3	11
valid_sources[0x6f]	394606	1		T1	470		T2	485		T3	22
valid_sources[0x70]	387640	1		T1	428		T2	429		T3	4
valid_sources[0x71]	385383	1		T1	543		T2	478		T3	5
valid_sources[0x72]	390143	1		T1	522		T2	427		T3	8
valid_sources[0x73]	385069	1		T1	511		T2	415		T3	12
valid_sources[0x74]	397869	1		T1	541		T2	469		T3	8
valid_sources[0x75]	473145	1		T1	465		T2	456		T3	30
valid_sources[0x76]	389212	1		T1	519		T2	417		T3	7
valid_sources[0x77]	392560	1		T1	492		T2	439		T3	8
valid_sources[0x78]	385350	1		T1	582		T2	411		T3	11
valid_sources[0x79]	395981	1		T1	491		T2	454		T3	6
valid_sources[0x7a]	387560	1		T1	450		T2	520		T3	16
valid_sources[0x7b]	425387	1		T1	502		T2	422		T3	24
valid_sources[0x7c]	387123	1		T1	531		T2	420		T3	22
valid_sources[0x7d]	389812	1		T1	504		T2	399		T3	16
valid_sources[0x7e]	392437	1		T1	440		T2	457		T3	20
valid_sources[0x7f]	387930	1		T1	539		T2	413		T3	1
valid_sources[0x80]	389741	1		T1	477		T2	401		T3	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

65913427

1

T1

37627

T2

56948

T3

1935

values[0x0]

all_enables

biggest_size

2565257

1

T1

33846

T2

30

T3

7

values[0x1]

all_enables

biggest_size

2561842

1

T1

33812

T2

34

T3

5