Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	9094225	0	0
cfg0_rd_A	2147483647	20741	0	0
compare_lower0_0_rd_A	2147483647	23661	0	0
compare_upper0_0_rd_A	2147483647	21468	0	0
ctrl_rd_A	2147483647	21273	0	0
intr_enable0_rd_A	2147483647	25594	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9094225	0	0
T1	573413	121186	0	0
T2	144976	0	0	0
T3	542934	0	0	0
T4	933343	0	0	0
T5	743393	196653	0	0
T6	501354	0	0	0
T7	47527	0	0	0
T8	465783	0	0	0
T9	167220	0	0	0
T10	2897	0	0	0
T11	0	247793	0	0
T30	0	1	0	0
T31	0	18	0	0
T32	0	267515	0	0
T33	0	1059	0	0
T34	0	850	0	0
T35	0	311	0	0
T36	0	127	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	20741	0	0
T5	743393	1878	0	0
T6	501354	0	0	0
T7	47527	0	0	0
T8	465783	0	0	0
T9	167220	0	0	0
T10	2897	0	0	0
T12	0	1	0	0
T18	106984	0	0	0
T19	277531	0	0	0
T20	143264	0	0	0
T21	433777	0	0	0
T37	0	18	0	0
T38	0	48	0	0
T39	0	6	0	0
T40	0	7	0	0
T41	0	13	0	0
T42	0	52	0	0
T43	0	5	0	0
T44	0	281	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	23661	0	0
T5	743393	2327	0	0
T6	501354	0	0	0
T7	47527	0	0	0
T8	465783	0	0	0
T9	167220	0	0	0
T10	2897	0	0	0
T12	0	12	0	0
T18	106984	0	0	0
T19	277531	0	0	0
T20	143264	0	0	0
T21	433777	0	0	0
T37	0	41	0	0
T38	0	10	0	0
T39	0	10	0	0
T40	0	4	0	0
T41	0	8	0	0
T42	0	33	0	0
T43	0	5	0	0
T45	0	5	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21468	0	0
T5	743393	2109	0	0
T6	501354	0	0	0
T7	47527	0	0	0
T8	465783	0	0	0
T9	167220	0	0	0
T10	2897	0	0	0
T12	0	16	0	0
T18	106984	0	0	0
T19	277531	0	0	0
T20	143264	0	0	0
T21	433777	0	0	0
T37	0	18	0	0
T38	0	24	0	0
T39	0	9	0	0
T41	0	20	0	0
T42	0	25	0	0
T43	0	7	0	0
T44	0	244	0	0
T45	0	3	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21273	0	0
T5	743393	2046	0	0
T6	501354	0	0	0
T7	47527	0	0	0
T8	465783	0	0	0
T9	167220	0	0	0
T10	2897	0	0	0
T18	106984	0	0	0
T19	277531	0	0	0
T20	143264	0	0	0
T21	433777	0	0	0
T37	0	29	0	0
T38	0	25	0	0
T39	0	12	0	0
T40	0	6	0	0
T41	0	23	0	0
T42	0	43	0	0
T43	0	9	0	0
T44	0	261	0	0
T46	0	24	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	25594	0	0
T5	743393	2329	0	0
T6	501354	0	0	0
T7	47527	0	0	0
T8	465783	0	0	0
T9	167220	0	0	0
T10	2897	0	0	0
T12	0	7	0	0
T18	106984	0	0	0
T19	277531	0	0	0
T20	143264	0	0	0
T21	433777	0	0	0
T37	0	48	0	0
T38	0	6	0	0
T39	0	3	0	0
T40	0	4	0	0
T41	0	11	0	0
T47	0	15	0	0
T48	0	25	0	0
T49	0	14	0	0