Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	10654381	0	0
cfg0_rd_A	2147483647	16519	0	0
compare_lower0_0_rd_A	2147483647	18312	0	0
compare_upper0_0_rd_A	2147483647	16663	0	0
ctrl_rd_A	2147483647	17080	0	0
intr_enable0_rd_A	2147483647	20963	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10654381	0	0
T2	421015	52534	0	0
T3	126628	0	0	0
T4	116693	0	0	0
T5	216040	0	0	0
T6	124178	0	0	0
T7	947874	0	0	0
T8	580921	0	0	0
T9	148131	0	0	0
T10	180601	0	0	0
T11	0	283850	0	0
T12	0	171930	0	0
T26	0	5	0	0
T27	0	5	0	0
T31	0	477945	0	0
T32	0	37658	0	0
T33	0	580	0	0
T34	0	242	0	0
T35	0	53	0	0
T36	107679	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16519	0	0
T12	688045	1465	0	0
T27	3817	0	0	0
T28	0	125	0	0
T37	1714	19	0	0
T38	4429	64	0	0
T39	2379	15	0	0
T40	0	16	0	0
T41	0	15	0	0
T42	0	26	0	0
T43	0	4	0	0
T44	0	72	0	0
T45	1411	0	0	0
T46	2600	0	0	0
T47	3020	0	0	0
T48	725	0	0	0
T49	1975	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	18312	0	0
T12	688045	1820	0	0
T27	3817	0	0	0
T28	0	94	0	0
T37	1714	9	0	0
T38	4429	38	0	0
T39	2379	13	0	0
T40	0	15	0	0
T41	0	8	0	0
T42	0	9	0	0
T43	0	12	0	0
T44	0	68	0	0
T45	1411	0	0	0
T46	2600	0	0	0
T47	3020	0	0	0
T48	725	0	0	0
T49	1975	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16663	0	0
T12	688045	1700	0	0
T27	3817	0	0	0
T28	0	79	0	0
T38	4429	66	0	0
T39	2379	15	0	0
T40	0	12	0	0
T41	0	20	0	0
T42	0	22	0	0
T43	0	16	0	0
T44	0	69	0	0
T45	1411	0	0	0
T46	2600	0	0	0
T47	3020	0	0	0
T48	725	0	0	0
T49	1975	0	0	0
T50	0	51	0	0
T51	986	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	17080	0	0
T12	688045	1897	0	0
T27	3817	0	0	0
T28	0	94	0	0
T37	1714	3	0	0
T38	4429	113	0	0
T39	2379	25	0	0
T40	0	27	0	0
T41	0	13	0	0
T42	0	9	0	0
T43	0	7	0	0
T44	0	85	0	0
T45	1411	0	0	0
T46	2600	0	0	0
T47	3020	0	0	0
T48	725	0	0	0
T49	1975	0	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	20963	0	0
T5	216040	78	0	0
T6	124178	0	0	0
T7	947874	0	0	0
T8	580921	0	0	0
T9	148131	0	0	0
T10	180601	0	0	0
T12	0	2032	0	0
T28	0	77	0	0
T30	591796	0	0	0
T36	107679	0	0	0
T37	0	10	0	0
T38	0	81	0	0
T39	0	17	0	0
T40	0	18	0	0
T52	0	22	0	0
T53	0	9	0	0
T54	0	12	0	0
T55	110201	0	0	0
T56	107370	0	0	0