Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	9408221	0	0
cfg0_rd_A	2147483647	16854	0	0
compare_lower0_0_rd_A	2147483647	18532	0	0
compare_upper0_0_rd_A	2147483647	15867	0	0
ctrl_rd_A	2147483647	16349	0	0
intr_enable0_rd_A	2147483647	19954	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9408221	0	0
T3	123111	30166	0	0
T4	213250	0	0	0
T5	890000	0	0	0
T6	314168	0	0	0
T7	188901	0	0	0
T8	142507	0	0	0
T9	988239	0	0	0
T10	481004	0	0	0
T13	0	244088	0	0
T14	0	235487	0	0
T33	0	69	0	0
T35	0	224689	0	0
T36	0	275024	0	0
T37	0	37587	0	0
T38	0	199094	0	0
T39	0	176	0	0
T40	0	300	0	0
T41	111082	0	0	0
T42	155119	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16854	0	0
T3	123111	303	0	0
T4	213250	0	0	0
T5	890000	0	0	0
T6	314168	0	0	0
T7	188901	0	0	0
T8	142507	0	0	0
T9	988239	0	0	0
T10	481004	0	0	0
T13	0	1299	0	0
T30	0	122	0	0
T32	0	5	0	0
T41	111082	0	0	0
T42	155119	0	0	0
T43	0	10	0	0
T44	0	187	0	0
T45	0	3	0	0
T46	0	7	0	0
T47	0	138	0	0
T48	0	112	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	18532	0	0
T3	123111	406	0	0
T4	213250	0	0	0
T5	890000	0	0	0
T6	314168	0	0	0
T7	188901	0	0	0
T8	142507	0	0	0
T9	988239	0	0	0
T10	481004	0	0	0
T13	0	1546	0	0
T30	0	78	0	0
T32	0	9	0	0
T40	0	16	0	0
T41	111082	0	0	0
T42	155119	0	0	0
T43	0	6	0	0
T44	0	108	0	0
T46	0	2	0	0
T47	0	90	0	0
T48	0	39	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15867	0	0
T3	123111	350	0	0
T4	213250	0	0	0
T5	890000	0	0	0
T6	314168	0	0	0
T7	188901	0	0	0
T8	142507	0	0	0
T9	988239	0	0	0
T10	481004	0	0	0
T13	0	1243	0	0
T30	0	74	0	0
T32	0	14	0	0
T41	111082	0	0	0
T42	155119	0	0	0
T44	0	117	0	0
T46	0	1	0	0
T47	0	54	0	0
T48	0	54	0	0
T49	0	10	0	0
T50	0	14	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16349	0	0
T3	123111	279	0	0
T4	213250	0	0	0
T5	890000	0	0	0
T6	314168	0	0	0
T7	188901	0	0	0
T8	142507	0	0	0
T9	988239	0	0	0
T10	481004	0	0	0
T13	0	1464	0	0
T30	0	81	0	0
T32	0	7	0	0
T40	0	8	0	0
T41	111082	0	0	0
T42	155119	0	0	0
T44	0	101	0	0
T45	0	1	0	0
T46	0	8	0	0
T47	0	61	0	0
T48	0	32	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	19954	0	0
T3	123111	422	0	0
T4	213250	0	0	0
T5	890000	0	0	0
T6	314168	0	0	0
T7	188901	0	0	0
T8	142507	0	0	0
T9	988239	0	0	0
T10	481004	0	0	0
T13	0	1680	0	0
T30	0	90	0	0
T32	0	11	0	0
T41	111082	0	0	0
T42	155119	0	0	0
T43	0	9	0	0
T51	0	26	0	0
T52	0	5	0	0
T53	0	16	0	0
T54	0	32	0	0
T55	0	9	0	0