Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	7989953	0	0
cfg0_rd_A	2147483647	27016	0	0
compare_lower0_0_rd_A	2147483647	30084	0	0
compare_upper0_0_rd_A	2147483647	27244	0	0
ctrl_rd_A	2147483647	26899	0	0
intr_enable0_rd_A	2147483647	33255	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7989953	0	0
T10	501641	209354	0	0
T11	128410	340006	0	0
T12	535484	134331	0	0
T30	0	12	0	0
T31	0	6	0	0
T32	0	10	0	0
T33	0	9	0	0
T34	563143	0	0	0
T35	104923	0	0	0
T36	0	64370	0	0
T37	0	98463	0	0
T38	0	52856	0	0
T39	563099	0	0	0
T40	534135	0	0	0
T41	379444	0	0	0
T42	364656	0	0	0
T43	373078	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	27016	0	0
T12	535484	623	0	0
T13	2250	30	0	0
T30	12576	187	0	0
T38	628160	546	0	0
T44	41041	766	0	0
T45	1180	2	0	0
T46	0	5	0	0
T47	0	50	0	0
T48	0	8	0	0
T49	0	88	0	0
T50	952274	0	0	0
T51	599796	0	0	0
T52	748580	0	0	0
T53	1175	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	30084	0	0
T12	535484	762	0	0
T13	2250	20	0	0
T30	12576	118	0	0
T38	628160	576	0	0
T44	41041	673	0	0
T45	1180	0	0	0
T46	0	5	0	0
T47	0	28	0	0
T48	0	6	0	0
T49	0	84	0	0
T50	952274	0	0	0
T51	599796	0	0	0
T52	748580	0	0	0
T53	1175	0	0	0
T54	0	17	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	27244	0	0
T12	535484	764	0	0
T13	2250	16	0	0
T30	12576	121	0	0
T38	628160	523	0	0
T44	41041	636	0	0
T45	1180	6	0	0
T46	0	8	0	0
T47	0	24	0	0
T48	0	4	0	0
T49	0	80	0	0
T50	952274	0	0	0
T51	599796	0	0	0
T52	748580	0	0	0
T53	1175	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	26899	0	0
T12	535484	749	0	0
T13	2250	15	0	0
T30	12576	78	0	0
T38	628160	460	0	0
T44	41041	607	0	0
T45	1180	1	0	0
T46	0	5	0	0
T47	0	26	0	0
T48	0	5	0	0
T49	0	85	0	0
T50	952274	0	0	0
T51	599796	0	0	0
T52	748580	0	0	0
T53	1175	0	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	33255	0	0
T11	128410	0	0	0
T12	535484	825	0	0
T13	0	9	0	0
T30	0	108	0	0
T34	563143	3	0	0
T35	104923	0	0	0
T38	628160	605	0	0
T41	379444	0	0	0
T42	364656	0	0	0
T43	373078	0	0	0
T44	0	702	0	0
T45	0	1	0	0
T50	952274	0	0	0
T51	599796	0	0	0
T55	0	75	0	0
T56	0	27	0	0
T57	0	26	0	0