Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	51792614	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	56518577	1		T1	20		T2	13		T3	120

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	104258345	1		T1	28		T2	19		T3	51
values[0x0]	1924180	1		T1	17		T2	8		T3	37
values[0x1]	2128666	1		T1	11		T2	11		T3	33

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	41278497	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	67032694	1		T1	23		T2	16		T3	120

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	306202	1		T8	1		T9	2		T37	2
valid_sources[0x01]	301207	1		T3	1		T4	7		T7	2
valid_sources[0x02]	312603	1		T9	1		T36	2		T37	2
valid_sources[0x03]	306745	1		T3	1		T7	1		T9	1
valid_sources[0x04]	299528	1		T4	4		T5	10		T8	1
valid_sources[0x05]	307646	1		T8	1		T44	1		T36	1
valid_sources[0x06]	310347	1		T8	2		T9	2		T17	1
valid_sources[0x07]	505048	1		T3	1		T9	3		T36	2
valid_sources[0x08]	306137	1		T5	13		T9	2		T43	1
valid_sources[0x09]	307410	1		T3	2		T5	14		T8	2
valid_sources[0x0a]	680189	1		T3	1		T9	2		T18	2
valid_sources[0x0b]	303547	1		T3	2		T4	4		T8	6
valid_sources[0x0c]	2778265	1		T5	4		T7	1		T8	2
valid_sources[0x0d]	306428	1		T8	3		T43	2		T36	1
valid_sources[0x0e]	309472	1		T5	1		T43	1		T37	2
valid_sources[0x0f]	302081	1		T3	1		T8	5		T9	1
valid_sources[0x10]	361904	1		T5	10		T36	4		T65	6
valid_sources[0x11]	302247	1		T2	6		T3	3		T4	2
valid_sources[0x12]	306777	1		T9	2		T17	1		T39	3
valid_sources[0x13]	304055	1		T3	1		T8	2		T9	2
valid_sources[0x14]	305236	1		T3	2		T8	1		T9	2
valid_sources[0x15]	329928	1		T18	1		T37	1		T38	21
valid_sources[0x16]	304612	1		T3	1		T9	1		T18	3
valid_sources[0x17]	309911	1		T3	1		T5	10		T9	3
valid_sources[0x18]	302798	1		T4	6		T9	1		T43	1
valid_sources[0x19]	311288	1		T4	7		T9	1		T43	2
valid_sources[0x1a]	301496	1		T5	1		T9	3		T36	2
valid_sources[0x1b]	304219	1		T5	7		T9	1		T36	1
valid_sources[0x1c]	307656	1		T3	1		T4	2		T9	1
valid_sources[0x1d]	306297	1		T3	1		T4	2		T18	39
valid_sources[0x1e]	297753	1		T3	1		T4	5		T5	23
valid_sources[0x1f]	307637	1		T3	1		T4	4		T9	2
valid_sources[0x20]	304605	1		T5	4		T18	16		T17	1
valid_sources[0x21]	533389	1		T2	3		T4	1		T9	1
valid_sources[0x22]	1742305	1		T1	56		T4	1		T8	3
valid_sources[0x23]	371844	1		T3	1		T4	3		T9	1
valid_sources[0x24]	361205	1		T4	2		T5	7		T9	2
valid_sources[0x25]	1822114	1		T17	1		T37	2		T40	1
valid_sources[0x26]	300227	1		T9	2		T37	3		T74	1
valid_sources[0x27]	301689	1		T2	2		T3	1		T5	8
valid_sources[0x28]	310668	1		T4	5		T9	2		T36	1
valid_sources[0x29]	302268	1		T3	3		T8	2		T9	3
valid_sources[0x2a]	316481	1		T5	2		T18	1		T43	1
valid_sources[0x2b]	306102	1		T2	1		T9	1		T43	1
valid_sources[0x2c]	305525	1		T9	1		T51	1		T37	1
valid_sources[0x2d]	303667	1		T4	2		T9	1		T43	2
valid_sources[0x2e]	381971	1		T8	2		T18	20		T43	1
valid_sources[0x2f]	374579	1		T44	1		T65	15		T37	2
valid_sources[0x30]	612759	1		T5	1		T9	1		T18	34
valid_sources[0x31]	300336	1		T5	11		T8	1		T9	1
valid_sources[0x32]	307398	1		T8	2		T9	2		T65	4
valid_sources[0x33]	303906	1		T8	1		T43	1		T37	3
valid_sources[0x34]	299471	1		T3	2		T7	1		T8	2
valid_sources[0x35]	301953	1		T3	1		T5	2		T8	2
valid_sources[0x36]	383339	1		T3	1		T5	4		T37	3
valid_sources[0x37]	313170	1		T3	1		T8	2		T9	2
valid_sources[0x38]	304104	1		T4	1		T9	1		T37	2
valid_sources[0x39]	304926	1		T18	1		T37	4		T39	1
valid_sources[0x3a]	392577	1		T8	1		T9	2		T37	4
valid_sources[0x3b]	313528	1		T3	2		T4	2		T8	1
valid_sources[0x3c]	304863	1		T3	1		T5	5		T9	2
valid_sources[0x3d]	308145	1		T5	1		T6	1		T8	5
valid_sources[0x3e]	306097	1		T3	3		T37	5		T39	1
valid_sources[0x3f]	322907	1		T8	1		T9	1		T44	1
valid_sources[0x40]	303319	1		T4	3		T17	1		T37	4
valid_sources[0x41]	305241	1		T4	1		T5	3		T18	21
valid_sources[0x42]	301871	1		T8	1		T9	1		T37	2
valid_sources[0x43]	308066	1		T3	1		T4	2		T6	2
valid_sources[0x44]	305139	1		T8	1		T65	9		T37	3
valid_sources[0x45]	307263	1		T8	1		T9	1		T18	1
valid_sources[0x46]	304977	1		T3	1		T9	2		T16	20
valid_sources[0x47]	297523	1		T4	1		T9	1		T36	4
valid_sources[0x48]	420029	1		T3	2		T4	6		T5	3
valid_sources[0x49]	381359	1		T5	5		T37	5		T40	1
valid_sources[0x4a]	312325	1		T3	1		T4	2		T8	1
valid_sources[0x4b]	301945	1		T43	3		T36	2		T65	8
valid_sources[0x4c]	309254	1		T5	6		T8	3		T9	1
valid_sources[0x4d]	304905	1		T37	3		T40	1		T57	1
valid_sources[0x4e]	302698	1		T3	1		T4	4		T7	1
valid_sources[0x4f]	297173	1		T3	2		T36	5		T37	1
valid_sources[0x50]	310393	1		T18	54		T17	1		T37	6
valid_sources[0x51]	302757	1		T9	2		T43	1		T37	1
valid_sources[0x52]	308242	1		T6	1		T17	5		T37	2
valid_sources[0x53]	306196	1		T3	3		T4	3		T8	4
valid_sources[0x54]	315098	1		T3	1		T4	5		T5	18
valid_sources[0x55]	312302	1		T4	2		T37	1		T39	2
valid_sources[0x56]	304370	1		T4	3		T9	1		T44	1
valid_sources[0x57]	445732	1		T6	1		T9	1		T43	1
valid_sources[0x58]	306944	1		T4	2		T9	2		T43	2
valid_sources[0x59]	303359	1		T9	1		T51	1		T36	2
valid_sources[0x5a]	307887	1		T5	27		T9	1		T18	1
valid_sources[0x5b]	309419	1		T9	2		T17	1		T37	1
valid_sources[0x5c]	298115	1		T6	1		T9	1		T43	1
valid_sources[0x5d]	303625	1		T4	1		T8	3		T9	1
valid_sources[0x5e]	310215	1		T6	1		T8	1		T17	1
valid_sources[0x5f]	301012	1		T9	2		T17	2		T37	1
valid_sources[0x60]	4798192	1		T5	10		T36	7		T37	5
valid_sources[0x61]	300954	1		T4	1		T7	2		T8	1
valid_sources[0x62]	368290	1		T4	4		T8	1		T9	3
valid_sources[0x63]	310717	1		T3	2		T6	1		T9	1
valid_sources[0x64]	302874	1		T36	3		T37	6		T39	3
valid_sources[0x65]	300776	1		T5	1		T18	1		T43	2
valid_sources[0x66]	322763	1		T4	10		T9	1		T37	4
valid_sources[0x67]	305621	1		T3	1		T4	1		T40	6
valid_sources[0x68]	312856	1		T5	7		T8	3		T9	3
valid_sources[0x69]	2143177	1		T9	2		T36	2		T41	4
valid_sources[0x6a]	308791	1		T3	1		T9	2		T43	1
valid_sources[0x6b]	308540	1		T3	1		T5	10		T8	1
valid_sources[0x6c]	308877	1		T65	13		T37	1		T39	1
valid_sources[0x6d]	306655	1		T9	2		T17	3		T37	3
valid_sources[0x6e]	1636741	1		T5	6		T8	1		T36	1
valid_sources[0x6f]	307408	1		T4	2		T5	6		T9	4
valid_sources[0x70]	299354	1		T9	1		T18	28		T37	1
valid_sources[0x71]	299917	1		T5	10		T36	3		T37	1
valid_sources[0x72]	305302	1		T8	1		T9	3		T36	3
valid_sources[0x73]	304818	1		T4	4		T5	2		T8	4
valid_sources[0x74]	345907	1		T4	1		T36	1		T37	1
valid_sources[0x75]	575985	1		T7	1		T9	2		T43	1
valid_sources[0x76]	303527	1		T5	7		T9	2		T37	2
valid_sources[0x77]	313717	1		T5	2		T8	1		T37	3
valid_sources[0x78]	314728	1		T4	1		T5	24		T9	1
valid_sources[0x79]	397000	1		T3	2		T9	3		T37	4
valid_sources[0x7a]	303161	1		T8	2		T9	1		T37	3
valid_sources[0x7b]	307762	1		T5	2		T8	1		T9	3
valid_sources[0x7c]	300227	1		T3	1		T4	1		T8	1
valid_sources[0x7d]	306666	1		T4	2		T6	1		T8	1
valid_sources[0x7e]	301376	1		T43	2		T36	5		T37	1
valid_sources[0x7f]	818357	1		T3	1		T5	6		T9	1
valid_sources[0x80]	690387	1		T44	1		T65	4		T56	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

52726183

1

T1

10

T2

10

T3

50

values[0x0]

all_enables

biggest_size

1896844

1

T1

8

T2

1

T3

37

values[0x1]

all_enables

biggest_size

1895550

1

T1

2

T2

2

T3

33