Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	6715739	0	0
cfg0_rd_A	2147483647	16141	0	0
compare_lower0_0_rd_A	2147483647	17501	0	0
compare_upper0_0_rd_A	2147483647	16027	0	0
ctrl_rd_A	2147483647	15672	0	0
intr_enable0_rd_A	2147483647	19663	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6715739	0	0
T5	8836	12	0	0
T6	1134	0	0	0
T7	1370	0	0	0
T8	2796	0	0	0
T9	3105	0	0	0
T10	1410	0	0	0
T16	1249	8	0	0
T17	0	28	0	0
T18	4573	732	0	0
T36	0	257	0	0
T37	0	16	0	0
T38	0	13	0	0
T39	0	228	0	0
T40	0	389	0	0
T42	0	24	0	0
T43	1280	0	0	0
T44	803	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16141	0	0
T8	2796	82	0	0
T9	3105	0	0	0
T10	1410	0	0	0
T16	1249	18	0	0
T17	977	0	0	0
T18	4573	0	0	0
T38	0	133	0	0
T42	0	15	0	0
T43	1280	0	0	0
T44	803	0	0	0
T45	0	15	0	0
T46	0	6	0	0
T47	0	3	0	0
T48	0	11	0	0
T49	0	10	0	0
T50	0	4	0	0
T51	1392	0	0	0
T52	992	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	17501	0	0
T8	2796	79	0	0
T9	3105	0	0	0
T10	1410	0	0	0
T16	1249	16	0	0
T17	977	0	0	0
T18	4573	0	0	0
T38	0	100	0	0
T42	0	6	0	0
T43	1280	0	0	0
T44	803	0	0	0
T45	0	7	0	0
T49	0	5	0	0
T50	0	2	0	0
T51	1392	0	0	0
T52	992	0	0	0
T53	0	36	0	0
T54	0	15	0	0
T55	0	16	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16027	0	0
T8	2796	45	0	0
T9	3105	0	0	0
T10	1410	0	0	0
T16	1249	6	0	0
T17	977	0	0	0
T18	4573	0	0	0
T38	0	140	0	0
T42	0	15	0	0
T43	1280	0	0	0
T44	803	0	0	0
T45	0	7	0	0
T46	0	3	0	0
T47	0	1	0	0
T49	0	8	0	0
T50	0	5	0	0
T51	1392	0	0	0
T52	992	0	0	0
T53	0	21	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15672	0	0
T8	2796	63	0	0
T9	3105	0	0	0
T10	1410	0	0	0
T16	1249	6	0	0
T17	977	0	0	0
T18	4573	0	0	0
T38	0	130	0	0
T42	0	6	0	0
T43	1280	0	0	0
T44	803	0	0	0
T45	0	12	0	0
T46	0	7	0	0
T48	0	4	0	0
T49	0	9	0	0
T51	1392	0	0	0
T52	992	0	0	0
T53	0	34	0	0
T54	0	2	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	19663	0	0
T1	1300	6	0	0
T2	845	0	0	0
T3	1265	0	0	0
T4	1325	0	0	0
T5	8836	0	0	0
T6	1134	0	0	0
T7	1370	0	0	0
T8	2796	61	0	0
T9	3105	0	0	0
T10	1410	25	0	0
T16	0	6	0	0
T38	0	88	0	0
T42	0	16	0	0
T45	0	9	0	0
T56	0	44	0	0
T57	0	31	0	0
T58	0	11	0	0