Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	54311175	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	58954569	1		T1	18		T2	22		T3	1415

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	109294427	1		T1	22		T2	29		T3	1273
values[0x0]	1884821	1		T1	8		T2	15		T3	677
values[0x1]	2086496	1		T1	12		T2	14		T3	595

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	43291689	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	69974055	1		T1	23		T2	29		T3	1595

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	341507	1		T3	6		T6	2		T14	4
valid_sources[0x01]	350604	1		T3	7		T4	6		T6	1
valid_sources[0x02]	349135	1		T3	30		T6	1		T7	7
valid_sources[0x03]	1160497	1		T3	2		T14	3		T37	3
valid_sources[0x04]	346140	1		T3	1		T6	3		T8	1
valid_sources[0x05]	356706	1		T1	2		T3	2		T8	2
valid_sources[0x06]	492959	1		T2	1		T3	22		T48	1
valid_sources[0x07]	347952	1		T47	3		T14	2		T41	2
valid_sources[0x08]	352844	1		T3	1		T48	2		T14	4
valid_sources[0x09]	352524	1		T3	4		T47	2		T14	3
valid_sources[0x0a]	345096	1		T3	3		T14	2		T49	2
valid_sources[0x0b]	347184	1		T8	1		T48	2		T14	1
valid_sources[0x0c]	341747	1		T2	1		T3	6		T7	2
valid_sources[0x0d]	350566	1		T3	3		T8	1		T48	5
valid_sources[0x0e]	350079	1		T3	12		T9	2		T14	1
valid_sources[0x0f]	347443	1		T3	4		T8	1		T48	1
valid_sources[0x10]	350964	1		T1	1		T3	11		T8	1
valid_sources[0x11]	344267	1		T2	3		T3	7		T9	3
valid_sources[0x12]	352694	1		T37	1		T45	4		T38	5
valid_sources[0x13]	348136	1		T3	11		T48	2		T14	4
valid_sources[0x14]	350498	1		T3	7		T8	1		T9	1
valid_sources[0x15]	375589	1		T3	25		T9	3		T38	2
valid_sources[0x16]	343072	1		T3	5		T8	1		T46	4
valid_sources[0x17]	346247	1		T3	8		T5	1		T48	4
valid_sources[0x18]	345082	1		T1	2		T3	7		T14	1
valid_sources[0x19]	1289691	1		T3	5		T9	1		T48	4
valid_sources[0x1a]	348153	1		T3	1		T8	1		T47	1
valid_sources[0x1b]	514954	1		T48	2		T14	6		T37	6
valid_sources[0x1c]	351631	1		T3	8		T5	1		T9	1
valid_sources[0x1d]	346551	1		T2	1		T5	1		T8	1
valid_sources[0x1e]	341684	1		T14	6		T15	18		T37	2
valid_sources[0x1f]	345280	1		T9	2		T10	10		T14	2
valid_sources[0x20]	341583	1		T3	6		T9	1		T48	2
valid_sources[0x21]	345846	1		T3	16		T5	2		T14	1
valid_sources[0x22]	349534	1		T3	42		T6	2		T8	1
valid_sources[0x23]	348246	1		T3	4		T5	1		T14	4
valid_sources[0x24]	347793	1		T3	27		T8	1		T14	1
valid_sources[0x25]	504877	1		T3	1		T14	5		T37	3
valid_sources[0x26]	1244174	1		T3	5		T9	2		T37	1
valid_sources[0x27]	339220	1		T2	1		T3	6		T16	6
valid_sources[0x28]	347550	1		T1	2		T14	4		T40	7
valid_sources[0x29]	345356	1		T3	3		T14	3		T45	17
valid_sources[0x2a]	349134	1		T14	6		T38	1		T43	1
valid_sources[0x2b]	345043	1		T3	8		T9	1		T47	2
valid_sources[0x2c]	348386	1		T3	10		T8	1		T41	2
valid_sources[0x2d]	352025	1		T2	1		T3	20		T4	7
valid_sources[0x2e]	1206701	1		T3	18		T8	1		T14	1
valid_sources[0x2f]	354966	1		T4	13		T6	3		T48	3
valid_sources[0x30]	346392	1		T1	3		T6	6		T9	4
valid_sources[0x31]	349352	1		T2	1		T3	3		T9	2
valid_sources[0x32]	427063	1		T3	17		T14	1		T40	2
valid_sources[0x33]	340264	1		T3	33		T9	1		T37	2
valid_sources[0x34]	350327	1		T6	1		T14	2		T46	9
valid_sources[0x35]	341156	1		T2	1		T3	33		T8	1
valid_sources[0x36]	386010	1		T3	16		T4	4		T14	2
valid_sources[0x37]	347017	1		T3	8		T9	2		T16	4
valid_sources[0x38]	871949	1		T3	17		T9	1		T47	2
valid_sources[0x39]	346105	1		T3	3		T14	3		T50	3
valid_sources[0x3a]	341921	1		T3	40		T4	12		T14	1
valid_sources[0x3b]	395648	1		T2	1		T48	3		T14	2
valid_sources[0x3c]	344813	1		T3	11		T7	11		T9	4
valid_sources[0x3d]	345014	1		T3	25		T14	1		T38	7
valid_sources[0x3e]	347311	1		T3	2		T9	1		T48	2
valid_sources[0x3f]	342466	1		T2	1		T3	1		T14	2
valid_sources[0x40]	354700	1		T3	12		T48	3		T14	4
valid_sources[0x41]	350532	1		T3	37		T8	2		T14	3
valid_sources[0x42]	356388	1		T5	1		T6	1		T14	2
valid_sources[0x43]	345042	1		T3	5		T5	1		T8	1
valid_sources[0x44]	351784	1		T8	1		T9	2		T48	2
valid_sources[0x45]	393650	1		T3	9		T47	1		T48	1
valid_sources[0x46]	350068	1		T2	2		T8	1		T14	1
valid_sources[0x47]	383585	1		T3	4		T9	2		T38	14
valid_sources[0x48]	351481	1		T8	1		T57	40		T46	7
valid_sources[0x49]	356647	1		T3	10		T8	1		T9	6
valid_sources[0x4a]	344425	1		T3	5		T9	3		T14	4
valid_sources[0x4b]	1642577	1		T3	23		T9	1		T48	1
valid_sources[0x4c]	349709	1		T1	2		T3	8		T8	2
valid_sources[0x4d]	768588	1		T48	3		T14	6		T46	12
valid_sources[0x4e]	344525	1		T2	2		T38	2		T58	1
valid_sources[0x4f]	350469	1		T9	2		T41	2		T63	1
valid_sources[0x50]	348135	1		T3	10		T6	1		T48	1
valid_sources[0x51]	345146	1		T3	6		T4	4		T6	2
valid_sources[0x52]	345620	1		T8	1		T9	1		T49	1
valid_sources[0x53]	378554	1		T9	1		T48	2		T38	2
valid_sources[0x54]	355906	1		T2	1		T3	15		T9	4
valid_sources[0x55]	350356	1		T3	14		T8	1		T14	1
valid_sources[0x56]	700067	1		T2	1		T3	12		T48	2
valid_sources[0x57]	344885	1		T3	23		T15	11		T37	1
valid_sources[0x58]	347512	1		T3	4		T48	1		T37	2
valid_sources[0x59]	353552	1		T3	7		T45	1		T43	1
valid_sources[0x5a]	350387	1		T3	17		T9	1		T14	4
valid_sources[0x5b]	342176	1		T2	1		T3	9		T14	6
valid_sources[0x5c]	342883	1		T3	5		T48	4		T38	1
valid_sources[0x5d]	339110	1		T3	22		T9	1		T48	1
valid_sources[0x5e]	374529	1		T3	10		T8	1		T9	1
valid_sources[0x5f]	347103	1		T3	12		T6	2		T8	1
valid_sources[0x60]	347002	1		T2	3		T3	8		T7	15
valid_sources[0x61]	343819	1		T3	7		T8	1		T9	1
valid_sources[0x62]	349504	1		T1	1		T2	1		T14	4
valid_sources[0x63]	342413	1		T3	1		T38	1		T58	7
valid_sources[0x64]	1106210	1		T3	22		T6	3		T9	3
valid_sources[0x65]	345472	1		T3	2		T6	3		T9	2
valid_sources[0x66]	342923	1		T3	18		T48	2		T14	1
valid_sources[0x67]	377474	1		T3	1		T6	1		T9	1
valid_sources[0x68]	346237	1		T3	11		T9	1		T48	3
valid_sources[0x69]	1282142	1		T1	1		T3	10		T48	1
valid_sources[0x6a]	354916	1		T3	18		T9	4		T48	1
valid_sources[0x6b]	346681	1		T3	26		T14	4		T37	1
valid_sources[0x6c]	340092	1		T1	3		T3	14		T4	14
valid_sources[0x6d]	341214	1		T2	1		T3	10		T9	1
valid_sources[0x6e]	348012	1		T3	9		T14	1		T40	1
valid_sources[0x6f]	349231	1		T3	30		T48	1		T46	3
valid_sources[0x70]	344831	1		T14	2		T46	10		T40	3
valid_sources[0x71]	373943	1		T3	29		T40	8		T41	3
valid_sources[0x72]	345459	1		T2	1		T48	1		T14	4
valid_sources[0x73]	351158	1		T14	3		T49	1		T41	5
valid_sources[0x74]	345164	1		T3	7		T14	4		T58	1
valid_sources[0x75]	342717	1		T2	2		T3	32		T8	2
valid_sources[0x76]	351210	1		T2	1		T3	2		T5	1
valid_sources[0x77]	366621	1		T2	2		T8	1		T48	1
valid_sources[0x78]	344023	1		T3	4		T48	1		T14	2
valid_sources[0x79]	350744	1		T2	2		T14	1		T37	1
valid_sources[0x7a]	349652	1		T3	28		T8	1		T38	15
valid_sources[0x7b]	347639	1		T3	7		T14	1		T37	2
valid_sources[0x7c]	344529	1		T14	1		T37	2		T38	6
valid_sources[0x7d]	349844	1		T2	1		T3	7		T14	1
valid_sources[0x7e]	342239	1		T3	9		T5	1		T6	1
valid_sources[0x7f]	347047	1		T3	27		T9	1		T48	2
valid_sources[0x80]	354093	1		T48	1		T49	1		T45	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

55237446

1

T1

8

T2

16

T3

618

values[0x0]

all_enables

biggest_size

1858330

1

T1

2

T2

6

T3

466

values[0x1]

all_enables

biggest_size

1858793

1

T1

8

T3

331

T4

25