Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	6565472	0	0
cfg0_rd_A	2147483647	10671	0	0
compare_lower0_0_rd_A	2147483647	11867	0	0
compare_upper0_0_rd_A	2147483647	10481	0	0
ctrl_rd_A	2147483647	10585	0	0
intr_enable0_rd_A	2147483647	12863	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6565472	0	0
T8	5608	366	0	0
T9	1729	49	0	0
T10	1135	0	0	0
T14	6799	7	0	0
T15	1599	0	0	0
T16	1021	0	0	0
T37	0	229	0	0
T38	0	7	0	0
T40	0	418	0	0
T41	0	587	0	0
T43	0	347	0	0
T45	0	23	0	0
T46	0	100	0	0
T47	915	0	0	0
T48	2038	0	0	0
T49	1526	0	0	0
T50	1164	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10671	0	0
T15	1599	7	0	0
T37	5455	16	0	0
T38	7115	0	0	0
T40	6967	0	0	0
T44	0	5	0	0
T45	1239	0	0	0
T46	3542	44	0	0
T51	0	56	0	0
T52	0	50	0	0
T53	0	196	0	0
T54	0	46	0	0
T55	0	145	0	0
T56	0	660	0	0
T57	898	0	0	0
T58	1554	0	0	0
T59	1462	0	0	0
T60	1096	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	11867	0	0
T15	1599	6	0	0
T37	5455	0	0	0
T38	7115	0	0	0
T40	6967	0	0	0
T45	1239	0	0	0
T46	3542	23	0	0
T51	0	37	0	0
T52	0	50	0	0
T53	0	101	0	0
T54	0	34	0	0
T55	0	74	0	0
T56	0	612	0	0
T57	898	0	0	0
T58	1554	0	0	0
T59	1462	0	0	0
T60	1096	0	0	0
T61	0	5	0	0
T62	0	19	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10481	0	0
T15	1599	11	0	0
T37	5455	0	0	0
T38	7115	0	0	0
T40	6967	0	0	0
T44	0	1	0	0
T45	1239	0	0	0
T46	3542	26	0	0
T51	0	65	0	0
T52	0	29	0	0
T53	0	110	0	0
T54	0	45	0	0
T55	0	63	0	0
T56	0	698	0	0
T57	898	0	0	0
T58	1554	0	0	0
T59	1462	0	0	0
T60	1096	0	0	0
T61	0	23	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10585	0	0
T15	1599	13	0	0
T37	5455	0	0	0
T38	7115	0	0	0
T40	6967	0	0	0
T44	0	6	0	0
T45	1239	0	0	0
T46	3542	36	0	0
T51	0	53	0	0
T52	0	95	0	0
T53	0	136	0	0
T54	0	30	0	0
T55	0	74	0	0
T56	0	669	0	0
T57	898	0	0	0
T58	1554	0	0	0
T59	1462	0	0	0
T60	1096	0	0	0
T61	0	1	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	12863	0	0
T2	1447	37	0	0
T3	18828	0	0	0
T4	1601	0	0	0
T5	834	0	0	0
T6	1412	0	0	0
T7	1224	0	0	0
T8	5608	0	0	0
T9	1729	0	0	0
T10	1135	0	0	0
T15	0	12	0	0
T16	1021	0	0	0
T44	0	5	0	0
T46	0	21	0	0
T51	0	54	0	0
T52	0	33	0	0
T53	0	82	0	0
T58	0	22	0	0
T63	0	7	0	0
T64	0	32	0	0