Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	10530388	0	0
cfg0_rd_A	2147483647	22325	0	0
compare_lower0_0_rd_A	2147483647	24718	0	0
compare_upper0_0_rd_A	2147483647	21308	0	0
ctrl_rd_A	2147483647	22179	0	0
intr_enable0_rd_A	2147483647	27051	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10530388	0	0
T13	536874	132609	0	0
T14	0	148743	0	0
T15	0	324509	0	0
T16	0	9	0	0
T17	0	260	0	0
T32	0	12	0	0
T34	0	314214	0	0
T35	0	485	0	0
T36	0	249	0	0
T37	0	591	0	0
T38	367699	0	0	0
T39	951532	0	0	0
T40	311097	0	0	0
T41	81193	0	0	0
T42	310534	0	0	0
T43	160376	0	0	0
T44	111529	0	0	0
T45	170044	0	0	0
T46	440945	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	22325	0	0
T13	536874	1458	0	0
T16	0	199	0	0
T33	0	40	0	0
T35	0	7	0	0
T38	367699	0	0	0
T39	951532	0	0	0
T40	311097	0	0	0
T41	81193	0	0	0
T42	310534	0	0	0
T43	160376	0	0	0
T44	111529	0	0	0
T45	170044	0	0	0
T46	440945	0	0	0
T47	0	66	0	0
T48	0	62	0	0
T49	0	44	0	0
T50	0	51	0	0
T51	0	40	0	0
T52	0	11	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	24718	0	0
T13	536874	1581	0	0
T16	0	108	0	0
T33	0	50	0	0
T35	0	9	0	0
T38	367699	0	0	0
T39	951532	0	0	0
T40	311097	0	0	0
T41	81193	0	0	0
T42	310534	0	0	0
T43	160376	0	0	0
T44	111529	0	0	0
T45	170044	0	0	0
T46	440945	0	0	0
T47	0	29	0	0
T48	0	55	0	0
T49	0	30	0	0
T50	0	79	0	0
T51	0	29	0	0
T52	0	3	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21308	0	0
T13	536874	1326	0	0
T16	0	100	0	0
T33	0	15	0	0
T35	0	2	0	0
T36	0	16	0	0
T38	367699	0	0	0
T39	951532	0	0	0
T40	311097	0	0	0
T41	81193	0	0	0
T42	310534	0	0	0
T43	160376	0	0	0
T44	111529	0	0	0
T45	170044	0	0	0
T46	440945	0	0	0
T47	0	52	0	0
T48	0	43	0	0
T49	0	53	0	0
T50	0	54	0	0
T51	0	44	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	22179	0	0
T13	536874	1456	0	0
T16	0	105	0	0
T33	0	57	0	0
T35	0	5	0	0
T38	367699	0	0	0
T39	951532	0	0	0
T40	311097	0	0	0
T41	81193	0	0	0
T42	310534	0	0	0
T43	160376	0	0	0
T44	111529	0	0	0
T45	170044	0	0	0
T46	440945	0	0	0
T47	0	41	0	0
T48	0	26	0	0
T49	0	41	0	0
T50	0	79	0	0
T51	0	39	0	0
T52	0	15	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	27051	0	0
T8	574661	115	0	0
T9	166761	0	0	0
T10	109687	0	0	0
T11	659111	0	0	0
T13	0	1869	0	0
T16	0	119	0	0
T33	0	14	0	0
T35	0	1	0	0
T36	0	4	0	0
T47	0	34	0	0
T48	0	75	0	0
T53	0	23	0	0
T54	0	9	0	0
T55	132939	0	0	0
T56	925033	0	0	0
T57	435934	0	0	0
T58	442875	0	0	0
T59	146762	0	0	0
T60	963303	0	0	0