Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	10029071	0	0
cfg0_rd_A	2147483647	24222	0	0
compare_lower0_0_rd_A	2147483647	27704	0	0
compare_upper0_0_rd_A	2147483647	24634	0	0
ctrl_rd_A	2147483647	24793	0	0
intr_enable0_rd_A	2147483647	30020	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10029071	0	0
T3	559807	106075	0	0
T4	765248	0	0	0
T5	527484	0	0	0
T6	532541	132739	0	0
T7	161205	0	0	0
T8	154994	0	0	0
T9	101025	0	0	0
T10	534970	0	0	0
T11	790279	203754	0	0
T12	0	4	0	0
T29	0	10	0	0
T31	0	569291	0	0
T32	0	330499	0	0
T33	0	266295	0	0
T34	0	136241	0	0
T35	0	58	0	0
T36	100384	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	24222	0	0
T6	532541	1230	0	0
T7	161205	0	0	0
T8	154994	0	0	0
T9	101025	0	0	0
T10	534970	0	0	0
T11	790279	0	0	0
T31	144098	0	0	0
T32	0	3202	0	0
T33	0	1369	0	0
T36	100384	0	0	0
T37	0	65	0	0
T38	0	8	0	0
T39	0	5	0	0
T40	0	19	0	0
T41	0	41	0	0
T42	0	63	0	0
T43	0	146	0	0
T44	480939	0	0	0
T45	102088	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	27704	0	0
T6	532541	1529	0	0
T7	161205	0	0	0
T8	154994	0	0	0
T9	101025	0	0	0
T10	534970	0	0	0
T11	790279	0	0	0
T31	144098	0	0	0
T32	0	3353	0	0
T33	0	1543	0	0
T36	100384	0	0	0
T37	0	43	0	0
T39	0	3	0	0
T40	0	9	0	0
T41	0	69	0	0
T42	0	45	0	0
T43	0	98	0	0
T44	480939	0	0	0
T45	102088	0	0	0
T46	0	27	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	24634	0	0
T6	532541	1299	0	0
T7	161205	0	0	0
T8	154994	0	0	0
T9	101025	0	0	0
T10	534970	0	0	0
T11	790279	0	0	0
T31	144098	0	0	0
T32	0	3140	0	0
T33	0	1550	0	0
T36	100384	0	0	0
T37	0	43	0	0
T39	0	8	0	0
T40	0	7	0	0
T41	0	43	0	0
T42	0	41	0	0
T44	480939	0	0	0
T45	102088	0	0	0
T46	0	10	0	0
T47	0	2	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	24793	0	0
T6	532541	1314	0	0
T7	161205	0	0	0
T8	154994	0	0	0
T9	101025	0	0	0
T10	534970	0	0	0
T11	790279	0	0	0
T31	144098	0	0	0
T32	0	3249	0	0
T33	0	1246	0	0
T36	100384	0	0	0
T37	0	32	0	0
T38	0	6	0	0
T40	0	21	0	0
T41	0	89	0	0
T42	0	22	0	0
T43	0	48	0	0
T44	480939	0	0	0
T45	102088	0	0	0
T46	0	25	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	30020	0	0
T6	532541	1534	0	0
T7	161205	0	0	0
T8	154994	0	0	0
T9	101025	0	0	0
T10	534970	0	0	0
T11	790279	0	0	0
T31	144098	0	0	0
T32	0	3650	0	0
T33	0	1831	0	0
T36	100384	0	0	0
T37	0	29	0	0
T38	0	7	0	0
T39	0	16	0	0
T40	0	16	0	0
T44	480939	0	0	0
T45	102088	0	0	0
T46	0	8	0	0
T47	0	5	0	0
T48	0	6	0	0