Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	66737208	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	73844304	1		T1	75054		T2	1587		T3	5228

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	134494804	1		T1	40006		T2	3141		T3	10248
values[0x0]	2889825	1		T1	24032		T2	4		T3	37
values[0x1]	3196883	1		T1	26344		T2	7		T3	27

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	53157303	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	87424209	1		T1	79462		T2	1891		T3	6228

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	437173	1		T1	324		T2	10		T3	37
valid_sources[0x01]	443847	1		T1	359		T2	7		T3	39
valid_sources[0x02]	438085	1		T1	330		T2	18		T3	30
valid_sources[0x03]	565040	1		T1	366		T2	9		T3	47
valid_sources[0x04]	448774	1		T1	358		T2	6		T3	38
valid_sources[0x05]	444584	1		T1	350		T2	23		T3	36
valid_sources[0x06]	630701	1		T1	366		T2	20		T3	39
valid_sources[0x07]	445833	1		T1	410		T2	10		T3	35
valid_sources[0x08]	438641	1		T1	337		T2	17		T3	43
valid_sources[0x09]	435113	1		T1	347		T2	7		T3	62
valid_sources[0x0a]	454362	1		T1	358		T2	8		T3	44
valid_sources[0x0b]	434496	1		T1	349		T2	12		T3	36
valid_sources[0x0c]	531088	1		T1	356		T2	16		T3	37
valid_sources[0x0d]	436082	1		T1	333		T2	12		T3	38
valid_sources[0x0e]	441385	1		T1	356		T2	11		T3	47
valid_sources[0x0f]	439168	1		T1	369		T2	9		T3	29
valid_sources[0x10]	439381	1		T1	350		T2	9		T3	29
valid_sources[0x11]	438977	1		T1	363		T2	22		T3	30
valid_sources[0x12]	564291	1		T1	357		T2	12		T3	29
valid_sources[0x13]	434831	1		T1	352		T2	11		T3	31
valid_sources[0x14]	442598	1		T1	365		T2	7		T3	38
valid_sources[0x15]	466444	1		T1	339		T2	10		T3	38
valid_sources[0x16]	483636	1		T1	337		T2	16		T3	37
valid_sources[0x17]	444020	1		T1	344		T2	17		T3	44
valid_sources[0x18]	452053	1		T1	343		T2	15		T3	50
valid_sources[0x19]	450786	1		T1	321		T2	11		T3	40
valid_sources[0x1a]	446969	1		T1	363		T2	12		T3	38
valid_sources[0x1b]	443609	1		T1	370		T2	13		T3	44
valid_sources[0x1c]	557454	1		T1	371		T2	11		T3	33
valid_sources[0x1d]	442212	1		T1	370		T2	20		T3	48
valid_sources[0x1e]	765450	1		T1	307		T2	14		T3	39
valid_sources[0x1f]	1191810	1		T1	353		T2	14		T3	40
valid_sources[0x20]	434776	1		T1	340		T2	12		T3	35
valid_sources[0x21]	439156	1		T1	348		T2	12		T3	39
valid_sources[0x22]	443919	1		T1	370		T2	12		T3	27
valid_sources[0x23]	434985	1		T1	311		T2	13		T3	39
valid_sources[0x24]	438004	1		T1	332		T2	11		T3	37
valid_sources[0x25]	1026407	1		T1	389		T2	12		T3	31
valid_sources[0x26]	435920	1		T1	380		T2	11		T3	45
valid_sources[0x27]	788956	1		T1	351		T2	12		T3	49
valid_sources[0x28]	442610	1		T1	341		T2	4		T3	41
valid_sources[0x29]	437407	1		T1	343		T2	13		T3	30
valid_sources[0x2a]	449187	1		T1	313		T2	4		T3	46
valid_sources[0x2b]	480071	1		T1	355		T2	11		T3	49
valid_sources[0x2c]	434687	1		T1	364		T2	7		T3	43
valid_sources[0x2d]	440689	1		T1	351		T2	20		T3	43
valid_sources[0x2e]	438121	1		T1	330		T2	11		T3	46
valid_sources[0x2f]	437850	1		T1	369		T2	17		T3	51
valid_sources[0x30]	998011	1		T1	350		T2	11		T3	38
valid_sources[0x31]	434784	1		T1	350		T2	7		T3	44
valid_sources[0x32]	445363	1		T1	343		T2	17		T3	50
valid_sources[0x33]	438232	1		T1	319		T2	8		T3	32
valid_sources[0x34]	439109	1		T1	328		T2	7		T3	42
valid_sources[0x35]	551995	1		T1	398		T2	12		T3	34
valid_sources[0x36]	439251	1		T1	390		T2	8		T3	35
valid_sources[0x37]	437658	1		T1	350		T2	18		T3	51
valid_sources[0x38]	437388	1		T1	377		T2	17		T3	42
valid_sources[0x39]	440478	1		T1	333		T2	14		T3	32
valid_sources[0x3a]	442915	1		T1	390		T2	15		T3	55
valid_sources[0x3b]	442631	1		T1	407		T2	21		T3	36
valid_sources[0x3c]	438528	1		T1	359		T2	7		T3	40
valid_sources[0x3d]	450665	1		T1	360		T2	6		T3	39
valid_sources[0x3e]	441505	1		T1	365		T2	9		T3	34
valid_sources[0x3f]	558377	1		T1	357		T2	12		T3	47
valid_sources[0x40]	436809	1		T1	340		T2	18		T3	34
valid_sources[0x41]	444190	1		T1	350		T2	8		T3	35
valid_sources[0x42]	452442	1		T1	353		T2	11		T3	42
valid_sources[0x43]	434267	1		T1	342		T2	12		T3	30
valid_sources[0x44]	495111	1		T1	361		T2	12		T3	33
valid_sources[0x45]	444771	1		T1	383		T2	13		T3	49
valid_sources[0x46]	438074	1		T1	354		T2	18		T3	36
valid_sources[0x47]	434544	1		T1	385		T2	27		T3	44
valid_sources[0x48]	435364	1		T1	398		T2	8		T3	43
valid_sources[0x49]	443244	1		T1	377		T2	9		T3	38
valid_sources[0x4a]	516364	1		T1	307		T2	22		T3	31
valid_sources[0x4b]	439383	1		T1	341		T2	7		T3	43
valid_sources[0x4c]	439172	1		T1	355		T2	6		T3	33
valid_sources[0x4d]	440422	1		T1	362		T2	7		T3	45
valid_sources[0x4e]	439404	1		T1	358		T2	10		T3	33
valid_sources[0x4f]	448399	1		T1	361		T2	14		T3	34
valid_sources[0x50]	445502	1		T1	344		T2	21		T3	44
valid_sources[0x51]	434107	1		T1	378		T2	11		T3	42
valid_sources[0x52]	438717	1		T1	379		T2	18		T3	40
valid_sources[0x53]	443720	1		T1	363		T2	9		T3	60
valid_sources[0x54]	503956	1		T1	356		T2	15		T3	44
valid_sources[0x55]	436471	1		T1	381		T2	11		T3	25
valid_sources[0x56]	491537	1		T1	356		T2	12		T3	35
valid_sources[0x57]	442901	1		T1	368		T2	13		T3	27
valid_sources[0x58]	611282	1		T1	321		T2	25		T3	37
valid_sources[0x59]	462598	1		T1	375		T2	9		T3	45
valid_sources[0x5a]	434716	1		T1	402		T2	7		T3	47
valid_sources[0x5b]	447714	1		T1	324		T2	19		T3	35
valid_sources[0x5c]	435168	1		T1	333		T2	18		T3	38
valid_sources[0x5d]	1304896	1		T1	403		T2	18		T3	43
valid_sources[0x5e]	847437	1		T1	361		T2	14		T3	34
valid_sources[0x5f]	435676	1		T1	390		T2	11		T3	32
valid_sources[0x60]	436843	1		T1	344		T2	17		T3	45
valid_sources[0x61]	523576	1		T1	332		T2	8		T3	29
valid_sources[0x62]	435994	1		T1	349		T2	11		T3	45
valid_sources[0x63]	435471	1		T1	329		T2	11		T3	45
valid_sources[0x64]	445474	1		T1	344		T2	10		T3	41
valid_sources[0x65]	737912	1		T1	367		T2	9		T3	39
valid_sources[0x66]	441127	1		T1	394		T2	9		T3	29
valid_sources[0x67]	434894	1		T1	379		T2	9		T3	37
valid_sources[0x68]	441003	1		T1	337		T2	9		T3	43
valid_sources[0x69]	439338	1		T1	327		T2	16		T3	50
valid_sources[0x6a]	441336	1		T1	337		T2	7		T3	41
valid_sources[0x6b]	439002	1		T1	348		T2	9		T3	33
valid_sources[0x6c]	438971	1		T1	346		T2	10		T3	40
valid_sources[0x6d]	438850	1		T1	316		T2	13		T3	44
valid_sources[0x6e]	445090	1		T1	365		T2	5		T3	46
valid_sources[0x6f]	437839	1		T1	306		T2	14		T3	43
valid_sources[0x70]	448432	1		T1	332		T2	7		T3	32
valid_sources[0x71]	433772	1		T1	356		T2	11		T3	44
valid_sources[0x72]	433412	1		T1	359		T2	10		T3	47
valid_sources[0x73]	500852	1		T1	337		T2	11		T3	51
valid_sources[0x74]	512243	1		T1	337		T2	19		T3	35
valid_sources[0x75]	435669	1		T1	338		T2	9		T3	32
valid_sources[0x76]	432458	1		T1	325		T2	13		T3	39
valid_sources[0x77]	3633671	1		T1	364		T2	17		T3	50
valid_sources[0x78]	438089	1		T1	353		T2	16		T3	36
valid_sources[0x79]	496231	1		T1	382		T2	17		T3	47
valid_sources[0x7a]	453311	1		T1	364		T2	17		T3	51
valid_sources[0x7b]	718412	1		T1	362		T2	9		T3	50
valid_sources[0x7c]	449832	1		T1	347		T2	12		T3	37
valid_sources[0x7d]	435079	1		T1	358		T2	14		T3	41
valid_sources[0x7e]	473817	1		T1	364		T2	13		T3	38
valid_sources[0x7f]	443002	1		T1	361		T2	11		T3	45
valid_sources[0x80]	436373	1		T1	338		T2	6		T3	45

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

68142979

1

T1

27500

T2

1580

T3

5183

values[0x0]

all_enables

biggest_size

2851217

1

T1

23768

T2

2

T3

30

values[0x1]

all_enables

biggest_size

2850108

1

T1

23786

T2

5

T3

15