Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	10058778	0	0
cfg0_rd_A	2147483647	20686	0	0
compare_lower0_0_rd_A	2147483647	23785	0	0
compare_upper0_0_rd_A	2147483647	20989	0	0
ctrl_rd_A	2147483647	20897	0	0
intr_enable0_rd_A	2147483647	25431	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10058778	0	0
T1	353142	82716	0	0
T2	267236	0	0	0
T3	165257	0	0	0
T4	576587	0	0	0
T5	268298	0	0	0
T6	217638	0	0	0
T7	191252	0	0	0
T8	681935	0	0	0
T9	816497	0	0	0
T10	365059	105697	0	0
T11	0	201121	0	0
T30	0	80814	0	0
T31	0	229358	0	0
T32	0	113741	0	0
T33	0	243940	0	0
T34	0	60301	0	0
T35	0	269607	0	0
T36	0	484	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	20686	0	0
T1	353142	880	0	0
T2	267236	0	0	0
T3	165257	0	0	0
T4	576587	0	0	0
T5	268298	0	0	0
T6	217638	0	0	0
T7	191252	0	0	0
T8	681935	0	0	0
T9	816497	0	0	0
T10	365059	0	0	0
T11	0	1146	0	0
T27	0	52	0	0
T31	0	2218	0	0
T32	0	1139	0	0
T37	0	27	0	0
T38	0	12	0	0
T39	0	36	0	0
T40	0	61	0	0
T41	0	28	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	23785	0	0
T1	353142	871	0	0
T2	267236	0	0	0
T3	165257	0	0	0
T4	576587	0	0	0
T5	268298	0	0	0
T6	217638	0	0	0
T7	191252	0	0	0
T8	681935	0	0	0
T9	816497	0	0	0
T10	365059	0	0	0
T11	0	1275	0	0
T27	0	8	0	0
T31	0	2691	0	0
T32	0	1346	0	0
T37	0	9	0	0
T38	0	4	0	0
T39	0	34	0	0
T40	0	35	0	0
T41	0	21	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	20989	0	0
T1	353142	809	0	0
T2	267236	0	0	0
T3	165257	0	0	0
T4	576587	0	0	0
T5	268298	0	0	0
T6	217638	0	0	0
T7	191252	0	0	0
T8	681935	0	0	0
T9	816497	0	0	0
T10	365059	0	0	0
T11	0	943	0	0
T27	0	27	0	0
T31	0	2175	0	0
T32	0	1315	0	0
T37	0	23	0	0
T38	0	4	0	0
T39	0	20	0	0
T40	0	49	0	0
T42	0	1	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	20897	0	0
T1	353142	833	0	0
T2	267236	0	0	0
T3	165257	0	0	0
T4	576587	0	0	0
T5	268298	0	0	0
T6	217638	0	0	0
T7	191252	0	0	0
T8	681935	0	0	0
T9	816497	0	0	0
T10	365059	0	0	0
T11	0	920	0	0
T27	0	9	0	0
T31	0	2287	0	0
T32	0	1240	0	0
T37	0	23	0	0
T38	0	1	0	0
T39	0	4	0	0
T40	0	33	0	0
T41	0	26	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	25431	0	0
T1	353142	1003	0	0
T2	267236	0	0	0
T3	165257	0	0	0
T4	576587	0	0	0
T5	268298	0	0	0
T6	217638	0	0	0
T7	191252	0	0	0
T8	681935	0	0	0
T9	816497	0	0	0
T10	365059	0	0	0
T11	0	1226	0	0
T19	0	18	0	0
T20	0	33	0	0
T27	0	11	0	0
T31	0	2697	0	0
T32	0	1425	0	0
T37	0	51	0	0
T43	0	45	0	0
T44	0	27	0	0