Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	9074222	0	0
cfg0_rd_A	2147483647	24195	0	0
compare_lower0_0_rd_A	2147483647	26675	0	0
compare_upper0_0_rd_A	2147483647	23530	0	0
ctrl_rd_A	2147483647	23520	0	0
intr_enable0_rd_A	2147483647	29156	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9074222	0	0
T3	391207	158614	0	0
T4	272019	0	0	0
T5	740747	0	0	0
T6	106775	0	0	0
T7	842976	0	0	0
T8	189201	0	0	0
T9	115096	0	0	0
T10	314418	0	0	0
T11	0	227393	0	0
T12	128367	0	0	0
T13	0	183576	0	0
T14	0	62	0	0
T15	0	9	0	0
T33	0	100	0	0
T35	0	450429	0	0
T36	0	193848	0	0
T37	0	219449	0	0
T38	0	122	0	0
T39	477598	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	24195	0	0
T15	0	115	0	0
T33	0	16	0	0
T35	188401	4451	0	0
T36	772095	1864	0	0
T40	0	10	0	0
T41	0	30	0	0
T42	0	7	0	0
T43	0	48	0	0
T44	0	4	0	0
T45	0	33	0	0
T46	121718	0	0	0
T47	135334	0	0	0
T48	119387	0	0	0
T49	779327	0	0	0
T50	386623	0	0	0
T51	796699	0	0	0
T52	392837	0	0	0
T53	108955	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	26675	0	0
T15	0	49	0	0
T33	0	26	0	0
T35	188401	5228	0	0
T36	772095	2185	0	0
T40	0	13	0	0
T41	0	26	0	0
T42	0	9	0	0
T43	0	80	0	0
T45	0	57	0	0
T46	121718	0	0	0
T47	135334	0	0	0
T48	119387	0	0	0
T49	779327	0	0	0
T50	386623	0	0	0
T51	796699	0	0	0
T52	392837	0	0	0
T53	108955	0	0	0
T54	0	11	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	23530	0	0
T15	0	44	0	0
T33	0	26	0	0
T35	188401	4260	0	0
T36	772095	1660	0	0
T40	0	23	0	0
T41	0	50	0	0
T42	0	6	0	0
T43	0	90	0	0
T45	0	31	0	0
T46	121718	0	0	0
T47	135334	0	0	0
T48	119387	0	0	0
T49	779327	0	0	0
T50	386623	0	0	0
T51	796699	0	0	0
T52	392837	0	0	0
T53	108955	0	0	0
T54	0	10	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	23520	0	0
T15	0	36	0	0
T33	0	28	0	0
T35	188401	4547	0	0
T36	772095	1782	0	0
T40	0	18	0	0
T41	0	37	0	0
T43	0	38	0	0
T44	0	4	0	0
T45	0	60	0	0
T46	121718	0	0	0
T47	135334	0	0	0
T48	119387	0	0	0
T49	779327	0	0	0
T50	386623	0	0	0
T51	796699	0	0	0
T52	392837	0	0	0
T53	108955	0	0	0
T54	0	3	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	29156	0	0
T15	0	30	0	0
T33	0	22	0	0
T35	188401	5205	0	0
T36	772095	2511	0	0
T40	0	21	0	0
T41	0	30	0	0
T43	0	53	0	0
T46	121718	0	0	0
T47	135334	0	0	0
T48	119387	0	0	0
T49	779327	0	0	0
T50	386623	0	0	0
T51	796699	0	0	0
T52	392837	0	0	0
T53	108955	0	0	0
T54	0	7	0	0
T55	0	40	0	0
T56	0	14	0	0