Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	60181620	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	68335681	1		T1	45768		T2	3474		T3	5646

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	121545305	1		T1	91355		T2	6850		T3	11308
values[0x0]	3311316	1		T1	19		T2	15		T3	20
values[0x1]	3660680	1		T1	19		T2	14		T3	20

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	47894897	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	80622404	1		T1	55000		T2	4178		T3	6791

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	399494	1		T1	363		T4	340		T5	43
valid_sources[0x01]	393880	1		T1	407		T4	298		T5	31
valid_sources[0x02]	396010	1		T1	246		T4	284		T5	44
valid_sources[0x03]	393869	1		T1	536		T4	242		T5	31
valid_sources[0x04]	397453	1		T1	290		T4	295		T5	55
valid_sources[0x05]	1026250	1		T1	494		T4	287		T5	19
valid_sources[0x06]	805535	1		T1	274		T4	297		T5	29
valid_sources[0x07]	394254	1		T1	418		T4	255		T5	27
valid_sources[0x08]	425420	1		T1	303		T4	322		T5	18
valid_sources[0x09]	868292	1		T1	323		T4	274		T5	34
valid_sources[0x0a]	392384	1		T1	336		T4	318		T5	19
valid_sources[0x0b]	397041	1		T1	382		T4	334		T5	32
valid_sources[0x0c]	397963	1		T1	349		T4	286		T5	21
valid_sources[0x0d]	396207	1		T1	332		T4	270		T5	24
valid_sources[0x0e]	396795	1		T1	392		T4	317		T5	16
valid_sources[0x0f]	393191	1		T1	343		T4	275		T5	33
valid_sources[0x10]	395001	1		T1	314		T4	297		T5	38
valid_sources[0x11]	429694	1		T1	339		T4	247		T5	24
valid_sources[0x12]	395694	1		T1	301		T4	257		T5	26
valid_sources[0x13]	440966	1		T1	266		T4	275		T5	37
valid_sources[0x14]	395771	1		T1	359		T4	303		T5	29
valid_sources[0x15]	397820	1		T1	464		T4	286		T5	45
valid_sources[0x16]	422144	1		T1	393		T4	288		T5	42
valid_sources[0x17]	396132	1		T1	287		T4	296		T5	28
valid_sources[0x18]	398100	1		T1	407		T4	303		T5	33
valid_sources[0x19]	912153	1		T1	290		T4	258		T5	42
valid_sources[0x1a]	390471	1		T1	410		T4	299		T5	38
valid_sources[0x1b]	389553	1		T1	405		T4	241		T5	18
valid_sources[0x1c]	401993	1		T1	408		T3	11348		T4	282
valid_sources[0x1d]	392316	1		T1	495		T4	255		T5	43
valid_sources[0x1e]	2031198	1		T1	251		T4	311		T5	25
valid_sources[0x1f]	397410	1		T1	449		T4	301		T5	31
valid_sources[0x20]	391029	1		T1	417		T4	306		T5	27
valid_sources[0x21]	1747141	1		T1	312		T4	301		T5	24
valid_sources[0x22]	392532	1		T1	351		T4	303		T5	26
valid_sources[0x23]	393976	1		T1	457		T4	295		T5	19
valid_sources[0x24]	399781	1		T1	323		T4	310		T5	16
valid_sources[0x25]	414961	1		T1	298		T4	290		T5	18
valid_sources[0x26]	409226	1		T1	357		T4	283		T5	27
valid_sources[0x27]	387534	1		T1	441		T4	285		T5	13
valid_sources[0x28]	820309	1		T1	285		T4	271		T5	37
valid_sources[0x29]	391825	1		T1	374		T4	294		T5	37
valid_sources[0x2a]	452591	1		T1	379		T4	306		T5	19
valid_sources[0x2b]	464589	1		T1	357		T4	344		T5	16
valid_sources[0x2c]	397568	1		T1	349		T4	269		T5	28
valid_sources[0x2d]	396826	1		T1	372		T4	298		T5	47
valid_sources[0x2e]	391379	1		T1	343		T4	278		T5	26
valid_sources[0x2f]	402911	1		T1	319		T4	263		T5	28
valid_sources[0x30]	406390	1		T1	333		T4	277		T5	24
valid_sources[0x31]	392885	1		T1	428		T4	277		T5	42
valid_sources[0x32]	394331	1		T1	303		T4	318		T5	36
valid_sources[0x33]	489338	1		T1	359		T4	256		T5	35
valid_sources[0x34]	394163	1		T1	290		T4	283		T5	22
valid_sources[0x35]	484136	1		T1	355		T4	278		T5	27
valid_sources[0x36]	394187	1		T1	305		T4	293		T5	35
valid_sources[0x37]	392103	1		T1	366		T4	306		T5	25
valid_sources[0x38]	400680	1		T1	449		T4	291		T5	13
valid_sources[0x39]	489317	1		T1	367		T4	286		T5	6
valid_sources[0x3a]	412538	1		T1	313		T4	291		T5	34
valid_sources[0x3b]	397799	1		T1	515		T4	314		T5	22
valid_sources[0x3c]	401296	1		T1	315		T4	301		T5	37
valid_sources[0x3d]	393052	1		T1	355		T4	302		T5	22
valid_sources[0x3e]	405804	1		T1	457		T4	298		T5	27
valid_sources[0x3f]	393122	1		T1	341		T4	256		T5	18
valid_sources[0x40]	395600	1		T1	479		T4	287		T5	32
valid_sources[0x41]	390906	1		T1	283		T4	255		T5	7
valid_sources[0x42]	394478	1		T1	286		T4	271		T5	45
valid_sources[0x43]	776183	1		T1	301		T4	312		T5	26
valid_sources[0x44]	393281	1		T1	255		T4	304		T5	31
valid_sources[0x45]	398205	1		T1	341		T4	317		T5	22
valid_sources[0x46]	394417	1		T1	446		T4	282		T5	20
valid_sources[0x47]	388506	1		T1	372		T4	254		T5	36
valid_sources[0x48]	393944	1		T1	375		T4	288		T5	31
valid_sources[0x49]	2586494	1		T1	302		T4	346		T5	27
valid_sources[0x4a]	399118	1		T1	489		T4	281		T5	24
valid_sources[0x4b]	392707	1		T1	319		T4	306		T5	29
valid_sources[0x4c]	438899	1		T1	445		T4	295		T5	27
valid_sources[0x4d]	734242	1		T1	232		T4	266		T5	18
valid_sources[0x4e]	390757	1		T1	313		T4	271		T5	33
valid_sources[0x4f]	956692	1		T1	401		T4	308		T5	20
valid_sources[0x50]	395527	1		T1	361		T4	307		T5	13
valid_sources[0x51]	391962	1		T1	350		T4	302		T5	47
valid_sources[0x52]	392333	1		T1	277		T4	312		T5	10
valid_sources[0x53]	394487	1		T1	379		T4	317		T5	25
valid_sources[0x54]	471528	1		T1	362		T4	253		T5	31
valid_sources[0x55]	396747	1		T1	394		T4	280		T5	17
valid_sources[0x56]	395627	1		T1	363		T4	292		T5	26
valid_sources[0x57]	397239	1		T1	399		T4	306		T5	50
valid_sources[0x58]	397676	1		T1	338		T4	306		T5	24
valid_sources[0x59]	416512	1		T1	497		T4	262		T5	48
valid_sources[0x5a]	396291	1		T1	324		T4	271		T5	28
valid_sources[0x5b]	624926	1		T1	460		T4	277		T5	15
valid_sources[0x5c]	392509	1		T1	406		T4	291		T5	18
valid_sources[0x5d]	396482	1		T1	414		T4	290		T5	35
valid_sources[0x5e]	393655	1		T1	470		T4	286		T5	30
valid_sources[0x5f]	398669	1		T1	310		T4	282		T5	14
valid_sources[0x60]	750230	1		T1	255		T4	269		T5	23
valid_sources[0x61]	394169	1		T1	394		T4	306		T5	14
valid_sources[0x62]	397563	1		T1	393		T4	306		T5	21
valid_sources[0x63]	394519	1		T1	334		T4	285		T5	19
valid_sources[0x64]	394493	1		T1	372		T4	327		T5	38
valid_sources[0x65]	393076	1		T1	372		T4	271		T5	26
valid_sources[0x66]	395684	1		T1	431		T4	295		T5	20
valid_sources[0x67]	395015	1		T1	355		T4	239		T5	36
valid_sources[0x68]	819087	1		T1	442		T4	286		T5	34
valid_sources[0x69]	388996	1		T1	444		T4	292		T5	18
valid_sources[0x6a]	405271	1		T1	257		T4	267		T5	20
valid_sources[0x6b]	587365	1		T1	403		T4	322		T5	32
valid_sources[0x6c]	397707	1		T1	489		T4	297		T5	29
valid_sources[0x6d]	430632	1		T1	380		T4	279		T5	25
valid_sources[0x6e]	393679	1		T1	407		T4	302		T5	14
valid_sources[0x6f]	396774	1		T1	290		T4	283		T5	44
valid_sources[0x70]	391871	1		T1	334		T4	271		T5	30
valid_sources[0x71]	395059	1		T1	427		T4	299		T5	19
valid_sources[0x72]	564483	1		T1	329		T4	266		T5	24
valid_sources[0x73]	391311	1		T1	270		T4	262		T5	18
valid_sources[0x74]	424854	1		T1	284		T4	292		T5	27
valid_sources[0x75]	1318181	1		T1	412		T4	310		T5	46
valid_sources[0x76]	393122	1		T1	294		T4	300		T5	36
valid_sources[0x77]	559199	1		T1	320		T4	318		T5	26
valid_sources[0x78]	396584	1		T1	378		T4	257		T5	16
valid_sources[0x79]	402211	1		T1	380		T4	264		T5	32
valid_sources[0x7a]	1275259	1		T1	348		T4	281		T5	35
valid_sources[0x7b]	448509	1		T1	363		T4	327		T5	35
valid_sources[0x7c]	394032	1		T1	246		T4	282		T5	59
valid_sources[0x7d]	397888	1		T1	417		T4	285		T5	34
valid_sources[0x7e]	398166	1		T1	274		T4	312		T5	32
valid_sources[0x7f]	392669	1		T1	430		T4	290		T5	11
valid_sources[0x80]	1445203	1		T1	429		T4	299		T5	31

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

61803057

1

T1

45741

T2

3451

T3

5613

values[0x0]

all_enables

biggest_size

3267464

1

T1

16

T2

13

T3

19

values[0x1]

all_enables

biggest_size

3265160

1

T1

11

T2

10

T3

14