Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	11549261	0	0
cfg0_rd_A	2147483647	21422	0	0
compare_lower0_0_rd_A	2147483647	22678	0	0
compare_upper0_0_rd_A	2147483647	20273	0	0
ctrl_rd_A	2147483647	20066	0	0
intr_enable0_rd_A	2147483647	25610	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	11549261	0	0
T11	561311	80296	0	0
T12	829220	323442	0	0
T13	0	43430	0	0
T14	3159	0	0	0
T21	882175	0	0	0
T22	540486	0	0	0
T23	110877	0	0	0
T24	164174	0	0	0
T25	482721	0	0	0
T26	567052	0	0	0
T27	432398	0	0	0
T31	0	485222	0	0
T32	0	160272	0	0
T33	0	213885	0	0
T34	0	175380	0	0
T35	0	156852	0	0
T36	0	904	0	0
T37	0	591	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21422	0	0
T13	153388	246	0	0
T16	0	51	0	0
T30	0	38	0	0
T31	169231	0	0	0
T33	0	2530	0	0
T36	0	18	0	0
T37	0	7	0	0
T38	0	7	0	0
T39	0	393	0	0
T40	0	64	0	0
T41	0	18	0	0
T42	153951	0	0	0
T43	310200	0	0	0
T44	237909	0	0	0
T45	735849	0	0	0
T46	759756	0	0	0
T47	12493	0	0	0
T48	453489	0	0	0
T49	436954	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	22678	0	0
T13	153388	331	0	0
T16	0	51	0	0
T30	0	10	0	0
T31	169231	0	0	0
T33	0	2496	0	0
T36	0	3	0	0
T37	0	6	0	0
T39	0	441	0	0
T40	0	40	0	0
T41	0	15	0	0
T42	153951	0	0	0
T43	310200	0	0	0
T44	237909	0	0	0
T45	735849	0	0	0
T46	759756	0	0	0
T47	12493	0	0	0
T48	453489	0	0	0
T49	436954	0	0	0
T50	0	129	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	20273	0	0
T13	153388	243	0	0
T16	0	39	0	0
T30	0	36	0	0
T31	169231	0	0	0
T33	0	2033	0	0
T36	0	6	0	0
T37	0	6	0	0
T39	0	430	0	0
T40	0	46	0	0
T41	0	12	0	0
T42	153951	0	0	0
T43	310200	0	0	0
T44	237909	0	0	0
T45	735849	0	0	0
T46	759756	0	0	0
T47	12493	0	0	0
T48	453489	0	0	0
T49	436954	0	0	0
T50	0	114	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	20066	0	0
T13	153388	280	0	0
T16	0	28	0	0
T30	0	19	0	0
T31	169231	0	0	0
T33	0	2114	0	0
T37	0	2	0	0
T38	0	4	0	0
T39	0	409	0	0
T40	0	42	0	0
T41	0	17	0	0
T42	153951	0	0	0
T43	310200	0	0	0
T44	237909	0	0	0
T45	735849	0	0	0
T46	759756	0	0	0
T47	12493	0	0	0
T48	453489	0	0	0
T49	436954	0	0	0
T50	0	139	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	25610	0	0
T13	153388	294	0	0
T16	0	28	0	0
T30	0	16	0	0
T31	169231	0	0	0
T33	0	2625	0	0
T36	0	32	0	0
T37	0	23	0	0
T39	0	399	0	0
T40	0	30	0	0
T42	153951	50	0	0
T43	310200	0	0	0
T44	237909	0	0	0
T45	735849	0	0	0
T46	759756	0	0	0
T47	12493	0	0	0
T48	453489	0	0	0
T49	436954	15	0	0